gpio/omap: enable irq at the end of all configuration in restore

Setup the interrupt enable registers only after we have configured the
required edge and required configurations, not before, to prevent
spurious events as part of restore routine.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f6b2c51b29354bcd19bcc286ec2bff79ac6ae8a3..41265e823b23a7908782ee002490557352e3a2b6 100644 (file)
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1352,10 +1352,6 @@ void omap2_gpio_resume_after_idle(void)
 #if defined(CONFIG_PM_RUNTIME)
 static void omap_gpio_restore_context(struct gpio_bank *bank)
 {
-       __raw_writel(bank->context.irqenable1,
-                               bank->base + bank->regs->irqenable);
-       __raw_writel(bank->context.irqenable2,
-                               bank->base + bank->regs->irqenable2);
        __raw_writel(bank->context.wake_en,
                                bank->base + bank->regs->wkup_en);
        __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
@@ -1375,6 +1371,11 @@ static void omap_gpio_restore_context(struct gpio_bank *bank)
                __raw_writel(bank->context.debounce_en,
                                        bank->base + bank->regs->debounce_en);
        }
+
+       __raw_writel(bank->context.irqenable1,
+                               bank->base + bank->regs->irqenable);
+       __raw_writel(bank->context.irqenable2,
+                               bank->base + bank->regs->irqenable2);
 }
 #endif /* CONFIG_PM_RUNTIME */
 #else