]> Pileus Git - ~andy/linux/commitdiff
clocksource: m86k: Convert to clocksource_register_hz/khz
authorjohn stultz <johnstul@us.ibm.com>
Tue, 25 Oct 2011 18:46:10 +0000 (11:46 -0700)
committerGreg Ungerer <gerg@uclinux.org>
Sat, 24 Dec 2011 11:47:56 +0000 (21:47 +1000)
Updated to merge the valid bits of the two m68k patches.

This converts the m86k clocksources to use clocksource_register_hz/khz

This is untested, so any assistance in testing would be appreciated!

CC: Geert Uytterhoeven <geert@linux-m68k.org>
CC: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: John Stultz <johnstul@us.ibm.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
arch/m68k/platform/68328/timers.c
arch/m68k/platform/coldfire/dma_timer.c
arch/m68k/platform/coldfire/pit.c
arch/m68k/platform/coldfire/sltimers.c
arch/m68k/platform/coldfire/timers.c

index 309f725995bf4900bb1423a64ad21f0353acd697..f2678866067bb3b41faf4eb1c7f71eae6ff63832 100644 (file)
@@ -93,7 +93,6 @@ static struct clocksource m68328_clk = {
        .name   = "timer",
        .rating = 250,
        .read   = m68328_read_clk,
-       .shift  = 20,
        .mask   = CLOCKSOURCE_MASK(32),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
@@ -115,8 +114,7 @@ void hw_timer_init(void)
 
        /* Enable timer 1 */
        TCTL |= TCTL_TEN;
-       m68328_clk.mult = clocksource_hz2mult(TICKS_PER_JIFFY*HZ, m68328_clk.shift);
-       clocksource_register(&m68328_clk);
+       clocksource_register_hz(&m68328_clk, TICKS_PER_JIFFY*HZ);
 }
 
 /***************************************************************************/
index a5f562823d7acfa9e5d4fc6a66d37b9cd31c4428..235ad57c470798c9538fab0fab7fef4936bd7a3c 100644 (file)
@@ -44,7 +44,6 @@ static struct clocksource clocksource_cf_dt = {
        .rating         = 200,
        .read           = cf_dt_get_cycles,
        .mask           = CLOCKSOURCE_MASK(32),
-       .shift          = 20,
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
@@ -60,9 +59,7 @@ static int __init  init_cf_dt_clocksource(void)
        __raw_writeb(0x00, DTER0);
        __raw_writel(0x00000000, DTRR0);
        __raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
-       clocksource_cf_dt.mult = clocksource_hz2mult(DMA_FREQ,
-                                                    clocksource_cf_dt.shift);
-       return clocksource_register(&clocksource_cf_dt);
+       return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
 }
 
 arch_initcall(init_cf_dt_clocksource);
index c2b980926becfb001f8ec21f8b98d5cc233550e8..02663d25822ddb6f8ce8363c8e7501f97b299867 100644 (file)
@@ -144,7 +144,6 @@ static struct clocksource pit_clk = {
        .name   = "pit",
        .rating = 100,
        .read   = pit_read_clk,
-       .shift  = 20,
        .mask   = CLOCKSOURCE_MASK(32),
 };
 
@@ -162,8 +161,7 @@ void hw_timer_init(void)
 
        setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
 
-       pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
-       clocksource_register(&pit_clk);
+       clocksource_register_hz(&pit_clk, FREQ);
 }
 
 /***************************************************************************/
index 6a85daf9a7fd5a2b3dfc7ed9cde4a487cc92500d..b7f822b552bbdba06474d78dfa2b89832d15995c 100644 (file)
@@ -114,7 +114,6 @@ static struct clocksource mcfslt_clk = {
        .name   = "slt",
        .rating = 250,
        .read   = mcfslt_read_clk,
-       .shift  = 20,
        .mask   = CLOCKSOURCE_MASK(32),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
@@ -136,8 +135,7 @@ void hw_timer_init(void)
 
        setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
 
-       mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
-       clocksource_register(&mcfslt_clk);
+       clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
 
 #ifdef CONFIG_HIGHPROFILE
        mcfslt_profile_init();
index 60242f65fea90a3df427d9fca7158cd37b45fb89..0d90da32fcdb7631f6eec295c9e98e0476e6ba3f 100644 (file)
@@ -88,7 +88,6 @@ static struct clocksource mcftmr_clk = {
        .name   = "tmr",
        .rating = 250,
        .read   = mcftmr_read_clk,
-       .shift  = 20,
        .mask   = CLOCKSOURCE_MASK(32),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 };
@@ -109,8 +108,7 @@ void hw_timer_init(void)
        __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
                MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
 
-       mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
-       clocksource_register(&mcftmr_clk);
+       clocksource_register_hz(&mcftmr_clk, FREQ);
 
        setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);