Merge branch 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm...

As promised bdw fixes come separate for now. Just a few minior things.

* 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915/bdw: PIPE_[BC] I[ME]R moved to powerwell
  drm/i915/bdw: Limit GTT to 2GB
  drm/i915/bdw: Add comment about gen8 HWS PGA
  drm/i915/bdw: Free correct number of ppgtt pages
  drm/i915/bdw: Do gen6 style reset for gen8
  drm/i915/bdw: GEN8 backlight support
  drm/i915/bdw: Add BDW to ULT macro

diff --combined drivers/gpu/drm/i915/i915_drv.h
index ccdbecca070d2340919d5499f80824ddb84db4ac,51951ef7e71df865a13d2f6a885b4518a5ba59c4..79ae94a436a00b2aa04610c4a7db07e1612cb37c
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1755,8 -1755,13 +1755,13 @@@ struct drm_i915_file_private 
  #define IS_MOBILE(dev)                (INTEL_INFO(dev)->is_mobile)
  #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0xFF00) == 0x0C00)
- #define IS_ULT(dev)           (IS_HASWELL(dev) && \
+ #define IS_BDW_ULT(dev)               (IS_BROADWELL(dev) && \
+                                (((dev)->pdev->device & 0xf) == 0x2  || \
+                                ((dev)->pdev->device & 0xf) == 0x6 || \
+                                ((dev)->pdev->device & 0xf) == 0xe))
+ #define IS_HSW_ULT(dev)               (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0xFF00) == 0x0A00)
+ #define IS_ULT(dev)           (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
  #define IS_HSW_GT3(dev)               (IS_HASWELL(dev) && \
                                 ((dev)->pdev->device & 0x00F0) == 0x0020)
  #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@@ -1816,7 -1821,6 +1821,7 @@@
  #define HAS_POWER_WELL(dev)   (IS_HASWELL(dev) || IS_BROADWELL(dev))
  #define HAS_FPGA_DBG_UNCLAIMED(dev)   (INTEL_INFO(dev)->has_fpga_dbg)
  #define HAS_PSR(dev)          (IS_HASWELL(dev) || IS_BROADWELL(dev))
 +#define HAS_PC8(dev)          (IS_HASWELL(dev)) /* XXX HSW:ULX */
  
  #define INTEL_PCH_DEVICE_ID_MASK              0xff00
  #define INTEL_PCH_IBX_DEVICE_ID_TYPE          0x3b00

diff --combined drivers/gpu/drm/i915/i915_gem_gtt.c
index 38cb8d44a0133a6c096524a553d45fcb33cd72a1,f69bdc741b8008729747feccc2cb66b6cc75f4af..c79dd2b1f70ecc2af6d0fb67a3c3289672eba7f9
--- 1/drivers/gpu/drm/i915/i915_gem_gtt.c
--- 2/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@@ -57,9 -57,7 +57,9 @@@ typedef gen8_gtt_pte_t gen8_ppgtt_pde_t
  #define HSW_WB_LLC_AGE3                       HSW_CACHEABILITY_CONTROL(0x2)
  #define HSW_WB_LLC_AGE0                       HSW_CACHEABILITY_CONTROL(0x3)
  #define HSW_WB_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0xb)
 +#define HSW_WB_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x8)
  #define HSW_WT_ELLC_LLC_AGE0          HSW_CACHEABILITY_CONTROL(0x6)
 +#define HSW_WT_ELLC_LLC_AGE3          HSW_CACHEABILITY_CONTROL(0x7)
  
  #define GEN8_PTES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
  #define GEN8_PDES_PER_PAGE            (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
@@@ -187,10 -185,10 +187,10 @@@ static gen6_gtt_pte_t iris_pte_encode(d
        case I915_CACHE_NONE:
                break;
        case I915_CACHE_WT:
 -              pte |= HSW_WT_ELLC_LLC_AGE0;
 +              pte |= HSW_WT_ELLC_LLC_AGE3;
                break;
        default:
 -              pte |= HSW_WB_ELLC_LLC_AGE0;
 +              pte |= HSW_WB_ELLC_LLC_AGE3;
                break;
        }
  
@@@ -337,8 -335,8 +337,8 @@@ static void gen8_ppgtt_cleanup(struct i
                kfree(ppgtt->gen8_pt_dma_addr[i]);
        }
  
-       __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT);
-       __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT);
+       __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
+       __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
  }
  
  /**
@@@ -1241,6 -1239,11 +1241,11 @@@ static inline unsigned int gen8_get_tot
        bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
        if (bdw_gmch_ctl)
                bdw_gmch_ctl = 1 << bdw_gmch_ctl;
+       if (bdw_gmch_ctl > 4) {
+               WARN_ON(!i915_preliminary_hw_support);
+               return 4<<20;
+       }
+ 
        return bdw_gmch_ctl << 20;
  }
  

diff --combined drivers/gpu/drm/i915/intel_pm.c
index 6e0d5e075b15cb338694013450da3752b92442f2,33a8dbe640398970a116c824bafa42fe8e87cd02..aa5f99c906ef7086a00835d0b793924a7e5a6051
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -1180,7 -1180,7 +1180,7 @@@ static bool g4x_compute_wm0(struct drm_
  
        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
        clock = adjusted_mode->crtc_clock;
 -      htotal = adjusted_mode->htotal;
 +      htotal = adjusted_mode->crtc_htotal;
        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
        pixel_size = crtc->fb->bits_per_pixel / 8;
  
@@@ -1267,7 -1267,7 +1267,7 @@@ static bool g4x_compute_srwm(struct drm
        crtc = intel_get_crtc_for_plane(dev, plane);
        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
        clock = adjusted_mode->crtc_clock;
 -      htotal = adjusted_mode->htotal;
 +      htotal = adjusted_mode->crtc_htotal;
        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
        pixel_size = crtc->fb->bits_per_pixel / 8;
  
@@@ -1498,7 -1498,7 +1498,7 @@@ static void i965_update_wm(struct drm_c
                const struct drm_display_mode *adjusted_mode =
                        &to_intel_crtc(crtc)->config.adjusted_mode;
                int clock = adjusted_mode->crtc_clock;
 -              int htotal = adjusted_mode->htotal;
 +              int htotal = adjusted_mode->crtc_htotal;
                int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
                int pixel_size = crtc->fb->bits_per_pixel / 8;
                unsigned long line_time_us;
@@@ -1624,8 -1624,8 +1624,8 @@@ static void i9xx_update_wm(struct drm_c
                const struct drm_display_mode *adjusted_mode =
                        &to_intel_crtc(enabled)->config.adjusted_mode;
                int clock = adjusted_mode->crtc_clock;
 -              int htotal = adjusted_mode->htotal;
 -              int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
 +              int htotal = adjusted_mode->crtc_htotal;
 +              int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
                int pixel_size = enabled->fb->bits_per_pixel / 8;
                unsigned long line_time_us;
                int entries;
@@@ -1776,7 -1776,7 +1776,7 @@@ static bool ironlake_compute_srwm(struc
        crtc = intel_get_crtc_for_plane(dev, plane);
        adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
        clock = adjusted_mode->crtc_clock;
 -      htotal = adjusted_mode->htotal;
 +      htotal = adjusted_mode->crtc_htotal;
        hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
        pixel_size = crtc->fb->bits_per_pixel / 8;
  
@@@ -2469,9 -2469,8 +2469,9 @@@ hsw_compute_linetime_wm(struct drm_devi
        /* The WM are computed with base on how long it takes to fill a single
         * row at the given clock rate, multiplied by 8.
         * */
 -      linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
 -      ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
 +      linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
 +                                   mode->crtc_clock);
 +      ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
                                         intel_ddi_get_cdclk_freq(dev_priv));
  
        return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
@@@ -3889,7 -3888,7 +3889,7 @@@ static void gen6_enable_rps(struct drm_
  
        I915_WRITE(GEN6_RC_SLEEP, 0);
        I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 -      if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
 +      if (IS_IVYBRIDGE(dev))
                I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
        else
                I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
@@@ -5685,6 -5684,7 +5685,7 @@@ static void __intel_set_power_well(stru
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
        bool is_enabled, enable_requested;
+       unsigned long irqflags;
        uint32_t tmp;
  
        tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@@ -5702,9 -5702,24 +5703,24 @@@
                                      HSW_PWR_WELL_STATE_ENABLED), 20))
                                DRM_ERROR("Timeout enabling power well\n");
                }
+ 
+               if (IS_BROADWELL(dev)) {
+                       spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+                       I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
+                                  dev_priv->de_irq_mask[PIPE_B]);
+                       I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
+                                  ~dev_priv->de_irq_mask[PIPE_B] |
+                                  GEN8_PIPE_VBLANK);
+                       I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
+                                  dev_priv->de_irq_mask[PIPE_C]);
+                       I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
+                                  ~dev_priv->de_irq_mask[PIPE_C] |
+                                  GEN8_PIPE_VBLANK);
+                       POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
+                       spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+               }
        } else {
                if (enable_requested) {
-                       unsigned long irqflags;
                        enum pipe p;
  
                        I915_WRITE(HSW_PWR_WELL_DRIVER, 0);

diff --combined drivers/gpu/drm/i915/intel_uncore.c
index 0b02078a0b848c4127385b1d3b5d3ab6be755c80,6a4f9b615de1a9b17e40b8452ad37d648d1c6bb6..25cbe073c388a3185d1a32afeb805993e43d12d3
--- 1/drivers/gpu/drm/i915/intel_uncore.c
--- 2/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@@ -217,19 -217,6 +217,19 @@@ static void gen6_force_wake_work(struc
        spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
  }
  
 +static void intel_uncore_forcewake_reset(struct drm_device *dev)
 +{
 +      struct drm_i915_private *dev_priv = dev->dev_private;
 +
 +      if (IS_VALLEYVIEW(dev)) {
 +              vlv_force_wake_reset(dev_priv);
 +      } else if (INTEL_INFO(dev)->gen >= 6) {
 +              __gen6_gt_force_wake_reset(dev_priv);
 +              if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 +                      __gen6_gt_force_wake_mt_reset(dev_priv);
 +      }
 +}
 +
  void intel_uncore_early_sanitize(struct drm_device *dev)
  {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@@ -247,8 -234,19 +247,8 @@@
                dev_priv->ellc_size = 128;
                DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
        }
 -}
  
 -static void intel_uncore_forcewake_reset(struct drm_device *dev)
 -{
 -      struct drm_i915_private *dev_priv = dev->dev_private;
 -
 -      if (IS_VALLEYVIEW(dev)) {
 -              vlv_force_wake_reset(dev_priv);
 -      } else if (INTEL_INFO(dev)->gen >= 6) {
 -              __gen6_gt_force_wake_reset(dev_priv);
 -              if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 -                      __gen6_gt_force_wake_mt_reset(dev_priv);
 -      }
 +      intel_uncore_forcewake_reset(dev);
  }
  
  void intel_uncore_sanitize(struct drm_device *dev)
@@@ -784,6 -782,7 +784,7 @@@ static int gen6_do_reset(struct drm_dev
  int intel_gpu_reset(struct drm_device *dev)
  {
        switch (INTEL_INFO(dev)->gen) {
+       case 8:
        case 7:
        case 6: return gen6_do_reset(dev);
        case 5: return ironlake_do_reset(dev);