#include <linux/platform_device.h>
#include <linux/i2c-gpio.h>
#include <linux/atmel-mci.h>
+ #include <linux/platform_data/atmel-aes.h>
#include <linux/platform_data/at91_adc.h>
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_DMA,
- .end = AT91SAM9G45_ID_DMA,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_UHPHS,
- .end = AT91SAM9G45_ID_UHPHS,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_UHPHS,
- .end = AT91SAM9G45_ID_UHPHS,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = AT91SAM9G45_ID_UDPHS,
- .end = AT91SAM9G45_ID_UDPHS,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_EMAC,
- .end = AT91SAM9G45_ID_EMAC,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_MCI0,
- .end = AT91SAM9G45_ID_MCI0,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_MCI1,
- .end = AT91SAM9G45_ID_MCI1,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TWI0,
- .end = AT91SAM9G45_ID_TWI0,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TWI1,
- .end = AT91SAM9G45_ID_TWI1,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_SPI0,
- .end = AT91SAM9G45_ID_SPI0,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_SPI1,
- .end = AT91SAM9G45_ID_SPI1,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_AC97C,
- .end = AT91SAM9G45_ID_AC97C,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_ISI,
- .end = AT91SAM9G45_ID_ISI,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_LCDC,
- .end = AT91SAM9G45_ID_LCDC,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TCB,
- .end = AT91SAM9G45_ID_TCB,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TCB,
- .end = AT91SAM9G45_ID_TCB,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_ID_SYS,
- .end = AT91_ID_SYS,
+ .start = NR_IRQS_LEGACY + AT91_ID_SYS,
+ .end = NR_IRQS_LEGACY + AT91_ID_SYS,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TSC,
- .end = AT91SAM9G45_ID_TSC,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
.flags = IORESOURCE_IRQ,
}
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_TSC,
- .end = AT91SAM9G45_ID_TSC,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
.flags = IORESOURCE_IRQ,
}
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_PWMC,
- .end = AT91SAM9G45_ID_PWMC,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_SSC0,
- .end = AT91SAM9G45_ID_SSC0,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_SSC1,
- .end = AT91SAM9G45_ID_SSC1,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_ID_SYS,
- .end = AT91_ID_SYS,
+ .start = NR_IRQS_LEGACY + AT91_ID_SYS,
+ .end = NR_IRQS_LEGACY + AT91_ID_SYS,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_US0,
- .end = AT91SAM9G45_ID_US0,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_US1,
- .end = AT91SAM9G45_ID_US1,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_US2,
- .end = AT91SAM9G45_ID_US2,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
.flags = IORESOURCE_IRQ,
},
};
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91SAM9G45_ID_US3,
- .end = AT91SAM9G45_ID_US3,
+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
.flags = IORESOURCE_IRQ,
},
};
void __init at91_add_device_serial(void) {}
#endif
+ /* --------------------------------------------------------------------
+ * SHA1/SHA256
+ * -------------------------------------------------------------------- */
+
+ #if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
+ static struct resource sha_resources[] = {
+ {
+ .start = AT91SAM9G45_BASE_SHA,
+ .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9G45_ID_AESTDESSHA,
+ .end = AT91SAM9G45_ID_AESTDESSHA,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ static struct platform_device at91sam9g45_sha_device = {
+ .name = "atmel_sha",
+ .id = -1,
+ .resource = sha_resources,
+ .num_resources = ARRAY_SIZE(sha_resources),
+ };
+
+ static void __init at91_add_device_sha(void)
+ {
+ platform_device_register(&at91sam9g45_sha_device);
+ }
+ #else
+ static void __init at91_add_device_sha(void) {}
+ #endif
+
+ /* --------------------------------------------------------------------
+ * DES/TDES
+ * -------------------------------------------------------------------- */
+
+ #if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
+ static struct resource tdes_resources[] = {
+ [0] = {
+ .start = AT91SAM9G45_BASE_TDES,
+ .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9G45_ID_AESTDESSHA,
+ .end = AT91SAM9G45_ID_AESTDESSHA,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ static struct platform_device at91sam9g45_tdes_device = {
+ .name = "atmel_tdes",
+ .id = -1,
+ .resource = tdes_resources,
+ .num_resources = ARRAY_SIZE(tdes_resources),
+ };
+
+ static void __init at91_add_device_tdes(void)
+ {
+ platform_device_register(&at91sam9g45_tdes_device);
+ }
+ #else
+ static void __init at91_add_device_tdes(void) {}
+ #endif
+
+ /* --------------------------------------------------------------------
+ * AES
+ * -------------------------------------------------------------------- */
+
+ #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
+ static struct aes_platform_data aes_data;
+ static u64 aes_dmamask = DMA_BIT_MASK(32);
+
+ static struct resource aes_resources[] = {
+ [0] = {
+ .start = AT91SAM9G45_BASE_AES,
+ .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AT91SAM9G45_ID_AESTDESSHA,
+ .end = AT91SAM9G45_ID_AESTDESSHA,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ static struct platform_device at91sam9g45_aes_device = {
+ .name = "atmel_aes",
+ .id = -1,
+ .dev = {
+ .dma_mask = &aes_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &aes_data,
+ },
+ .resource = aes_resources,
+ .num_resources = ARRAY_SIZE(aes_resources),
+ };
+
+ static void __init at91_add_device_aes(void)
+ {
+ struct at_dma_slave *atslave;
+ struct aes_dma_data *alt_atslave;
+
+ alt_atslave = kzalloc(sizeof(struct aes_dma_data), GFP_KERNEL);
+
+ /* DMA TX slave channel configuration */
+ atslave = &alt_atslave->txdata;
+ atslave->dma_dev = &at_hdmac_device.dev;
+ atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
+ ATC_SRC_PER(AT_DMA_ID_AES_RX);
+
+ /* DMA RX slave channel configuration */
+ atslave = &alt_atslave->rxdata;
+ atslave->dma_dev = &at_hdmac_device.dev;
+ atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
+ ATC_DST_PER(AT_DMA_ID_AES_TX);
+
+ aes_data.dma_slave = alt_atslave;
+ platform_device_register(&at91sam9g45_aes_device);
+ }
+ #else
+ static void __init at91_add_device_aes(void) {}
+ #endif
/* -------------------------------------------------------------------- */
/*
at91_add_device_trng();
at91_add_device_watchdog();
at91_add_device_tc();
+ at91_add_device_sha();
+ at91_add_device_tdes();
+ at91_add_device_aes();
return 0;
}
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