]> Pileus Git - ~andy/linux/commitdiff
MIPS: /proc/cpuinfo: always print the supported ISA
authorAaro Koskinen <aaro.koskinen@iki.fi>
Mon, 30 Dec 2013 23:26:31 +0000 (01:26 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Jan 2014 21:39:46 +0000 (22:39 +0100)
Currently the supported ISA is only printed on the latest architectures.
Print it also on legacy platforms.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6295/

arch/mips/kernel/proc.c

index db49bfafa329bc4b74cb855695b2931b89b298de..00d20974b3e7b2bde15969c78402dbea65793edc 100644 (file)
@@ -65,26 +65,25 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                                cpu_data[n].watch_reg_masks[i]);
                seq_printf(m, "]\n");
        }
-       if (cpu_has_mips_r) {
-               seq_printf(m, "isa\t\t\t: mips1");
-               if (cpu_has_mips_2)
-                       seq_printf(m, "%s", " mips2");
-               if (cpu_has_mips_3)
-                       seq_printf(m, "%s", " mips3");
-               if (cpu_has_mips_4)
-                       seq_printf(m, "%s", " mips4");
-               if (cpu_has_mips_5)
-                       seq_printf(m, "%s", " mips5");
-               if (cpu_has_mips32r1)
-                       seq_printf(m, "%s", " mips32r1");
-               if (cpu_has_mips32r2)
-                       seq_printf(m, "%s", " mips32r2");
-               if (cpu_has_mips64r1)
-                       seq_printf(m, "%s", " mips64r1");
-               if (cpu_has_mips64r2)
-                       seq_printf(m, "%s", " mips64r2");
-               seq_printf(m, "\n");
-       }
+
+       seq_printf(m, "isa\t\t\t: mips1");
+       if (cpu_has_mips_2)
+               seq_printf(m, "%s", " mips2");
+       if (cpu_has_mips_3)
+               seq_printf(m, "%s", " mips3");
+       if (cpu_has_mips_4)
+               seq_printf(m, "%s", " mips4");
+       if (cpu_has_mips_5)
+               seq_printf(m, "%s", " mips5");
+       if (cpu_has_mips32r1)
+               seq_printf(m, "%s", " mips32r1");
+       if (cpu_has_mips32r2)
+               seq_printf(m, "%s", " mips32r2");
+       if (cpu_has_mips64r1)
+               seq_printf(m, "%s", " mips64r1");
+       if (cpu_has_mips64r2)
+               seq_printf(m, "%s", " mips64r2");
+       seq_printf(m, "\n");
 
        seq_printf(m, "ASEs implemented\t:");
        if (cpu_has_mips16)     seq_printf(m, "%s", " mips16");