ARM: mcpm: use -st dsb option prior to sev instructions

In a similar manner to our spinlock implementation, mcpm uses sev to
wake up cores waiting on a lock when the lock is unlocked. In order to
ensure that the final write unlocking the lock is visible, a dsb
instruction is executed immediately prior to the sev.

This patch changes these dsbs to use the -st option, since we only
require that the store unlocking the lock is made visible.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
index 80f033614a1fa07d90de18de6673ce45ec0bf91b..39c96df3477a41549d71e1a18733dd85f4a168df 100644 (file)
--- a/arch/arm/common/mcpm_head.S
+++ b/arch/arm/common/mcpm_head.S
@@ -151,7 +151,7 @@ mcpm_setup_leave:
 
        mov     r0, #INBOUND_NOT_COMING_UP
        strb    r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
-       dsb
+       dsb     st
        sev
 
        mov     r0, r11

diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S
index ff198583f683930951e93a4503ed651e76c7d939..8b7df283fedf8e16361f9834349e5f2934fba92e 100644 (file)
--- a/arch/arm/common/vlock.S
+++ b/arch/arm/common/vlock.S
@@ -42,7 +42,7 @@
        dmb
        mov     \rscratch, #0
        strb    \rscratch, [\rbase, \rcpu]
-       dsb
+       dsb     st
        sev
 .endm
 
@@ -102,7 +102,7 @@ ENTRY(vlock_unlock)
        dmb
        mov     r1, #VLOCK_OWNER_NONE
        strb    r1, [r0, #VLOCK_OWNER_OFFSET]
-       dsb
+       dsb     st
        sev
        bx      lr
 ENDPROC(vlock_unlock)