Pileus Git - ~andy/linux/blob - sound/pci/hda/patch_ca0132.c

   1 /*
   2  * HD audio interface patch for Creative CA0132 chip
   3  *
   4  * Copyright (c) 2011, Creative Technology Ltd.
   5  *
   6  * Based on patch_ca0110.c
   7  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   8  *
   9  *  This driver is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License as published by
  11  *  the Free Software Foundation; either version 2 of the License, or
  12  *  (at your option) any later version.
  13  *
  14  *  This driver is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/pci.h>
  28 #include <linux/mutex.h>
  29 #include <linux/module.h>
  30 #include <linux/firmware.h>
  31 #include <sound/core.h>
  32 #include "hda_codec.h"
  33 #include "hda_local.h"
  34 #include "hda_auto_parser.h"
  35 #include "hda_jack.h"
  36
  37 #include "ca0132_regs.h"
  38
  39 /* Enable this to see controls for tuning purpose. */
  40 /*#define ENABLE_TUNING_CONTROLS*/
  41
  42 #define FLOAT_ZERO      0x00000000
  43 #define FLOAT_ONE       0x3f800000
  44 #define FLOAT_TWO       0x40000000
  45 #define FLOAT_MINUS_5   0xc0a00000
  46
  47 #define UNSOL_TAG_HP    0x10
  48 #define UNSOL_TAG_AMIC1 0x12
  49 #define UNSOL_TAG_DSP   0x16
  50
  51 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  52 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  53
  54 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  55 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  56 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  57
  58 #define MASTERCONTROL                           0x80
  59 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  60 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  61
  62 #define WIDGET_CHIP_CTRL      0x15
  63 #define WIDGET_DSP_CTRL       0x16
  64
  65 #define MEM_CONNID_MICIN1     3
  66 #define MEM_CONNID_MICIN2     5
  67 #define MEM_CONNID_MICOUT1    12
  68 #define MEM_CONNID_MICOUT2    14
  69 #define MEM_CONNID_WUH        10
  70 #define MEM_CONNID_DSP        16
  71 #define MEM_CONNID_DMIC       100
  72
  73 #define SCP_SET    0
  74 #define SCP_GET    1
  75
  76 #define EFX_FILE   "ctefx.bin"
  77
  78 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  79 MODULE_FIRMWARE(EFX_FILE);
  80 #endif
  81
  82 static char *dirstr[2] = { "Playback", "Capture" };
  83
  84 enum {
  85         SPEAKER_OUT,
  86         HEADPHONE_OUT
  87 };
  88
  89 enum {
  90         DIGITAL_MIC,
  91         LINE_MIC_IN
  92 };
  93
  94 enum {
  95 #define VNODE_START_NID    0x80
  96         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
  97         VNID_MIC,
  98         VNID_HP_SEL,
  99         VNID_AMIC1_SEL,
 100         VNID_HP_ASEL,
 101         VNID_AMIC1_ASEL,
 102         VNODE_END_NID,
 103 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 104
 105 #define EFFECT_START_NID    0x90
 106 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 107         SURROUND = OUT_EFFECT_START_NID,
 108         CRYSTALIZER,
 109         DIALOG_PLUS,
 110         SMART_VOLUME,
 111         X_BASS,
 112         EQUALIZER,
 113         OUT_EFFECT_END_NID,
 114 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 115
 116 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 117         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 118         VOICE_FOCUS,
 119         MIC_SVM,
 120         NOISE_REDUCTION,
 121         IN_EFFECT_END_NID,
 122 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 123
 124         VOICEFX = IN_EFFECT_END_NID,
 125         PLAY_ENHANCEMENT,
 126         CRYSTAL_VOICE,
 127         EFFECT_END_NID
 128 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 129 };
 130
 131 /* Effects values size*/
 132 #define EFFECT_VALS_MAX_COUNT 12
 133
 134 /* Latency introduced by DSP blocks in milliseconds. */
 135 #define DSP_CAPTURE_INIT_LATENCY        0
 136 #define DSP_CRYSTAL_VOICE_LATENCY       124
 137 #define DSP_PLAYBACK_INIT_LATENCY       13
 138 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 139 #define DSP_SPEAKER_OUT_LATENCY         7
 140
 141 struct ct_effect {
 142         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 143         hda_nid_t nid;
 144         int mid; /*effect module ID*/
 145         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 146         int direct; /* 0:output; 1:input*/
 147         int params; /* number of default non-on/off params */
 148         /*effect default values, 1st is on/off. */
 149         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 150 };
 151
 152 #define EFX_DIR_OUT 0
 153 #define EFX_DIR_IN  1
 154
 155 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 156         { .name = "Surround",
 157           .nid = SURROUND,
 158           .mid = 0x96,
 159           .reqs = {0, 1},
 160           .direct = EFX_DIR_OUT,
 161           .params = 1,
 162           .def_vals = {0x3F800000, 0x3F2B851F}
 163         },
 164         { .name = "Crystalizer",
 165           .nid = CRYSTALIZER,
 166           .mid = 0x96,
 167           .reqs = {7, 8},
 168           .direct = EFX_DIR_OUT,
 169           .params = 1,
 170           .def_vals = {0x3F800000, 0x3F266666}
 171         },
 172         { .name = "Dialog Plus",
 173           .nid = DIALOG_PLUS,
 174           .mid = 0x96,
 175           .reqs = {2, 3},
 176           .direct = EFX_DIR_OUT,
 177           .params = 1,
 178           .def_vals = {0x00000000, 0x3F000000}
 179         },
 180         { .name = "Smart Volume",
 181           .nid = SMART_VOLUME,
 182           .mid = 0x96,
 183           .reqs = {4, 5, 6},
 184           .direct = EFX_DIR_OUT,
 185           .params = 2,
 186           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 187         },
 188         { .name = "X-Bass",
 189           .nid = X_BASS,
 190           .mid = 0x96,
 191           .reqs = {24, 23, 25},
 192           .direct = EFX_DIR_OUT,
 193           .params = 2,
 194           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 195         },
 196         { .name = "Equalizer",
 197           .nid = EQUALIZER,
 198           .mid = 0x96,
 199           .reqs = {9, 10, 11, 12, 13, 14,
 200                         15, 16, 17, 18, 19, 20},
 201           .direct = EFX_DIR_OUT,
 202           .params = 11,
 203           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 204                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 205                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 206         },
 207         { .name = "Echo Cancellation",
 208           .nid = ECHO_CANCELLATION,
 209           .mid = 0x95,
 210           .reqs = {0, 1, 2, 3},
 211           .direct = EFX_DIR_IN,
 212           .params = 3,
 213           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 214         },
 215         { .name = "Voice Focus",
 216           .nid = VOICE_FOCUS,
 217           .mid = 0x95,
 218           .reqs = {6, 7, 8, 9},
 219           .direct = EFX_DIR_IN,
 220           .params = 3,
 221           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 222         },
 223         { .name = "Mic SVM",
 224           .nid = MIC_SVM,
 225           .mid = 0x95,
 226           .reqs = {44, 45},
 227           .direct = EFX_DIR_IN,
 228           .params = 1,
 229           .def_vals = {0x00000000, 0x3F3D70A4}
 230         },
 231         { .name = "Noise Reduction",
 232           .nid = NOISE_REDUCTION,
 233           .mid = 0x95,
 234           .reqs = {4, 5},
 235           .direct = EFX_DIR_IN,
 236           .params = 1,
 237           .def_vals = {0x3F800000, 0x3F000000}
 238         },
 239         { .name = "VoiceFX",
 240           .nid = VOICEFX,
 241           .mid = 0x95,
 242           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 243           .direct = EFX_DIR_IN,
 244           .params = 8,
 245           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 246                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 247                        0x00000000}
 248         }
 249 };
 250
 251 /* Tuning controls */
 252 #ifdef ENABLE_TUNING_CONTROLS
 253
 254 enum {
 255 #define TUNING_CTL_START_NID  0xC0
 256         WEDGE_ANGLE = TUNING_CTL_START_NID,
 257         SVM_LEVEL,
 258         EQUALIZER_BAND_0,
 259         EQUALIZER_BAND_1,
 260         EQUALIZER_BAND_2,
 261         EQUALIZER_BAND_3,
 262         EQUALIZER_BAND_4,
 263         EQUALIZER_BAND_5,
 264         EQUALIZER_BAND_6,
 265         EQUALIZER_BAND_7,
 266         EQUALIZER_BAND_8,
 267         EQUALIZER_BAND_9,
 268         TUNING_CTL_END_NID
 269 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 270 };
 271
 272 struct ct_tuning_ctl {
 273         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 274         hda_nid_t parent_nid;
 275         hda_nid_t nid;
 276         int mid; /*effect module ID*/
 277         int req; /*effect module request*/
 278         int direct; /* 0:output; 1:input*/
 279         unsigned int def_val;/*effect default values*/
 280 };
 281
 282 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 283         { .name = "Wedge Angle",
 284           .parent_nid = VOICE_FOCUS,
 285           .nid = WEDGE_ANGLE,
 286           .mid = 0x95,
 287           .req = 8,
 288           .direct = EFX_DIR_IN,
 289           .def_val = 0x41F00000
 290         },
 291         { .name = "SVM Level",
 292           .parent_nid = MIC_SVM,
 293           .nid = SVM_LEVEL,
 294           .mid = 0x95,
 295           .req = 45,
 296           .direct = EFX_DIR_IN,
 297           .def_val = 0x3F3D70A4
 298         },
 299         { .name = "EQ Band0",
 300           .parent_nid = EQUALIZER,
 301           .nid = EQUALIZER_BAND_0,
 302           .mid = 0x96,
 303           .req = 11,
 304           .direct = EFX_DIR_OUT,
 305           .def_val = 0x00000000
 306         },
 307         { .name = "EQ Band1",
 308           .parent_nid = EQUALIZER,
 309           .nid = EQUALIZER_BAND_1,
 310           .mid = 0x96,
 311           .req = 12,
 312           .direct = EFX_DIR_OUT,
 313           .def_val = 0x00000000
 314         },
 315         { .name = "EQ Band2",
 316           .parent_nid = EQUALIZER,
 317           .nid = EQUALIZER_BAND_2,
 318           .mid = 0x96,
 319           .req = 13,
 320           .direct = EFX_DIR_OUT,
 321           .def_val = 0x00000000
 322         },
 323         { .name = "EQ Band3",
 324           .parent_nid = EQUALIZER,
 325           .nid = EQUALIZER_BAND_3,
 326           .mid = 0x96,
 327           .req = 14,
 328           .direct = EFX_DIR_OUT,
 329           .def_val = 0x00000000
 330         },
 331         { .name = "EQ Band4",
 332           .parent_nid = EQUALIZER,
 333           .nid = EQUALIZER_BAND_4,
 334           .mid = 0x96,
 335           .req = 15,
 336           .direct = EFX_DIR_OUT,
 337           .def_val = 0x00000000
 338         },
 339         { .name = "EQ Band5",
 340           .parent_nid = EQUALIZER,
 341           .nid = EQUALIZER_BAND_5,
 342           .mid = 0x96,
 343           .req = 16,
 344           .direct = EFX_DIR_OUT,
 345           .def_val = 0x00000000
 346         },
 347         { .name = "EQ Band6",
 348           .parent_nid = EQUALIZER,
 349           .nid = EQUALIZER_BAND_6,
 350           .mid = 0x96,
 351           .req = 17,
 352           .direct = EFX_DIR_OUT,
 353           .def_val = 0x00000000
 354         },
 355         { .name = "EQ Band7",
 356           .parent_nid = EQUALIZER,
 357           .nid = EQUALIZER_BAND_7,
 358           .mid = 0x96,
 359           .req = 18,
 360           .direct = EFX_DIR_OUT,
 361           .def_val = 0x00000000
 362         },
 363         { .name = "EQ Band8",
 364           .parent_nid = EQUALIZER,
 365           .nid = EQUALIZER_BAND_8,
 366           .mid = 0x96,
 367           .req = 19,
 368           .direct = EFX_DIR_OUT,
 369           .def_val = 0x00000000
 370         },
 371         { .name = "EQ Band9",
 372           .parent_nid = EQUALIZER,
 373           .nid = EQUALIZER_BAND_9,
 374           .mid = 0x96,
 375           .req = 20,
 376           .direct = EFX_DIR_OUT,
 377           .def_val = 0x00000000
 378         }
 379 };
 380 #endif
 381
 382 /* Voice FX Presets */
 383 #define VOICEFX_MAX_PARAM_COUNT 9
 384
 385 struct ct_voicefx {
 386         char *name;
 387         hda_nid_t nid;
 388         int mid;
 389         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 390 };
 391
 392 struct ct_voicefx_preset {
 393         char *name; /*preset name*/
 394         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 395 };
 396
 397 static struct ct_voicefx ca0132_voicefx = {
 398         .name = "VoiceFX Capture Switch",
 399         .nid = VOICEFX,
 400         .mid = 0x95,
 401         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 402 };
 403
 404 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 405         { .name = "Neutral",
 406           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 407                     0x44FA0000, 0x3F800000, 0x3F800000,
 408                     0x3F800000, 0x00000000, 0x00000000 }
 409         },
 410         { .name = "Female2Male",
 411           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 412                     0x44FA0000, 0x3F19999A, 0x3F866666,
 413                     0x3F800000, 0x00000000, 0x00000000 }
 414         },
 415         { .name = "Male2Female",
 416           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 417                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 418                     0x3F800000, 0x00000000, 0x00000000 }
 419         },
 420         { .name = "ScrappyKid",
 421           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 422                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 423                     0x3F800000, 0x00000000, 0x00000000 }
 424         },
 425         { .name = "Elderly",
 426           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 427                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 428                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 429         },
 430         { .name = "Orc",
 431           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 432                     0x45098000, 0x3F266666, 0x3FC00000,
 433                     0x3F800000, 0x00000000, 0x00000000 }
 434         },
 435         { .name = "Elf",
 436           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 437                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 438                     0x3F800000, 0x00000000, 0x00000000 }
 439         },
 440         { .name = "Dwarf",
 441           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 442                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 443                     0x3F800000, 0x00000000, 0x00000000 }
 444         },
 445         { .name = "AlienBrute",
 446           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 447                     0x451F6000, 0x3F266666, 0x3FA7D945,
 448                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 449         },
 450         { .name = "Robot",
 451           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 452                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 453                     0xBC07010E, 0x00000000, 0x00000000 }
 454         },
 455         { .name = "Marine",
 456           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 457                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 458                     0x3F0A3D71, 0x00000000, 0x00000000 }
 459         },
 460         { .name = "Emo",
 461           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 462                     0x44FA0000, 0x3F800000, 0x3F800000,
 463                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 464         },
 465         { .name = "DeepVoice",
 466           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 467                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 468                     0x3F800000, 0x00000000, 0x00000000 }
 469         },
 470         { .name = "Munchkin",
 471           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 472                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 473                     0x3F800000, 0x00000000, 0x00000000 }
 474         }
 475 };
 476
 477 enum hda_cmd_vendor_io {
 478         /* for DspIO node */
 479         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 480         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 481
 482         VENDOR_DSPIO_STATUS                  = 0xF01,
 483         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 484         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 485         VENDOR_DSPIO_DSP_INIT                = 0x703,
 486         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 487         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 488
 489         /* for ChipIO node */
 490         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 491         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 492         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 493         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 494         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 495
 496         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 497         VENDOR_CHIPIO_STATUS                 = 0xF01,
 498         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 499         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 500
 501         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 502         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 503
 504         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 505         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 506
 507         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 508         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 509         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 510         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 511         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 512         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 513         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 514         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 515
 516         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 517         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 518         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 519         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 520
 521         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 522         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 523         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 524         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 525
 526         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 527         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 528         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 529         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 530         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 531         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 532
 533         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 534 };
 535
 536 /*
 537  *  Control flag IDs
 538  */
 539 enum control_flag_id {
 540         /* Connection manager stream setup is bypassed/enabled */
 541         CONTROL_FLAG_C_MGR                  = 0,
 542         /* DSP DMA is bypassed/enabled */
 543         CONTROL_FLAG_DMA                    = 1,
 544         /* 8051 'idle' mode is disabled/enabled */
 545         CONTROL_FLAG_IDLE_ENABLE            = 2,
 546         /* Tracker for the SPDIF-in path is bypassed/enabled */
 547         CONTROL_FLAG_TRACKER                = 3,
 548         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 549         CONTROL_FLAG_SPDIF2OUT              = 4,
 550         /* Digital Microphone is disabled/enabled */
 551         CONTROL_FLAG_DMIC                   = 5,
 552         /* ADC_B rate is 48 kHz/96 kHz */
 553         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 554         /* ADC_C rate is 48 kHz/96 kHz */
 555         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 556         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 557         CONTROL_FLAG_DAC_96KHZ              = 8,
 558         /* DSP rate is 48 kHz/96 kHz */
 559         CONTROL_FLAG_DSP_96KHZ              = 9,
 560         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 561         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 562         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 563         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 564         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 565         CONTROL_FLAG_DECODE_LOOP            = 12,
 566         /* De-emphasis filter on DAC-1 disabled/enabled */
 567         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 568         /* De-emphasis filter on DAC-2 disabled/enabled */
 569         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 570         /* De-emphasis filter on DAC-3 disabled/enabled */
 571         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 572         /* High-pass filter on ADC_B disabled/enabled */
 573         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 574         /* High-pass filter on ADC_C disabled/enabled */
 575         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 576         /* Common mode on Port_A disabled/enabled */
 577         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 578         /* Common mode on Port_D disabled/enabled */
 579         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 580         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 581         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 582         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 583         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 584         /* ASI rate is 48kHz/96kHz */
 585         CONTROL_FLAG_ASI_96KHZ              = 22,
 586         /* DAC power settings able to control attached ports no/yes */
 587         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 588         /* Clock Stop OK reporting is disabled/enabled */
 589         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 590         /* Number of control flags */
 591         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 592 };
 593
 594 /*
 595  * Control parameter IDs
 596  */
 597 enum control_param_id {
 598         /* 0: None, 1: Mic1In*/
 599         CONTROL_PARAM_VIP_SOURCE               = 1,
 600         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 601         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 602         /* Port A output stage gain setting to use when 16 Ohm output
 603          * impedance is selected*/
 604         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 605         /* Port D output stage gain setting to use when 16 Ohm output
 606          * impedance is selected*/
 607         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 608
 609         /* Stream Control */
 610
 611         /* Select stream with the given ID */
 612         CONTROL_PARAM_STREAM_ID                = 24,
 613         /* Source connection point for the selected stream */
 614         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 615         /* Destination connection point for the selected stream */
 616         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 617         /* Number of audio channels in the selected stream */
 618         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 619         /*Enable control for the selected stream */
 620         CONTROL_PARAM_STREAM_CONTROL           = 28,
 621
 622         /* Connection Point Control */
 623
 624         /* Select connection point with the given ID */
 625         CONTROL_PARAM_CONN_POINT_ID            = 29,
 626         /* Connection point sample rate */
 627         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 628
 629         /* Node Control */
 630
 631         /* Select HDA node with the given ID */
 632         CONTROL_PARAM_NODE_ID                  = 31
 633 };
 634
 635 /*
 636  *  Dsp Io Status codes
 637  */
 638 enum hda_vendor_status_dspio {
 639         /* Success */
 640         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 641         /* Busy, unable to accept new command, the host must retry */
 642         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
 643         /* SCP command queue is full */
 644         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
 645         /* SCP response queue is empty */
 646         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
 647 };
 648
 649 /*
 650  *  Chip Io Status codes
 651  */
 652 enum hda_vendor_status_chipio {
 653         /* Success */
 654         VENDOR_STATUS_CHIPIO_OK   = 0x00,
 655         /* Busy, unable to accept new command, the host must retry */
 656         VENDOR_STATUS_CHIPIO_BUSY = 0x01
 657 };
 658
 659 /*
 660  *  CA0132 sample rate
 661  */
 662 enum ca0132_sample_rate {
 663         SR_6_000        = 0x00,
 664         SR_8_000        = 0x01,
 665         SR_9_600        = 0x02,
 666         SR_11_025       = 0x03,
 667         SR_16_000       = 0x04,
 668         SR_22_050       = 0x05,
 669         SR_24_000       = 0x06,
 670         SR_32_000       = 0x07,
 671         SR_44_100       = 0x08,
 672         SR_48_000       = 0x09,
 673         SR_88_200       = 0x0A,
 674         SR_96_000       = 0x0B,
 675         SR_144_000      = 0x0C,
 676         SR_176_400      = 0x0D,
 677         SR_192_000      = 0x0E,
 678         SR_384_000      = 0x0F,
 679
 680         SR_COUNT        = 0x10,
 681
 682         SR_RATE_UNKNOWN = 0x1F
 683 };
 684
 685 enum dsp_download_state {
 686         DSP_DOWNLOAD_FAILED = -1,
 687         DSP_DOWNLOAD_INIT   = 0,
 688         DSP_DOWNLOADING     = 1,
 689         DSP_DOWNLOADED      = 2
 690 };
 691
 692 /* retrieve parameters from hda format */
 693 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
 694 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
 695 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
 696 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
 697
 698 /*
 699  * CA0132 specific
 700  */
 701
 702 struct ca0132_spec {
 703         struct snd_kcontrol_new *mixers[5];
 704         unsigned int num_mixers;
 705         const struct hda_verb *base_init_verbs;
 706         const struct hda_verb *base_exit_verbs;
 707         const struct hda_verb *init_verbs[5];
 708         unsigned int num_init_verbs;  /* exclude base init verbs */
 709         struct auto_pin_cfg autocfg;
 710
 711         /* Nodes configurations */
 712         struct hda_multi_out multiout;
 713         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
 714         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
 715         unsigned int num_outputs;
 716         hda_nid_t input_pins[AUTO_PIN_LAST];
 717         hda_nid_t adcs[AUTO_PIN_LAST];
 718         hda_nid_t dig_out;
 719         hda_nid_t dig_in;
 720         unsigned int num_inputs;
 721         hda_nid_t shared_mic_nid;
 722         hda_nid_t shared_out_nid;
 723         struct hda_pcm pcm_rec[5]; /* PCM information */
 724
 725         /* chip access */
 726         struct mutex chipio_mutex; /* chip access mutex */
 727         u32 curr_chip_addx;
 728
 729         /* DSP download related */
 730         enum dsp_download_state dsp_state;
 731         unsigned int dsp_stream_id;
 732         unsigned int wait_scp;
 733         unsigned int wait_scp_header;
 734         unsigned int wait_num_data;
 735         unsigned int scp_resp_header;
 736         unsigned int scp_resp_data[4];
 737         unsigned int scp_resp_count;
 738
 739         /* mixer and effects related */
 740         unsigned char dmic_ctl;
 741         int cur_out_type;
 742         int cur_mic_type;
 743         long vnode_lvol[VNODES_COUNT];
 744         long vnode_rvol[VNODES_COUNT];
 745         long vnode_lswitch[VNODES_COUNT];
 746         long vnode_rswitch[VNODES_COUNT];
 747         long effects_switch[EFFECTS_COUNT];
 748         long voicefx_val;
 749         long cur_mic_boost;
 750
 751         struct hda_codec *codec;
 752         struct delayed_work unsol_hp_work;
 753
 754 #ifdef ENABLE_TUNING_CONTROLS
 755         long cur_ctl_vals[TUNING_CTLS_COUNT];
 756 #endif
 757 };
 758
 759 /*
 760  * CA0132 codec access
 761  */
 762 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
 763                 unsigned int verb, unsigned int parm, unsigned int *res)
 764 {
 765         unsigned int response;
 766         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
 767         *res = response;
 768
 769         return ((response == -1) ? -1 : 0);
 770 }
 771
 772 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
 773                 unsigned short converter_format, unsigned int *res)
 774 {
 775         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
 776                                 converter_format & 0xffff, res);
 777 }
 778
 779 static int codec_set_converter_stream_channel(struct hda_codec *codec,
 780                                 hda_nid_t nid, unsigned char stream,
 781                                 unsigned char channel, unsigned int *res)
 782 {
 783         unsigned char converter_stream_channel = 0;
 784
 785         converter_stream_channel = (stream << 4) | (channel & 0x0f);
 786         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
 787                                 converter_stream_channel, res);
 788 }
 789
 790 /* Chip access helper function */
 791 static int chipio_send(struct hda_codec *codec,
 792                        unsigned int reg,
 793                        unsigned int data)
 794 {
 795         unsigned int res;
 796         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 797
 798         /* send bits of data specified by reg */
 799         do {
 800                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 801                                          reg, data);
 802                 if (res == VENDOR_STATUS_CHIPIO_OK)
 803                         return 0;
 804                 msleep(20);
 805         } while (time_before(jiffies, timeout));
 806
 807         return -EIO;
 808 }
 809
 810 /*
 811  * Write chip address through the vendor widget -- NOT protected by the Mutex!
 812  */
 813 static int chipio_write_address(struct hda_codec *codec,
 814                                 unsigned int chip_addx)
 815 {
 816         struct ca0132_spec *spec = codec->spec;
 817         int res;
 818
 819         if (spec->curr_chip_addx == chip_addx)
 820                         return 0;
 821
 822         /* send low 16 bits of the address */
 823         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
 824                           chip_addx & 0xffff);
 825
 826         if (res != -EIO) {
 827                 /* send high 16 bits of the address */
 828                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
 829                                   chip_addx >> 16);
 830         }
 831
 832         spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
 833
 834         return res;
 835 }
 836
 837 /*
 838  * Write data through the vendor widget -- NOT protected by the Mutex!
 839  */
 840 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
 841 {
 842         struct ca0132_spec *spec = codec->spec;
 843         int res;
 844
 845         /* send low 16 bits of the data */
 846         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
 847
 848         if (res != -EIO) {
 849                 /* send high 16 bits of the data */
 850                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
 851                                   data >> 16);
 852         }
 853
 854         /*If no error encountered, automatically increment the address
 855         as per chip behaviour*/
 856         spec->curr_chip_addx = (res != -EIO) ?
 857                                         (spec->curr_chip_addx + 4) : ~0UL;
 858         return res;
 859 }
 860
 861 /*
 862  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
 863  */
 864 static int chipio_write_data_multiple(struct hda_codec *codec,
 865                                       const u32 *data,
 866                                       unsigned int count)
 867 {
 868         int status = 0;
 869
 870         if (data == NULL) {
 871                 snd_printdd(KERN_ERR "chipio_write_data null ptr\n");
 872                 return -EINVAL;
 873         }
 874
 875         while ((count-- != 0) && (status == 0))
 876                 status = chipio_write_data(codec, *data++);
 877
 878         return status;
 879 }
 880
 881
 882 /*
 883  * Read data through the vendor widget -- NOT protected by the Mutex!
 884  */
 885 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
 886 {
 887         struct ca0132_spec *spec = codec->spec;
 888         int res;
 889
 890         /* post read */
 891         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
 892
 893         if (res != -EIO) {
 894                 /* read status */
 895                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
 896         }
 897
 898         if (res != -EIO) {
 899                 /* read data */
 900                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
 901                                            VENDOR_CHIPIO_HIC_READ_DATA,
 902                                            0);
 903         }
 904
 905         /*If no error encountered, automatically increment the address
 906         as per chip behaviour*/
 907         spec->curr_chip_addx = (res != -EIO) ?
 908                                         (spec->curr_chip_addx + 4) : ~0UL;
 909         return res;
 910 }
 911
 912 /*
 913  * Write given value to the given address through the chip I/O widget.
 914  * protected by the Mutex
 915  */
 916 static int chipio_write(struct hda_codec *codec,
 917                 unsigned int chip_addx, const unsigned int data)
 918 {
 919         struct ca0132_spec *spec = codec->spec;
 920         int err;
 921
 922         mutex_lock(&spec->chipio_mutex);
 923
 924         /* write the address, and if successful proceed to write data */
 925         err = chipio_write_address(codec, chip_addx);
 926         if (err < 0)
 927                 goto exit;
 928
 929         err = chipio_write_data(codec, data);
 930         if (err < 0)
 931                 goto exit;
 932
 933 exit:
 934         mutex_unlock(&spec->chipio_mutex);
 935         return err;
 936 }
 937
 938 /*
 939  * Write multiple values to the given address through the chip I/O widget.
 940  * protected by the Mutex
 941  */
 942 static int chipio_write_multiple(struct hda_codec *codec,
 943                                  u32 chip_addx,
 944                                  const u32 *data,
 945                                  unsigned int count)
 946 {
 947         struct ca0132_spec *spec = codec->spec;
 948         int status;
 949
 950         mutex_lock(&spec->chipio_mutex);
 951         status = chipio_write_address(codec, chip_addx);
 952         if (status < 0)
 953                 goto error;
 954
 955         status = chipio_write_data_multiple(codec, data, count);
 956 error:
 957         mutex_unlock(&spec->chipio_mutex);
 958
 959         return status;
 960 }
 961
 962 /*
 963  * Read the given address through the chip I/O widget
 964  * protected by the Mutex
 965  */
 966 static int chipio_read(struct hda_codec *codec,
 967                 unsigned int chip_addx, unsigned int *data)
 968 {
 969         struct ca0132_spec *spec = codec->spec;
 970         int err;
 971
 972         mutex_lock(&spec->chipio_mutex);
 973
 974         /* write the address, and if successful proceed to write data */
 975         err = chipio_write_address(codec, chip_addx);
 976         if (err < 0)
 977                 goto exit;
 978
 979         err = chipio_read_data(codec, data);
 980         if (err < 0)
 981                 goto exit;
 982
 983 exit:
 984         mutex_unlock(&spec->chipio_mutex);
 985         return err;
 986 }
 987
 988 /*
 989  * Set chip control flags through the chip I/O widget.
 990  */
 991 static void chipio_set_control_flag(struct hda_codec *codec,
 992                                     enum control_flag_id flag_id,
 993                                     bool flag_state)
 994 {
 995         unsigned int val;
 996         unsigned int flag_bit;
 997
 998         flag_bit = (flag_state ? 1 : 0);
 999         val = (flag_bit << 7) | (flag_id);
1000         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1001                             VENDOR_CHIPIO_FLAG_SET, val);
1002 }
1003
1004 /*
1005  * Set chip parameters through the chip I/O widget.
1006  */
1007 static void chipio_set_control_param(struct hda_codec *codec,
1008                 enum control_param_id param_id, int param_val)
1009 {
1010         struct ca0132_spec *spec = codec->spec;
1011         int val;
1012
1013         if ((param_id < 32) && (param_val < 8)) {
1014                 val = (param_val << 5) | (param_id);
1015                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1016                                     VENDOR_CHIPIO_PARAM_SET, val);
1017         } else {
1018                 mutex_lock(&spec->chipio_mutex);
1019                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1020                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1021                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1022                                             param_id);
1023                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1024                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1025                                             param_val);
1026                 }
1027                 mutex_unlock(&spec->chipio_mutex);
1028         }
1029 }
1030
1031 /*
1032  * Set sampling rate of the connection point.
1033  */
1034 static void chipio_set_conn_rate(struct hda_codec *codec,
1035                                 int connid, enum ca0132_sample_rate rate)
1036 {
1037         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1038         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1039                                  rate);
1040 }
1041
1042 /*
1043  * Enable clocks.
1044  */
1045 static void chipio_enable_clocks(struct hda_codec *codec)
1046 {
1047         struct ca0132_spec *spec = codec->spec;
1048
1049         mutex_lock(&spec->chipio_mutex);
1050         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1051                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1052         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1054         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1055                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1056         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1057                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1058         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1059                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1060         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1061                             VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1062         mutex_unlock(&spec->chipio_mutex);
1063 }
1064
1065 /*
1066  * CA0132 DSP IO stuffs
1067  */
1068 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1069                       unsigned int data)
1070 {
1071         int res;
1072         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1073
1074         /* send bits of data specified by reg to dsp */
1075         do {
1076                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1077                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1078                         return res;
1079                 msleep(20);
1080         } while (time_before(jiffies, timeout));
1081
1082         return -EIO;
1083 }
1084
1085 /*
1086  * Wait for DSP to be ready for commands
1087  */
1088 static void dspio_write_wait(struct hda_codec *codec)
1089 {
1090         int status;
1091         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1092
1093         do {
1094                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1095                                                 VENDOR_DSPIO_STATUS, 0);
1096                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1097                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1098                         break;
1099                 msleep(1);
1100         } while (time_before(jiffies, timeout));
1101 }
1102
1103 /*
1104  * Write SCP data to DSP
1105  */
1106 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1107 {
1108         struct ca0132_spec *spec = codec->spec;
1109         int status;
1110
1111         dspio_write_wait(codec);
1112
1113         mutex_lock(&spec->chipio_mutex);
1114         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1115                             scp_data & 0xffff);
1116         if (status < 0)
1117                 goto error;
1118
1119         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1120                                     scp_data >> 16);
1121         if (status < 0)
1122                 goto error;
1123
1124         /* OK, now check if the write itself has executed*/
1125         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1126                                     VENDOR_DSPIO_STATUS, 0);
1127 error:
1128         mutex_unlock(&spec->chipio_mutex);
1129
1130         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1131                         -EIO : 0;
1132 }
1133
1134 /*
1135  * Write multiple SCP data to DSP
1136  */
1137 static int dspio_write_multiple(struct hda_codec *codec,
1138                                 unsigned int *buffer, unsigned int size)
1139 {
1140         int status = 0;
1141         unsigned int count;
1142
1143         if ((buffer == NULL))
1144                 return -EINVAL;
1145
1146         count = 0;
1147         while (count < size) {
1148                 status = dspio_write(codec, *buffer++);
1149                 if (status != 0)
1150                         break;
1151                 count++;
1152         }
1153
1154         return status;
1155 }
1156
1157 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1158 {
1159         int status;
1160
1161         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1162         if (status == -EIO)
1163                 return status;
1164
1165         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1166         if (status == -EIO ||
1167             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1168                 return -EIO;
1169
1170         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1171                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
1172
1173         return 0;
1174 }
1175
1176 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1177                                unsigned int *buf_size, unsigned int size_count)
1178 {
1179         int status = 0;
1180         unsigned int size = *buf_size;
1181         unsigned int count;
1182         unsigned int skip_count;
1183         unsigned int dummy;
1184
1185         if ((buffer == NULL))
1186                 return -1;
1187
1188         count = 0;
1189         while (count < size && count < size_count) {
1190                 status = dspio_read(codec, buffer++);
1191                 if (status != 0)
1192                         break;
1193                 count++;
1194         }
1195
1196         skip_count = count;
1197         if (status == 0) {
1198                 while (skip_count < size) {
1199                         status = dspio_read(codec, &dummy);
1200                         if (status != 0)
1201                                 break;
1202                         skip_count++;
1203                 }
1204         }
1205         *buf_size = count;
1206
1207         return status;
1208 }
1209
1210 /*
1211  * Construct the SCP header using corresponding fields
1212  */
1213 static inline unsigned int
1214 make_scp_header(unsigned int target_id, unsigned int source_id,
1215                 unsigned int get_flag, unsigned int req,
1216                 unsigned int device_flag, unsigned int resp_flag,
1217                 unsigned int error_flag, unsigned int data_size)
1218 {
1219         unsigned int header = 0;
1220
1221         header = (data_size & 0x1f) << 27;
1222         header |= (error_flag & 0x01) << 26;
1223         header |= (resp_flag & 0x01) << 25;
1224         header |= (device_flag & 0x01) << 24;
1225         header |= (req & 0x7f) << 17;
1226         header |= (get_flag & 0x01) << 16;
1227         header |= (source_id & 0xff) << 8;
1228         header |= target_id & 0xff;
1229
1230         return header;
1231 }
1232
1233 /*
1234  * Extract corresponding fields from SCP header
1235  */
1236 static inline void
1237 extract_scp_header(unsigned int header,
1238                    unsigned int *target_id, unsigned int *source_id,
1239                    unsigned int *get_flag, unsigned int *req,
1240                    unsigned int *device_flag, unsigned int *resp_flag,
1241                    unsigned int *error_flag, unsigned int *data_size)
1242 {
1243         if (data_size)
1244                 *data_size = (header >> 27) & 0x1f;
1245         if (error_flag)
1246                 *error_flag = (header >> 26) & 0x01;
1247         if (resp_flag)
1248                 *resp_flag = (header >> 25) & 0x01;
1249         if (device_flag)
1250                 *device_flag = (header >> 24) & 0x01;
1251         if (req)
1252                 *req = (header >> 17) & 0x7f;
1253         if (get_flag)
1254                 *get_flag = (header >> 16) & 0x01;
1255         if (source_id)
1256                 *source_id = (header >> 8) & 0xff;
1257         if (target_id)
1258                 *target_id = header & 0xff;
1259 }
1260
1261 #define SCP_MAX_DATA_WORDS  (16)
1262
1263 /* Structure to contain any SCP message */
1264 struct scp_msg {
1265         unsigned int hdr;
1266         unsigned int data[SCP_MAX_DATA_WORDS];
1267 };
1268
1269 static void dspio_clear_response_queue(struct hda_codec *codec)
1270 {
1271         unsigned int dummy = 0;
1272         int status = -1;
1273
1274         /* clear all from the response queue */
1275         do {
1276                 status = dspio_read(codec, &dummy);
1277         } while (status == 0);
1278 }
1279
1280 static int dspio_get_response_data(struct hda_codec *codec)
1281 {
1282         struct ca0132_spec *spec = codec->spec;
1283         unsigned int data = 0;
1284         unsigned int count;
1285
1286         if (dspio_read(codec, &data) < 0)
1287                 return -EIO;
1288
1289         if ((data & 0x00ffffff) == spec->wait_scp_header) {
1290                 spec->scp_resp_header = data;
1291                 spec->scp_resp_count = data >> 27;
1292                 count = spec->wait_num_data;
1293                 dspio_read_multiple(codec, spec->scp_resp_data,
1294                                     &spec->scp_resp_count, count);
1295                 return 0;
1296         }
1297
1298         return -EIO;
1299 }
1300
1301 /*
1302  * Send SCP message to DSP
1303  */
1304 static int dspio_send_scp_message(struct hda_codec *codec,
1305                                   unsigned char *send_buf,
1306                                   unsigned int send_buf_size,
1307                                   unsigned char *return_buf,
1308                                   unsigned int return_buf_size,
1309                                   unsigned int *bytes_returned)
1310 {
1311         struct ca0132_spec *spec = codec->spec;
1312         int status = -1;
1313         unsigned int scp_send_size = 0;
1314         unsigned int total_size;
1315         bool waiting_for_resp = false;
1316         unsigned int header;
1317         struct scp_msg *ret_msg;
1318         unsigned int resp_src_id, resp_target_id;
1319         unsigned int data_size, src_id, target_id, get_flag, device_flag;
1320
1321         if (bytes_returned)
1322                 *bytes_returned = 0;
1323
1324         /* get scp header from buffer */
1325         header = *((unsigned int *)send_buf);
1326         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1327                            &device_flag, NULL, NULL, &data_size);
1328         scp_send_size = data_size + 1;
1329         total_size = (scp_send_size * 4);
1330
1331         if (send_buf_size < total_size)
1332                 return -EINVAL;
1333
1334         if (get_flag || device_flag) {
1335                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1336                         return -EINVAL;
1337
1338                 spec->wait_scp_header = *((unsigned int *)send_buf);
1339
1340                 /* swap source id with target id */
1341                 resp_target_id = src_id;
1342                 resp_src_id = target_id;
1343                 spec->wait_scp_header &= 0xffff0000;
1344                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1345                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1346                 spec->wait_scp = 1;
1347                 waiting_for_resp = true;
1348         }
1349
1350         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1351                                       scp_send_size);
1352         if (status < 0) {
1353                 spec->wait_scp = 0;
1354                 return status;
1355         }
1356
1357         if (waiting_for_resp) {
1358                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1359                 memset(return_buf, 0, return_buf_size);
1360                 do {
1361                         msleep(20);
1362                 } while (spec->wait_scp && time_before(jiffies, timeout));
1363                 waiting_for_resp = false;
1364                 if (!spec->wait_scp) {
1365                         ret_msg = (struct scp_msg *)return_buf;
1366                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1367                         memcpy(&ret_msg->data, spec->scp_resp_data,
1368                                spec->wait_num_data);
1369                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
1370                         status = 0;
1371                 } else {
1372                         status = -EIO;
1373                 }
1374                 spec->wait_scp = 0;
1375         }
1376
1377         return status;
1378 }
1379
1380 /**
1381  * Prepare and send the SCP message to DSP
1382  * @codec: the HDA codec
1383  * @mod_id: ID of the DSP module to send the command
1384  * @req: ID of request to send to the DSP module
1385  * @dir: SET or GET
1386  * @data: pointer to the data to send with the request, request specific
1387  * @len: length of the data, in bytes
1388  * @reply: point to the buffer to hold data returned for a reply
1389  * @reply_len: length of the reply buffer returned from GET
1390  *
1391  * Returns zero or a negative error code.
1392  */
1393 static int dspio_scp(struct hda_codec *codec,
1394                 int mod_id, int req, int dir, void *data, unsigned int len,
1395                 void *reply, unsigned int *reply_len)
1396 {
1397         int status = 0;
1398         struct scp_msg scp_send, scp_reply;
1399         unsigned int ret_bytes, send_size, ret_size;
1400         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1401         unsigned int reply_data_size;
1402
1403         memset(&scp_send, 0, sizeof(scp_send));
1404         memset(&scp_reply, 0, sizeof(scp_reply));
1405
1406         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1407                 return -EINVAL;
1408
1409         if (dir == SCP_GET && reply == NULL) {
1410                 snd_printdd(KERN_ERR "dspio_scp get but has no buffer\n");
1411                 return -EINVAL;
1412         }
1413
1414         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1415                 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms\n");
1416                 return -EINVAL;
1417         }
1418
1419         scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1420                                        0, 0, 0, len/sizeof(unsigned int));
1421         if (data != NULL && len > 0) {
1422                 len = min((unsigned int)(sizeof(scp_send.data)), len);
1423                 memcpy(scp_send.data, data, len);
1424         }
1425
1426         ret_bytes = 0;
1427         send_size = sizeof(unsigned int) + len;
1428         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1429                                         send_size, (unsigned char *)&scp_reply,
1430                                         sizeof(scp_reply), &ret_bytes);
1431
1432         if (status < 0) {
1433                 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed\n");
1434                 return status;
1435         }
1436
1437         /* extract send and reply headers members */
1438         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1439                            NULL, NULL, NULL, NULL, NULL);
1440         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1441                            &reply_resp_flag, &reply_error_flag,
1442                            &reply_data_size);
1443
1444         if (!send_get_flag)
1445                 return 0;
1446
1447         if (reply_resp_flag && !reply_error_flag) {
1448                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1449                                         / sizeof(unsigned int);
1450
1451                 if (*reply_len < ret_size*sizeof(unsigned int)) {
1452                         snd_printdd(KERN_ERR "reply too long for buf\n");
1453                         return -EINVAL;
1454                 } else if (ret_size != reply_data_size) {
1455                         snd_printdd(KERN_ERR "RetLen and HdrLen .NE.\n");
1456                         return -EINVAL;
1457                 } else {
1458                         *reply_len = ret_size*sizeof(unsigned int);
1459                         memcpy(reply, scp_reply.data, *reply_len);
1460                 }
1461         } else {
1462                 snd_printdd(KERN_ERR "reply ill-formed or errflag set\n");
1463                 return -EIO;
1464         }
1465
1466         return status;
1467 }
1468
1469 /*
1470  * Set DSP parameters
1471  */
1472 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1473                         int req, void *data, unsigned int len)
1474 {
1475         return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1476 }
1477
1478 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1479                         int req, unsigned int data)
1480 {
1481         return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1482 }
1483
1484 /*
1485  * Allocate a DSP DMA channel via an SCP message
1486  */
1487 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1488 {
1489         int status = 0;
1490         unsigned int size = sizeof(dma_chan);
1491
1492         snd_printdd(KERN_INFO "     dspio_alloc_dma_chan() -- begin\n");
1493         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1494                         SCP_GET, NULL, 0, dma_chan, &size);
1495
1496         if (status < 0) {
1497                 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed\n");
1498                 return status;
1499         }
1500
1501         if ((*dma_chan + 1) == 0) {
1502                 snd_printdd(KERN_INFO "no free dma channels to allocate\n");
1503                 return -EBUSY;
1504         }
1505
1506         snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1507         snd_printdd(KERN_INFO "     dspio_alloc_dma_chan() -- complete\n");
1508
1509         return status;
1510 }
1511
1512 /*
1513  * Free a DSP DMA via an SCP message
1514  */
1515 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1516 {
1517         int status = 0;
1518         unsigned int dummy = 0;
1519
1520         snd_printdd(KERN_INFO "     dspio_free_dma_chan() -- begin\n");
1521         snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1522
1523         status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1524                            SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1525
1526         if (status < 0) {
1527                 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed\n");
1528                 return status;
1529         }
1530
1531         snd_printdd(KERN_INFO "     dspio_free_dma_chan() -- complete\n");
1532
1533         return status;
1534 }
1535
1536 /*
1537  * (Re)start the DSP
1538  */
1539 static int dsp_set_run_state(struct hda_codec *codec)
1540 {
1541         unsigned int dbg_ctrl_reg;
1542         unsigned int halt_state;
1543         int err;
1544
1545         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1546         if (err < 0)
1547                 return err;
1548
1549         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1550                       DSP_DBGCNTL_STATE_LOBIT;
1551
1552         if (halt_state != 0) {
1553                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1554                                   DSP_DBGCNTL_SS_MASK);
1555                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1556                                    dbg_ctrl_reg);
1557                 if (err < 0)
1558                         return err;
1559
1560                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1561                                 DSP_DBGCNTL_EXEC_MASK;
1562                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1563                                    dbg_ctrl_reg);
1564                 if (err < 0)
1565                         return err;
1566         }
1567
1568         return 0;
1569 }
1570
1571 /*
1572  * Reset the DSP
1573  */
1574 static int dsp_reset(struct hda_codec *codec)
1575 {
1576         unsigned int res;
1577         int retry = 20;
1578
1579         snd_printdd("dsp_reset\n");
1580         do {
1581                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1582                 retry--;
1583         } while (res == -EIO && retry);
1584
1585         if (!retry) {
1586                 snd_printdd("dsp_reset timeout\n");
1587                 return -EIO;
1588         }
1589
1590         return 0;
1591 }
1592
1593 /*
1594  * Convert chip address to DSP address
1595  */
1596 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1597                                         bool *code, bool *yram)
1598 {
1599         *code = *yram = false;
1600
1601         if (UC_RANGE(chip_addx, 1)) {
1602                 *code = true;
1603                 return UC_OFF(chip_addx);
1604         } else if (X_RANGE_ALL(chip_addx, 1)) {
1605                 return X_OFF(chip_addx);
1606         } else if (Y_RANGE_ALL(chip_addx, 1)) {
1607                 *yram = true;
1608                 return Y_OFF(chip_addx);
1609         }
1610
1611         return INVALID_CHIP_ADDRESS;
1612 }
1613
1614 /*
1615  * Check if the DSP DMA is active
1616  */
1617 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1618 {
1619         unsigned int dma_chnlstart_reg;
1620
1621         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1622
1623         return ((dma_chnlstart_reg & (1 <<
1624                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1625 }
1626
1627 static int dsp_dma_setup_common(struct hda_codec *codec,
1628                                 unsigned int chip_addx,
1629                                 unsigned int dma_chan,
1630                                 unsigned int port_map_mask,
1631                                 bool ovly)
1632 {
1633         int status = 0;
1634         unsigned int chnl_prop;
1635         unsigned int dsp_addx;
1636         unsigned int active;
1637         bool code, yram;
1638
1639         snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------\n");
1640
1641         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1642                 snd_printdd(KERN_ERR "dma chan num invalid\n");
1643                 return -EINVAL;
1644         }
1645
1646         if (dsp_is_dma_active(codec, dma_chan)) {
1647                 snd_printdd(KERN_ERR "dma already active\n");
1648                 return -EBUSY;
1649         }
1650
1651         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1652
1653         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1654                 snd_printdd(KERN_ERR "invalid chip addr\n");
1655                 return -ENXIO;
1656         }
1657
1658         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1659         active = 0;
1660
1661         snd_printdd(KERN_INFO "   dsp_dma_setup_common()    start reg pgm\n");
1662
1663         if (ovly) {
1664                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1665                                      &chnl_prop);
1666
1667                 if (status < 0) {
1668                         snd_printdd(KERN_ERR "read CHNLPROP Reg fail\n");
1669                         return status;
1670                 }
1671                 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP\n");
1672         }
1673
1674         if (!code)
1675                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1676         else
1677                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1678
1679         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1680
1681         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1682         if (status < 0) {
1683                 snd_printdd(KERN_ERR "write CHNLPROP Reg fail\n");
1684                 return status;
1685         }
1686         snd_printdd(KERN_INFO "   dsp_dma_setup_common()    Write CHNLPROP\n");
1687
1688         if (ovly) {
1689                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1690                                      &active);
1691
1692                 if (status < 0) {
1693                         snd_printdd(KERN_ERR "read ACTIVE Reg fail\n");
1694                         return status;
1695                 }
1696                 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE\n");
1697         }
1698
1699         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1700                 DSPDMAC_ACTIVE_AAR_MASK;
1701
1702         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1703         if (status < 0) {
1704                 snd_printdd(KERN_ERR "write ACTIVE Reg fail\n");
1705                 return status;
1706         }
1707
1708         snd_printdd(KERN_INFO "   dsp_dma_setup_common()    Write ACTIVE\n");
1709
1710         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1711                               port_map_mask);
1712         if (status < 0) {
1713                 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail\n");
1714                 return status;
1715         }
1716         snd_printdd(KERN_INFO "   dsp_dma_setup_common()    Write AUDCHSEL\n");
1717
1718         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1719                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1720         if (status < 0) {
1721                 snd_printdd(KERN_ERR "write IRQCNT Reg fail\n");
1722                 return status;
1723         }
1724         snd_printdd(KERN_INFO "   dsp_dma_setup_common()    Write IRQCNT\n");
1725
1726         snd_printdd(
1727                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1728                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1729                    chip_addx, dsp_addx, dma_chan,
1730                    port_map_mask, chnl_prop, active);
1731
1732         snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------\n");
1733
1734         return 0;
1735 }
1736
1737 /*
1738  * Setup the DSP DMA per-transfer-specific registers
1739  */
1740 static int dsp_dma_setup(struct hda_codec *codec,
1741                         unsigned int chip_addx,
1742                         unsigned int count,
1743                         unsigned int dma_chan)
1744 {
1745         int status = 0;
1746         bool code, yram;
1747         unsigned int dsp_addx;
1748         unsigned int addr_field;
1749         unsigned int incr_field;
1750         unsigned int base_cnt;
1751         unsigned int cur_cnt;
1752         unsigned int dma_cfg = 0;
1753         unsigned int adr_ofs = 0;
1754         unsigned int xfr_cnt = 0;
1755         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1756                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1757
1758         snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------\n");
1759
1760         if (count > max_dma_count) {
1761                 snd_printdd(KERN_ERR "count too big\n");
1762                 return -EINVAL;
1763         }
1764
1765         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1766         if (dsp_addx == INVALID_CHIP_ADDRESS) {
1767                 snd_printdd(KERN_ERR "invalid chip addr\n");
1768                 return -ENXIO;
1769         }
1770
1771         snd_printdd(KERN_INFO "   dsp_dma_setup()    start reg pgm\n");
1772
1773         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1774         incr_field   = 0;
1775
1776         if (!code) {
1777                 addr_field <<= 1;
1778                 if (yram)
1779                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1780
1781                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1782         }
1783
1784         dma_cfg = addr_field + incr_field;
1785         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1786                                 dma_cfg);
1787         if (status < 0) {
1788                 snd_printdd(KERN_ERR "write DMACFG Reg fail\n");
1789                 return status;
1790         }
1791         snd_printdd(KERN_INFO "   dsp_dma_setup()    Write DMACFG\n");
1792
1793         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1794                                                         (code ? 0 : 1));
1795
1796         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1797                                 adr_ofs);
1798         if (status < 0) {
1799                 snd_printdd(KERN_ERR "write DSPADROFS Reg fail\n");
1800                 return status;
1801         }
1802         snd_printdd(KERN_INFO "   dsp_dma_setup()    Write DSPADROFS\n");
1803
1804         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1805
1806         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1807
1808         xfr_cnt = base_cnt | cur_cnt;
1809
1810         status = chipio_write(codec,
1811                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1812         if (status < 0) {
1813                 snd_printdd(KERN_ERR "write XFRCNT Reg fail\n");
1814                 return status;
1815         }
1816         snd_printdd(KERN_INFO "   dsp_dma_setup()    Write XFRCNT\n");
1817
1818         snd_printdd(
1819                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1820                    "ADROFS=0x%x, XFRCNT=0x%x\n",
1821                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1822
1823         snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------\n");
1824
1825         return 0;
1826 }
1827
1828 /*
1829  * Start the DSP DMA
1830  */
1831 static int dsp_dma_start(struct hda_codec *codec,
1832                          unsigned int dma_chan, bool ovly)
1833 {
1834         unsigned int reg = 0;
1835         int status = 0;
1836
1837         snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------\n");
1838
1839         if (ovly) {
1840                 status = chipio_read(codec,
1841                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1842
1843                 if (status < 0) {
1844                         snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
1845                         return status;
1846                 }
1847                 snd_printdd(KERN_INFO "-- dsp_dma_start()    Read CHNLSTART\n");
1848
1849                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1850                                 DSPDMAC_CHNLSTART_DIS_MASK);
1851         }
1852
1853         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1854                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1855         if (status < 0) {
1856                 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
1857                 return status;
1858         }
1859         snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------\n");
1860
1861         return status;
1862 }
1863
1864 /*
1865  * Stop the DSP DMA
1866  */
1867 static int dsp_dma_stop(struct hda_codec *codec,
1868                         unsigned int dma_chan, bool ovly)
1869 {
1870         unsigned int reg = 0;
1871         int status = 0;
1872
1873         snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------\n");
1874
1875         if (ovly) {
1876                 status = chipio_read(codec,
1877                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1878
1879                 if (status < 0) {
1880                         snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
1881                         return status;
1882                 }
1883                 snd_printdd(KERN_INFO "-- dsp_dma_stop()    Read CHNLSTART\n");
1884                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1885                                 DSPDMAC_CHNLSTART_DIS_MASK);
1886         }
1887
1888         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1889                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1890         if (status < 0) {
1891                 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
1892                 return status;
1893         }
1894         snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------\n");
1895
1896         return status;
1897 }
1898
1899 /**
1900  * Allocate router ports
1901  *
1902  * @codec: the HDA codec
1903  * @num_chans: number of channels in the stream
1904  * @ports_per_channel: number of ports per channel
1905  * @start_device: start device
1906  * @port_map: pointer to the port list to hold the allocated ports
1907  *
1908  * Returns zero or a negative error code.
1909  */
1910 static int dsp_allocate_router_ports(struct hda_codec *codec,
1911                                      unsigned int num_chans,
1912                                      unsigned int ports_per_channel,
1913                                      unsigned int start_device,
1914                                      unsigned int *port_map)
1915 {
1916         int status = 0;
1917         int res;
1918         u8 val;
1919
1920         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1921         if (status < 0)
1922                 return status;
1923
1924         val = start_device << 6;
1925         val |= (ports_per_channel - 1) << 4;
1926         val |= num_chans - 1;
1927
1928         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1929                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1930                             val);
1931
1932         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1933                             VENDOR_CHIPIO_PORT_ALLOC_SET,
1934                             MEM_CONNID_DSP);
1935
1936         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1937         if (status < 0)
1938                 return status;
1939
1940         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1941                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1942
1943         *port_map = res;
1944
1945         return (res < 0) ? res : 0;
1946 }
1947
1948 /*
1949  * Free router ports
1950  */
1951 static int dsp_free_router_ports(struct hda_codec *codec)
1952 {
1953         int status = 0;
1954
1955         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1956         if (status < 0)
1957                 return status;
1958
1959         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960                             VENDOR_CHIPIO_PORT_FREE_SET,
1961                             MEM_CONNID_DSP);
1962
1963         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1964
1965         return status;
1966 }
1967
1968 /*
1969  * Allocate DSP ports for the download stream
1970  */
1971 static int dsp_allocate_ports(struct hda_codec *codec,
1972                         unsigned int num_chans,
1973                         unsigned int rate_multi, unsigned int *port_map)
1974 {
1975         int status;
1976
1977         snd_printdd(KERN_INFO "     dsp_allocate_ports() -- begin\n");
1978
1979         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1980                 snd_printdd(KERN_ERR "bad rate multiple\n");
1981                 return -EINVAL;
1982         }
1983
1984         status = dsp_allocate_router_ports(codec, num_chans,
1985                                            rate_multi, 0, port_map);
1986
1987         snd_printdd(KERN_INFO "     dsp_allocate_ports() -- complete\n");
1988
1989         return status;
1990 }
1991
1992 static int dsp_allocate_ports_format(struct hda_codec *codec,
1993                         const unsigned short fmt,
1994                         unsigned int *port_map)
1995 {
1996         int status;
1997         unsigned int num_chans;
1998
1999         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2000         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2001         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2002
2003         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2004                 snd_printdd(KERN_ERR "bad rate multiple\n");
2005                 return -EINVAL;
2006         }
2007
2008         num_chans = get_hdafmt_chs(fmt) + 1;
2009
2010         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2011
2012         return status;
2013 }
2014
2015 /*
2016  * free DSP ports
2017  */
2018 static int dsp_free_ports(struct hda_codec *codec)
2019 {
2020         int status;
2021
2022         snd_printdd(KERN_INFO "     dsp_free_ports() -- begin\n");
2023
2024         status = dsp_free_router_ports(codec);
2025         if (status < 0) {
2026                 snd_printdd(KERN_ERR "free router ports fail\n");
2027                 return status;
2028         }
2029         snd_printdd(KERN_INFO "     dsp_free_ports() -- complete\n");
2030
2031         return status;
2032 }
2033
2034 /*
2035  *  HDA DMA engine stuffs for DSP code download
2036  */
2037 struct dma_engine {
2038         struct hda_codec *codec;
2039         unsigned short m_converter_format;
2040         struct snd_dma_buffer *dmab;
2041         unsigned int buf_size;
2042 };
2043
2044
2045 enum dma_state {
2046         DMA_STATE_STOP  = 0,
2047         DMA_STATE_RUN   = 1
2048 };
2049
2050 static int dma_convert_to_hda_format(
2051                 unsigned int sample_rate,
2052                 unsigned short channels,
2053                 unsigned short *hda_format)
2054 {
2055         unsigned int format_val;
2056
2057         format_val = snd_hda_calc_stream_format(
2058                                 sample_rate,
2059                                 channels,
2060                                 SNDRV_PCM_FORMAT_S32_LE,
2061                                 32, 0);
2062
2063         if (hda_format)
2064                 *hda_format = (unsigned short)format_val;
2065
2066         return 0;
2067 }
2068
2069 /*
2070  *  Reset DMA for DSP download
2071  */
2072 static int dma_reset(struct dma_engine *dma)
2073 {
2074         struct hda_codec *codec = dma->codec;
2075         struct ca0132_spec *spec = codec->spec;
2076         int status;
2077
2078         if (dma->dmab->area)
2079                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2080
2081         status = snd_hda_codec_load_dsp_prepare(codec,
2082                         dma->m_converter_format,
2083                         dma->buf_size,
2084                         dma->dmab);
2085         if (status < 0)
2086                 return status;
2087         spec->dsp_stream_id = status;
2088         return 0;
2089 }
2090
2091 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2092 {
2093         bool cmd;
2094
2095         snd_printdd("dma_set_state state=%d\n", state);
2096
2097         switch (state) {
2098         case DMA_STATE_STOP:
2099                 cmd = false;
2100                 break;
2101         case DMA_STATE_RUN:
2102                 cmd = true;
2103                 break;
2104         default:
2105                 return 0;
2106         }
2107
2108         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2109         return 0;
2110 }
2111
2112 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2113 {
2114         return dma->dmab->bytes;
2115 }
2116
2117 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2118 {
2119         return dma->dmab->area;
2120 }
2121
2122 static int dma_xfer(struct dma_engine *dma,
2123                 const unsigned int *data,
2124                 unsigned int count)
2125 {
2126         memcpy(dma->dmab->area, data, count);
2127         return 0;
2128 }
2129
2130 static void dma_get_converter_format(
2131                 struct dma_engine *dma,
2132                 unsigned short *format)
2133 {
2134         if (format)
2135                 *format = dma->m_converter_format;
2136 }
2137
2138 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2139 {
2140         struct ca0132_spec *spec = dma->codec->spec;
2141
2142         return spec->dsp_stream_id;
2143 }
2144
2145 struct dsp_image_seg {
2146         u32 magic;
2147         u32 chip_addr;
2148         u32 count;
2149         u32 data[0];
2150 };
2151
2152 static const u32 g_magic_value = 0x4c46584d;
2153 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2154
2155 static bool is_valid(const struct dsp_image_seg *p)
2156 {
2157         return p->magic == g_magic_value;
2158 }
2159
2160 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2161 {
2162         return g_chip_addr_magic_value == p->chip_addr;
2163 }
2164
2165 static bool is_last(const struct dsp_image_seg *p)
2166 {
2167         return p->count == 0;
2168 }
2169
2170 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2171 {
2172         return sizeof(*p) + p->count*sizeof(u32);
2173 }
2174
2175 static const struct dsp_image_seg *get_next_seg_ptr(
2176                                 const struct dsp_image_seg *p)
2177 {
2178         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2179 }
2180
2181 /*
2182  * CA0132 chip DSP transfer stuffs.  For DSP download.
2183  */
2184 #define INVALID_DMA_CHANNEL (~0U)
2185
2186 /*
2187  * Program a list of address/data pairs via the ChipIO widget.
2188  * The segment data is in the format of successive pairs of words.
2189  * These are repeated as indicated by the segment's count field.
2190  */
2191 static int dspxfr_hci_write(struct hda_codec *codec,
2192                         const struct dsp_image_seg *fls)
2193 {
2194         int status;
2195         const u32 *data;
2196         unsigned int count;
2197
2198         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2199                 snd_printdd(KERN_ERR "hci_write invalid params\n");
2200                 return -EINVAL;
2201         }
2202
2203         count = fls->count;
2204         data = (u32 *)(fls->data);
2205         while (count >= 2) {
2206                 status = chipio_write(codec, data[0], data[1]);
2207                 if (status < 0) {
2208                         snd_printdd(KERN_ERR "hci_write chipio failed\n");
2209                         return status;
2210                 }
2211                 count -= 2;
2212                 data  += 2;
2213         }
2214         return 0;
2215 }
2216
2217 /**
2218  * Write a block of data into DSP code or data RAM using pre-allocated
2219  * DMA engine.
2220  *
2221  * @codec: the HDA codec
2222  * @fls: pointer to a fast load image
2223  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2224  *         no relocation
2225  * @dma_engine: pointer to DMA engine to be used for DSP download
2226  * @dma_chan: The number of DMA channels used for DSP download
2227  * @port_map_mask: port mapping
2228  * @ovly: TRUE if overlay format is required
2229  *
2230  * Returns zero or a negative error code.
2231  */
2232 static int dspxfr_one_seg(struct hda_codec *codec,
2233                         const struct dsp_image_seg *fls,
2234                         unsigned int reloc,
2235                         struct dma_engine *dma_engine,
2236                         unsigned int dma_chan,
2237                         unsigned int port_map_mask,
2238                         bool ovly)
2239 {
2240         int status = 0;
2241         bool comm_dma_setup_done = false;
2242         const unsigned int *data;
2243         unsigned int chip_addx;
2244         unsigned int words_to_write;
2245         unsigned int buffer_size_words;
2246         unsigned char *buffer_addx;
2247         unsigned short hda_format;
2248         unsigned int sample_rate_div;
2249         unsigned int sample_rate_mul;
2250         unsigned int num_chans;
2251         unsigned int hda_frame_size_words;
2252         unsigned int remainder_words;
2253         const u32 *data_remainder;
2254         u32 chip_addx_remainder;
2255         unsigned int run_size_words;
2256         const struct dsp_image_seg *hci_write = NULL;
2257         unsigned long timeout;
2258         bool dma_active;
2259
2260         if (fls == NULL)
2261                 return -EINVAL;
2262         if (is_hci_prog_list_seg(fls)) {
2263                 hci_write = fls;
2264                 fls = get_next_seg_ptr(fls);
2265         }
2266
2267         if (hci_write && (!fls || is_last(fls))) {
2268                 snd_printdd("hci_write\n");
2269                 return dspxfr_hci_write(codec, hci_write);
2270         }
2271
2272         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2273                 snd_printdd("Invalid Params\n");
2274                 return -EINVAL;
2275         }
2276
2277         data = fls->data;
2278         chip_addx = fls->chip_addr,
2279         words_to_write = fls->count;
2280
2281         if (!words_to_write)
2282                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2283         if (reloc)
2284                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2285
2286         if (!UC_RANGE(chip_addx, words_to_write) &&
2287             !X_RANGE_ALL(chip_addx, words_to_write) &&
2288             !Y_RANGE_ALL(chip_addx, words_to_write)) {
2289                 snd_printdd("Invalid chip_addx Params\n");
2290                 return -EINVAL;
2291         }
2292
2293         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2294                                         sizeof(u32);
2295
2296         buffer_addx = dma_get_buffer_addr(dma_engine);
2297
2298         if (buffer_addx == NULL) {
2299                 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2300                 return -EINVAL;
2301         }
2302
2303         dma_get_converter_format(dma_engine, &hda_format);
2304         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2305         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2306         num_chans = get_hdafmt_chs(hda_format) + 1;
2307
2308         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2309                         (num_chans * sample_rate_mul / sample_rate_div));
2310
2311         if (hda_frame_size_words == 0) {
2312                 snd_printdd(KERN_ERR "frmsz zero\n");
2313                 return -EINVAL;
2314         }
2315
2316         buffer_size_words = min(buffer_size_words,
2317                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2318                                 65536 : 32768));
2319         buffer_size_words -= buffer_size_words % hda_frame_size_words;
2320         snd_printdd(
2321                    "chpadr=0x%08x frmsz=%u nchan=%u "
2322                    "rate_mul=%u div=%u bufsz=%u\n",
2323                    chip_addx, hda_frame_size_words, num_chans,
2324                    sample_rate_mul, sample_rate_div, buffer_size_words);
2325
2326         if (buffer_size_words < hda_frame_size_words) {
2327                 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2328                 return -EINVAL;
2329         }
2330
2331         remainder_words = words_to_write % hda_frame_size_words;
2332         data_remainder = data;
2333         chip_addx_remainder = chip_addx;
2334
2335         data += remainder_words;
2336         chip_addx += remainder_words*sizeof(u32);
2337         words_to_write -= remainder_words;
2338
2339         while (words_to_write != 0) {
2340                 run_size_words = min(buffer_size_words, words_to_write);
2341                 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2342                             words_to_write, run_size_words, remainder_words);
2343                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2344                 if (!comm_dma_setup_done) {
2345                         status = dsp_dma_stop(codec, dma_chan, ovly);
2346                         if (status < 0)
2347                                 return status;
2348                         status = dsp_dma_setup_common(codec, chip_addx,
2349                                                 dma_chan, port_map_mask, ovly);
2350                         if (status < 0)
2351                                 return status;
2352                         comm_dma_setup_done = true;
2353                 }
2354
2355                 status = dsp_dma_setup(codec, chip_addx,
2356                                                 run_size_words, dma_chan);
2357                 if (status < 0)
2358                         return status;
2359                 status = dsp_dma_start(codec, dma_chan, ovly);
2360                 if (status < 0)
2361                         return status;
2362                 if (!dsp_is_dma_active(codec, dma_chan)) {
2363                         snd_printdd(KERN_ERR "dspxfr:DMA did not start\n");
2364                         return -EIO;
2365                 }
2366                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2367                 if (status < 0)
2368                         return status;
2369                 if (remainder_words != 0) {
2370                         status = chipio_write_multiple(codec,
2371                                                 chip_addx_remainder,
2372                                                 data_remainder,
2373                                                 remainder_words);
2374                         if (status < 0)
2375                                 return status;
2376                         remainder_words = 0;
2377                 }
2378                 if (hci_write) {
2379                         status = dspxfr_hci_write(codec, hci_write);
2380                         if (status < 0)
2381                                 return status;
2382                         hci_write = NULL;
2383                 }
2384
2385                 timeout = jiffies + msecs_to_jiffies(2000);
2386                 do {
2387                         dma_active = dsp_is_dma_active(codec, dma_chan);
2388                         if (!dma_active)
2389                                 break;
2390                         msleep(20);
2391                 } while (time_before(jiffies, timeout));
2392                 if (dma_active)
2393                         break;
2394
2395                 snd_printdd(KERN_INFO "+++++ DMA complete\n");
2396                 dma_set_state(dma_engine, DMA_STATE_STOP);
2397                 status = dma_reset(dma_engine);
2398
2399                 if (status < 0)
2400                         return status;
2401
2402                 data += run_size_words;
2403                 chip_addx += run_size_words*sizeof(u32);
2404                 words_to_write -= run_size_words;
2405         }
2406
2407         if (remainder_words != 0) {
2408                 status = chipio_write_multiple(codec, chip_addx_remainder,
2409                                         data_remainder, remainder_words);
2410         }
2411
2412         return status;
2413 }
2414
2415 /**
2416  * Write the entire DSP image of a DSP code/data overlay to DSP memories
2417  *
2418  * @codec: the HDA codec
2419  * @fls_data: pointer to a fast load image
2420  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2421  *         no relocation
2422  * @sample_rate: sampling rate of the stream used for DSP download
2423  * @number_channels: channels of the stream used for DSP download
2424  * @ovly: TRUE if overlay format is required
2425  *
2426  * Returns zero or a negative error code.
2427  */
2428 static int dspxfr_image(struct hda_codec *codec,
2429                         const struct dsp_image_seg *fls_data,
2430                         unsigned int reloc,
2431                         unsigned int sample_rate,
2432                         unsigned short channels,
2433                         bool ovly)
2434 {
2435         struct ca0132_spec *spec = codec->spec;
2436         int status;
2437         unsigned short hda_format = 0;
2438         unsigned int response;
2439         unsigned char stream_id = 0;
2440         struct dma_engine *dma_engine;
2441         unsigned int dma_chan;
2442         unsigned int port_map_mask;
2443
2444         if (fls_data == NULL)
2445                 return -EINVAL;
2446
2447         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2448         if (!dma_engine)
2449                 return -ENOMEM;
2450
2451         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2452         if (!dma_engine->dmab) {
2453                 kfree(dma_engine);
2454                 return -ENOMEM;
2455         }
2456
2457         dma_engine->codec = codec;
2458         dma_convert_to_hda_format(sample_rate, channels, &hda_format);
2459         dma_engine->m_converter_format = hda_format;
2460         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2461                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2462
2463         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2464
2465         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2466                                         hda_format, &response);
2467
2468         if (status < 0) {
2469                 snd_printdd(KERN_ERR "set converter format fail\n");
2470                 goto exit;
2471         }
2472
2473         status = snd_hda_codec_load_dsp_prepare(codec,
2474                                 dma_engine->m_converter_format,
2475                                 dma_engine->buf_size,
2476                                 dma_engine->dmab);
2477         if (status < 0)
2478                 goto exit;
2479         spec->dsp_stream_id = status;
2480
2481         if (ovly) {
2482                 status = dspio_alloc_dma_chan(codec, &dma_chan);
2483                 if (status < 0) {
2484                         snd_printdd(KERN_ERR "alloc dmachan fail\n");
2485                         dma_chan = INVALID_DMA_CHANNEL;
2486                         goto exit;
2487                 }
2488         }
2489
2490         port_map_mask = 0;
2491         status = dsp_allocate_ports_format(codec, hda_format,
2492                                         &port_map_mask);
2493         if (status < 0) {
2494                 snd_printdd(KERN_ERR "alloc ports fail\n");
2495                 goto exit;
2496         }
2497
2498         stream_id = dma_get_stream_id(dma_engine);
2499         status = codec_set_converter_stream_channel(codec,
2500                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
2501         if (status < 0) {
2502                 snd_printdd(KERN_ERR "set stream chan fail\n");
2503                 goto exit;
2504         }
2505
2506         while ((fls_data != NULL) && !is_last(fls_data)) {
2507                 if (!is_valid(fls_data)) {
2508                         snd_printdd(KERN_ERR "FLS check fail\n");
2509                         status = -EINVAL;
2510                         goto exit;
2511                 }
2512                 status = dspxfr_one_seg(codec, fls_data, reloc,
2513                                         dma_engine, dma_chan,
2514                                         port_map_mask, ovly);
2515                 if (status < 0)
2516                         break;
2517
2518                 if (is_hci_prog_list_seg(fls_data))
2519                         fls_data = get_next_seg_ptr(fls_data);
2520
2521                 if ((fls_data != NULL) && !is_last(fls_data))
2522                         fls_data = get_next_seg_ptr(fls_data);
2523         }
2524
2525         if (port_map_mask != 0)
2526                 status = dsp_free_ports(codec);
2527
2528         if (status < 0)
2529                 goto exit;
2530
2531         status = codec_set_converter_stream_channel(codec,
2532                                 WIDGET_CHIP_CTRL, 0, 0, &response);
2533
2534 exit:
2535         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2536                 dspio_free_dma_chan(codec, dma_chan);
2537
2538         if (dma_engine->dmab->area)
2539                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2540         kfree(dma_engine->dmab);
2541         kfree(dma_engine);
2542
2543         return status;
2544 }
2545
2546 /*
2547  * CA0132 DSP download stuffs.
2548  */
2549 static void dspload_post_setup(struct hda_codec *codec)
2550 {
2551         snd_printdd(KERN_INFO "---- dspload_post_setup ------\n");
2552
2553         /*set DSP speaker to 2.0 configuration*/
2554         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2555         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2556
2557         /*update write pointer*/
2558         chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2559 }
2560
2561 /**
2562  * Download DSP from a DSP Image Fast Load structure. This structure is a
2563  * linear, non-constant sized element array of structures, each of which
2564  * contain the count of the data to be loaded, the data itself, and the
2565  * corresponding starting chip address of the starting data location.
2566  *
2567  * @codec: the HDA codec
2568  * @fls: pointer to a fast load image
2569  * @ovly: TRUE if overlay format is required
2570  * @reloc: Relocation address for loading single-segment overlays, or 0 for
2571  *         no relocation
2572  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2573  * @router_chans: number of audio router channels to be allocated (0 means use
2574  *                internal defaults; max is 32)
2575  *
2576  * Returns zero or a negative error code.
2577  */
2578 static int dspload_image(struct hda_codec *codec,
2579                         const struct dsp_image_seg *fls,
2580                         bool ovly,
2581                         unsigned int reloc,
2582                         bool autostart,
2583                         int router_chans)
2584 {
2585         int status = 0;
2586         unsigned int sample_rate;
2587         unsigned short channels;
2588
2589         snd_printdd(KERN_INFO "---- dspload_image begin ------\n");
2590         if (router_chans == 0) {
2591                 if (!ovly)
2592                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2593                 else
2594                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2595         }
2596
2597         sample_rate = 48000;
2598         channels = (unsigned short)router_chans;
2599
2600         while (channels > 16) {
2601                 sample_rate *= 2;
2602                 channels /= 2;
2603         }
2604
2605         do {
2606                 snd_printdd(KERN_INFO "Ready to program DMA\n");
2607                 if (!ovly)
2608                         status = dsp_reset(codec);
2609
2610                 if (status < 0)
2611                         break;
2612
2613                 snd_printdd(KERN_INFO "dsp_reset() complete\n");
2614                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2615                                       ovly);
2616
2617                 if (status < 0)
2618                         break;
2619
2620                 snd_printdd(KERN_INFO "dspxfr_image() complete\n");
2621                 if (autostart && !ovly) {
2622                         dspload_post_setup(codec);
2623                         status = dsp_set_run_state(codec);
2624                 }
2625
2626                 snd_printdd(KERN_INFO "LOAD FINISHED\n");
2627         } while (0);
2628
2629         return status;
2630 }
2631
2632 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2633 static bool dspload_is_loaded(struct hda_codec *codec)
2634 {
2635         unsigned int data = 0;
2636         int status = 0;
2637
2638         status = chipio_read(codec, 0x40004, &data);
2639         if ((status < 0) || (data != 1))
2640                 return false;
2641
2642         return true;
2643 }
2644 #else
2645 #define dspload_is_loaded(codec)        false
2646 #endif
2647
2648 static bool dspload_wait_loaded(struct hda_codec *codec)
2649 {
2650         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2651
2652         do {
2653                 if (dspload_is_loaded(codec)) {
2654                         pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2655                         return true;
2656                 }
2657                 msleep(20);
2658         } while (time_before(jiffies, timeout));
2659
2660         pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2661         return false;
2662 }
2663
2664 /*
2665  * PCM stuffs
2666  */
2667 static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
2668                                  u32 stream_tag,
2669                                  int channel_id, int format)
2670 {
2671         unsigned int oldval, newval;
2672
2673         if (!nid)
2674                 return;
2675
2676         snd_printdd(
2677                    "ca0132_setup_stream: NID=0x%x, stream=0x%x, "
2678                    "channel=%d, format=0x%x\n",
2679                    nid, stream_tag, channel_id, format);
2680
2681         /* update the format-id if changed */
2682         oldval = snd_hda_codec_read(codec, nid, 0,
2683                                     AC_VERB_GET_STREAM_FORMAT,
2684                                     0);
2685         if (oldval != format) {
2686                 msleep(20);
2687                 snd_hda_codec_write(codec, nid, 0,
2688                                     AC_VERB_SET_STREAM_FORMAT,
2689                                     format);
2690         }
2691
2692         oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2693         newval = (stream_tag << 4) | channel_id;
2694         if (oldval != newval) {
2695                 snd_hda_codec_write(codec, nid, 0,
2696                                     AC_VERB_SET_CHANNEL_STREAMID,
2697                                     newval);
2698         }
2699 }
2700
2701 static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
2702 {
2703         unsigned int val;
2704
2705         if (!nid)
2706                 return;
2707
2708         snd_printdd(KERN_INFO "ca0132_cleanup_stream: NID=0x%x\n", nid);
2709
2710         val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
2711         if (!val)
2712                 return;
2713
2714         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
2715         snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2716 }
2717
2718 /*
2719  * PCM callbacks
2720  */
2721 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2722                         struct hda_codec *codec,
2723                         unsigned int stream_tag,
2724                         unsigned int format,
2725                         struct snd_pcm_substream *substream)
2726 {
2727         struct ca0132_spec *spec = codec->spec;
2728
2729         ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2730
2731         return 0;
2732 }
2733
2734 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2735                         struct hda_codec *codec,
2736                         struct snd_pcm_substream *substream)
2737 {
2738         struct ca0132_spec *spec = codec->spec;
2739
2740         if (spec->dsp_state == DSP_DOWNLOADING)
2741                 return 0;
2742
2743         /*If Playback effects are on, allow stream some time to flush
2744          *effects tail*/
2745         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2746                 msleep(50);
2747
2748         ca0132_cleanup_stream(codec, spec->dacs[0]);
2749
2750         return 0;
2751 }
2752
2753 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2754                         struct hda_codec *codec,
2755                         struct snd_pcm_substream *substream)
2756 {
2757         struct ca0132_spec *spec = codec->spec;
2758         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2759         struct snd_pcm_runtime *runtime = substream->runtime;
2760
2761         if (spec->dsp_state != DSP_DOWNLOADED)
2762                 return 0;
2763
2764         /* Add latency if playback enhancement and either effect is enabled. */
2765         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2766                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2767                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2768                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2769         }
2770
2771         /* Applying Speaker EQ adds latency as well. */
2772         if (spec->cur_out_type == SPEAKER_OUT)
2773                 latency += DSP_SPEAKER_OUT_LATENCY;
2774
2775         return (latency * runtime->rate) / 1000;
2776 }
2777
2778 /*
2779  * Digital out
2780  */
2781 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2782                                         struct hda_codec *codec,
2783                                         struct snd_pcm_substream *substream)
2784 {
2785         struct ca0132_spec *spec = codec->spec;
2786         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2787 }
2788
2789 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2790                         struct hda_codec *codec,
2791                         unsigned int stream_tag,
2792                         unsigned int format,
2793                         struct snd_pcm_substream *substream)
2794 {
2795         struct ca0132_spec *spec = codec->spec;
2796         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2797                                              stream_tag, format, substream);
2798 }
2799
2800 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2801                         struct hda_codec *codec,
2802                         struct snd_pcm_substream *substream)
2803 {
2804         struct ca0132_spec *spec = codec->spec;
2805         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2806 }
2807
2808 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2809                                          struct hda_codec *codec,
2810                                          struct snd_pcm_substream *substream)
2811 {
2812         struct ca0132_spec *spec = codec->spec;
2813         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2814 }
2815
2816 /*
2817  * Analog capture
2818  */
2819 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2820                                         struct hda_codec *codec,
2821                                         unsigned int stream_tag,
2822                                         unsigned int format,
2823                                         struct snd_pcm_substream *substream)
2824 {
2825         struct ca0132_spec *spec = codec->spec;
2826
2827         ca0132_setup_stream(codec, spec->adcs[substream->number],
2828                             stream_tag, 0, format);
2829
2830         return 0;
2831 }
2832
2833 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2834                         struct hda_codec *codec,
2835                         struct snd_pcm_substream *substream)
2836 {
2837         struct ca0132_spec *spec = codec->spec;
2838
2839         if (spec->dsp_state == DSP_DOWNLOADING)
2840                 return 0;
2841
2842         ca0132_cleanup_stream(codec, hinfo->nid);
2843         return 0;
2844 }
2845
2846 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2847                         struct hda_codec *codec,
2848                         struct snd_pcm_substream *substream)
2849 {
2850         struct ca0132_spec *spec = codec->spec;
2851         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2852         struct snd_pcm_runtime *runtime = substream->runtime;
2853
2854         if (spec->dsp_state != DSP_DOWNLOADED)
2855                 return 0;
2856
2857         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2858                 latency += DSP_CRYSTAL_VOICE_LATENCY;
2859
2860         return (latency * runtime->rate) / 1000;
2861 }
2862
2863 /*
2864  * Controls stuffs.
2865  */
2866
2867 /*
2868  * Mixer controls helpers.
2869  */
2870 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2871         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2872           .name = xname, \
2873           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2874           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2875                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2876                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2877           .info = ca0132_volume_info, \
2878           .get = ca0132_volume_get, \
2879           .put = ca0132_volume_put, \
2880           .tlv = { .c = ca0132_volume_tlv }, \
2881           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2882
2883 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2884         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2885           .name = xname, \
2886           .subdevice = HDA_SUBDEV_AMP_FLAG, \
2887           .info = snd_hda_mixer_amp_switch_info, \
2888           .get = ca0132_switch_get, \
2889           .put = ca0132_switch_put, \
2890           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2891
2892 /* stereo */
2893 #define CA0132_CODEC_VOL(xname, nid, dir) \
2894         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2895 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2896         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2897
2898 /* The followings are for tuning of products */
2899 #ifdef ENABLE_TUNING_CONTROLS
2900
2901 static unsigned int voice_focus_vals_lookup[] = {
2902 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2903 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2904 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2905 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2906 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2907 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2908 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2909 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2910 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2911 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2912 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2913 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2914 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2915 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2916 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2917 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2918 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2919 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2920 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2921 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2922 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2923 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2924 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2925 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2926 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2927 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2928 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2929 };
2930
2931 static unsigned int mic_svm_vals_lookup[] = {
2932 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2933 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2934 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2935 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2936 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2937 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2938 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2939 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2940 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2941 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2942 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2943 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2944 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2945 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2946 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2947 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2948 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2949 };
2950
2951 static unsigned int equalizer_vals_lookup[] = {
2952 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2953 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2954 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2955 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2956 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2957 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2958 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2959 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2960 0x41C00000
2961 };
2962
2963 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2964                           unsigned int *lookup, int idx)
2965 {
2966         int i = 0;
2967
2968         for (i = 0; i < TUNING_CTLS_COUNT; i++)
2969                 if (nid == ca0132_tuning_ctls[i].nid)
2970                         break;
2971
2972         snd_hda_power_up(codec);
2973         dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2974                         ca0132_tuning_ctls[i].req,
2975                         &(lookup[idx]), sizeof(unsigned int));
2976         snd_hda_power_down(codec);
2977
2978         return 1;
2979 }
2980
2981 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2982                           struct snd_ctl_elem_value *ucontrol)
2983 {
2984         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2985         struct ca0132_spec *spec = codec->spec;
2986         hda_nid_t nid = get_amp_nid(kcontrol);
2987         long *valp = ucontrol->value.integer.value;
2988         int idx = nid - TUNING_CTL_START_NID;
2989
2990         *valp = spec->cur_ctl_vals[idx];
2991         return 0;
2992 }
2993
2994 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2995                               struct snd_ctl_elem_info *uinfo)
2996 {
2997         int chs = get_amp_channels(kcontrol);
2998         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2999         uinfo->count = chs == 3 ? 2 : 1;
3000         uinfo->value.integer.min = 20;
3001         uinfo->value.integer.max = 180;
3002         uinfo->value.integer.step = 1;
3003
3004         return 0;
3005 }
3006
3007 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3008                                 struct snd_ctl_elem_value *ucontrol)
3009 {
3010         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3011         struct ca0132_spec *spec = codec->spec;
3012         hda_nid_t nid = get_amp_nid(kcontrol);
3013         long *valp = ucontrol->value.integer.value;
3014         int idx;
3015
3016         idx = nid - TUNING_CTL_START_NID;
3017         /* any change? */
3018         if (spec->cur_ctl_vals[idx] == *valp)
3019                 return 0;
3020
3021         spec->cur_ctl_vals[idx] = *valp;
3022
3023         idx = *valp - 20;
3024         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3025
3026         return 1;
3027 }
3028
3029 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3030                               struct snd_ctl_elem_info *uinfo)
3031 {
3032         int chs = get_amp_channels(kcontrol);
3033         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3034         uinfo->count = chs == 3 ? 2 : 1;
3035         uinfo->value.integer.min = 0;
3036         uinfo->value.integer.max = 100;
3037         uinfo->value.integer.step = 1;
3038
3039         return 0;
3040 }
3041
3042 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3043                                 struct snd_ctl_elem_value *ucontrol)
3044 {
3045         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3046         struct ca0132_spec *spec = codec->spec;
3047         hda_nid_t nid = get_amp_nid(kcontrol);
3048         long *valp = ucontrol->value.integer.value;
3049         int idx;
3050
3051         idx = nid - TUNING_CTL_START_NID;
3052         /* any change? */
3053         if (spec->cur_ctl_vals[idx] == *valp)
3054                 return 0;
3055
3056         spec->cur_ctl_vals[idx] = *valp;
3057
3058         idx = *valp;
3059         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3060
3061         return 0;
3062 }
3063
3064 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3065                               struct snd_ctl_elem_info *uinfo)
3066 {
3067         int chs = get_amp_channels(kcontrol);
3068         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3069         uinfo->count = chs == 3 ? 2 : 1;
3070         uinfo->value.integer.min = 0;
3071         uinfo->value.integer.max = 48;
3072         uinfo->value.integer.step = 1;
3073
3074         return 0;
3075 }
3076
3077 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3078                                 struct snd_ctl_elem_value *ucontrol)
3079 {
3080         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3081         struct ca0132_spec *spec = codec->spec;
3082         hda_nid_t nid = get_amp_nid(kcontrol);
3083         long *valp = ucontrol->value.integer.value;
3084         int idx;
3085
3086         idx = nid - TUNING_CTL_START_NID;
3087         /* any change? */
3088         if (spec->cur_ctl_vals[idx] == *valp)
3089                 return 0;
3090
3091         spec->cur_ctl_vals[idx] = *valp;
3092
3093         idx = *valp;
3094         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3095
3096         return 1;
3097 }
3098
3099 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3100 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3101
3102 static int add_tuning_control(struct hda_codec *codec,
3103                                 hda_nid_t pnid, hda_nid_t nid,
3104                                 const char *name, int dir)
3105 {
3106         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3107         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3108         struct snd_kcontrol_new knew =
3109                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3110
3111         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3112                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3113         knew.tlv.c = 0;
3114         knew.tlv.p = 0;
3115         switch (pnid) {
3116         case VOICE_FOCUS:
3117                 knew.info = voice_focus_ctl_info;
3118                 knew.get = tuning_ctl_get;
3119                 knew.put = voice_focus_ctl_put;
3120                 knew.tlv.p = voice_focus_db_scale;
3121                 break;
3122         case MIC_SVM:
3123                 knew.info = mic_svm_ctl_info;
3124                 knew.get = tuning_ctl_get;
3125                 knew.put = mic_svm_ctl_put;
3126                 break;
3127         case EQUALIZER:
3128                 knew.info = equalizer_ctl_info;
3129                 knew.get = tuning_ctl_get;
3130                 knew.put = equalizer_ctl_put;
3131                 knew.tlv.p = eq_db_scale;
3132                 break;
3133         default:
3134                 return 0;
3135         }
3136         knew.private_value =
3137                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3138         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3139         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3140 }
3141
3142 static int add_tuning_ctls(struct hda_codec *codec)
3143 {
3144         int i;
3145         int err;
3146
3147         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3148                 err = add_tuning_control(codec,
3149                                         ca0132_tuning_ctls[i].parent_nid,
3150                                         ca0132_tuning_ctls[i].nid,
3151                                         ca0132_tuning_ctls[i].name,
3152                                         ca0132_tuning_ctls[i].direct);
3153                 if (err < 0)
3154                         return err;
3155         }
3156
3157         return 0;
3158 }
3159
3160 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3161 {
3162         struct ca0132_spec *spec = codec->spec;
3163         int i;
3164
3165         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
3166         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3167         /* SVM level defaults to 0.74. */
3168         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3169
3170         /* EQ defaults to 0dB. */
3171         for (i = 2; i < TUNING_CTLS_COUNT; i++)
3172                 spec->cur_ctl_vals[i] = 24;
3173 }
3174 #endif /*ENABLE_TUNING_CONTROLS*/
3175
3176 /*
3177  * Select the active output.
3178  * If autodetect is enabled, output will be selected based on jack detection.
3179  * If jack inserted, headphone will be selected, else built-in speakers
3180  * If autodetect is disabled, output will be selected based on selection.
3181  */
3182 static int ca0132_select_out(struct hda_codec *codec)
3183 {
3184         struct ca0132_spec *spec = codec->spec;
3185         unsigned int pin_ctl;
3186         int jack_present;
3187         int auto_jack;
3188         unsigned int tmp;
3189         int err;
3190
3191         snd_printdd(KERN_INFO "ca0132_select_out\n");
3192
3193         snd_hda_power_up(codec);
3194
3195         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3196
3197         if (auto_jack)
3198                 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3199         else
3200                 jack_present =
3201                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3202
3203         if (jack_present)
3204                 spec->cur_out_type = HEADPHONE_OUT;
3205         else
3206                 spec->cur_out_type = SPEAKER_OUT;
3207
3208         if (spec->cur_out_type == SPEAKER_OUT) {
3209                 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3210                 /*speaker out config*/
3211                 tmp = FLOAT_ONE;
3212                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3213                 if (err < 0)
3214                         goto exit;
3215                 /*enable speaker EQ*/
3216                 tmp = FLOAT_ONE;
3217                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3218                 if (err < 0)
3219                         goto exit;
3220
3221                 /* Setup EAPD */
3222                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3223                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3224                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3225                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3226                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3227                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3228                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3229                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3230
3231                 /* disable headphone node */
3232                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3233                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3234                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3235                                     pin_ctl & ~PIN_HP);
3236                 /* enable speaker node */
3237                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3238                                              AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3239                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3240                                     pin_ctl | PIN_OUT);
3241         } else {
3242                 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3243                 /*headphone out config*/
3244                 tmp = FLOAT_ZERO;
3245                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3246                 if (err < 0)
3247                         goto exit;
3248                 /*disable speaker EQ*/
3249                 tmp = FLOAT_ZERO;
3250                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3251                 if (err < 0)
3252                         goto exit;
3253
3254                 /* Setup EAPD */
3255                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3256                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3257                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3258                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3259                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3260                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3261                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3262                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3263
3264                 /* disable speaker*/
3265                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3266                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3267                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3268                                     pin_ctl & ~PIN_HP);
3269                 /* enable headphone*/
3270                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3271                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3272                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3273                                     pin_ctl | PIN_HP);
3274         }
3275
3276 exit:
3277         snd_hda_power_down(codec);
3278
3279         return err < 0 ? err : 0;
3280 }
3281
3282 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3283 {
3284         struct ca0132_spec *spec = container_of(
3285                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3286         ca0132_select_out(spec->codec);
3287         snd_hda_jack_report_sync(spec->codec);
3288 }
3289
3290 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3291 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3292 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3293
3294 /*
3295  * Select the active VIP source
3296  */
3297 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3298 {
3299         struct ca0132_spec *spec = codec->spec;
3300         unsigned int tmp;
3301
3302         if (spec->dsp_state != DSP_DOWNLOADED)
3303                 return 0;
3304
3305         /* if CrystalVoice if off, vipsource should be 0 */
3306         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3307             (val == 0)) {
3308                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3309                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3310                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3311                 if (spec->cur_mic_type == DIGITAL_MIC)
3312                         tmp = FLOAT_TWO;
3313                 else
3314                         tmp = FLOAT_ONE;
3315                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3316                 tmp = FLOAT_ZERO;
3317                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3318         } else {
3319                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3320                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3321                 if (spec->cur_mic_type == DIGITAL_MIC)
3322                         tmp = FLOAT_TWO;
3323                 else
3324                         tmp = FLOAT_ONE;
3325                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3326                 tmp = FLOAT_ONE;
3327                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3328                 msleep(20);
3329                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3330         }
3331
3332         return 1;
3333 }
3334
3335 /*
3336  * Select the active microphone.
3337  * If autodetect is enabled, mic will be selected based on jack detection.
3338  * If jack inserted, ext.mic will be selected, else built-in mic
3339  * If autodetect is disabled, mic will be selected based on selection.
3340  */
3341 static int ca0132_select_mic(struct hda_codec *codec)
3342 {
3343         struct ca0132_spec *spec = codec->spec;
3344         int jack_present;
3345         int auto_jack;
3346
3347         snd_printdd(KERN_INFO "ca0132_select_mic\n");
3348
3349         snd_hda_power_up(codec);
3350
3351         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3352
3353         if (auto_jack)
3354                 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3355         else
3356                 jack_present =
3357                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3358
3359         if (jack_present)
3360                 spec->cur_mic_type = LINE_MIC_IN;
3361         else
3362                 spec->cur_mic_type = DIGITAL_MIC;
3363
3364         if (spec->cur_mic_type == DIGITAL_MIC) {
3365                 /* enable digital Mic */
3366                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3367                 ca0132_set_dmic(codec, 1);
3368                 ca0132_mic_boost_set(codec, 0);
3369                 /* set voice focus */
3370                 ca0132_effects_set(codec, VOICE_FOCUS,
3371                                    spec->effects_switch
3372                                    [VOICE_FOCUS - EFFECT_START_NID]);
3373         } else {
3374                 /* disable digital Mic */
3375                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3376                 ca0132_set_dmic(codec, 0);
3377                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3378                 /* disable voice focus */
3379                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3380         }
3381
3382         snd_hda_power_down(codec);
3383
3384         return 0;
3385 }
3386
3387 /*
3388  * Check if VNODE settings take effect immediately.
3389  */
3390 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3391                                      hda_nid_t vnid,
3392                                      hda_nid_t *shared_nid)
3393 {
3394         struct ca0132_spec *spec = codec->spec;
3395         hda_nid_t nid;
3396
3397         switch (vnid) {
3398         case VNID_SPK:
3399                 nid = spec->shared_out_nid;
3400                 break;
3401         case VNID_MIC:
3402                 nid = spec->shared_mic_nid;
3403                 break;
3404         default:
3405                 return false;
3406         }
3407
3408         if (shared_nid)
3409                 *shared_nid = nid;
3410
3411         return true;
3412 }
3413
3414 /*
3415 * The following functions are control change helpers.
3416 * They return 0 if no changed.  Return 1 if changed.
3417 */
3418 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3419 {
3420         struct ca0132_spec *spec = codec->spec;
3421         unsigned int tmp;
3422
3423         /* based on CrystalVoice state to enable VoiceFX. */
3424         if (enable) {
3425                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3426                         FLOAT_ONE : FLOAT_ZERO;
3427         } else {
3428                 tmp = FLOAT_ZERO;
3429         }
3430
3431         dspio_set_uint_param(codec, ca0132_voicefx.mid,
3432                              ca0132_voicefx.reqs[0], tmp);
3433
3434         return 1;
3435 }
3436
3437 /*
3438  * Set the effects parameters
3439  */
3440 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3441 {
3442         struct ca0132_spec *spec = codec->spec;
3443         unsigned int on;
3444         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3445         int err = 0;
3446         int idx = nid - EFFECT_START_NID;
3447
3448         if ((idx < 0) || (idx >= num_fx))
3449                 return 0; /* no changed */
3450
3451         /* for out effect, qualify with PE */
3452         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3453                 /* if PE if off, turn off out effects. */
3454                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3455                         val = 0;
3456         }
3457
3458         /* for in effect, qualify with CrystalVoice */
3459         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3460                 /* if CrystalVoice if off, turn off in effects. */
3461                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3462                         val = 0;
3463
3464                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3465                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3466                         val = 0;
3467         }
3468
3469         snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n",
3470                     nid, val);
3471
3472         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3473         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3474                                    ca0132_effects[idx].reqs[0], on);
3475
3476         if (err < 0)
3477                 return 0; /* no changed */
3478
3479         return 1;
3480 }
3481
3482 /*
3483  * Turn on/off Playback Enhancements
3484  */
3485 static int ca0132_pe_switch_set(struct hda_codec *codec)
3486 {
3487         struct ca0132_spec *spec = codec->spec;
3488         hda_nid_t nid;
3489         int i, ret = 0;
3490
3491         snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3492                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3493
3494         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3495         nid = OUT_EFFECT_START_NID;
3496         /* PE affects all out effects */
3497         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3498                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3499
3500         return ret;
3501 }
3502
3503 /* Check if Mic1 is streaming, if so, stop streaming */
3504 static int stop_mic1(struct hda_codec *codec)
3505 {
3506         struct ca0132_spec *spec = codec->spec;
3507         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3508                                                  AC_VERB_GET_CONV, 0);
3509         if (oldval != 0)
3510                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3511                                     AC_VERB_SET_CHANNEL_STREAMID,
3512                                     0);
3513         return oldval;
3514 }
3515
3516 /* Resume Mic1 streaming if it was stopped. */
3517 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3518 {
3519         struct ca0132_spec *spec = codec->spec;
3520         /* Restore the previous stream and channel */
3521         if (oldval != 0)
3522                 snd_hda_codec_write(codec, spec->adcs[0], 0,
3523                                     AC_VERB_SET_CHANNEL_STREAMID,
3524                                     oldval);
3525 }
3526
3527 /*
3528  * Turn on/off CrystalVoice
3529  */
3530 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3531 {
3532         struct ca0132_spec *spec = codec->spec;
3533         hda_nid_t nid;
3534         int i, ret = 0;
3535         unsigned int oldval;
3536
3537         snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3538                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3539
3540         i = IN_EFFECT_START_NID - EFFECT_START_NID;
3541         nid = IN_EFFECT_START_NID;
3542         /* CrystalVoice affects all in effects */
3543         for (; nid < IN_EFFECT_END_NID; nid++, i++)
3544                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3545
3546         /* including VoiceFX */
3547         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3548
3549         /* set correct vipsource */
3550         oldval = stop_mic1(codec);
3551         ret |= ca0132_set_vipsource(codec, 1);
3552         resume_mic1(codec, oldval);
3553         return ret;
3554 }
3555
3556 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3557 {
3558         struct ca0132_spec *spec = codec->spec;
3559         int ret = 0;
3560
3561         if (val) /* on */
3562                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3563                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3564         else /* off */
3565                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3566                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3567
3568         return ret;
3569 }
3570
3571 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3572                                 struct snd_ctl_elem_value *ucontrol)
3573 {
3574         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3575         hda_nid_t nid = get_amp_nid(kcontrol);
3576         hda_nid_t shared_nid = 0;
3577         bool effective;
3578         int ret = 0;
3579         struct ca0132_spec *spec = codec->spec;
3580         int auto_jack;
3581
3582         if (nid == VNID_HP_SEL) {
3583                 auto_jack =
3584                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3585                 if (!auto_jack)
3586                         ca0132_select_out(codec);
3587                 return 1;
3588         }
3589
3590         if (nid == VNID_AMIC1_SEL) {
3591                 auto_jack =
3592                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3593                 if (!auto_jack)
3594                         ca0132_select_mic(codec);
3595                 return 1;
3596         }
3597
3598         if (nid == VNID_HP_ASEL) {
3599                 ca0132_select_out(codec);
3600                 return 1;
3601         }
3602
3603         if (nid == VNID_AMIC1_ASEL) {
3604                 ca0132_select_mic(codec);
3605                 return 1;
3606         }
3607
3608         /* if effective conditions, then update hw immediately. */
3609         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3610         if (effective) {
3611                 int dir = get_amp_direction(kcontrol);
3612                 int ch = get_amp_channels(kcontrol);
3613                 unsigned long pval;
3614
3615                 mutex_lock(&codec->control_mutex);
3616                 pval = kcontrol->private_value;
3617                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3618                                                                 0, dir);
3619                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3620                 kcontrol->private_value = pval;
3621                 mutex_unlock(&codec->control_mutex);
3622         }
3623
3624         return ret;
3625 }
3626 /* End of control change helpers. */
3627
3628 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3629                                  struct snd_ctl_elem_info *uinfo)
3630 {
3631         unsigned int items = sizeof(ca0132_voicefx_presets)
3632                                 / sizeof(struct ct_voicefx_preset);
3633
3634         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3635         uinfo->count = 1;
3636         uinfo->value.enumerated.items = items;
3637         if (uinfo->value.enumerated.item >= items)
3638                 uinfo->value.enumerated.item = items - 1;
3639         strcpy(uinfo->value.enumerated.name,
3640                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3641         return 0;
3642 }
3643
3644 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3645                                 struct snd_ctl_elem_value *ucontrol)
3646 {
3647         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3648         struct ca0132_spec *spec = codec->spec;
3649
3650         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3651         return 0;
3652 }
3653
3654 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3655                                 struct snd_ctl_elem_value *ucontrol)
3656 {
3657         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3658         struct ca0132_spec *spec = codec->spec;
3659         int i, err = 0;
3660         int sel = ucontrol->value.enumerated.item[0];
3661         unsigned int items = sizeof(ca0132_voicefx_presets)
3662                                 / sizeof(struct ct_voicefx_preset);
3663
3664         if (sel >= items)
3665                 return 0;
3666
3667         snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3668                     sel, ca0132_voicefx_presets[sel].name);
3669
3670         /*
3671          * Idx 0 is default.
3672          * Default needs to qualify with CrystalVoice state.
3673          */
3674         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3675                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3676                                 ca0132_voicefx.reqs[i],
3677                                 ca0132_voicefx_presets[sel].vals[i]);
3678                 if (err < 0)
3679                         break;
3680         }
3681
3682         if (err >= 0) {
3683                 spec->voicefx_val = sel;
3684                 /* enable voice fx */
3685                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3686         }
3687
3688         return 1;
3689 }
3690
3691 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3692                                 struct snd_ctl_elem_value *ucontrol)
3693 {
3694         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3695         struct ca0132_spec *spec = codec->spec;
3696         hda_nid_t nid = get_amp_nid(kcontrol);
3697         int ch = get_amp_channels(kcontrol);
3698         long *valp = ucontrol->value.integer.value;
3699
3700         /* vnode */
3701         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3702                 if (ch & 1) {
3703                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3704                         valp++;
3705                 }
3706                 if (ch & 2) {
3707                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3708                         valp++;
3709                 }
3710                 return 0;
3711         }
3712
3713         /* effects, include PE and CrystalVoice */
3714         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3715                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3716                 return 0;
3717         }
3718
3719         /* mic boost */
3720         if (nid == spec->input_pins[0]) {
3721                 *valp = spec->cur_mic_boost;
3722                 return 0;
3723         }
3724
3725         return 0;
3726 }
3727
3728 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3729                              struct snd_ctl_elem_value *ucontrol)
3730 {
3731         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3732         struct ca0132_spec *spec = codec->spec;
3733         hda_nid_t nid = get_amp_nid(kcontrol);
3734         int ch = get_amp_channels(kcontrol);
3735         long *valp = ucontrol->value.integer.value;
3736         int changed = 1;
3737
3738         snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3739                     nid, *valp);
3740
3741         snd_hda_power_up(codec);
3742         /* vnode */
3743         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3744                 if (ch & 1) {
3745                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3746                         valp++;
3747                 }
3748                 if (ch & 2) {
3749                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3750                         valp++;
3751                 }
3752                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3753                 goto exit;
3754         }
3755
3756         /* PE */
3757         if (nid == PLAY_ENHANCEMENT) {
3758                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3759                 changed = ca0132_pe_switch_set(codec);
3760                 goto exit;
3761         }
3762
3763         /* CrystalVoice */
3764         if (nid == CRYSTAL_VOICE) {
3765                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3766                 changed = ca0132_cvoice_switch_set(codec);
3767                 goto exit;
3768         }
3769
3770         /* out and in effects */
3771         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3772             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3773                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3774                 changed = ca0132_effects_set(codec, nid, *valp);
3775                 goto exit;
3776         }
3777
3778         /* mic boost */
3779         if (nid == spec->input_pins[0]) {
3780                 spec->cur_mic_boost = *valp;
3781
3782                 /* Mic boost does not apply to Digital Mic */
3783                 if (spec->cur_mic_type != DIGITAL_MIC)
3784                         changed = ca0132_mic_boost_set(codec, *valp);
3785                 goto exit;
3786         }
3787
3788 exit:
3789         snd_hda_power_down(codec);
3790         return changed;
3791 }
3792
3793 /*
3794  * Volume related
3795  */
3796 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3797                               struct snd_ctl_elem_info *uinfo)
3798 {
3799         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3800         struct ca0132_spec *spec = codec->spec;
3801         hda_nid_t nid = get_amp_nid(kcontrol);
3802         int ch = get_amp_channels(kcontrol);
3803         int dir = get_amp_direction(kcontrol);
3804         unsigned long pval;
3805         int err;
3806
3807         switch (nid) {
3808         case VNID_SPK:
3809                 /* follow shared_out info */
3810                 nid = spec->shared_out_nid;
3811                 mutex_lock(&codec->control_mutex);
3812                 pval = kcontrol->private_value;
3813                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3814                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3815                 kcontrol->private_value = pval;
3816                 mutex_unlock(&codec->control_mutex);
3817                 break;
3818         case VNID_MIC:
3819                 /* follow shared_mic info */
3820                 nid = spec->shared_mic_nid;
3821                 mutex_lock(&codec->control_mutex);
3822                 pval = kcontrol->private_value;
3823                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3824                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3825                 kcontrol->private_value = pval;
3826                 mutex_unlock(&codec->control_mutex);
3827                 break;
3828         default:
3829                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3830         }
3831         return err;
3832 }
3833
3834 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3835                                 struct snd_ctl_elem_value *ucontrol)
3836 {
3837         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3838         struct ca0132_spec *spec = codec->spec;
3839         hda_nid_t nid = get_amp_nid(kcontrol);
3840         int ch = get_amp_channels(kcontrol);
3841         long *valp = ucontrol->value.integer.value;
3842
3843         /* store the left and right volume */
3844         if (ch & 1) {
3845                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3846                 valp++;
3847         }
3848         if (ch & 2) {
3849                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3850                 valp++;
3851         }
3852         return 0;
3853 }
3854
3855 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3856                                 struct snd_ctl_elem_value *ucontrol)
3857 {
3858         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3859         struct ca0132_spec *spec = codec->spec;
3860         hda_nid_t nid = get_amp_nid(kcontrol);
3861         int ch = get_amp_channels(kcontrol);
3862         long *valp = ucontrol->value.integer.value;
3863         hda_nid_t shared_nid = 0;
3864         bool effective;
3865         int changed = 1;
3866
3867         /* store the left and right volume */
3868         if (ch & 1) {
3869                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3870                 valp++;
3871         }
3872         if (ch & 2) {
3873                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3874                 valp++;
3875         }
3876
3877         /* if effective conditions, then update hw immediately. */
3878         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3879         if (effective) {
3880                 int dir = get_amp_direction(kcontrol);
3881                 unsigned long pval;
3882
3883                 snd_hda_power_up(codec);
3884                 mutex_lock(&codec->control_mutex);
3885                 pval = kcontrol->private_value;
3886                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3887                                                                 0, dir);
3888                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3889                 kcontrol->private_value = pval;
3890                 mutex_unlock(&codec->control_mutex);
3891                 snd_hda_power_down(codec);
3892         }
3893
3894         return changed;
3895 }
3896
3897 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3898                              unsigned int size, unsigned int __user *tlv)
3899 {
3900         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3901         struct ca0132_spec *spec = codec->spec;
3902         hda_nid_t nid = get_amp_nid(kcontrol);
3903         int ch = get_amp_channels(kcontrol);
3904         int dir = get_amp_direction(kcontrol);
3905         unsigned long pval;
3906         int err;
3907
3908         switch (nid) {
3909         case VNID_SPK:
3910                 /* follow shared_out tlv */
3911                 nid = spec->shared_out_nid;
3912                 mutex_lock(&codec->control_mutex);
3913                 pval = kcontrol->private_value;
3914                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3915                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3916                 kcontrol->private_value = pval;
3917                 mutex_unlock(&codec->control_mutex);
3918                 break;
3919         case VNID_MIC:
3920                 /* follow shared_mic tlv */
3921                 nid = spec->shared_mic_nid;
3922                 mutex_lock(&codec->control_mutex);
3923                 pval = kcontrol->private_value;
3924                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3925                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3926                 kcontrol->private_value = pval;
3927                 mutex_unlock(&codec->control_mutex);
3928                 break;
3929         default:
3930                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3931         }
3932         return err;
3933 }
3934
3935 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3936                          const char *pfx, int dir)
3937 {
3938         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3939         int type = dir ? HDA_INPUT : HDA_OUTPUT;
3940         struct snd_kcontrol_new knew =
3941                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3942         sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3943         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3944 }
3945
3946 static int add_voicefx(struct hda_codec *codec)
3947 {
3948         struct snd_kcontrol_new knew =
3949                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3950                                     VOICEFX, 1, 0, HDA_INPUT);
3951         knew.info = ca0132_voicefx_info;
3952         knew.get = ca0132_voicefx_get;
3953         knew.put = ca0132_voicefx_put;
3954         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3955 }
3956
3957 /*
3958  * When changing Node IDs for Mixer Controls below, make sure to update
3959  * Node IDs in ca0132_config() as well.
3960  */
3961 static struct snd_kcontrol_new ca0132_mixer[] = {
3962         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3963         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3964         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3965         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3966         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3967         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3968         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3969         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3970         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3971                                0x12, 1, HDA_INPUT),
3972         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3973                                VNID_HP_SEL, 1, HDA_OUTPUT),
3974         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3975                                VNID_AMIC1_SEL, 1, HDA_INPUT),
3976         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3977                                VNID_HP_ASEL, 1, HDA_OUTPUT),
3978         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3979                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
3980         { } /* end */
3981 };
3982
3983 static int ca0132_build_controls(struct hda_codec *codec)
3984 {
3985         struct ca0132_spec *spec = codec->spec;
3986         int i, num_fx;
3987         int err = 0;
3988
3989         /* Add Mixer controls */
3990         for (i = 0; i < spec->num_mixers; i++) {
3991                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3992                 if (err < 0)
3993                         return err;
3994         }
3995
3996         /* Add in and out effects controls.
3997          * VoiceFX, PE and CrystalVoice are added separately.
3998          */
3999         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4000         for (i = 0; i < num_fx; i++) {
4001                 err = add_fx_switch(codec, ca0132_effects[i].nid,
4002                                     ca0132_effects[i].name,
4003                                     ca0132_effects[i].direct);
4004                 if (err < 0)
4005                         return err;
4006         }
4007
4008         err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
4009         if (err < 0)
4010                 return err;
4011
4012         err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
4013         if (err < 0)
4014                 return err;
4015
4016         add_voicefx(codec);
4017
4018 #ifdef ENABLE_TUNING_CONTROLS
4019         add_tuning_ctls(codec);
4020 #endif
4021
4022         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
4023         if (err < 0)
4024                 return err;
4025
4026         if (spec->dig_out) {
4027                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
4028                                                     spec->dig_out);
4029                 if (err < 0)
4030                         return err;
4031                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
4032                 if (err < 0)
4033                         return err;
4034                 /* spec->multiout.share_spdif = 1; */
4035         }
4036
4037         if (spec->dig_in) {
4038                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
4039                 if (err < 0)
4040                         return err;
4041         }
4042         return 0;
4043 }
4044
4045 /*
4046  * PCM
4047  */
4048 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
4049         .substreams = 1,
4050         .channels_min = 2,
4051         .channels_max = 6,
4052         .ops = {
4053                 .prepare = ca0132_playback_pcm_prepare,
4054                 .cleanup = ca0132_playback_pcm_cleanup,
4055                 .get_delay = ca0132_playback_pcm_delay,
4056         },
4057 };
4058
4059 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4060         .substreams = 1,
4061         .channels_min = 2,
4062         .channels_max = 2,
4063         .ops = {
4064                 .prepare = ca0132_capture_pcm_prepare,
4065                 .cleanup = ca0132_capture_pcm_cleanup,
4066                 .get_delay = ca0132_capture_pcm_delay,
4067         },
4068 };
4069
4070 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4071         .substreams = 1,
4072         .channels_min = 2,
4073         .channels_max = 2,
4074         .ops = {
4075                 .open = ca0132_dig_playback_pcm_open,
4076                 .close = ca0132_dig_playback_pcm_close,
4077                 .prepare = ca0132_dig_playback_pcm_prepare,
4078                 .cleanup = ca0132_dig_playback_pcm_cleanup
4079         },
4080 };
4081
4082 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4083         .substreams = 1,
4084         .channels_min = 2,
4085         .channels_max = 2,
4086 };
4087
4088 static int ca0132_build_pcms(struct hda_codec *codec)
4089 {
4090         struct ca0132_spec *spec = codec->spec;
4091         struct hda_pcm *info = spec->pcm_rec;
4092
4093         codec->pcm_info = info;
4094         codec->num_pcms = 0;
4095
4096         info->name = "CA0132 Analog";
4097         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4098         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4099         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4100                 spec->multiout.max_channels;
4101         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4102         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4103         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4104         codec->num_pcms++;
4105
4106         info++;
4107         info->name = "CA0132 Analog Mic-In2";
4108         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4109         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4110         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4111         codec->num_pcms++;
4112
4113         info++;
4114         info->name = "CA0132 What U Hear";
4115         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4116         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4117         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4118         codec->num_pcms++;
4119
4120         if (!spec->dig_out && !spec->dig_in)
4121                 return 0;
4122
4123         info++;
4124         info->name = "CA0132 Digital";
4125         info->pcm_type = HDA_PCM_TYPE_SPDIF;
4126         if (spec->dig_out) {
4127                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4128                         ca0132_pcm_digital_playback;
4129                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4130         }
4131         if (spec->dig_in) {
4132                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4133                         ca0132_pcm_digital_capture;
4134                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4135         }
4136         codec->num_pcms++;
4137
4138         return 0;
4139 }
4140
4141 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4142 {
4143         if (pin) {
4144                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4145                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4146                         snd_hda_codec_write(codec, pin, 0,
4147                                             AC_VERB_SET_AMP_GAIN_MUTE,
4148                                             AMP_OUT_UNMUTE);
4149         }
4150         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4151                 snd_hda_codec_write(codec, dac, 0,
4152                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4153 }
4154
4155 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4156 {
4157         if (pin) {
4158                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4159                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4160                         snd_hda_codec_write(codec, pin, 0,
4161                                             AC_VERB_SET_AMP_GAIN_MUTE,
4162                                             AMP_IN_UNMUTE(0));
4163         }
4164         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4165                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4166                                     AMP_IN_UNMUTE(0));
4167
4168                 /* init to 0 dB and unmute. */
4169                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4170                                          HDA_AMP_VOLMASK, 0x5a);
4171                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4172                                          HDA_AMP_MUTE, 0);
4173         }
4174 }
4175
4176 static void ca0132_init_unsol(struct hda_codec *codec)
4177 {
4178         snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4179         snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4180 }
4181
4182 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4183 {
4184         unsigned int caps;
4185
4186         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4187                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4188         snd_hda_override_amp_caps(codec, nid, dir, caps);
4189 }
4190
4191 /*
4192  * Switch between Digital built-in mic and analog mic.
4193  */
4194 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4195 {
4196         struct ca0132_spec *spec = codec->spec;
4197         unsigned int tmp;
4198         u8 val;
4199         unsigned int oldval;
4200
4201         snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4202
4203         oldval = stop_mic1(codec);
4204         ca0132_set_vipsource(codec, 0);
4205         if (enable) {
4206                 /* set DMic input as 2-ch */
4207                 tmp = FLOAT_TWO;
4208                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4209
4210                 val = spec->dmic_ctl;
4211                 val |= 0x80;
4212                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4213                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4214
4215                 if (!(spec->dmic_ctl & 0x20))
4216                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4217         } else {
4218                 /* set AMic input as mono */
4219                 tmp = FLOAT_ONE;
4220                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4221
4222                 val = spec->dmic_ctl;
4223                 /* clear bit7 and bit5 to disable dmic */
4224                 val &= 0x5f;
4225                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4226                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
4227
4228                 if (!(spec->dmic_ctl & 0x20))
4229                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4230         }
4231         ca0132_set_vipsource(codec, 1);
4232         resume_mic1(codec, oldval);
4233 }
4234
4235 /*
4236  * Initialization for Digital Mic.
4237  */
4238 static void ca0132_init_dmic(struct hda_codec *codec)
4239 {
4240         struct ca0132_spec *spec = codec->spec;
4241         u8 val;
4242
4243         /* Setup Digital Mic here, but don't enable.
4244          * Enable based on jack detect.
4245          */
4246
4247         /* MCLK uses MPIO1, set to enable.
4248          * Bit 2-0: MPIO select
4249          * Bit   3: set to disable
4250          * Bit 7-4: reserved
4251          */
4252         val = 0x01;
4253         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4254                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4255
4256         /* Data1 uses MPIO3. Data2 not use
4257          * Bit 2-0: Data1 MPIO select
4258          * Bit   3: set disable Data1
4259          * Bit 6-4: Data2 MPIO select
4260          * Bit   7: set disable Data2
4261          */
4262         val = 0x83;
4263         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4264                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
4265
4266         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4267          * Bit 3-0: Channel mask
4268          * Bit   4: set for 48KHz, clear for 32KHz
4269          * Bit   5: mode
4270          * Bit   6: set to select Data2, clear for Data1
4271          * Bit   7: set to enable DMic, clear for AMic
4272          */
4273         val = 0x23;
4274         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4275         spec->dmic_ctl = val;
4276         snd_hda_codec_write(codec, spec->input_pins[0], 0,
4277                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
4278 }
4279
4280 /*
4281  * Initialization for Analog Mic 2
4282  */
4283 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4284 {
4285         struct ca0132_spec *spec = codec->spec;
4286
4287         mutex_lock(&spec->chipio_mutex);
4288         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4289                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4290         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4291                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4292         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4293                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4294         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4295                             VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4296         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4297                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4298         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4299                             VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4300         mutex_unlock(&spec->chipio_mutex);
4301 }
4302
4303 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4304 {
4305         struct ca0132_spec *spec = codec->spec;
4306         int i;
4307         hda_nid_t nid;
4308
4309         snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4310         nid = codec->start_nid;
4311         for (i = 0; i < codec->num_nodes; i++, nid++)
4312                 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4313                                                      AC_PAR_AUDIO_WIDGET_CAP);
4314
4315         for (i = 0; i < spec->multiout.num_dacs; i++)
4316                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4317
4318         for (i = 0; i < spec->num_outputs; i++)
4319                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4320
4321         for (i = 0; i < spec->num_inputs; i++) {
4322                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4323                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4324         }
4325 }
4326
4327 /*
4328  * Setup default parameters for DSP
4329  */
4330 static void ca0132_setup_defaults(struct hda_codec *codec)
4331 {
4332         struct ca0132_spec *spec = codec->spec;
4333         unsigned int tmp;
4334         int num_fx;
4335         int idx, i;
4336
4337         if (spec->dsp_state != DSP_DOWNLOADED)
4338                 return;
4339
4340         /* out, in effects + voicefx */
4341         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4342         for (idx = 0; idx < num_fx; idx++) {
4343                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4344                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4345                                              ca0132_effects[idx].reqs[i],
4346                                              ca0132_effects[idx].def_vals[i]);
4347                 }
4348         }
4349
4350         /*remove DSP headroom*/
4351         tmp = FLOAT_ZERO;
4352         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4353
4354         /*set speaker EQ bypass attenuation*/
4355         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4356
4357         /* set AMic1 and AMic2 as mono mic */
4358         tmp = FLOAT_ONE;
4359         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4360         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4361
4362         /* set AMic1 as CrystalVoice input */
4363         tmp = FLOAT_ONE;
4364         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4365
4366         /* set WUH source */
4367         tmp = FLOAT_TWO;
4368         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4369 }
4370
4371 /*
4372  * Initialization of flags in chip
4373  */
4374 static void ca0132_init_flags(struct hda_codec *codec)
4375 {
4376         chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4377         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4378         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4379         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4380         chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4381         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4382 }
4383
4384 /*
4385  * Initialization of parameters in chip
4386  */
4387 static void ca0132_init_params(struct hda_codec *codec)
4388 {
4389         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4390         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4391 }
4392
4393 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4394 {
4395         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4396         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4397         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4398         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4399         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4400         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4401
4402         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4403         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4404         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4405 }
4406
4407 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4408 {
4409         bool dsp_loaded = false;
4410         const struct dsp_image_seg *dsp_os_image;
4411         const struct firmware *fw_entry;
4412
4413         if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
4414                 return false;
4415
4416         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4417         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4418                 pr_err("ca0132 dspload_image failed.\n");
4419                 goto exit_download;
4420         }
4421
4422         dsp_loaded = dspload_wait_loaded(codec);
4423
4424 exit_download:
4425         release_firmware(fw_entry);
4426
4427         return dsp_loaded;
4428 }
4429
4430 static void ca0132_download_dsp(struct hda_codec *codec)
4431 {
4432         struct ca0132_spec *spec = codec->spec;
4433
4434 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4435         return; /* NOP */
4436 #endif
4437
4438         chipio_enable_clocks(codec);
4439         spec->dsp_state = DSP_DOWNLOADING;
4440         if (!ca0132_download_dsp_images(codec))
4441                 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4442         else
4443                 spec->dsp_state = DSP_DOWNLOADED;
4444
4445         if (spec->dsp_state == DSP_DOWNLOADED)
4446                 ca0132_set_dsp_msr(codec, true);
4447 }
4448
4449 static void ca0132_process_dsp_response(struct hda_codec *codec)
4450 {
4451         struct ca0132_spec *spec = codec->spec;
4452
4453         snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4454         if (spec->wait_scp) {
4455                 if (dspio_get_response_data(codec) >= 0)
4456                         spec->wait_scp = 0;
4457         }
4458
4459         dspio_clear_response_queue(codec);
4460 }
4461
4462 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4463 {
4464         struct ca0132_spec *spec = codec->spec;
4465
4466         if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4467                 ca0132_process_dsp_response(codec);
4468         } else {
4469                 res = snd_hda_jack_get_action(codec,
4470                                 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4471
4472                 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4473
4474                 switch (res) {
4475                 case UNSOL_TAG_HP:
4476                         /* Delay enabling the HP amp, to let the mic-detection
4477                          * state machine run.
4478                          */
4479                         cancel_delayed_work_sync(&spec->unsol_hp_work);
4480                         queue_delayed_work(codec->bus->workq,
4481                                            &spec->unsol_hp_work,
4482                                            msecs_to_jiffies(500));
4483                         break;
4484                 case UNSOL_TAG_AMIC1:
4485                         ca0132_select_mic(codec);
4486                         snd_hda_jack_report_sync(codec);
4487                         break;
4488                 default:
4489                         break;
4490                 }
4491         }
4492 }
4493
4494 /*
4495  * Verbs tables.
4496  */
4497
4498 /* Sends before DSP download. */
4499 static struct hda_verb ca0132_base_init_verbs[] = {
4500         /*enable ct extension*/
4501         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4502         /*enable DSP node unsol, needed for DSP download*/
4503         {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4504         {}
4505 };
4506
4507 /* Send at exit. */
4508 static struct hda_verb ca0132_base_exit_verbs[] = {
4509         /*set afg to D3*/
4510         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4511         /*disable ct extension*/
4512         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4513         {}
4514 };
4515
4516 /* Other verbs tables.  Sends after DSP download. */
4517 static struct hda_verb ca0132_init_verbs0[] = {
4518         /* chip init verbs */
4519         {0x15, 0x70D, 0xF0},
4520         {0x15, 0x70E, 0xFE},
4521         {0x15, 0x707, 0x75},
4522         {0x15, 0x707, 0xD3},
4523         {0x15, 0x707, 0x09},
4524         {0x15, 0x707, 0x53},
4525         {0x15, 0x707, 0xD4},
4526         {0x15, 0x707, 0xEF},
4527         {0x15, 0x707, 0x75},
4528         {0x15, 0x707, 0xD3},
4529         {0x15, 0x707, 0x09},
4530         {0x15, 0x707, 0x02},
4531         {0x15, 0x707, 0x37},
4532         {0x15, 0x707, 0x78},
4533         {0x15, 0x53C, 0xCE},
4534         {0x15, 0x575, 0xC9},
4535         {0x15, 0x53D, 0xCE},
4536         {0x15, 0x5B7, 0xC9},
4537         {0x15, 0x70D, 0xE8},
4538         {0x15, 0x70E, 0xFE},
4539         {0x15, 0x707, 0x02},
4540         {0x15, 0x707, 0x68},
4541         {0x15, 0x707, 0x62},
4542         {0x15, 0x53A, 0xCE},
4543         {0x15, 0x546, 0xC9},
4544         {0x15, 0x53B, 0xCE},
4545         {0x15, 0x5E8, 0xC9},
4546         {0x15, 0x717, 0x0D},
4547         {0x15, 0x718, 0x20},
4548         {}
4549 };
4550
4551 static struct hda_verb ca0132_init_verbs1[] = {
4552         {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4553         {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4554         /* config EAPD */
4555         {0x0b, 0x78D, 0x00},
4556         /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4557         /*{0x10, 0x78D, 0x02},*/
4558         /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4559         {}
4560 };
4561
4562 static void ca0132_init_chip(struct hda_codec *codec)
4563 {
4564         struct ca0132_spec *spec = codec->spec;
4565         int num_fx;
4566         int i;
4567         unsigned int on;
4568
4569         mutex_init(&spec->chipio_mutex);
4570
4571         spec->cur_out_type = SPEAKER_OUT;
4572         spec->cur_mic_type = DIGITAL_MIC;
4573         spec->cur_mic_boost = 0;
4574
4575         for (i = 0; i < VNODES_COUNT; i++) {
4576                 spec->vnode_lvol[i] = 0x5a;
4577                 spec->vnode_rvol[i] = 0x5a;
4578                 spec->vnode_lswitch[i] = 0;
4579                 spec->vnode_rswitch[i] = 0;
4580         }
4581
4582         /*
4583          * Default states for effects are in ca0132_effects[].
4584          */
4585         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4586         for (i = 0; i < num_fx; i++) {
4587                 on = (unsigned int)ca0132_effects[i].reqs[0];
4588                 spec->effects_switch[i] = on ? 1 : 0;
4589         }
4590
4591         spec->voicefx_val = 0;
4592         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4593         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4594
4595 #ifdef ENABLE_TUNING_CONTROLS
4596         ca0132_init_tuning_defaults(codec);
4597 #endif
4598 }
4599
4600 static void ca0132_exit_chip(struct hda_codec *codec)
4601 {
4602         /* put any chip cleanup stuffs here. */
4603
4604         if (dspload_is_loaded(codec))
4605                 dsp_reset(codec);
4606 }
4607
4608 static int ca0132_init(struct hda_codec *codec)
4609 {
4610         struct ca0132_spec *spec = codec->spec;
4611         struct auto_pin_cfg *cfg = &spec->autocfg;
4612         int i;
4613
4614         spec->dsp_state = DSP_DOWNLOAD_INIT;
4615         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4616
4617         snd_hda_power_up(codec);
4618
4619         ca0132_init_params(codec);
4620         ca0132_init_flags(codec);
4621         snd_hda_sequence_write(codec, spec->base_init_verbs);
4622         ca0132_download_dsp(codec);
4623         ca0132_refresh_widget_caps(codec);
4624         ca0132_setup_defaults(codec);
4625         ca0132_init_analog_mic2(codec);
4626         ca0132_init_dmic(codec);
4627
4628         for (i = 0; i < spec->num_outputs; i++)
4629                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4630
4631         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4632
4633         for (i = 0; i < spec->num_inputs; i++)
4634                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4635
4636         init_input(codec, cfg->dig_in_pin, spec->dig_in);
4637
4638         for (i = 0; i < spec->num_init_verbs; i++)
4639                 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4640
4641         ca0132_init_unsol(codec);
4642
4643         ca0132_select_out(codec);
4644         ca0132_select_mic(codec);
4645
4646         snd_hda_jack_report_sync(codec);
4647
4648         snd_hda_power_down(codec);
4649
4650         return 0;
4651 }
4652
4653 static void ca0132_free(struct hda_codec *codec)
4654 {
4655         struct ca0132_spec *spec = codec->spec;
4656
4657         cancel_delayed_work_sync(&spec->unsol_hp_work);
4658         snd_hda_power_up(codec);
4659         snd_hda_sequence_write(codec, spec->base_exit_verbs);
4660         ca0132_exit_chip(codec);
4661         snd_hda_power_down(codec);
4662         kfree(codec->spec);
4663 }
4664
4665 static struct hda_codec_ops ca0132_patch_ops = {
4666         .build_controls = ca0132_build_controls,
4667         .build_pcms = ca0132_build_pcms,
4668         .init = ca0132_init,
4669         .free = ca0132_free,
4670         .unsol_event = ca0132_unsol_event,
4671 };
4672
4673 static void ca0132_config(struct hda_codec *codec)
4674 {
4675         struct ca0132_spec *spec = codec->spec;
4676         struct auto_pin_cfg *cfg = &spec->autocfg;
4677
4678         spec->dacs[0] = 0x2;
4679         spec->dacs[1] = 0x3;
4680         spec->dacs[2] = 0x4;
4681
4682         spec->multiout.dac_nids = spec->dacs;
4683         spec->multiout.num_dacs = 3;
4684         spec->multiout.max_channels = 2;
4685
4686         spec->num_outputs = 2;
4687         spec->out_pins[0] = 0x0b; /* speaker out */
4688         spec->out_pins[1] = 0x10; /* headphone out */
4689         spec->shared_out_nid = 0x2;
4690
4691         spec->num_inputs = 3;
4692         spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4693         spec->adcs[1] = 0x8; /* analog mic2 */
4694         spec->adcs[2] = 0xa; /* what u hear */
4695         spec->shared_mic_nid = 0x7;
4696
4697         spec->input_pins[0] = 0x12;
4698         spec->input_pins[1] = 0x11;
4699         spec->input_pins[2] = 0x13;
4700
4701         /* SPDIF I/O */
4702         spec->dig_out = 0x05;
4703         spec->multiout.dig_out_nid = spec->dig_out;
4704         cfg->dig_out_pins[0] = 0x0c;
4705         cfg->dig_outs = 1;
4706         cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4707         spec->dig_in = 0x09;
4708         cfg->dig_in_pin = 0x0e;
4709         cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4710 }
4711
4712 static int patch_ca0132(struct hda_codec *codec)
4713 {
4714         struct ca0132_spec *spec;
4715         int err;
4716
4717         snd_printdd("patch_ca0132\n");
4718
4719         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4720         if (!spec)
4721                 return -ENOMEM;
4722         codec->spec = spec;
4723         spec->codec = codec;
4724
4725         spec->num_mixers = 1;
4726         spec->mixers[0] = ca0132_mixer;
4727
4728         spec->base_init_verbs = ca0132_base_init_verbs;
4729         spec->base_exit_verbs = ca0132_base_exit_verbs;
4730         spec->init_verbs[0] = ca0132_init_verbs0;
4731         spec->init_verbs[1] = ca0132_init_verbs1;
4732         spec->num_init_verbs = 2;
4733
4734         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4735
4736         ca0132_init_chip(codec);
4737
4738         ca0132_config(codec);
4739
4740         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4741         if (err < 0)
4742                 return err;
4743
4744         codec->patch_ops = ca0132_patch_ops;
4745
4746         return 0;
4747 }
4748
4749 /*
4750  * patch entries
4751  */
4752 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4753         { .id = 0x11020011, .name = "CA0132",     .patch = patch_ca0132 },
4754         {} /* terminator */
4755 };
4756
4757 MODULE_ALIAS("snd-hda-codec-id:11020011");
4758
4759 MODULE_LICENSE("GPL");
4760 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4761
4762 static struct hda_codec_preset_list ca0132_list = {
4763         .preset = snd_hda_preset_ca0132,
4764         .owner = THIS_MODULE,
4765 };
4766
4767 static int __init patch_ca0132_init(void)
4768 {
4769         return snd_hda_add_codec_preset(&ca0132_list);
4770 }
4771
4772 static void __exit patch_ca0132_exit(void)
4773 {
4774         snd_hda_delete_codec_preset(&ca0132_list);
4775 }
4776
4777 module_init(patch_ca0132_init)
4778 module_exit(patch_ca0132_exit)