Pileus Git - ~andy/linux/blob - drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70 #include "xhci-trace.h"
  71
  72 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  73                 struct xhci_virt_device *virt_dev,
  74                 struct xhci_event_cmd *event);
  75
  76 /*
  77  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  78  * address of the TRB.
  79  */
  80 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  81                 union xhci_trb *trb)
  82 {
  83         unsigned long segment_offset;
  84
  85         if (!seg || !trb || trb < seg->trbs)
  86                 return 0;
  87         /* offset in TRBs */
  88         segment_offset = trb - seg->trbs;
  89         if (segment_offset > TRBS_PER_SEGMENT)
  90                 return 0;
  91         return seg->dma + (segment_offset * sizeof(*trb));
  92 }
  93
  94 /* Does this link TRB point to the first segment in a ring,
  95  * or was the previous TRB the last TRB on the last segment in the ERST?
  96  */
  97 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  98                 struct xhci_segment *seg, union xhci_trb *trb)
  99 {
 100         if (ring == xhci->event_ring)
 101                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 102                         (seg->next == xhci->event_ring->first_seg);
 103         else
 104                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 105 }
 106
 107 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 108  * segment?  I.e. would the updated event TRB pointer step off the end of the
 109  * event seg?
 110  */
 111 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 112                 struct xhci_segment *seg, union xhci_trb *trb)
 113 {
 114         if (ring == xhci->event_ring)
 115                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 116         else
 117                 return TRB_TYPE_LINK_LE32(trb->link.control);
 118 }
 119
 120 static int enqueue_is_link_trb(struct xhci_ring *ring)
 121 {
 122         struct xhci_link_trb *link = &ring->enqueue->link;
 123         return TRB_TYPE_LINK_LE32(link->control);
 124 }
 125
 126 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring)
 127 {
 128         /* Enqueue pointer can be left pointing to the link TRB,
 129          * we must handle that
 130          */
 131         if (TRB_TYPE_LINK_LE32(ring->enqueue->link.control))
 132                 return ring->enq_seg->next->trbs;
 133         return ring->enqueue;
 134 }
 135
 136 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 137  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 138  * effect the ring dequeue or enqueue pointers.
 139  */
 140 static void next_trb(struct xhci_hcd *xhci,
 141                 struct xhci_ring *ring,
 142                 struct xhci_segment **seg,
 143                 union xhci_trb **trb)
 144 {
 145         if (last_trb(xhci, ring, *seg, *trb)) {
 146                 *seg = (*seg)->next;
 147                 *trb = ((*seg)->trbs);
 148         } else {
 149                 (*trb)++;
 150         }
 151 }
 152
 153 /*
 154  * See Cycle bit rules. SW is the consumer for the event ring only.
 155  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 156  */
 157 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 158 {
 159         ring->deq_updates++;
 160
 161         /*
 162          * If this is not event ring, and the dequeue pointer
 163          * is not on a link TRB, there is one more usable TRB
 164          */
 165         if (ring->type != TYPE_EVENT &&
 166                         !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 167                 ring->num_trbs_free++;
 168
 169         do {
 170                 /*
 171                  * Update the dequeue pointer further if that was a link TRB or
 172                  * we're at the end of an event ring segment (which doesn't have
 173                  * link TRBS)
 174                  */
 175                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 176                         if (ring->type == TYPE_EVENT &&
 177                                         last_trb_on_last_seg(xhci, ring,
 178                                                 ring->deq_seg, ring->dequeue)) {
 179                                 ring->cycle_state ^= 1;
 180                         }
 181                         ring->deq_seg = ring->deq_seg->next;
 182                         ring->dequeue = ring->deq_seg->trbs;
 183                 } else {
 184                         ring->dequeue++;
 185                 }
 186         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 187 }
 188
 189 /*
 190  * See Cycle bit rules. SW is the consumer for the event ring only.
 191  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 192  *
 193  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 194  * chain bit is set), then set the chain bit in all the following link TRBs.
 195  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 196  * have their chain bit cleared (so that each Link TRB is a separate TD).
 197  *
 198  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 199  * set, but other sections talk about dealing with the chain bit set.  This was
 200  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 201  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 202  *
 203  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 204  *                      prepare_transfer()?
 205  */
 206 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 207                         bool more_trbs_coming)
 208 {
 209         u32 chain;
 210         union xhci_trb *next;
 211
 212         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 213         /* If this is not event ring, there is one less usable TRB */
 214         if (ring->type != TYPE_EVENT &&
 215                         !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 216                 ring->num_trbs_free--;
 217         next = ++(ring->enqueue);
 218
 219         ring->enq_updates++;
 220         /* Update the dequeue pointer further if that was a link TRB or we're at
 221          * the end of an event ring segment (which doesn't have link TRBS)
 222          */
 223         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 224                 if (ring->type != TYPE_EVENT) {
 225                         /*
 226                          * If the caller doesn't plan on enqueueing more
 227                          * TDs before ringing the doorbell, then we
 228                          * don't want to give the link TRB to the
 229                          * hardware just yet.  We'll give the link TRB
 230                          * back in prepare_ring() just before we enqueue
 231                          * the TD at the top of the ring.
 232                          */
 233                         if (!chain && !more_trbs_coming)
 234                                 break;
 235
 236                         /* If we're not dealing with 0.95 hardware or
 237                          * isoc rings on AMD 0.96 host,
 238                          * carry over the chain bit of the previous TRB
 239                          * (which may mean the chain bit is cleared).
 240                          */
 241                         if (!(ring->type == TYPE_ISOC &&
 242                                         (xhci->quirks & XHCI_AMD_0x96_HOST))
 243                                                 && !xhci_link_trb_quirk(xhci)) {
 244                                 next->link.control &=
 245                                         cpu_to_le32(~TRB_CHAIN);
 246                                 next->link.control |=
 247                                         cpu_to_le32(chain);
 248                         }
 249                         /* Give this link TRB to the hardware */
 250                         wmb();
 251                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
 252
 253                         /* Toggle the cycle bit after the last ring segment. */
 254                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 255                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 256                         }
 257                 }
 258                 ring->enq_seg = ring->enq_seg->next;
 259                 ring->enqueue = ring->enq_seg->trbs;
 260                 next = ring->enqueue;
 261         }
 262 }
 263
 264 /*
 265  * Check to see if there's room to enqueue num_trbs on the ring and make sure
 266  * enqueue pointer will not advance into dequeue segment. See rules above.
 267  */
 268 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 269                 unsigned int num_trbs)
 270 {
 271         int num_trbs_in_deq_seg;
 272
 273         if (ring->num_trbs_free < num_trbs)
 274                 return 0;
 275
 276         if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 277                 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 278                 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 279                         return 0;
 280         }
 281
 282         return 1;
 283 }
 284
 285 /* Ring the host controller doorbell after placing a command on the ring */
 286 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 287 {
 288         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 289                 return;
 290
 291         xhci_dbg(xhci, "// Ding dong!\n");
 292         writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 293         /* Flush PCI posted writes */
 294         readl(&xhci->dba->doorbell[0]);
 295 }
 296
 297 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 298 {
 299         u64 temp_64;
 300         int ret;
 301
 302         xhci_dbg(xhci, "Abort command ring\n");
 303
 304         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 305                 xhci_dbg(xhci, "The command ring isn't running, "
 306                                 "Have the command ring been stopped?\n");
 307                 return 0;
 308         }
 309
 310         temp_64 = readq(&xhci->op_regs->cmd_ring);
 311         if (!(temp_64 & CMD_RING_RUNNING)) {
 312                 xhci_dbg(xhci, "Command ring had been stopped\n");
 313                 return 0;
 314         }
 315         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 316         writeq(temp_64 | CMD_RING_ABORT, &xhci->op_regs->cmd_ring);
 317
 318         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 319          * time the completion od all xHCI commands, including
 320          * the Command Abort operation. If software doesn't see
 321          * CRR negated in a timely manner (e.g. longer than 5
 322          * seconds), then it should assume that the there are
 323          * larger problems with the xHC and assert HCRST.
 324          */
 325         ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 326                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 327         if (ret < 0) {
 328                 xhci_err(xhci, "Stopped the command ring failed, "
 329                                 "maybe the host is dead\n");
 330                 xhci->xhc_state |= XHCI_STATE_DYING;
 331                 xhci_quiesce(xhci);
 332                 xhci_halt(xhci);
 333                 return -ESHUTDOWN;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int xhci_queue_cd(struct xhci_hcd *xhci,
 340                 struct xhci_command *command,
 341                 union xhci_trb *cmd_trb)
 342 {
 343         struct xhci_cd *cd;
 344         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 345         if (!cd)
 346                 return -ENOMEM;
 347         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 348
 349         cd->command = command;
 350         cd->cmd_trb = cmd_trb;
 351         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 352
 353         return 0;
 354 }
 355
 356 /*
 357  * Cancel the command which has issue.
 358  *
 359  * Some commands may hang due to waiting for acknowledgement from
 360  * usb device. It is outside of the xHC's ability to control and
 361  * will cause the command ring is blocked. When it occurs software
 362  * should intervene to recover the command ring.
 363  * See Section 4.6.1.1 and 4.6.1.2
 364  */
 365 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 366                 union xhci_trb *cmd_trb)
 367 {
 368         int retval = 0;
 369         unsigned long flags;
 370
 371         spin_lock_irqsave(&xhci->lock, flags);
 372
 373         if (xhci->xhc_state & XHCI_STATE_DYING) {
 374                 xhci_warn(xhci, "Abort the command ring,"
 375                                 " but the xHCI is dead.\n");
 376                 retval = -ESHUTDOWN;
 377                 goto fail;
 378         }
 379
 380         /* queue the cmd desriptor to cancel_cmd_list */
 381         retval = xhci_queue_cd(xhci, command, cmd_trb);
 382         if (retval) {
 383                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 384                 goto fail;
 385         }
 386
 387         /* abort command ring */
 388         retval = xhci_abort_cmd_ring(xhci);
 389         if (retval) {
 390                 xhci_err(xhci, "Abort command ring failed\n");
 391                 if (unlikely(retval == -ESHUTDOWN)) {
 392                         spin_unlock_irqrestore(&xhci->lock, flags);
 393                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 394                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 395                         return retval;
 396                 }
 397         }
 398
 399 fail:
 400         spin_unlock_irqrestore(&xhci->lock, flags);
 401         return retval;
 402 }
 403
 404 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 405                 unsigned int slot_id,
 406                 unsigned int ep_index,
 407                 unsigned int stream_id)
 408 {
 409         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 410         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 411         unsigned int ep_state = ep->ep_state;
 412
 413         /* Don't ring the doorbell for this endpoint if there are pending
 414          * cancellations because we don't want to interrupt processing.
 415          * We don't want to restart any stream rings if there's a set dequeue
 416          * pointer command pending because the device can choose to start any
 417          * stream once the endpoint is on the HW schedule.
 418          * FIXME - check all the stream rings for pending cancellations.
 419          */
 420         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 421             (ep_state & EP_HALTED))
 422                 return;
 423         writel(DB_VALUE(ep_index, stream_id), db_addr);
 424         /* The CPU has better things to do at this point than wait for a
 425          * write-posting flush.  It'll get there soon enough.
 426          */
 427 }
 428
 429 /* Ring the doorbell for any rings with pending URBs */
 430 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 431                 unsigned int slot_id,
 432                 unsigned int ep_index)
 433 {
 434         unsigned int stream_id;
 435         struct xhci_virt_ep *ep;
 436
 437         ep = &xhci->devs[slot_id]->eps[ep_index];
 438
 439         /* A ring has pending URBs if its TD list is not empty */
 440         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 441                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 442                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 443                 return;
 444         }
 445
 446         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 447                         stream_id++) {
 448                 struct xhci_stream_info *stream_info = ep->stream_info;
 449                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 450                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 451                                                 stream_id);
 452         }
 453 }
 454
 455 /*
 456  * Find the segment that trb is in.  Start searching in start_seg.
 457  * If we must move past a segment that has a link TRB with a toggle cycle state
 458  * bit set, then we will toggle the value pointed at by cycle_state.
 459  */
 460 static struct xhci_segment *find_trb_seg(
 461                 struct xhci_segment *start_seg,
 462                 union xhci_trb  *trb, int *cycle_state)
 463 {
 464         struct xhci_segment *cur_seg = start_seg;
 465         struct xhci_generic_trb *generic_trb;
 466
 467         while (cur_seg->trbs > trb ||
 468                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 469                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 470                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 471                         *cycle_state ^= 0x1;
 472                 cur_seg = cur_seg->next;
 473                 if (cur_seg == start_seg)
 474                         /* Looped over the entire list.  Oops! */
 475                         return NULL;
 476         }
 477         return cur_seg;
 478 }
 479
 480
 481 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 482                 unsigned int slot_id, unsigned int ep_index,
 483                 unsigned int stream_id)
 484 {
 485         struct xhci_virt_ep *ep;
 486
 487         ep = &xhci->devs[slot_id]->eps[ep_index];
 488         /* Common case: no streams */
 489         if (!(ep->ep_state & EP_HAS_STREAMS))
 490                 return ep->ring;
 491
 492         if (stream_id == 0) {
 493                 xhci_warn(xhci,
 494                                 "WARN: Slot ID %u, ep index %u has streams, "
 495                                 "but URB has no stream ID.\n",
 496                                 slot_id, ep_index);
 497                 return NULL;
 498         }
 499
 500         if (stream_id < ep->stream_info->num_streams)
 501                 return ep->stream_info->stream_rings[stream_id];
 502
 503         xhci_warn(xhci,
 504                         "WARN: Slot ID %u, ep index %u has "
 505                         "stream IDs 1 to %u allocated, "
 506                         "but stream ID %u is requested.\n",
 507                         slot_id, ep_index,
 508                         ep->stream_info->num_streams - 1,
 509                         stream_id);
 510         return NULL;
 511 }
 512
 513 /* Get the right ring for the given URB.
 514  * If the endpoint supports streams, boundary check the URB's stream ID.
 515  * If the endpoint doesn't support streams, return the singular endpoint ring.
 516  */
 517 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 518                 struct urb *urb)
 519 {
 520         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 521                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 522 }
 523
 524 /*
 525  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 526  * Record the new state of the xHC's endpoint ring dequeue segment,
 527  * dequeue pointer, and new consumer cycle state in state.
 528  * Update our internal representation of the ring's dequeue pointer.
 529  *
 530  * We do this in three jumps:
 531  *  - First we update our new ring state to be the same as when the xHC stopped.
 532  *  - Then we traverse the ring to find the segment that contains
 533  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 534  *    any link TRBs with the toggle cycle bit set.
 535  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 536  *    if we've moved it past a link TRB with the toggle cycle bit set.
 537  *
 538  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 539  * with correct __le32 accesses they should work fine.  Only users of this are
 540  * in here.
 541  */
 542 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 543                 unsigned int slot_id, unsigned int ep_index,
 544                 unsigned int stream_id, struct xhci_td *cur_td,
 545                 struct xhci_dequeue_state *state)
 546 {
 547         struct xhci_virt_device *dev = xhci->devs[slot_id];
 548         struct xhci_ring *ep_ring;
 549         struct xhci_generic_trb *trb;
 550         struct xhci_ep_ctx *ep_ctx;
 551         dma_addr_t addr;
 552
 553         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 554                         ep_index, stream_id);
 555         if (!ep_ring) {
 556                 xhci_warn(xhci, "WARN can't find new dequeue state "
 557                                 "for invalid stream ID %u.\n",
 558                                 stream_id);
 559                 return;
 560         }
 561         state->new_cycle_state = 0;
 562         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 563                         "Finding segment containing stopped TRB.");
 564         state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 565                         dev->eps[ep_index].stopped_trb,
 566                         &state->new_cycle_state);
 567         if (!state->new_deq_seg) {
 568                 WARN_ON(1);
 569                 return;
 570         }
 571
 572         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 573         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 574                         "Finding endpoint context");
 575         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 576         state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 577
 578         state->new_deq_ptr = cur_td->last_trb;
 579         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 580                         "Finding segment containing last TRB in TD.");
 581         state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 582                         state->new_deq_ptr,
 583                         &state->new_cycle_state);
 584         if (!state->new_deq_seg) {
 585                 WARN_ON(1);
 586                 return;
 587         }
 588
 589         trb = &state->new_deq_ptr->generic;
 590         if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 591             (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 592                 state->new_cycle_state ^= 0x1;
 593         next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 594
 595         /*
 596          * If there is only one segment in a ring, find_trb_seg()'s while loop
 597          * will not run, and it will return before it has a chance to see if it
 598          * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 599          * ended just before the link TRB on a one-segment ring, or if the TD
 600          * wrapped around the top of the ring, because it doesn't have the TD in
 601          * question.  Look for the one-segment case where stalled TRB's address
 602          * is greater than the new dequeue pointer address.
 603          */
 604         if (ep_ring->first_seg == ep_ring->first_seg->next &&
 605                         state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 606                 state->new_cycle_state ^= 0x1;
 607         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 608                         "Cycle state = 0x%x", state->new_cycle_state);
 609
 610         /* Don't update the ring cycle state for the producer (us). */
 611         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 612                         "New dequeue segment = %p (virtual)",
 613                         state->new_deq_seg);
 614         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 615         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 616                         "New dequeue pointer = 0x%llx (DMA)",
 617                         (unsigned long long) addr);
 618 }
 619
 620 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 621  * (The last TRB actually points to the ring enqueue pointer, which is not part
 622  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 623  */
 624 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 625                 struct xhci_td *cur_td, bool flip_cycle)
 626 {
 627         struct xhci_segment *cur_seg;
 628         union xhci_trb *cur_trb;
 629
 630         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 631                         true;
 632                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 633                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 634                         /* Unchain any chained Link TRBs, but
 635                          * leave the pointers intact.
 636                          */
 637                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 638                         /* Flip the cycle bit (link TRBs can't be the first
 639                          * or last TRB).
 640                          */
 641                         if (flip_cycle)
 642                                 cur_trb->generic.field[3] ^=
 643                                         cpu_to_le32(TRB_CYCLE);
 644                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 645                                         "Cancel (unchain) link TRB");
 646                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 647                                         "Address = %p (0x%llx dma); "
 648                                         "in seg %p (0x%llx dma)",
 649                                         cur_trb,
 650                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 651                                         cur_seg,
 652                                         (unsigned long long)cur_seg->dma);
 653                 } else {
 654                         cur_trb->generic.field[0] = 0;
 655                         cur_trb->generic.field[1] = 0;
 656                         cur_trb->generic.field[2] = 0;
 657                         /* Preserve only the cycle bit of this TRB */
 658                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 659                         /* Flip the cycle bit except on the first or last TRB */
 660                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 661                                         cur_trb != cur_td->last_trb)
 662                                 cur_trb->generic.field[3] ^=
 663                                         cpu_to_le32(TRB_CYCLE);
 664                         cur_trb->generic.field[3] |= cpu_to_le32(
 665                                 TRB_TYPE(TRB_TR_NOOP));
 666                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 667                                         "TRB to noop at offset 0x%llx",
 668                                         (unsigned long long)
 669                                         xhci_trb_virt_to_dma(cur_seg, cur_trb));
 670                 }
 671                 if (cur_trb == cur_td->last_trb)
 672                         break;
 673         }
 674 }
 675
 676 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 677                 unsigned int ep_index, unsigned int stream_id,
 678                 struct xhci_segment *deq_seg,
 679                 union xhci_trb *deq_ptr, u32 cycle_state);
 680
 681 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 682                 unsigned int slot_id, unsigned int ep_index,
 683                 unsigned int stream_id,
 684                 struct xhci_dequeue_state *deq_state)
 685 {
 686         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 687
 688         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 689                         "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 690                         "new deq ptr = %p (0x%llx dma), new cycle = %u",
 691                         deq_state->new_deq_seg,
 692                         (unsigned long long)deq_state->new_deq_seg->dma,
 693                         deq_state->new_deq_ptr,
 694                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 695                         deq_state->new_cycle_state);
 696         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 697                         deq_state->new_deq_seg,
 698                         deq_state->new_deq_ptr,
 699                         (u32) deq_state->new_cycle_state);
 700         /* Stop the TD queueing code from ringing the doorbell until
 701          * this command completes.  The HC won't set the dequeue pointer
 702          * if the ring is running, and ringing the doorbell starts the
 703          * ring running.
 704          */
 705         ep->ep_state |= SET_DEQ_PENDING;
 706 }
 707
 708 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 709                 struct xhci_virt_ep *ep)
 710 {
 711         ep->ep_state &= ~EP_HALT_PENDING;
 712         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 713          * timer is running on another CPU, we don't decrement stop_cmds_pending
 714          * (since we didn't successfully stop the watchdog timer).
 715          */
 716         if (del_timer(&ep->stop_cmd_timer))
 717                 ep->stop_cmds_pending--;
 718 }
 719
 720 /* Must be called with xhci->lock held in interrupt context */
 721 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 722                 struct xhci_td *cur_td, int status)
 723 {
 724         struct usb_hcd *hcd;
 725         struct urb      *urb;
 726         struct urb_priv *urb_priv;
 727
 728         urb = cur_td->urb;
 729         urb_priv = urb->hcpriv;
 730         urb_priv->td_cnt++;
 731         hcd = bus_to_hcd(urb->dev->bus);
 732
 733         /* Only giveback urb when this is the last td in urb */
 734         if (urb_priv->td_cnt == urb_priv->length) {
 735                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 736                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 737                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 738                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 739                                         usb_amd_quirk_pll_enable();
 740                         }
 741                 }
 742                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 743
 744                 spin_unlock(&xhci->lock);
 745                 usb_hcd_giveback_urb(hcd, urb, status);
 746                 xhci_urb_free_priv(xhci, urb_priv);
 747                 spin_lock(&xhci->lock);
 748         }
 749 }
 750
 751 /*
 752  * When we get a command completion for a Stop Endpoint Command, we need to
 753  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 754  *
 755  *  1. If the HW was in the middle of processing the TD that needs to be
 756  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 757  *     in the TD with a Set Dequeue Pointer Command.
 758  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 759  *     bit cleared) so that the HW will skip over them.
 760  */
 761 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 762                 union xhci_trb *trb, struct xhci_event_cmd *event)
 763 {
 764         unsigned int ep_index;
 765         struct xhci_virt_device *virt_dev;
 766         struct xhci_ring *ep_ring;
 767         struct xhci_virt_ep *ep;
 768         struct list_head *entry;
 769         struct xhci_td *cur_td = NULL;
 770         struct xhci_td *last_unlinked_td;
 771
 772         struct xhci_dequeue_state deq_state;
 773
 774         if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 775                 virt_dev = xhci->devs[slot_id];
 776                 if (virt_dev)
 777                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 778                                 event);
 779                 else
 780                         xhci_warn(xhci, "Stop endpoint command "
 781                                 "completion for disabled slot %u\n",
 782                                 slot_id);
 783                 return;
 784         }
 785
 786         memset(&deq_state, 0, sizeof(deq_state));
 787         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 788         ep = &xhci->devs[slot_id]->eps[ep_index];
 789
 790         if (list_empty(&ep->cancelled_td_list)) {
 791                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 792                 ep->stopped_td = NULL;
 793                 ep->stopped_trb = NULL;
 794                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 795                 return;
 796         }
 797
 798         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 799          * We have the xHCI lock, so nothing can modify this list until we drop
 800          * it.  We're also in the event handler, so we can't get re-interrupted
 801          * if another Stop Endpoint command completes
 802          */
 803         list_for_each(entry, &ep->cancelled_td_list) {
 804                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 805                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 806                                 "Removing canceled TD starting at 0x%llx (dma).",
 807                                 (unsigned long long)xhci_trb_virt_to_dma(
 808                                         cur_td->start_seg, cur_td->first_trb));
 809                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 810                 if (!ep_ring) {
 811                         /* This shouldn't happen unless a driver is mucking
 812                          * with the stream ID after submission.  This will
 813                          * leave the TD on the hardware ring, and the hardware
 814                          * will try to execute it, and may access a buffer
 815                          * that has already been freed.  In the best case, the
 816                          * hardware will execute it, and the event handler will
 817                          * ignore the completion event for that TD, since it was
 818                          * removed from the td_list for that endpoint.  In
 819                          * short, don't muck with the stream ID after
 820                          * submission.
 821                          */
 822                         xhci_warn(xhci, "WARN Cancelled URB %p "
 823                                         "has invalid stream ID %u.\n",
 824                                         cur_td->urb,
 825                                         cur_td->urb->stream_id);
 826                         goto remove_finished_td;
 827                 }
 828                 /*
 829                  * If we stopped on the TD we need to cancel, then we have to
 830                  * move the xHC endpoint ring dequeue pointer past this TD.
 831                  */
 832                 if (cur_td == ep->stopped_td)
 833                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 834                                         cur_td->urb->stream_id,
 835                                         cur_td, &deq_state);
 836                 else
 837                         td_to_noop(xhci, ep_ring, cur_td, false);
 838 remove_finished_td:
 839                 /*
 840                  * The event handler won't see a completion for this TD anymore,
 841                  * so remove it from the endpoint ring's TD list.  Keep it in
 842                  * the cancelled TD list for URB completion later.
 843                  */
 844                 list_del_init(&cur_td->td_list);
 845         }
 846         last_unlinked_td = cur_td;
 847         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 848
 849         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 850         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 851                 xhci_queue_new_dequeue_state(xhci,
 852                                 slot_id, ep_index,
 853                                 ep->stopped_td->urb->stream_id,
 854                                 &deq_state);
 855                 xhci_ring_cmd_db(xhci);
 856         } else {
 857                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 858                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 859         }
 860
 861         /* Clear stopped_td and stopped_trb if endpoint is not halted */
 862         if (!(ep->ep_state & EP_HALTED)) {
 863                 ep->stopped_td = NULL;
 864                 ep->stopped_trb = NULL;
 865         }
 866
 867         /*
 868          * Drop the lock and complete the URBs in the cancelled TD list.
 869          * New TDs to be cancelled might be added to the end of the list before
 870          * we can complete all the URBs for the TDs we already unlinked.
 871          * So stop when we've completed the URB for the last TD we unlinked.
 872          */
 873         do {
 874                 cur_td = list_entry(ep->cancelled_td_list.next,
 875                                 struct xhci_td, cancelled_td_list);
 876                 list_del_init(&cur_td->cancelled_td_list);
 877
 878                 /* Clean up the cancelled URB */
 879                 /* Doesn't matter what we pass for status, since the core will
 880                  * just overwrite it (because the URB has been unlinked).
 881                  */
 882                 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 883
 884                 /* Stop processing the cancelled list if the watchdog timer is
 885                  * running.
 886                  */
 887                 if (xhci->xhc_state & XHCI_STATE_DYING)
 888                         return;
 889         } while (cur_td != last_unlinked_td);
 890
 891         /* Return to the event handler with xhci->lock re-acquired */
 892 }
 893
 894 /* Watchdog timer function for when a stop endpoint command fails to complete.
 895  * In this case, we assume the host controller is broken or dying or dead.  The
 896  * host may still be completing some other events, so we have to be careful to
 897  * let the event ring handler and the URB dequeueing/enqueueing functions know
 898  * through xhci->state.
 899  *
 900  * The timer may also fire if the host takes a very long time to respond to the
 901  * command, and the stop endpoint command completion handler cannot delete the
 902  * timer before the timer function is called.  Another endpoint cancellation may
 903  * sneak in before the timer function can grab the lock, and that may queue
 904  * another stop endpoint command and add the timer back.  So we cannot use a
 905  * simple flag to say whether there is a pending stop endpoint command for a
 906  * particular endpoint.
 907  *
 908  * Instead we use a combination of that flag and a counter for the number of
 909  * pending stop endpoint commands.  If the timer is the tail end of the last
 910  * stop endpoint command, and the endpoint's command is still pending, we assume
 911  * the host is dying.
 912  */
 913 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 914 {
 915         struct xhci_hcd *xhci;
 916         struct xhci_virt_ep *ep;
 917         struct xhci_virt_ep *temp_ep;
 918         struct xhci_ring *ring;
 919         struct xhci_td *cur_td;
 920         int ret, i, j;
 921         unsigned long flags;
 922
 923         ep = (struct xhci_virt_ep *) arg;
 924         xhci = ep->xhci;
 925
 926         spin_lock_irqsave(&xhci->lock, flags);
 927
 928         ep->stop_cmds_pending--;
 929         if (xhci->xhc_state & XHCI_STATE_DYING) {
 930                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 931                                 "Stop EP timer ran, but another timer marked "
 932                                 "xHCI as DYING, exiting.");
 933                 spin_unlock_irqrestore(&xhci->lock, flags);
 934                 return;
 935         }
 936         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 937                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 938                                 "Stop EP timer ran, but no command pending, "
 939                                 "exiting.");
 940                 spin_unlock_irqrestore(&xhci->lock, flags);
 941                 return;
 942         }
 943
 944         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 945         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 946         /* Oops, HC is dead or dying or at least not responding to the stop
 947          * endpoint command.
 948          */
 949         xhci->xhc_state |= XHCI_STATE_DYING;
 950         /* Disable interrupts from the host controller and start halting it */
 951         xhci_quiesce(xhci);
 952         spin_unlock_irqrestore(&xhci->lock, flags);
 953
 954         ret = xhci_halt(xhci);
 955
 956         spin_lock_irqsave(&xhci->lock, flags);
 957         if (ret < 0) {
 958                 /* This is bad; the host is not responding to commands and it's
 959                  * not allowing itself to be halted.  At least interrupts are
 960                  * disabled. If we call usb_hc_died(), it will attempt to
 961                  * disconnect all device drivers under this host.  Those
 962                  * disconnect() methods will wait for all URBs to be unlinked,
 963                  * so we must complete them.
 964                  */
 965                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 966                 xhci_warn(xhci, "Completing active URBs anyway.\n");
 967                 /* We could turn all TDs on the rings to no-ops.  This won't
 968                  * help if the host has cached part of the ring, and is slow if
 969                  * we want to preserve the cycle bit.  Skip it and hope the host
 970                  * doesn't touch the memory.
 971                  */
 972         }
 973         for (i = 0; i < MAX_HC_SLOTS; i++) {
 974                 if (!xhci->devs[i])
 975                         continue;
 976                 for (j = 0; j < 31; j++) {
 977                         temp_ep = &xhci->devs[i]->eps[j];
 978                         ring = temp_ep->ring;
 979                         if (!ring)
 980                                 continue;
 981                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 982                                         "Killing URBs for slot ID %u, "
 983                                         "ep index %u", i, j);
 984                         while (!list_empty(&ring->td_list)) {
 985                                 cur_td = list_first_entry(&ring->td_list,
 986                                                 struct xhci_td,
 987                                                 td_list);
 988                                 list_del_init(&cur_td->td_list);
 989                                 if (!list_empty(&cur_td->cancelled_td_list))
 990                                         list_del_init(&cur_td->cancelled_td_list);
 991                                 xhci_giveback_urb_in_irq(xhci, cur_td,
 992                                                 -ESHUTDOWN);
 993                         }
 994                         while (!list_empty(&temp_ep->cancelled_td_list)) {
 995                                 cur_td = list_first_entry(
 996                                                 &temp_ep->cancelled_td_list,
 997                                                 struct xhci_td,
 998                                                 cancelled_td_list);
 999                                 list_del_init(&cur_td->cancelled_td_list);
1000                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1001                                                 -ESHUTDOWN);
1002                         }
1003                 }
1004         }
1005         spin_unlock_irqrestore(&xhci->lock, flags);
1006         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1007                         "Calling usb_hc_died()");
1008         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1009         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1010                         "xHCI host controller is dead.");
1011 }
1012
1013
1014 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1015                 struct xhci_virt_device *dev,
1016                 struct xhci_ring *ep_ring,
1017                 unsigned int ep_index)
1018 {
1019         union xhci_trb *dequeue_temp;
1020         int num_trbs_free_temp;
1021         bool revert = false;
1022
1023         num_trbs_free_temp = ep_ring->num_trbs_free;
1024         dequeue_temp = ep_ring->dequeue;
1025
1026         /* If we get two back-to-back stalls, and the first stalled transfer
1027          * ends just before a link TRB, the dequeue pointer will be left on
1028          * the link TRB by the code in the while loop.  So we have to update
1029          * the dequeue pointer one segment further, or we'll jump off
1030          * the segment into la-la-land.
1031          */
1032         if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1033                 ep_ring->deq_seg = ep_ring->deq_seg->next;
1034                 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1035         }
1036
1037         while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1038                 /* We have more usable TRBs */
1039                 ep_ring->num_trbs_free++;
1040                 ep_ring->dequeue++;
1041                 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1042                                 ep_ring->dequeue)) {
1043                         if (ep_ring->dequeue ==
1044                                         dev->eps[ep_index].queued_deq_ptr)
1045                                 break;
1046                         ep_ring->deq_seg = ep_ring->deq_seg->next;
1047                         ep_ring->dequeue = ep_ring->deq_seg->trbs;
1048                 }
1049                 if (ep_ring->dequeue == dequeue_temp) {
1050                         revert = true;
1051                         break;
1052                 }
1053         }
1054
1055         if (revert) {
1056                 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1057                 ep_ring->num_trbs_free = num_trbs_free_temp;
1058         }
1059 }
1060
1061 /*
1062  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1063  * we need to clear the set deq pending flag in the endpoint ring state, so that
1064  * the TD queueing code can ring the doorbell again.  We also need to ring the
1065  * endpoint doorbell to restart the ring, but only if there aren't more
1066  * cancellations pending.
1067  */
1068 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1069                 union xhci_trb *trb, u32 cmd_comp_code)
1070 {
1071         unsigned int ep_index;
1072         unsigned int stream_id;
1073         struct xhci_ring *ep_ring;
1074         struct xhci_virt_device *dev;
1075         struct xhci_ep_ctx *ep_ctx;
1076         struct xhci_slot_ctx *slot_ctx;
1077
1078         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1079         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1080         dev = xhci->devs[slot_id];
1081
1082         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1083         if (!ep_ring) {
1084                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1085                                 "freed stream ID %u\n",
1086                                 stream_id);
1087                 /* XXX: Harmless??? */
1088                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1089                 return;
1090         }
1091
1092         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1093         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1094
1095         if (cmd_comp_code != COMP_SUCCESS) {
1096                 unsigned int ep_state;
1097                 unsigned int slot_state;
1098
1099                 switch (cmd_comp_code) {
1100                 case COMP_TRB_ERR:
1101                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1102                                         "of stream ID configuration\n");
1103                         break;
1104                 case COMP_CTX_STATE:
1105                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1106                                         "to incorrect slot or ep state.\n");
1107                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1108                         ep_state &= EP_STATE_MASK;
1109                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1110                         slot_state = GET_SLOT_STATE(slot_state);
1111                         xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1112                                         "Slot state = %u, EP state = %u",
1113                                         slot_state, ep_state);
1114                         break;
1115                 case COMP_EBADSLT:
1116                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1117                                         "slot %u was not enabled.\n", slot_id);
1118                         break;
1119                 default:
1120                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1121                                         "completion code of %u.\n",
1122                                   cmd_comp_code);
1123                         break;
1124                 }
1125                 /* OK what do we do now?  The endpoint state is hosed, and we
1126                  * should never get to this point if the synchronization between
1127                  * queueing, and endpoint state are correct.  This might happen
1128                  * if the device gets disconnected after we've finished
1129                  * cancelling URBs, which might not be an error...
1130                  */
1131         } else {
1132                 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1133                         "Successful Set TR Deq Ptr cmd, deq = @%08llx",
1134                          le64_to_cpu(ep_ctx->deq));
1135                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1136                                          dev->eps[ep_index].queued_deq_ptr) ==
1137                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1138                         /* Update the ring's dequeue segment and dequeue pointer
1139                          * to reflect the new position.
1140                          */
1141                         update_ring_for_set_deq_completion(xhci, dev,
1142                                 ep_ring, ep_index);
1143                 } else {
1144                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1145                                         "Ptr command & xHCI internal state.\n");
1146                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1147                                         dev->eps[ep_index].queued_deq_seg,
1148                                         dev->eps[ep_index].queued_deq_ptr);
1149                 }
1150         }
1151
1152         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1153         dev->eps[ep_index].queued_deq_seg = NULL;
1154         dev->eps[ep_index].queued_deq_ptr = NULL;
1155         /* Restart any rings with pending URBs */
1156         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1157 }
1158
1159 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1160                 union xhci_trb *trb, u32 cmd_comp_code)
1161 {
1162         unsigned int ep_index;
1163
1164         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1165         /* This command will only fail if the endpoint wasn't halted,
1166          * but we don't care.
1167          */
1168         xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1169                 "Ignoring reset ep completion code of %u", cmd_comp_code);
1170
1171         /* HW with the reset endpoint quirk needs to have a configure endpoint
1172          * command complete before the endpoint can be used.  Queue that here
1173          * because the HW can't handle two commands being queued in a row.
1174          */
1175         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1176                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1177                                 "Queueing configure endpoint command");
1178                 xhci_queue_configure_endpoint(xhci,
1179                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1180                                 false);
1181                 xhci_ring_cmd_db(xhci);
1182         } else {
1183                 /* Clear our internal halted state and restart the ring(s) */
1184                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1185                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1186         }
1187 }
1188
1189 /* Complete the command and detele it from the devcie's command queue.
1190  */
1191 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1192                 struct xhci_command *command, u32 status)
1193 {
1194         command->status = status;
1195         list_del(&command->cmd_list);
1196         if (command->completion)
1197                 complete(command->completion);
1198         else
1199                 xhci_free_command(xhci, command);
1200 }
1201
1202
1203 /* Check to see if a command in the device's command queue matches this one.
1204  * Signal the completion or free the command, and return 1.  Return 0 if the
1205  * completed command isn't at the head of the command list.
1206  */
1207 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1208                 struct xhci_virt_device *virt_dev,
1209                 struct xhci_event_cmd *event)
1210 {
1211         struct xhci_command *command;
1212
1213         if (list_empty(&virt_dev->cmd_list))
1214                 return 0;
1215
1216         command = list_entry(virt_dev->cmd_list.next,
1217                         struct xhci_command, cmd_list);
1218         if (xhci->cmd_ring->dequeue != command->command_trb)
1219                 return 0;
1220
1221         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1222                         GET_COMP_CODE(le32_to_cpu(event->status)));
1223         return 1;
1224 }
1225
1226 /*
1227  * Finding the command trb need to be cancelled and modifying it to
1228  * NO OP command. And if the command is in device's command wait
1229  * list, finishing and freeing it.
1230  *
1231  * If we can't find the command trb, we think it had already been
1232  * executed.
1233  */
1234 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1235 {
1236         struct xhci_segment *cur_seg;
1237         union xhci_trb *cmd_trb;
1238         u32 cycle_state;
1239
1240         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1241                 return;
1242
1243         /* find the current segment of command ring */
1244         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1245                         xhci->cmd_ring->dequeue, &cycle_state);
1246
1247         if (!cur_seg) {
1248                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1249                                 xhci->cmd_ring->dequeue,
1250                                 (unsigned long long)
1251                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1252                                         xhci->cmd_ring->dequeue));
1253                 xhci_debug_ring(xhci, xhci->cmd_ring);
1254                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1255                 return;
1256         }
1257
1258         /* find the command trb matched by cd from command ring */
1259         for (cmd_trb = xhci->cmd_ring->dequeue;
1260                         cmd_trb != xhci->cmd_ring->enqueue;
1261                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1262                 /* If the trb is link trb, continue */
1263                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1264                         continue;
1265
1266                 if (cur_cd->cmd_trb == cmd_trb) {
1267
1268                         /* If the command in device's command list, we should
1269                          * finish it and free the command structure.
1270                          */
1271                         if (cur_cd->command)
1272                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1273                                         cur_cd->command, COMP_CMD_STOP);
1274
1275                         /* get cycle state from the origin command trb */
1276                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1277                                 & TRB_CYCLE;
1278
1279                         /* modify the command trb to NO OP command */
1280                         cmd_trb->generic.field[0] = 0;
1281                         cmd_trb->generic.field[1] = 0;
1282                         cmd_trb->generic.field[2] = 0;
1283                         cmd_trb->generic.field[3] = cpu_to_le32(
1284                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1285                         break;
1286                 }
1287         }
1288 }
1289
1290 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1291 {
1292         struct xhci_cd *cur_cd, *next_cd;
1293
1294         if (list_empty(&xhci->cancel_cmd_list))
1295                 return;
1296
1297         list_for_each_entry_safe(cur_cd, next_cd,
1298                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1299                 xhci_cmd_to_noop(xhci, cur_cd);
1300                 list_del(&cur_cd->cancel_cmd_list);
1301                 kfree(cur_cd);
1302         }
1303 }
1304
1305 /*
1306  * traversing the cancel_cmd_list. If the command descriptor according
1307  * to cmd_trb is found, the function free it and return 1, otherwise
1308  * return 0.
1309  */
1310 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1311                 union xhci_trb *cmd_trb)
1312 {
1313         struct xhci_cd *cur_cd, *next_cd;
1314
1315         if (list_empty(&xhci->cancel_cmd_list))
1316                 return 0;
1317
1318         list_for_each_entry_safe(cur_cd, next_cd,
1319                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1320                 if (cur_cd->cmd_trb == cmd_trb) {
1321                         if (cur_cd->command)
1322                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1323                                         cur_cd->command, COMP_CMD_STOP);
1324                         list_del(&cur_cd->cancel_cmd_list);
1325                         kfree(cur_cd);
1326                         return 1;
1327                 }
1328         }
1329
1330         return 0;
1331 }
1332
1333 /*
1334  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1335  * trb pointed by the command ring dequeue pointer is the trb we want to
1336  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1337  * traverse the cancel_cmd_list to trun the all of the commands according
1338  * to command descriptor to NO-OP trb.
1339  */
1340 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1341                 int cmd_trb_comp_code)
1342 {
1343         int cur_trb_is_good = 0;
1344
1345         /* Searching the cmd trb pointed by the command ring dequeue
1346          * pointer in command descriptor list. If it is found, free it.
1347          */
1348         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1349                         xhci->cmd_ring->dequeue);
1350
1351         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1352                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1353         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1354                 /* traversing the cancel_cmd_list and canceling
1355                  * the command according to command descriptor
1356                  */
1357                 xhci_cancel_cmd_in_cd_list(xhci);
1358
1359                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1360                 /*
1361                  * ring command ring doorbell again to restart the
1362                  * command ring
1363                  */
1364                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1365                         xhci_ring_cmd_db(xhci);
1366         }
1367         return cur_trb_is_good;
1368 }
1369
1370 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1371                 u32 cmd_comp_code)
1372 {
1373         if (cmd_comp_code == COMP_SUCCESS)
1374                 xhci->slot_id = slot_id;
1375         else
1376                 xhci->slot_id = 0;
1377         complete(&xhci->addr_dev);
1378 }
1379
1380 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1381 {
1382         struct xhci_virt_device *virt_dev;
1383
1384         virt_dev = xhci->devs[slot_id];
1385         if (!virt_dev)
1386                 return;
1387         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1388                 /* Delete default control endpoint resources */
1389                 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1390         xhci_free_virt_device(xhci, slot_id);
1391 }
1392
1393 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1394                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1395 {
1396         struct xhci_virt_device *virt_dev;
1397         struct xhci_input_control_ctx *ctrl_ctx;
1398         unsigned int ep_index;
1399         unsigned int ep_state;
1400         u32 add_flags, drop_flags;
1401
1402         virt_dev = xhci->devs[slot_id];
1403         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1404                 return;
1405         /*
1406          * Configure endpoint commands can come from the USB core
1407          * configuration or alt setting changes, or because the HW
1408          * needed an extra configure endpoint command after a reset
1409          * endpoint command or streams were being configured.
1410          * If the command was for a halted endpoint, the xHCI driver
1411          * is not waiting on the configure endpoint command.
1412          */
1413         ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1414         if (!ctrl_ctx) {
1415                 xhci_warn(xhci, "Could not get input context, bad type.\n");
1416                 return;
1417         }
1418
1419         add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1420         drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1421         /* Input ctx add_flags are the endpoint index plus one */
1422         ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1423
1424         /* A usb_set_interface() call directly after clearing a halted
1425          * condition may race on this quirky hardware.  Not worth
1426          * worrying about, since this is prototype hardware.  Not sure
1427          * if this will work for streams, but streams support was
1428          * untested on this prototype.
1429          */
1430         if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1431                         ep_index != (unsigned int) -1 &&
1432                         add_flags - SLOT_FLAG == drop_flags) {
1433                 ep_state = virt_dev->eps[ep_index].ep_state;
1434                 if (!(ep_state & EP_HALTED))
1435                         goto bandwidth_change;
1436                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1437                                 "Completed config ep cmd - "
1438                                 "last ep index = %d, state = %d",
1439                                 ep_index, ep_state);
1440                 /* Clear internal halted state and restart ring(s) */
1441                 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1442                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1443                 return;
1444         }
1445 bandwidth_change:
1446         xhci_dbg_trace(xhci,  trace_xhci_dbg_context_change,
1447                         "Completed config ep cmd");
1448         virt_dev->cmd_status = cmd_comp_code;
1449         complete(&virt_dev->cmd_completion);
1450         return;
1451 }
1452
1453 static void xhci_handle_cmd_eval_ctx(struct xhci_hcd *xhci, int slot_id,
1454                 struct xhci_event_cmd *event, u32 cmd_comp_code)
1455 {
1456         struct xhci_virt_device *virt_dev;
1457
1458         virt_dev = xhci->devs[slot_id];
1459         if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1460                 return;
1461         virt_dev->cmd_status = cmd_comp_code;
1462         complete(&virt_dev->cmd_completion);
1463 }
1464
1465 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id,
1466                 u32 cmd_comp_code)
1467 {
1468         xhci->devs[slot_id]->cmd_status = cmd_comp_code;
1469         complete(&xhci->addr_dev);
1470 }
1471
1472 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1473                 struct xhci_event_cmd *event)
1474 {
1475         struct xhci_virt_device *virt_dev;
1476
1477         xhci_dbg(xhci, "Completed reset device command.\n");
1478         virt_dev = xhci->devs[slot_id];
1479         if (virt_dev)
1480                 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1481         else
1482                 xhci_warn(xhci, "Reset device command completion "
1483                                 "for disabled slot %u\n", slot_id);
1484 }
1485
1486 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1487                 struct xhci_event_cmd *event)
1488 {
1489         if (!(xhci->quirks & XHCI_NEC_HOST)) {
1490                 xhci->error_bitmask |= 1 << 6;
1491                 return;
1492         }
1493         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1494                         "NEC firmware version %2x.%02x",
1495                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1496                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1497 }
1498
1499 static void handle_cmd_completion(struct xhci_hcd *xhci,
1500                 struct xhci_event_cmd *event)
1501 {
1502         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1503         u64 cmd_dma;
1504         dma_addr_t cmd_dequeue_dma;
1505         u32 cmd_comp_code;
1506         union xhci_trb *cmd_trb;
1507         u32 cmd_type;
1508
1509         cmd_dma = le64_to_cpu(event->cmd_trb);
1510         cmd_trb = xhci->cmd_ring->dequeue;
1511         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1512                         cmd_trb);
1513         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1514         if (cmd_dequeue_dma == 0) {
1515                 xhci->error_bitmask |= 1 << 4;
1516                 return;
1517         }
1518         /* Does the DMA address match our internal dequeue pointer address? */
1519         if (cmd_dma != (u64) cmd_dequeue_dma) {
1520                 xhci->error_bitmask |= 1 << 5;
1521                 return;
1522         }
1523
1524         trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1525
1526         cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1527         if (cmd_comp_code == COMP_CMD_ABORT || cmd_comp_code == COMP_CMD_STOP) {
1528                 /* If the return value is 0, we think the trb pointed by
1529                  * command ring dequeue pointer is a good trb. The good
1530                  * trb means we don't want to cancel the trb, but it have
1531                  * been stopped by host. So we should handle it normally.
1532                  * Otherwise, driver should invoke inc_deq() and return.
1533                  */
1534                 if (handle_stopped_cmd_ring(xhci, cmd_comp_code)) {
1535                         inc_deq(xhci, xhci->cmd_ring);
1536                         return;
1537                 }
1538                 /* There is no command to handle if we get a stop event when the
1539                  * command ring is empty, event->cmd_trb points to the next
1540                  * unset command
1541                  */
1542                 if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1543                         return;
1544         }
1545
1546         cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1547         switch (cmd_type) {
1548         case TRB_ENABLE_SLOT:
1549                 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1550                 break;
1551         case TRB_DISABLE_SLOT:
1552                 xhci_handle_cmd_disable_slot(xhci, slot_id);
1553                 break;
1554         case TRB_CONFIG_EP:
1555                 xhci_handle_cmd_config_ep(xhci, slot_id, event, cmd_comp_code);
1556                 break;
1557         case TRB_EVAL_CONTEXT:
1558                 xhci_handle_cmd_eval_ctx(xhci, slot_id, event, cmd_comp_code);
1559                 break;
1560         case TRB_ADDR_DEV:
1561                 xhci_handle_cmd_addr_dev(xhci, slot_id, cmd_comp_code);
1562                 break;
1563         case TRB_STOP_RING:
1564                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1565                                 le32_to_cpu(cmd_trb->generic.field[3])));
1566                 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1567                 break;
1568         case TRB_SET_DEQ:
1569                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1570                                 le32_to_cpu(cmd_trb->generic.field[3])));
1571                 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1572                 break;
1573         case TRB_CMD_NOOP:
1574                 break;
1575         case TRB_RESET_EP:
1576                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1577                                 le32_to_cpu(cmd_trb->generic.field[3])));
1578                 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1579                 break;
1580         case TRB_RESET_DEV:
1581                 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1582                                 le32_to_cpu(cmd_trb->generic.field[3])));
1583                 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1584                 break;
1585         case TRB_NEC_GET_FW:
1586                 xhci_handle_cmd_nec_get_fw(xhci, event);
1587                 break;
1588         default:
1589                 /* Skip over unknown commands on the event ring */
1590                 xhci->error_bitmask |= 1 << 6;
1591                 break;
1592         }
1593         inc_deq(xhci, xhci->cmd_ring);
1594 }
1595
1596 static void handle_vendor_event(struct xhci_hcd *xhci,
1597                 union xhci_trb *event)
1598 {
1599         u32 trb_type;
1600
1601         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1602         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1603         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1604                 handle_cmd_completion(xhci, &event->event_cmd);
1605 }
1606
1607 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1608  * port registers -- USB 3.0 and USB 2.0).
1609  *
1610  * Returns a zero-based port number, which is suitable for indexing into each of
1611  * the split roothubs' port arrays and bus state arrays.
1612  * Add one to it in order to call xhci_find_slot_id_by_port.
1613  */
1614 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1615                 struct xhci_hcd *xhci, u32 port_id)
1616 {
1617         unsigned int i;
1618         unsigned int num_similar_speed_ports = 0;
1619
1620         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1621          * and usb2_ports are 0-based indexes.  Count the number of similar
1622          * speed ports, up to 1 port before this port.
1623          */
1624         for (i = 0; i < (port_id - 1); i++) {
1625                 u8 port_speed = xhci->port_array[i];
1626
1627                 /*
1628                  * Skip ports that don't have known speeds, or have duplicate
1629                  * Extended Capabilities port speed entries.
1630                  */
1631                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1632                         continue;
1633
1634                 /*
1635                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1636                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1637                  * matches the device speed, it's a similar speed port.
1638                  */
1639                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1640                         num_similar_speed_ports++;
1641         }
1642         return num_similar_speed_ports;
1643 }
1644
1645 static void handle_device_notification(struct xhci_hcd *xhci,
1646                 union xhci_trb *event)
1647 {
1648         u32 slot_id;
1649         struct usb_device *udev;
1650
1651         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1652         if (!xhci->devs[slot_id]) {
1653                 xhci_warn(xhci, "Device Notification event for "
1654                                 "unused slot %u\n", slot_id);
1655                 return;
1656         }
1657
1658         xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1659                         slot_id);
1660         udev = xhci->devs[slot_id]->udev;
1661         if (udev && udev->parent)
1662                 usb_wakeup_notification(udev->parent, udev->portnum);
1663 }
1664
1665 static void handle_port_status(struct xhci_hcd *xhci,
1666                 union xhci_trb *event)
1667 {
1668         struct usb_hcd *hcd;
1669         u32 port_id;
1670         u32 temp, temp1;
1671         int max_ports;
1672         int slot_id;
1673         unsigned int faked_port_index;
1674         u8 major_revision;
1675         struct xhci_bus_state *bus_state;
1676         __le32 __iomem **port_array;
1677         bool bogus_port_status = false;
1678
1679         /* Port status change events always have a successful completion code */
1680         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1681                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1682                 xhci->error_bitmask |= 1 << 8;
1683         }
1684         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1685         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1686
1687         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1688         if ((port_id <= 0) || (port_id > max_ports)) {
1689                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1690                 inc_deq(xhci, xhci->event_ring);
1691                 return;
1692         }
1693
1694         /* Figure out which usb_hcd this port is attached to:
1695          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1696          */
1697         major_revision = xhci->port_array[port_id - 1];
1698
1699         /* Find the right roothub. */
1700         hcd = xhci_to_hcd(xhci);
1701         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1702                 hcd = xhci->shared_hcd;
1703
1704         if (major_revision == 0) {
1705                 xhci_warn(xhci, "Event for port %u not in "
1706                                 "Extended Capabilities, ignoring.\n",
1707                                 port_id);
1708                 bogus_port_status = true;
1709                 goto cleanup;
1710         }
1711         if (major_revision == DUPLICATE_ENTRY) {
1712                 xhci_warn(xhci, "Event for port %u duplicated in"
1713                                 "Extended Capabilities, ignoring.\n",
1714                                 port_id);
1715                 bogus_port_status = true;
1716                 goto cleanup;
1717         }
1718
1719         /*
1720          * Hardware port IDs reported by a Port Status Change Event include USB
1721          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1722          * resume event, but we first need to translate the hardware port ID
1723          * into the index into the ports on the correct split roothub, and the
1724          * correct bus_state structure.
1725          */
1726         bus_state = &xhci->bus_state[hcd_index(hcd)];
1727         if (hcd->speed == HCD_USB3)
1728                 port_array = xhci->usb3_ports;
1729         else
1730                 port_array = xhci->usb2_ports;
1731         /* Find the faked port hub number */
1732         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1733                         port_id);
1734
1735         temp = readl(port_array[faked_port_index]);
1736         if (hcd->state == HC_STATE_SUSPENDED) {
1737                 xhci_dbg(xhci, "resume root hub\n");
1738                 usb_hcd_resume_root_hub(hcd);
1739         }
1740
1741         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1742                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1743
1744                 temp1 = readl(&xhci->op_regs->command);
1745                 if (!(temp1 & CMD_RUN)) {
1746                         xhci_warn(xhci, "xHC is not running.\n");
1747                         goto cleanup;
1748                 }
1749
1750                 if (DEV_SUPERSPEED(temp)) {
1751                         xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1752                         /* Set a flag to say the port signaled remote wakeup,
1753                          * so we can tell the difference between the end of
1754                          * device and host initiated resume.
1755                          */
1756                         bus_state->port_remote_wakeup |= 1 << faked_port_index;
1757                         xhci_test_and_clear_bit(xhci, port_array,
1758                                         faked_port_index, PORT_PLC);
1759                         xhci_set_link_state(xhci, port_array, faked_port_index,
1760                                                 XDEV_U0);
1761                         /* Need to wait until the next link state change
1762                          * indicates the device is actually in U0.
1763                          */
1764                         bogus_port_status = true;
1765                         goto cleanup;
1766                 } else {
1767                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1768                         bus_state->resume_done[faked_port_index] = jiffies +
1769                                 msecs_to_jiffies(20);
1770                         set_bit(faked_port_index, &bus_state->resuming_ports);
1771                         mod_timer(&hcd->rh_timer,
1772                                   bus_state->resume_done[faked_port_index]);
1773                         /* Do the rest in GetPortStatus */
1774                 }
1775         }
1776
1777         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1778                         DEV_SUPERSPEED(temp)) {
1779                 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1780                 /* We've just brought the device into U0 through either the
1781                  * Resume state after a device remote wakeup, or through the
1782                  * U3Exit state after a host-initiated resume.  If it's a device
1783                  * initiated remote wake, don't pass up the link state change,
1784                  * so the roothub behavior is consistent with external
1785                  * USB 3.0 hub behavior.
1786                  */
1787                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1788                                 faked_port_index + 1);
1789                 if (slot_id && xhci->devs[slot_id])
1790                         xhci_ring_device(xhci, slot_id);
1791                 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1792                         bus_state->port_remote_wakeup &=
1793                                 ~(1 << faked_port_index);
1794                         xhci_test_and_clear_bit(xhci, port_array,
1795                                         faked_port_index, PORT_PLC);
1796                         usb_wakeup_notification(hcd->self.root_hub,
1797                                         faked_port_index + 1);
1798                         bogus_port_status = true;
1799                         goto cleanup;
1800                 }
1801         }
1802
1803         /*
1804          * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1805          * RExit to a disconnect state).  If so, let the the driver know it's
1806          * out of the RExit state.
1807          */
1808         if (!DEV_SUPERSPEED(temp) &&
1809                         test_and_clear_bit(faked_port_index,
1810                                 &bus_state->rexit_ports)) {
1811                 complete(&bus_state->rexit_done[faked_port_index]);
1812                 bogus_port_status = true;
1813                 goto cleanup;
1814         }
1815
1816         if (hcd->speed != HCD_USB3)
1817                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1818                                         PORT_PLC);
1819
1820 cleanup:
1821         /* Update event ring dequeue pointer before dropping the lock */
1822         inc_deq(xhci, xhci->event_ring);
1823
1824         /* Don't make the USB core poll the roothub if we got a bad port status
1825          * change event.  Besides, at that point we can't tell which roothub
1826          * (USB 2.0 or USB 3.0) to kick.
1827          */
1828         if (bogus_port_status)
1829                 return;
1830
1831         /*
1832          * xHCI port-status-change events occur when the "or" of all the
1833          * status-change bits in the portsc register changes from 0 to 1.
1834          * New status changes won't cause an event if any other change
1835          * bits are still set.  When an event occurs, switch over to
1836          * polling to avoid losing status changes.
1837          */
1838         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1839         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1840         spin_unlock(&xhci->lock);
1841         /* Pass this up to the core */
1842         usb_hcd_poll_rh_status(hcd);
1843         spin_lock(&xhci->lock);
1844 }
1845
1846 /*
1847  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1848  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1849  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1850  * returns 0.
1851  */
1852 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1853                 union xhci_trb  *start_trb,
1854                 union xhci_trb  *end_trb,
1855                 dma_addr_t      suspect_dma)
1856 {
1857         dma_addr_t start_dma;
1858         dma_addr_t end_seg_dma;
1859         dma_addr_t end_trb_dma;
1860         struct xhci_segment *cur_seg;
1861
1862         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1863         cur_seg = start_seg;
1864
1865         do {
1866                 if (start_dma == 0)
1867                         return NULL;
1868                 /* We may get an event for a Link TRB in the middle of a TD */
1869                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1870                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1871                 /* If the end TRB isn't in this segment, this is set to 0 */
1872                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1873
1874                 if (end_trb_dma > 0) {
1875                         /* The end TRB is in this segment, so suspect should be here */
1876                         if (start_dma <= end_trb_dma) {
1877                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1878                                         return cur_seg;
1879                         } else {
1880                                 /* Case for one segment with
1881                                  * a TD wrapped around to the top
1882                                  */
1883                                 if ((suspect_dma >= start_dma &&
1884                                                         suspect_dma <= end_seg_dma) ||
1885                                                 (suspect_dma >= cur_seg->dma &&
1886                                                  suspect_dma <= end_trb_dma))
1887                                         return cur_seg;
1888                         }
1889                         return NULL;
1890                 } else {
1891                         /* Might still be somewhere in this segment */
1892                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1893                                 return cur_seg;
1894                 }
1895                 cur_seg = cur_seg->next;
1896                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1897         } while (cur_seg != start_seg);
1898
1899         return NULL;
1900 }
1901
1902 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1903                 unsigned int slot_id, unsigned int ep_index,
1904                 unsigned int stream_id,
1905                 struct xhci_td *td, union xhci_trb *event_trb)
1906 {
1907         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1908         ep->ep_state |= EP_HALTED;
1909         ep->stopped_td = td;
1910         ep->stopped_trb = event_trb;
1911         ep->stopped_stream = stream_id;
1912
1913         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1914         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1915
1916         ep->stopped_td = NULL;
1917         ep->stopped_trb = NULL;
1918         ep->stopped_stream = 0;
1919
1920         xhci_ring_cmd_db(xhci);
1921 }
1922
1923 /* Check if an error has halted the endpoint ring.  The class driver will
1924  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1925  * However, a babble and other errors also halt the endpoint ring, and the class
1926  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1927  * Ring Dequeue Pointer command manually.
1928  */
1929 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1930                 struct xhci_ep_ctx *ep_ctx,
1931                 unsigned int trb_comp_code)
1932 {
1933         /* TRB completion codes that may require a manual halt cleanup */
1934         if (trb_comp_code == COMP_TX_ERR ||
1935                         trb_comp_code == COMP_BABBLE ||
1936                         trb_comp_code == COMP_SPLIT_ERR)
1937                 /* The 0.96 spec says a babbling control endpoint
1938                  * is not halted. The 0.96 spec says it is.  Some HW
1939                  * claims to be 0.95 compliant, but it halts the control
1940                  * endpoint anyway.  Check if a babble halted the
1941                  * endpoint.
1942                  */
1943                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1944                     cpu_to_le32(EP_STATE_HALTED))
1945                         return 1;
1946
1947         return 0;
1948 }
1949
1950 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1951 {
1952         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1953                 /* Vendor defined "informational" completion code,
1954                  * treat as not-an-error.
1955                  */
1956                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1957                                 trb_comp_code);
1958                 xhci_dbg(xhci, "Treating code as success.\n");
1959                 return 1;
1960         }
1961         return 0;
1962 }
1963
1964 /*
1965  * Finish the td processing, remove the td from td list;
1966  * Return 1 if the urb can be given back.
1967  */
1968 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1969         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1970         struct xhci_virt_ep *ep, int *status, bool skip)
1971 {
1972         struct xhci_virt_device *xdev;
1973         struct xhci_ring *ep_ring;
1974         unsigned int slot_id;
1975         int ep_index;
1976         struct urb *urb = NULL;
1977         struct xhci_ep_ctx *ep_ctx;
1978         int ret = 0;
1979         struct urb_priv *urb_priv;
1980         u32 trb_comp_code;
1981
1982         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1983         xdev = xhci->devs[slot_id];
1984         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1985         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1986         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1987         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1988
1989         if (skip)
1990                 goto td_cleanup;
1991
1992         if (trb_comp_code == COMP_STOP_INVAL ||
1993                         trb_comp_code == COMP_STOP) {
1994                 /* The Endpoint Stop Command completion will take care of any
1995                  * stopped TDs.  A stopped TD may be restarted, so don't update
1996                  * the ring dequeue pointer or take this TD off any lists yet.
1997                  */
1998                 ep->stopped_td = td;
1999                 ep->stopped_trb = event_trb;
2000                 return 0;
2001         } else {
2002                 if (trb_comp_code == COMP_STALL) {
2003                         /* The transfer is completed from the driver's
2004                          * perspective, but we need to issue a set dequeue
2005                          * command for this stalled endpoint to move the dequeue
2006                          * pointer past the TD.  We can't do that here because
2007                          * the halt condition must be cleared first.  Let the
2008                          * USB class driver clear the stall later.
2009                          */
2010                         ep->stopped_td = td;
2011                         ep->stopped_trb = event_trb;
2012                         ep->stopped_stream = ep_ring->stream_id;
2013                 } else if (xhci_requires_manual_halt_cleanup(xhci,
2014                                         ep_ctx, trb_comp_code)) {
2015                         /* Other types of errors halt the endpoint, but the
2016                          * class driver doesn't call usb_reset_endpoint() unless
2017                          * the error is -EPIPE.  Clear the halted status in the
2018                          * xHCI hardware manually.
2019                          */
2020                         xhci_cleanup_halted_endpoint(xhci,
2021                                         slot_id, ep_index, ep_ring->stream_id,
2022                                         td, event_trb);
2023                 } else {
2024                         /* Update ring dequeue pointer */
2025                         while (ep_ring->dequeue != td->last_trb)
2026                                 inc_deq(xhci, ep_ring);
2027                         inc_deq(xhci, ep_ring);
2028                 }
2029
2030 td_cleanup:
2031                 /* Clean up the endpoint's TD list */
2032                 urb = td->urb;
2033                 urb_priv = urb->hcpriv;
2034
2035                 /* Do one last check of the actual transfer length.
2036                  * If the host controller said we transferred more data than
2037                  * the buffer length, urb->actual_length will be a very big
2038                  * number (since it's unsigned).  Play it safe and say we didn't
2039                  * transfer anything.
2040                  */
2041                 if (urb->actual_length > urb->transfer_buffer_length) {
2042                         xhci_warn(xhci, "URB transfer length is wrong, "
2043                                         "xHC issue? req. len = %u, "
2044                                         "act. len = %u\n",
2045                                         urb->transfer_buffer_length,
2046                                         urb->actual_length);
2047                         urb->actual_length = 0;
2048                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2049                                 *status = -EREMOTEIO;
2050                         else
2051                                 *status = 0;
2052                 }
2053                 list_del_init(&td->td_list);
2054                 /* Was this TD slated to be cancelled but completed anyway? */
2055                 if (!list_empty(&td->cancelled_td_list))
2056                         list_del_init(&td->cancelled_td_list);
2057
2058                 urb_priv->td_cnt++;
2059                 /* Giveback the urb when all the tds are completed */
2060                 if (urb_priv->td_cnt == urb_priv->length) {
2061                         ret = 1;
2062                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2063                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
2064                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
2065                                         == 0) {
2066                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
2067                                                 usb_amd_quirk_pll_enable();
2068                                 }
2069                         }
2070                 }
2071         }
2072
2073         return ret;
2074 }
2075
2076 /*
2077  * Process control tds, update urb status and actual_length.
2078  */
2079 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2080         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2081         struct xhci_virt_ep *ep, int *status)
2082 {
2083         struct xhci_virt_device *xdev;
2084         struct xhci_ring *ep_ring;
2085         unsigned int slot_id;
2086         int ep_index;
2087         struct xhci_ep_ctx *ep_ctx;
2088         u32 trb_comp_code;
2089
2090         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2091         xdev = xhci->devs[slot_id];
2092         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2093         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2094         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2095         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2096
2097         switch (trb_comp_code) {
2098         case COMP_SUCCESS:
2099                 if (event_trb == ep_ring->dequeue) {
2100                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2101                                         "without IOC set??\n");
2102                         *status = -ESHUTDOWN;
2103                 } else if (event_trb != td->last_trb) {
2104                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2105                                         "without IOC set??\n");
2106                         *status = -ESHUTDOWN;
2107                 } else {
2108                         *status = 0;
2109                 }
2110                 break;
2111         case COMP_SHORT_TX:
2112                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2113                         *status = -EREMOTEIO;
2114                 else
2115                         *status = 0;
2116                 break;
2117         case COMP_STOP_INVAL:
2118         case COMP_STOP:
2119                 return finish_td(xhci, td, event_trb, event, ep, status, false);
2120         default:
2121                 if (!xhci_requires_manual_halt_cleanup(xhci,
2122                                         ep_ctx, trb_comp_code))
2123                         break;
2124                 xhci_dbg(xhci, "TRB error code %u, "
2125                                 "halted endpoint index = %u\n",
2126                                 trb_comp_code, ep_index);
2127                 /* else fall through */
2128         case COMP_STALL:
2129                 /* Did we transfer part of the data (middle) phase? */
2130                 if (event_trb != ep_ring->dequeue &&
2131                                 event_trb != td->last_trb)
2132                         td->urb->actual_length =
2133                                 td->urb->transfer_buffer_length -
2134                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2135                 else
2136                         td->urb->actual_length = 0;
2137
2138                 xhci_cleanup_halted_endpoint(xhci,
2139                         slot_id, ep_index, 0, td, event_trb);
2140                 return finish_td(xhci, td, event_trb, event, ep, status, true);
2141         }
2142         /*
2143          * Did we transfer any data, despite the errors that might have
2144          * happened?  I.e. did we get past the setup stage?
2145          */
2146         if (event_trb != ep_ring->dequeue) {
2147                 /* The event was for the status stage */
2148                 if (event_trb == td->last_trb) {
2149                         if (td->urb->actual_length != 0) {
2150                                 /* Don't overwrite a previously set error code
2151                                  */
2152                                 if ((*status == -EINPROGRESS || *status == 0) &&
2153                                                 (td->urb->transfer_flags
2154                                                  & URB_SHORT_NOT_OK))
2155                                         /* Did we already see a short data
2156                                          * stage? */
2157                                         *status = -EREMOTEIO;
2158                         } else {
2159                                 td->urb->actual_length =
2160                                         td->urb->transfer_buffer_length;
2161                         }
2162                 } else {
2163                 /* Maybe the event was for the data stage? */
2164                         td->urb->actual_length =
2165                                 td->urb->transfer_buffer_length -
2166                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2167                         xhci_dbg(xhci, "Waiting for status "
2168                                         "stage event\n");
2169                         return 0;
2170                 }
2171         }
2172
2173         return finish_td(xhci, td, event_trb, event, ep, status, false);
2174 }
2175
2176 /*
2177  * Process isochronous tds, update urb packet status and actual_length.
2178  */
2179 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2180         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2181         struct xhci_virt_ep *ep, int *status)
2182 {
2183         struct xhci_ring *ep_ring;
2184         struct urb_priv *urb_priv;
2185         int idx;
2186         int len = 0;
2187         union xhci_trb *cur_trb;
2188         struct xhci_segment *cur_seg;
2189         struct usb_iso_packet_descriptor *frame;
2190         u32 trb_comp_code;
2191         bool skip_td = false;
2192
2193         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2194         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2195         urb_priv = td->urb->hcpriv;
2196         idx = urb_priv->td_cnt;
2197         frame = &td->urb->iso_frame_desc[idx];
2198
2199         /* handle completion code */
2200         switch (trb_comp_code) {
2201         case COMP_SUCCESS:
2202                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2203                         frame->status = 0;
2204                         break;
2205                 }
2206                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2207                         trb_comp_code = COMP_SHORT_TX;
2208         case COMP_SHORT_TX:
2209                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2210                                 -EREMOTEIO : 0;
2211                 break;
2212         case COMP_BW_OVER:
2213                 frame->status = -ECOMM;
2214                 skip_td = true;
2215                 break;
2216         case COMP_BUFF_OVER:
2217         case COMP_BABBLE:
2218                 frame->status = -EOVERFLOW;
2219                 skip_td = true;
2220                 break;
2221         case COMP_DEV_ERR:
2222         case COMP_STALL:
2223         case COMP_TX_ERR:
2224                 frame->status = -EPROTO;
2225                 skip_td = true;
2226                 break;
2227         case COMP_STOP:
2228         case COMP_STOP_INVAL:
2229                 break;
2230         default:
2231                 frame->status = -1;
2232                 break;
2233         }
2234
2235         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2236                 frame->actual_length = frame->length;
2237                 td->urb->actual_length += frame->length;
2238         } else {
2239                 for (cur_trb = ep_ring->dequeue,
2240                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2241                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2242                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2243                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2244                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2245                 }
2246                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2247                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2248
2249                 if (trb_comp_code != COMP_STOP_INVAL) {
2250                         frame->actual_length = len;
2251                         td->urb->actual_length += len;
2252                 }
2253         }
2254
2255         return finish_td(xhci, td, event_trb, event, ep, status, false);
2256 }
2257
2258 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2259                         struct xhci_transfer_event *event,
2260                         struct xhci_virt_ep *ep, int *status)
2261 {
2262         struct xhci_ring *ep_ring;
2263         struct urb_priv *urb_priv;
2264         struct usb_iso_packet_descriptor *frame;
2265         int idx;
2266
2267         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2268         urb_priv = td->urb->hcpriv;
2269         idx = urb_priv->td_cnt;
2270         frame = &td->urb->iso_frame_desc[idx];
2271
2272         /* The transfer is partly done. */
2273         frame->status = -EXDEV;
2274
2275         /* calc actual length */
2276         frame->actual_length = 0;
2277
2278         /* Update ring dequeue pointer */
2279         while (ep_ring->dequeue != td->last_trb)
2280                 inc_deq(xhci, ep_ring);
2281         inc_deq(xhci, ep_ring);
2282
2283         return finish_td(xhci, td, NULL, event, ep, status, true);
2284 }
2285
2286 /*
2287  * Process bulk and interrupt tds, update urb status and actual_length.
2288  */
2289 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2290         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2291         struct xhci_virt_ep *ep, int *status)
2292 {
2293         struct xhci_ring *ep_ring;
2294         union xhci_trb *cur_trb;
2295         struct xhci_segment *cur_seg;
2296         u32 trb_comp_code;
2297
2298         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2299         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2300
2301         switch (trb_comp_code) {
2302         case COMP_SUCCESS:
2303                 /* Double check that the HW transferred everything. */
2304                 if (event_trb != td->last_trb ||
2305                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2306                         xhci_warn(xhci, "WARN Successful completion "
2307                                         "on short TX\n");
2308                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2309                                 *status = -EREMOTEIO;
2310                         else
2311                                 *status = 0;
2312                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2313                                 trb_comp_code = COMP_SHORT_TX;
2314                 } else {
2315                         *status = 0;
2316                 }
2317                 break;
2318         case COMP_SHORT_TX:
2319                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2320                         *status = -EREMOTEIO;
2321                 else
2322                         *status = 0;
2323                 break;
2324         default:
2325                 /* Others already handled above */
2326                 break;
2327         }
2328         if (trb_comp_code == COMP_SHORT_TX)
2329                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2330                                 "%d bytes untransferred\n",
2331                                 td->urb->ep->desc.bEndpointAddress,
2332                                 td->urb->transfer_buffer_length,
2333                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2334         /* Fast path - was this the last TRB in the TD for this URB? */
2335         if (event_trb == td->last_trb) {
2336                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2337                         td->urb->actual_length =
2338                                 td->urb->transfer_buffer_length -
2339                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2340                         if (td->urb->transfer_buffer_length <
2341                                         td->urb->actual_length) {
2342                                 xhci_warn(xhci, "HC gave bad length "
2343                                                 "of %d bytes left\n",
2344                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2345                                 td->urb->actual_length = 0;
2346                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2347                                         *status = -EREMOTEIO;
2348                                 else
2349                                         *status = 0;
2350                         }
2351                         /* Don't overwrite a previously set error code */
2352                         if (*status == -EINPROGRESS) {
2353                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2354                                         *status = -EREMOTEIO;
2355                                 else
2356                                         *status = 0;
2357                         }
2358                 } else {
2359                         td->urb->actual_length =
2360                                 td->urb->transfer_buffer_length;
2361                         /* Ignore a short packet completion if the
2362                          * untransferred length was zero.
2363                          */
2364                         if (*status == -EREMOTEIO)
2365                                 *status = 0;
2366                 }
2367         } else {
2368                 /* Slow path - walk the list, starting from the dequeue
2369                  * pointer, to get the actual length transferred.
2370                  */
2371                 td->urb->actual_length = 0;
2372                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2373                                 cur_trb != event_trb;
2374                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2375                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2376                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2377                                 td->urb->actual_length +=
2378                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2379                 }
2380                 /* If the ring didn't stop on a Link or No-op TRB, add
2381                  * in the actual bytes transferred from the Normal TRB
2382                  */
2383                 if (trb_comp_code != COMP_STOP_INVAL)
2384                         td->urb->actual_length +=
2385                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2386                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2387         }
2388
2389         return finish_td(xhci, td, event_trb, event, ep, status, false);
2390 }
2391
2392 /*
2393  * If this function returns an error condition, it means it got a Transfer
2394  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2395  * At this point, the host controller is probably hosed and should be reset.
2396  */
2397 static int handle_tx_event(struct xhci_hcd *xhci,
2398                 struct xhci_transfer_event *event)
2399         __releases(&xhci->lock)
2400         __acquires(&xhci->lock)
2401 {
2402         struct xhci_virt_device *xdev;
2403         struct xhci_virt_ep *ep;
2404         struct xhci_ring *ep_ring;
2405         unsigned int slot_id;
2406         int ep_index;
2407         struct xhci_td *td = NULL;
2408         dma_addr_t event_dma;
2409         struct xhci_segment *event_seg;
2410         union xhci_trb *event_trb;
2411         struct urb *urb = NULL;
2412         int status = -EINPROGRESS;
2413         struct urb_priv *urb_priv;
2414         struct xhci_ep_ctx *ep_ctx;
2415         struct list_head *tmp;
2416         u32 trb_comp_code;
2417         int ret = 0;
2418         int td_num = 0;
2419
2420         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2421         xdev = xhci->devs[slot_id];
2422         if (!xdev) {
2423                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2424                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2425                          (unsigned long long) xhci_trb_virt_to_dma(
2426                                  xhci->event_ring->deq_seg,
2427                                  xhci->event_ring->dequeue),
2428                          lower_32_bits(le64_to_cpu(event->buffer)),
2429                          upper_32_bits(le64_to_cpu(event->buffer)),
2430                          le32_to_cpu(event->transfer_len),
2431                          le32_to_cpu(event->flags));
2432                 xhci_dbg(xhci, "Event ring:\n");
2433                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2434                 return -ENODEV;
2435         }
2436
2437         /* Endpoint ID is 1 based, our index is zero based */
2438         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2439         ep = &xdev->eps[ep_index];
2440         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2441         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2442         if (!ep_ring ||
2443             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2444             EP_STATE_DISABLED) {
2445                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2446                                 "or incorrect stream ring\n");
2447                 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2448                          (unsigned long long) xhci_trb_virt_to_dma(
2449                                  xhci->event_ring->deq_seg,
2450                                  xhci->event_ring->dequeue),
2451                          lower_32_bits(le64_to_cpu(event->buffer)),
2452                          upper_32_bits(le64_to_cpu(event->buffer)),
2453                          le32_to_cpu(event->transfer_len),
2454                          le32_to_cpu(event->flags));
2455                 xhci_dbg(xhci, "Event ring:\n");
2456                 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2457                 return -ENODEV;
2458         }
2459
2460         /* Count current td numbers if ep->skip is set */
2461         if (ep->skip) {
2462                 list_for_each(tmp, &ep_ring->td_list)
2463                         td_num++;
2464         }
2465
2466         event_dma = le64_to_cpu(event->buffer);
2467         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2468         /* Look for common error cases */
2469         switch (trb_comp_code) {
2470         /* Skip codes that require special handling depending on
2471          * transfer type
2472          */
2473         case COMP_SUCCESS:
2474                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2475                         break;
2476                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2477                         trb_comp_code = COMP_SHORT_TX;
2478                 else
2479                         xhci_warn_ratelimited(xhci,
2480                                         "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2481         case COMP_SHORT_TX:
2482                 break;
2483         case COMP_STOP:
2484                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2485                 break;
2486         case COMP_STOP_INVAL:
2487                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2488                 break;
2489         case COMP_STALL:
2490                 xhci_dbg(xhci, "Stalled endpoint\n");
2491                 ep->ep_state |= EP_HALTED;
2492                 status = -EPIPE;
2493                 break;
2494         case COMP_TRB_ERR:
2495                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2496                 status = -EILSEQ;
2497                 break;
2498         case COMP_SPLIT_ERR:
2499         case COMP_TX_ERR:
2500                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2501                 status = -EPROTO;
2502                 break;
2503         case COMP_BABBLE:
2504                 xhci_dbg(xhci, "Babble error on endpoint\n");
2505                 status = -EOVERFLOW;
2506                 break;
2507         case COMP_DB_ERR:
2508                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2509                 status = -ENOSR;
2510                 break;
2511         case COMP_BW_OVER:
2512                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2513                 break;
2514         case COMP_BUFF_OVER:
2515                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2516                 break;
2517         case COMP_UNDERRUN:
2518                 /*
2519                  * When the Isoch ring is empty, the xHC will generate
2520                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2521                  * Underrun Event for OUT Isoch endpoint.
2522                  */
2523                 xhci_dbg(xhci, "underrun event on endpoint\n");
2524                 if (!list_empty(&ep_ring->td_list))
2525                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2526                                         "still with TDs queued?\n",
2527                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2528                                  ep_index);
2529                 goto cleanup;
2530         case COMP_OVERRUN:
2531                 xhci_dbg(xhci, "overrun event on endpoint\n");
2532                 if (!list_empty(&ep_ring->td_list))
2533                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2534                                         "still with TDs queued?\n",
2535                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2536                                  ep_index);
2537                 goto cleanup;
2538         case COMP_DEV_ERR:
2539                 xhci_warn(xhci, "WARN: detect an incompatible device");
2540                 status = -EPROTO;
2541                 break;
2542         case COMP_MISSED_INT:
2543                 /*
2544                  * When encounter missed service error, one or more isoc tds
2545                  * may be missed by xHC.
2546                  * Set skip flag of the ep_ring; Complete the missed tds as
2547                  * short transfer when process the ep_ring next time.
2548                  */
2549                 ep->skip = true;
2550                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2551                 goto cleanup;
2552         default:
2553                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2554                         status = 0;
2555                         break;
2556                 }
2557                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2558                                 "busted\n");
2559                 goto cleanup;
2560         }
2561
2562         do {
2563                 /* This TRB should be in the TD at the head of this ring's
2564                  * TD list.
2565                  */
2566                 if (list_empty(&ep_ring->td_list)) {
2567                         /*
2568                          * A stopped endpoint may generate an extra completion
2569                          * event if the device was suspended.  Don't print
2570                          * warnings.
2571                          */
2572                         if (!(trb_comp_code == COMP_STOP ||
2573                                                 trb_comp_code == COMP_STOP_INVAL)) {
2574                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2575                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2576                                                 ep_index);
2577                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2578                                                 (le32_to_cpu(event->flags) &
2579                                                  TRB_TYPE_BITMASK)>>10);
2580                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2581                         }
2582                         if (ep->skip) {
2583                                 ep->skip = false;
2584                                 xhci_dbg(xhci, "td_list is empty while skip "
2585                                                 "flag set. Clear skip flag.\n");
2586                         }
2587                         ret = 0;
2588                         goto cleanup;
2589                 }
2590
2591                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2592                 if (ep->skip && td_num == 0) {
2593                         ep->skip = false;
2594                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2595                                                 "Clear skip flag.\n");
2596                         ret = 0;
2597                         goto cleanup;
2598                 }
2599
2600                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2601                 if (ep->skip)
2602                         td_num--;
2603
2604                 /* Is this a TRB in the currently executing TD? */
2605                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2606                                 td->last_trb, event_dma);
2607
2608                 /*
2609                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2610                  * is not in the current TD pointed by ep_ring->dequeue because
2611                  * that the hardware dequeue pointer still at the previous TRB
2612                  * of the current TD. The previous TRB maybe a Link TD or the
2613                  * last TRB of the previous TD. The command completion handle
2614                  * will take care the rest.
2615                  */
2616                 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2617                         ret = 0;
2618                         goto cleanup;
2619                 }
2620
2621                 if (!event_seg) {
2622                         if (!ep->skip ||
2623                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2624                                 /* Some host controllers give a spurious
2625                                  * successful event after a short transfer.
2626                                  * Ignore it.
2627                                  */
2628                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2629                                                 ep_ring->last_td_was_short) {
2630                                         ep_ring->last_td_was_short = false;
2631                                         ret = 0;
2632                                         goto cleanup;
2633                                 }
2634                                 /* HC is busted, give up! */
2635                                 xhci_err(xhci,
2636                                         "ERROR Transfer event TRB DMA ptr not "
2637                                         "part of current TD\n");
2638                                 return -ESHUTDOWN;
2639                         }
2640
2641                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2642                         goto cleanup;
2643                 }
2644                 if (trb_comp_code == COMP_SHORT_TX)
2645                         ep_ring->last_td_was_short = true;
2646                 else
2647                         ep_ring->last_td_was_short = false;
2648
2649                 if (ep->skip) {
2650                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2651                         ep->skip = false;
2652                 }
2653
2654                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2655                                                 sizeof(*event_trb)];
2656                 /*
2657                  * No-op TRB should not trigger interrupts.
2658                  * If event_trb is a no-op TRB, it means the
2659                  * corresponding TD has been cancelled. Just ignore
2660                  * the TD.
2661                  */
2662                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2663                         xhci_dbg(xhci,
2664                                  "event_trb is a no-op TRB. Skip it\n");
2665                         goto cleanup;
2666                 }
2667
2668                 /* Now update the urb's actual_length and give back to
2669                  * the core
2670                  */
2671                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2672                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2673                                                  &status);
2674                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2675                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2676                                                  &status);
2677                 else
2678                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2679                                                  ep, &status);
2680
2681 cleanup:
2682                 /*
2683                  * Do not update event ring dequeue pointer if ep->skip is set.
2684                  * Will roll back to continue process missed tds.
2685                  */
2686                 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2687                         inc_deq(xhci, xhci->event_ring);
2688                 }
2689
2690                 if (ret) {
2691                         urb = td->urb;
2692                         urb_priv = urb->hcpriv;
2693                         /* Leave the TD around for the reset endpoint function
2694                          * to use(but only if it's not a control endpoint,
2695                          * since we already queued the Set TR dequeue pointer
2696                          * command for stalled control endpoints).
2697                          */
2698                         if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2699                                 (trb_comp_code != COMP_STALL &&
2700                                         trb_comp_code != COMP_BABBLE))
2701                                 xhci_urb_free_priv(xhci, urb_priv);
2702                         else
2703                                 kfree(urb_priv);
2704
2705                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2706                         if ((urb->actual_length != urb->transfer_buffer_length &&
2707                                                 (urb->transfer_flags &
2708                                                  URB_SHORT_NOT_OK)) ||
2709                                         (status != 0 &&
2710                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2711                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2712                                                 "expected = %d, status = %d\n",
2713                                                 urb, urb->actual_length,
2714                                                 urb->transfer_buffer_length,
2715                                                 status);
2716                         spin_unlock(&xhci->lock);
2717                         /* EHCI, UHCI, and OHCI always unconditionally set the
2718                          * urb->status of an isochronous endpoint to 0.
2719                          */
2720                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2721                                 status = 0;
2722                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2723                         spin_lock(&xhci->lock);
2724                 }
2725
2726         /*
2727          * If ep->skip is set, it means there are missed tds on the
2728          * endpoint ring need to take care of.
2729          * Process them as short transfer until reach the td pointed by
2730          * the event.
2731          */
2732         } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2733
2734         return 0;
2735 }
2736
2737 /*
2738  * This function handles all OS-owned events on the event ring.  It may drop
2739  * xhci->lock between event processing (e.g. to pass up port status changes).
2740  * Returns >0 for "possibly more events to process" (caller should call again),
2741  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2742  */
2743 static int xhci_handle_event(struct xhci_hcd *xhci)
2744 {
2745         union xhci_trb *event;
2746         int update_ptrs = 1;
2747         int ret;
2748
2749         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2750                 xhci->error_bitmask |= 1 << 1;
2751                 return 0;
2752         }
2753
2754         event = xhci->event_ring->dequeue;
2755         /* Does the HC or OS own the TRB? */
2756         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2757             xhci->event_ring->cycle_state) {
2758                 xhci->error_bitmask |= 1 << 2;
2759                 return 0;
2760         }
2761
2762         /*
2763          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2764          * speculative reads of the event's flags/data below.
2765          */
2766         rmb();
2767         /* FIXME: Handle more event types. */
2768         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2769         case TRB_TYPE(TRB_COMPLETION):
2770                 handle_cmd_completion(xhci, &event->event_cmd);
2771                 break;
2772         case TRB_TYPE(TRB_PORT_STATUS):
2773                 handle_port_status(xhci, event);
2774                 update_ptrs = 0;
2775                 break;
2776         case TRB_TYPE(TRB_TRANSFER):
2777                 ret = handle_tx_event(xhci, &event->trans_event);
2778                 if (ret < 0)
2779                         xhci->error_bitmask |= 1 << 9;
2780                 else
2781                         update_ptrs = 0;
2782                 break;
2783         case TRB_TYPE(TRB_DEV_NOTE):
2784                 handle_device_notification(xhci, event);
2785                 break;
2786         default:
2787                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2788                     TRB_TYPE(48))
2789                         handle_vendor_event(xhci, event);
2790                 else
2791                         xhci->error_bitmask |= 1 << 3;
2792         }
2793         /* Any of the above functions may drop and re-acquire the lock, so check
2794          * to make sure a watchdog timer didn't mark the host as non-responsive.
2795          */
2796         if (xhci->xhc_state & XHCI_STATE_DYING) {
2797                 xhci_dbg(xhci, "xHCI host dying, returning from "
2798                                 "event handler.\n");
2799                 return 0;
2800         }
2801
2802         if (update_ptrs)
2803                 /* Update SW event ring dequeue pointer */
2804                 inc_deq(xhci, xhci->event_ring);
2805
2806         /* Are there more items on the event ring?  Caller will call us again to
2807          * check.
2808          */
2809         return 1;
2810 }
2811
2812 /*
2813  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2814  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2815  * indicators of an event TRB error, but we check the status *first* to be safe.
2816  */
2817 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2818 {
2819         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2820         u32 status;
2821         u64 temp_64;
2822         union xhci_trb *event_ring_deq;
2823         dma_addr_t deq;
2824
2825         spin_lock(&xhci->lock);
2826         /* Check if the xHC generated the interrupt, or the irq is shared */
2827         status = readl(&xhci->op_regs->status);
2828         if (status == 0xffffffff)
2829                 goto hw_died;
2830
2831         if (!(status & STS_EINT)) {
2832                 spin_unlock(&xhci->lock);
2833                 return IRQ_NONE;
2834         }
2835         if (status & STS_FATAL) {
2836                 xhci_warn(xhci, "WARNING: Host System Error\n");
2837                 xhci_halt(xhci);
2838 hw_died:
2839                 spin_unlock(&xhci->lock);
2840                 return -ESHUTDOWN;
2841         }
2842
2843         /*
2844          * Clear the op reg interrupt status first,
2845          * so we can receive interrupts from other MSI-X interrupters.
2846          * Write 1 to clear the interrupt status.
2847          */
2848         status |= STS_EINT;
2849         writel(status, &xhci->op_regs->status);
2850         /* FIXME when MSI-X is supported and there are multiple vectors */
2851         /* Clear the MSI-X event interrupt status */
2852
2853         if (hcd->irq) {
2854                 u32 irq_pending;
2855                 /* Acknowledge the PCI interrupt */
2856                 irq_pending = readl(&xhci->ir_set->irq_pending);
2857                 irq_pending |= IMAN_IP;
2858                 writel(irq_pending, &xhci->ir_set->irq_pending);
2859         }
2860
2861         if (xhci->xhc_state & XHCI_STATE_DYING) {
2862                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2863                                 "Shouldn't IRQs be disabled?\n");
2864                 /* Clear the event handler busy flag (RW1C);
2865                  * the event ring should be empty.
2866                  */
2867                 temp_64 = readq(&xhci->ir_set->erst_dequeue);
2868                 writeq(temp_64 | ERST_EHB, &xhci->ir_set->erst_dequeue);
2869                 spin_unlock(&xhci->lock);
2870
2871                 return IRQ_HANDLED;
2872         }
2873
2874         event_ring_deq = xhci->event_ring->dequeue;
2875         /* FIXME this should be a delayed service routine
2876          * that clears the EHB.
2877          */
2878         while (xhci_handle_event(xhci) > 0) {}
2879
2880         temp_64 = readq(&xhci->ir_set->erst_dequeue);
2881         /* If necessary, update the HW's version of the event ring deq ptr. */
2882         if (event_ring_deq != xhci->event_ring->dequeue) {
2883                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2884                                 xhci->event_ring->dequeue);
2885                 if (deq == 0)
2886                         xhci_warn(xhci, "WARN something wrong with SW event "
2887                                         "ring dequeue ptr.\n");
2888                 /* Update HC event ring dequeue pointer */
2889                 temp_64 &= ERST_PTR_MASK;
2890                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2891         }
2892
2893         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2894         temp_64 |= ERST_EHB;
2895         writeq(temp_64, &xhci->ir_set->erst_dequeue);
2896
2897         spin_unlock(&xhci->lock);
2898
2899         return IRQ_HANDLED;
2900 }
2901
2902 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2903 {
2904         return xhci_irq(hcd);
2905 }
2906
2907 /****           Endpoint Ring Operations        ****/
2908
2909 /*
2910  * Generic function for queueing a TRB on a ring.
2911  * The caller must have checked to make sure there's room on the ring.
2912  *
2913  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2914  *                      prepare_transfer()?
2915  */
2916 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2917                 bool more_trbs_coming,
2918                 u32 field1, u32 field2, u32 field3, u32 field4)
2919 {
2920         struct xhci_generic_trb *trb;
2921
2922         trb = &ring->enqueue->generic;
2923         trb->field[0] = cpu_to_le32(field1);
2924         trb->field[1] = cpu_to_le32(field2);
2925         trb->field[2] = cpu_to_le32(field3);
2926         trb->field[3] = cpu_to_le32(field4);
2927         inc_enq(xhci, ring, more_trbs_coming);
2928 }
2929
2930 /*
2931  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2932  * FIXME allocate segments if the ring is full.
2933  */
2934 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2935                 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2936 {
2937         unsigned int num_trbs_needed;
2938
2939         /* Make sure the endpoint has been added to xHC schedule */
2940         switch (ep_state) {
2941         case EP_STATE_DISABLED:
2942                 /*
2943                  * USB core changed config/interfaces without notifying us,
2944                  * or hardware is reporting the wrong state.
2945                  */
2946                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2947                 return -ENOENT;
2948         case EP_STATE_ERROR:
2949                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2950                 /* FIXME event handling code for error needs to clear it */
2951                 /* XXX not sure if this should be -ENOENT or not */
2952                 return -EINVAL;
2953         case EP_STATE_HALTED:
2954                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2955         case EP_STATE_STOPPED:
2956         case EP_STATE_RUNNING:
2957                 break;
2958         default:
2959                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2960                 /*
2961                  * FIXME issue Configure Endpoint command to try to get the HC
2962                  * back into a known state.
2963                  */
2964                 return -EINVAL;
2965         }
2966
2967         while (1) {
2968                 if (room_on_ring(xhci, ep_ring, num_trbs)) {
2969                         union xhci_trb *trb = ep_ring->enqueue;
2970                         unsigned int usable = ep_ring->enq_seg->trbs +
2971                                         TRBS_PER_SEGMENT - 1 - trb;
2972                         u32 nop_cmd;
2973
2974                         /*
2975                          * Section 4.11.7.1 TD Fragments states that a link
2976                          * TRB must only occur at the boundary between
2977                          * data bursts (eg 512 bytes for 480M).
2978                          * While it is possible to split a large fragment
2979                          * we don't know the size yet.
2980                          * Simplest solution is to fill the trb before the
2981                          * LINK with nop commands.
2982                          */
2983                         if (num_trbs == 1 || num_trbs <= usable || usable == 0)
2984                                 break;
2985
2986                         if (ep_ring->type != TYPE_BULK)
2987                                 /*
2988                                  * While isoc transfers might have a buffer that
2989                                  * crosses a 64k boundary it is unlikely.
2990                                  * Since we can't add NOPs without generating
2991                                  * gaps in the traffic just hope it never
2992                                  * happens at the end of the ring.
2993                                  * This could be fixed by writing a LINK TRB
2994                                  * instead of the first NOP - however the
2995                                  * TRB_TYPE_LINK_LE32() calls would all need
2996                                  * changing to check the ring length.
2997                                  */
2998                                 break;
2999
3000                         if (num_trbs >= TRBS_PER_SEGMENT) {
3001                                 xhci_err(xhci, "Too many fragments %d, max %d\n",
3002                                                 num_trbs, TRBS_PER_SEGMENT - 1);
3003                                 return -EINVAL;
3004                         }
3005
3006                         nop_cmd = cpu_to_le32(TRB_TYPE(TRB_TR_NOOP) |
3007                                         ep_ring->cycle_state);
3008                         ep_ring->num_trbs_free -= usable;
3009                         do {
3010                                 trb->generic.field[0] = 0;
3011                                 trb->generic.field[1] = 0;
3012                                 trb->generic.field[2] = 0;
3013                                 trb->generic.field[3] = nop_cmd;
3014                                 trb++;
3015                         } while (--usable);
3016                         ep_ring->enqueue = trb;
3017                         if (room_on_ring(xhci, ep_ring, num_trbs))
3018                                 break;
3019                 }
3020
3021                 if (ep_ring == xhci->cmd_ring) {
3022                         xhci_err(xhci, "Do not support expand command ring\n");
3023                         return -ENOMEM;
3024                 }
3025
3026                 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3027                                 "ERROR no room on ep ring, try ring expansion");
3028                 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3029                 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3030                                         mem_flags)) {
3031                         xhci_err(xhci, "Ring expansion failed\n");
3032                         return -ENOMEM;
3033                 }
3034         }
3035
3036         if (enqueue_is_link_trb(ep_ring)) {
3037                 struct xhci_ring *ring = ep_ring;
3038                 union xhci_trb *next;
3039
3040                 next = ring->enqueue;
3041
3042                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3043                         /* If we're not dealing with 0.95 hardware or isoc rings
3044                          * on AMD 0.96 host, clear the chain bit.
3045                          */
3046                         if (!xhci_link_trb_quirk(xhci) &&
3047                                         !(ring->type == TYPE_ISOC &&
3048                                          (xhci->quirks & XHCI_AMD_0x96_HOST)))
3049                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
3050                         else
3051                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
3052
3053                         wmb();
3054                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
3055
3056                         /* Toggle the cycle bit after the last ring segment. */
3057                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
3058                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
3059                         }
3060                         ring->enq_seg = ring->enq_seg->next;
3061                         ring->enqueue = ring->enq_seg->trbs;
3062                         next = ring->enqueue;
3063                 }
3064         }
3065
3066         return 0;
3067 }
3068
3069 static int prepare_transfer(struct xhci_hcd *xhci,
3070                 struct xhci_virt_device *xdev,
3071                 unsigned int ep_index,
3072                 unsigned int stream_id,
3073                 unsigned int num_trbs,
3074                 struct urb *urb,
3075                 unsigned int td_index,
3076                 gfp_t mem_flags)
3077 {
3078         int ret;
3079         struct urb_priv *urb_priv;
3080         struct xhci_td  *td;
3081         struct xhci_ring *ep_ring;
3082         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3083
3084         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3085         if (!ep_ring) {
3086                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3087                                 stream_id);
3088                 return -EINVAL;
3089         }
3090
3091         ret = prepare_ring(xhci, ep_ring,
3092                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3093                            num_trbs, mem_flags);
3094         if (ret)
3095                 return ret;
3096
3097         urb_priv = urb->hcpriv;
3098         td = urb_priv->td[td_index];
3099
3100         INIT_LIST_HEAD(&td->td_list);
3101         INIT_LIST_HEAD(&td->cancelled_td_list);
3102
3103         if (td_index == 0) {
3104                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3105                 if (unlikely(ret))
3106                         return ret;
3107         }
3108
3109         td->urb = urb;
3110         /* Add this TD to the tail of the endpoint ring's TD list */
3111         list_add_tail(&td->td_list, &ep_ring->td_list);
3112         td->start_seg = ep_ring->enq_seg;
3113         td->first_trb = ep_ring->enqueue;
3114
3115         urb_priv->td[td_index] = td;
3116
3117         return 0;
3118 }
3119
3120 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
3121 {
3122         int num_sgs, num_trbs, running_total, temp, i;
3123         struct scatterlist *sg;
3124
3125         sg = NULL;
3126         num_sgs = urb->num_mapped_sgs;
3127         temp = urb->transfer_buffer_length;
3128
3129         num_trbs = 0;
3130         for_each_sg(urb->sg, sg, num_sgs, i) {
3131                 unsigned int len = sg_dma_len(sg);
3132
3133                 /* Scatter gather list entries may cross 64KB boundaries */
3134                 running_total = TRB_MAX_BUFF_SIZE -
3135                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
3136                 running_total &= TRB_MAX_BUFF_SIZE - 1;
3137                 if (running_total != 0)
3138                         num_trbs++;
3139
3140                 /* How many more 64KB chunks to transfer, how many more TRBs? */
3141                 while (running_total < sg_dma_len(sg) && running_total < temp) {
3142                         num_trbs++;
3143                         running_total += TRB_MAX_BUFF_SIZE;
3144                 }
3145                 len = min_t(int, len, temp);
3146                 temp -= len;
3147                 if (temp == 0)
3148                         break;
3149         }
3150         return num_trbs;
3151 }
3152
3153 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3154 {
3155         if (num_trbs != 0)
3156                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3157                                 "TRBs, %d left\n", __func__,
3158                                 urb->ep->desc.bEndpointAddress, num_trbs);
3159         if (running_total != urb->transfer_buffer_length)
3160                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3161                                 "queued %#x (%d), asked for %#x (%d)\n",
3162                                 __func__,
3163                                 urb->ep->desc.bEndpointAddress,
3164                                 running_total, running_total,
3165                                 urb->transfer_buffer_length,
3166                                 urb->transfer_buffer_length);
3167 }
3168
3169 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3170                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3171                 struct xhci_generic_trb *start_trb)
3172 {
3173         /*
3174          * Pass all the TRBs to the hardware at once and make sure this write
3175          * isn't reordered.
3176          */
3177         wmb();
3178         if (start_cycle)
3179                 start_trb->field[3] |= cpu_to_le32(start_cycle);
3180         else
3181                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3182         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3183 }
3184
3185 /*
3186  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3187  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3188  * (comprised of sg list entries) can take several service intervals to
3189  * transmit.
3190  */
3191 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3192                 struct urb *urb, int slot_id, unsigned int ep_index)
3193 {
3194         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3195                         xhci->devs[slot_id]->out_ctx, ep_index);
3196         int xhci_interval;
3197         int ep_interval;
3198
3199         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3200         ep_interval = urb->interval;
3201         /* Convert to microframes */
3202         if (urb->dev->speed == USB_SPEED_LOW ||
3203                         urb->dev->speed == USB_SPEED_FULL)
3204                 ep_interval *= 8;
3205         /* FIXME change this to a warning and a suggestion to use the new API
3206          * to set the polling interval (once the API is added).
3207          */
3208         if (xhci_interval != ep_interval) {
3209                 dev_dbg_ratelimited(&urb->dev->dev,
3210                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3211                                 ep_interval, ep_interval == 1 ? "" : "s",
3212                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3213                 urb->interval = xhci_interval;
3214                 /* Convert back to frames for LS/FS devices */
3215                 if (urb->dev->speed == USB_SPEED_LOW ||
3216                                 urb->dev->speed == USB_SPEED_FULL)
3217                         urb->interval /= 8;
3218         }
3219         return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3220 }
3221
3222 /*
3223  * The TD size is the number of bytes remaining in the TD (including this TRB),
3224  * right shifted by 10.
3225  * It must fit in bits 21:17, so it can't be bigger than 31.
3226  */
3227 static u32 xhci_td_remainder(unsigned int remainder)
3228 {
3229         u32 max = (1 << (21 - 17 + 1)) - 1;
3230
3231         if ((remainder >> 10) >= max)
3232                 return max << 17;
3233         else
3234                 return (remainder >> 10) << 17;
3235 }
3236
3237 /*
3238  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3239  * packets remaining in the TD (*not* including this TRB).
3240  *
3241  * Total TD packet count = total_packet_count =
3242  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3243  *
3244  * Packets transferred up to and including this TRB = packets_transferred =
3245  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3246  *
3247  * TD size = total_packet_count - packets_transferred
3248  *
3249  * It must fit in bits 21:17, so it can't be bigger than 31.
3250  * The last TRB in a TD must have the TD size set to zero.
3251  */
3252 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3253                 unsigned int total_packet_count, struct urb *urb,
3254                 unsigned int num_trbs_left)
3255 {
3256         int packets_transferred;
3257
3258         /* One TRB with a zero-length data packet. */
3259         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3260                 return 0;
3261
3262         /* All the TRB queueing functions don't count the current TRB in
3263          * running_total.
3264          */
3265         packets_transferred = (running_total + trb_buff_len) /
3266                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3267
3268         if ((total_packet_count - packets_transferred) > 31)
3269                 return 31 << 17;
3270         return (total_packet_count - packets_transferred) << 17;
3271 }
3272
3273 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3274                 struct urb *urb, int slot_id, unsigned int ep_index)
3275 {
3276         struct xhci_ring *ep_ring;
3277         unsigned int num_trbs;
3278         struct urb_priv *urb_priv;
3279         struct xhci_td *td;
3280         struct scatterlist *sg;
3281         int num_sgs;
3282         int trb_buff_len, this_sg_len, running_total;
3283         unsigned int total_packet_count;
3284         bool first_trb;
3285         u64 addr;
3286         bool more_trbs_coming;
3287
3288         struct xhci_generic_trb *start_trb;
3289         int start_cycle;
3290
3291         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3292         if (!ep_ring)
3293                 return -EINVAL;
3294
3295         num_trbs = count_sg_trbs_needed(xhci, urb);
3296         num_sgs = urb->num_mapped_sgs;
3297         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3298                         usb_endpoint_maxp(&urb->ep->desc));
3299
3300         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3301                         ep_index, urb->stream_id,
3302                         num_trbs, urb, 0, mem_flags);
3303         if (trb_buff_len < 0)
3304                 return trb_buff_len;
3305
3306         urb_priv = urb->hcpriv;
3307         td = urb_priv->td[0];
3308
3309         /*
3310          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3311          * until we've finished creating all the other TRBs.  The ring's cycle
3312          * state may change as we enqueue the other TRBs, so save it too.
3313          */
3314         start_trb = &ep_ring->enqueue->generic;
3315         start_cycle = ep_ring->cycle_state;
3316
3317         running_total = 0;
3318         /*
3319          * How much data is in the first TRB?
3320          *
3321          * There are three forces at work for TRB buffer pointers and lengths:
3322          * 1. We don't want to walk off the end of this sg-list entry buffer.
3323          * 2. The transfer length that the driver requested may be smaller than
3324          *    the amount of memory allocated for this scatter-gather list.
3325          * 3. TRBs buffers can't cross 64KB boundaries.
3326          */
3327         sg = urb->sg;
3328         addr = (u64) sg_dma_address(sg);
3329         this_sg_len = sg_dma_len(sg);
3330         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3331         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3332         if (trb_buff_len > urb->transfer_buffer_length)
3333                 trb_buff_len = urb->transfer_buffer_length;
3334
3335         first_trb = true;
3336         /* Queue the first TRB, even if it's zero-length */
3337         do {
3338                 u32 field = 0;
3339                 u32 length_field = 0;
3340                 u32 remainder = 0;
3341
3342                 /* Don't change the cycle bit of the first TRB until later */
3343                 if (first_trb) {
3344                         first_trb = false;
3345                         if (start_cycle == 0)
3346                                 field |= 0x1;
3347                 } else
3348                         field |= ep_ring->cycle_state;
3349
3350                 /* Chain all the TRBs together; clear the chain bit in the last
3351                  * TRB to indicate it's the last TRB in the chain.
3352                  */
3353                 if (num_trbs > 1) {
3354                         field |= TRB_CHAIN;
3355                 } else {
3356                         /* FIXME - add check for ZERO_PACKET flag before this */
3357                         td->last_trb = ep_ring->enqueue;
3358                         field |= TRB_IOC;
3359                 }
3360
3361                 /* Only set interrupt on short packet for IN endpoints */
3362                 if (usb_urb_dir_in(urb))
3363                         field |= TRB_ISP;
3364
3365                 if (TRB_MAX_BUFF_SIZE -
3366                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3367                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3368                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3369                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3370                                         (unsigned int) addr + trb_buff_len);
3371                 }
3372
3373                 /* Set the TRB length, TD size, and interrupter fields. */
3374                 if (xhci->hci_version < 0x100) {
3375                         remainder = xhci_td_remainder(
3376                                         urb->transfer_buffer_length -
3377                                         running_total);
3378                 } else {
3379                         remainder = xhci_v1_0_td_remainder(running_total,
3380                                         trb_buff_len, total_packet_count, urb,
3381                                         num_trbs - 1);
3382                 }
3383                 length_field = TRB_LEN(trb_buff_len) |
3384                         remainder |
3385                         TRB_INTR_TARGET(0);
3386
3387                 if (num_trbs > 1)
3388                         more_trbs_coming = true;
3389                 else
3390                         more_trbs_coming = false;
3391                 queue_trb(xhci, ep_ring, more_trbs_coming,
3392                                 lower_32_bits(addr),
3393                                 upper_32_bits(addr),
3394                                 length_field,
3395                                 field | TRB_TYPE(TRB_NORMAL));
3396                 --num_trbs;
3397                 running_total += trb_buff_len;
3398
3399                 /* Calculate length for next transfer --
3400                  * Are we done queueing all the TRBs for this sg entry?
3401                  */
3402                 this_sg_len -= trb_buff_len;
3403                 if (this_sg_len == 0) {
3404                         --num_sgs;
3405                         if (num_sgs == 0)
3406                                 break;
3407                         sg = sg_next(sg);
3408                         addr = (u64) sg_dma_address(sg);
3409                         this_sg_len = sg_dma_len(sg);
3410                 } else {
3411                         addr += trb_buff_len;
3412                 }
3413
3414                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3415                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3416                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3417                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3418                         trb_buff_len =
3419                                 urb->transfer_buffer_length - running_total;
3420         } while (running_total < urb->transfer_buffer_length);
3421
3422         check_trb_math(urb, num_trbs, running_total);
3423         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3424                         start_cycle, start_trb);
3425         return 0;
3426 }
3427
3428 /* This is very similar to what ehci-q.c qtd_fill() does */
3429 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3430                 struct urb *urb, int slot_id, unsigned int ep_index)
3431 {
3432         struct xhci_ring *ep_ring;
3433         struct urb_priv *urb_priv;
3434         struct xhci_td *td;
3435         int num_trbs;
3436         struct xhci_generic_trb *start_trb;
3437         bool first_trb;
3438         bool more_trbs_coming;
3439         int start_cycle;
3440         u32 field, length_field;
3441
3442         int running_total, trb_buff_len, ret;
3443         unsigned int total_packet_count;
3444         u64 addr;
3445
3446         if (urb->num_sgs)
3447                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3448
3449         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3450         if (!ep_ring)
3451                 return -EINVAL;
3452
3453         num_trbs = 0;
3454         /* How much data is (potentially) left before the 64KB boundary? */
3455         running_total = TRB_MAX_BUFF_SIZE -
3456                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3457         running_total &= TRB_MAX_BUFF_SIZE - 1;
3458
3459         /* If there's some data on this 64KB chunk, or we have to send a
3460          * zero-length transfer, we need at least one TRB
3461          */
3462         if (running_total != 0 || urb->transfer_buffer_length == 0)
3463                 num_trbs++;
3464         /* How many more 64KB chunks to transfer, how many more TRBs? */
3465         while (running_total < urb->transfer_buffer_length) {
3466                 num_trbs++;
3467                 running_total += TRB_MAX_BUFF_SIZE;
3468         }
3469         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3470
3471         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3472                         ep_index, urb->stream_id,
3473                         num_trbs, urb, 0, mem_flags);
3474         if (ret < 0)
3475                 return ret;
3476
3477         urb_priv = urb->hcpriv;
3478         td = urb_priv->td[0];
3479
3480         /*
3481          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3482          * until we've finished creating all the other TRBs.  The ring's cycle
3483          * state may change as we enqueue the other TRBs, so save it too.
3484          */
3485         start_trb = &ep_ring->enqueue->generic;
3486         start_cycle = ep_ring->cycle_state;
3487
3488         running_total = 0;
3489         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3490                         usb_endpoint_maxp(&urb->ep->desc));
3491         /* How much data is in the first TRB? */
3492         addr = (u64) urb->transfer_dma;
3493         trb_buff_len = TRB_MAX_BUFF_SIZE -
3494                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3495         if (trb_buff_len > urb->transfer_buffer_length)
3496                 trb_buff_len = urb->transfer_buffer_length;
3497
3498         first_trb = true;
3499
3500         /* Queue the first TRB, even if it's zero-length */
3501         do {
3502                 u32 remainder = 0;
3503                 field = 0;
3504
3505                 /* Don't change the cycle bit of the first TRB until later */
3506                 if (first_trb) {
3507                         first_trb = false;
3508                         if (start_cycle == 0)
3509                                 field |= 0x1;
3510                 } else
3511                         field |= ep_ring->cycle_state;
3512
3513                 /* Chain all the TRBs together; clear the chain bit in the last
3514                  * TRB to indicate it's the last TRB in the chain.
3515                  */
3516                 if (num_trbs > 1) {
3517                         field |= TRB_CHAIN;
3518                 } else {
3519                         /* FIXME - add check for ZERO_PACKET flag before this */
3520                         td->last_trb = ep_ring->enqueue;
3521                         field |= TRB_IOC;
3522                 }
3523
3524                 /* Only set interrupt on short packet for IN endpoints */
3525                 if (usb_urb_dir_in(urb))
3526                         field |= TRB_ISP;
3527
3528                 /* Set the TRB length, TD size, and interrupter fields. */
3529                 if (xhci->hci_version < 0x100) {
3530                         remainder = xhci_td_remainder(
3531                                         urb->transfer_buffer_length -
3532                                         running_total);
3533                 } else {
3534                         remainder = xhci_v1_0_td_remainder(running_total,
3535                                         trb_buff_len, total_packet_count, urb,
3536                                         num_trbs - 1);
3537                 }
3538                 length_field = TRB_LEN(trb_buff_len) |
3539                         remainder |
3540                         TRB_INTR_TARGET(0);
3541
3542                 if (num_trbs > 1)
3543                         more_trbs_coming = true;
3544                 else
3545                         more_trbs_coming = false;
3546                 queue_trb(xhci, ep_ring, more_trbs_coming,
3547                                 lower_32_bits(addr),
3548                                 upper_32_bits(addr),
3549                                 length_field,
3550                                 field | TRB_TYPE(TRB_NORMAL));
3551                 --num_trbs;
3552                 running_total += trb_buff_len;
3553
3554                 /* Calculate length for next transfer */
3555                 addr += trb_buff_len;
3556                 trb_buff_len = urb->transfer_buffer_length - running_total;
3557                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3558                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3559         } while (running_total < urb->transfer_buffer_length);
3560
3561         check_trb_math(urb, num_trbs, running_total);
3562         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3563                         start_cycle, start_trb);
3564         return 0;
3565 }
3566
3567 /* Caller must have locked xhci->lock */
3568 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3569                 struct urb *urb, int slot_id, unsigned int ep_index)
3570 {
3571         struct xhci_ring *ep_ring;
3572         int num_trbs;
3573         int ret;
3574         struct usb_ctrlrequest *setup;
3575         struct xhci_generic_trb *start_trb;
3576         int start_cycle;
3577         u32 field, length_field;
3578         struct urb_priv *urb_priv;
3579         struct xhci_td *td;
3580
3581         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3582         if (!ep_ring)
3583                 return -EINVAL;
3584
3585         /*
3586          * Need to copy setup packet into setup TRB, so we can't use the setup
3587          * DMA address.
3588          */
3589         if (!urb->setup_packet)
3590                 return -EINVAL;
3591
3592         /* 1 TRB for setup, 1 for status */
3593         num_trbs = 2;
3594         /*
3595          * Don't need to check if we need additional event data and normal TRBs,
3596          * since data in control transfers will never get bigger than 16MB
3597          * XXX: can we get a buffer that crosses 64KB boundaries?
3598          */
3599         if (urb->transfer_buffer_length > 0)
3600                 num_trbs++;
3601         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3602                         ep_index, urb->stream_id,
3603                         num_trbs, urb, 0, mem_flags);
3604         if (ret < 0)
3605                 return ret;
3606
3607         urb_priv = urb->hcpriv;
3608         td = urb_priv->td[0];
3609
3610         /*
3611          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3612          * until we've finished creating all the other TRBs.  The ring's cycle
3613          * state may change as we enqueue the other TRBs, so save it too.
3614          */
3615         start_trb = &ep_ring->enqueue->generic;
3616         start_cycle = ep_ring->cycle_state;
3617
3618         /* Queue setup TRB - see section 6.4.1.2.1 */
3619         /* FIXME better way to translate setup_packet into two u32 fields? */
3620         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3621         field = 0;
3622         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3623         if (start_cycle == 0)
3624                 field |= 0x1;
3625
3626         /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3627         if (xhci->hci_version == 0x100) {
3628                 if (urb->transfer_buffer_length > 0) {
3629                         if (setup->bRequestType & USB_DIR_IN)
3630                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3631                         else
3632                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3633                 }
3634         }
3635
3636         queue_trb(xhci, ep_ring, true,
3637                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3638                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3639                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3640                   /* Immediate data in pointer */
3641                   field);
3642
3643         /* If there's data, queue data TRBs */
3644         /* Only set interrupt on short packet for IN endpoints */
3645         if (usb_urb_dir_in(urb))
3646                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3647         else
3648                 field = TRB_TYPE(TRB_DATA);
3649
3650         length_field = TRB_LEN(urb->transfer_buffer_length) |
3651                 xhci_td_remainder(urb->transfer_buffer_length) |
3652                 TRB_INTR_TARGET(0);
3653         if (urb->transfer_buffer_length > 0) {
3654                 if (setup->bRequestType & USB_DIR_IN)
3655                         field |= TRB_DIR_IN;
3656                 queue_trb(xhci, ep_ring, true,
3657                                 lower_32_bits(urb->transfer_dma),
3658                                 upper_32_bits(urb->transfer_dma),
3659                                 length_field,
3660                                 field | ep_ring->cycle_state);
3661         }
3662
3663         /* Save the DMA address of the last TRB in the TD */
3664         td->last_trb = ep_ring->enqueue;
3665
3666         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3667         /* If the device sent data, the status stage is an OUT transfer */
3668         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3669                 field = 0;
3670         else
3671                 field = TRB_DIR_IN;
3672         queue_trb(xhci, ep_ring, false,
3673                         0,
3674                         0,
3675                         TRB_INTR_TARGET(0),
3676                         /* Event on completion */
3677                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3678
3679         giveback_first_trb(xhci, slot_id, ep_index, 0,
3680                         start_cycle, start_trb);
3681         return 0;
3682 }
3683
3684 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3685                 struct urb *urb, int i)
3686 {
3687         int num_trbs = 0;
3688         u64 addr, td_len;
3689
3690         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3691         td_len = urb->iso_frame_desc[i].length;
3692
3693         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3694                         TRB_MAX_BUFF_SIZE);
3695         if (num_trbs == 0)
3696                 num_trbs++;
3697
3698         return num_trbs;
3699 }
3700
3701 /*
3702  * The transfer burst count field of the isochronous TRB defines the number of
3703  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3704  * devices can burst up to bMaxBurst number of packets per service interval.
3705  * This field is zero based, meaning a value of zero in the field means one
3706  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3707  * zero.  Only xHCI 1.0 host controllers support this field.
3708  */
3709 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3710                 struct usb_device *udev,
3711                 struct urb *urb, unsigned int total_packet_count)
3712 {
3713         unsigned int max_burst;
3714
3715         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3716                 return 0;
3717
3718         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3719         return roundup(total_packet_count, max_burst + 1) - 1;
3720 }
3721
3722 /*
3723  * Returns the number of packets in the last "burst" of packets.  This field is
3724  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3725  * the last burst packet count is equal to the total number of packets in the
3726  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3727  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3728  * contain 1 to (bMaxBurst + 1) packets.
3729  */
3730 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3731                 struct usb_device *udev,
3732                 struct urb *urb, unsigned int total_packet_count)
3733 {
3734         unsigned int max_burst;
3735         unsigned int residue;
3736
3737         if (xhci->hci_version < 0x100)
3738                 return 0;
3739
3740         switch (udev->speed) {
3741         case USB_SPEED_SUPER:
3742                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3743                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3744                 residue = total_packet_count % (max_burst + 1);
3745                 /* If residue is zero, the last burst contains (max_burst + 1)
3746                  * number of packets, but the TLBPC field is zero-based.
3747                  */
3748                 if (residue == 0)
3749                         return max_burst;
3750                 return residue - 1;
3751         default:
3752                 if (total_packet_count == 0)
3753                         return 0;
3754                 return total_packet_count - 1;
3755         }
3756 }
3757
3758 /* This is for isoc transfer */
3759 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3760                 struct urb *urb, int slot_id, unsigned int ep_index)
3761 {
3762         struct xhci_ring *ep_ring;
3763         struct urb_priv *urb_priv;
3764         struct xhci_td *td;
3765         int num_tds, trbs_per_td;
3766         struct xhci_generic_trb *start_trb;
3767         bool first_trb;
3768         int start_cycle;
3769         u32 field, length_field;
3770         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3771         u64 start_addr, addr;
3772         int i, j;
3773         bool more_trbs_coming;
3774
3775         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3776
3777         num_tds = urb->number_of_packets;
3778         if (num_tds < 1) {
3779                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3780                 return -EINVAL;
3781         }
3782
3783         start_addr = (u64) urb->transfer_dma;
3784         start_trb = &ep_ring->enqueue->generic;
3785         start_cycle = ep_ring->cycle_state;
3786
3787         urb_priv = urb->hcpriv;
3788         /* Queue the first TRB, even if it's zero-length */
3789         for (i = 0; i < num_tds; i++) {
3790                 unsigned int total_packet_count;
3791                 unsigned int burst_count;
3792                 unsigned int residue;
3793
3794                 first_trb = true;
3795                 running_total = 0;
3796                 addr = start_addr + urb->iso_frame_desc[i].offset;
3797                 td_len = urb->iso_frame_desc[i].length;
3798                 td_remain_len = td_len;
3799                 total_packet_count = DIV_ROUND_UP(td_len,
3800                                 GET_MAX_PACKET(
3801                                         usb_endpoint_maxp(&urb->ep->desc)));
3802                 /* A zero-length transfer still involves at least one packet. */
3803                 if (total_packet_count == 0)
3804                         total_packet_count++;
3805                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3806                                 total_packet_count);
3807                 residue = xhci_get_last_burst_packet_count(xhci,
3808                                 urb->dev, urb, total_packet_count);
3809
3810                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3811
3812                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3813                                 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3814                 if (ret < 0) {
3815                         if (i == 0)
3816                                 return ret;
3817                         goto cleanup;
3818                 }
3819
3820                 td = urb_priv->td[i];
3821                 for (j = 0; j < trbs_per_td; j++) {
3822                         u32 remainder = 0;
3823                         field = 0;
3824
3825                         if (first_trb) {
3826                                 field = TRB_TBC(burst_count) |
3827                                         TRB_TLBPC(residue);
3828                                 /* Queue the isoc TRB */
3829                                 field |= TRB_TYPE(TRB_ISOC);
3830                                 /* Assume URB_ISO_ASAP is set */
3831                                 field |= TRB_SIA;
3832                                 if (i == 0) {
3833                                         if (start_cycle == 0)
3834                                                 field |= 0x1;
3835                                 } else
3836                                         field |= ep_ring->cycle_state;
3837                                 first_trb = false;
3838                         } else {
3839                                 /* Queue other normal TRBs */
3840                                 field |= TRB_TYPE(TRB_NORMAL);
3841                                 field |= ep_ring->cycle_state;
3842                         }
3843
3844                         /* Only set interrupt on short packet for IN EPs */
3845                         if (usb_urb_dir_in(urb))
3846                                 field |= TRB_ISP;
3847
3848                         /* Chain all the TRBs together; clear the chain bit in
3849                          * the last TRB to indicate it's the last TRB in the
3850                          * chain.
3851                          */
3852                         if (j < trbs_per_td - 1) {
3853                                 field |= TRB_CHAIN;
3854                                 more_trbs_coming = true;
3855                         } else {
3856                                 td->last_trb = ep_ring->enqueue;
3857                                 field |= TRB_IOC;
3858                                 if (xhci->hci_version == 0x100 &&
3859                                                 !(xhci->quirks &
3860                                                         XHCI_AVOID_BEI)) {
3861                                         /* Set BEI bit except for the last td */
3862                                         if (i < num_tds - 1)
3863                                                 field |= TRB_BEI;
3864                                 }
3865                                 more_trbs_coming = false;
3866                         }
3867
3868                         /* Calculate TRB length */
3869                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3870                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3871                         if (trb_buff_len > td_remain_len)
3872                                 trb_buff_len = td_remain_len;
3873
3874                         /* Set the TRB length, TD size, & interrupter fields. */
3875                         if (xhci->hci_version < 0x100) {
3876                                 remainder = xhci_td_remainder(
3877                                                 td_len - running_total);
3878                         } else {
3879                                 remainder = xhci_v1_0_td_remainder(
3880                                                 running_total, trb_buff_len,
3881                                                 total_packet_count, urb,
3882                                                 (trbs_per_td - j - 1));
3883                         }
3884                         length_field = TRB_LEN(trb_buff_len) |
3885                                 remainder |
3886                                 TRB_INTR_TARGET(0);
3887
3888                         queue_trb(xhci, ep_ring, more_trbs_coming,
3889                                 lower_32_bits(addr),
3890                                 upper_32_bits(addr),
3891                                 length_field,
3892                                 field);
3893                         running_total += trb_buff_len;
3894
3895                         addr += trb_buff_len;
3896                         td_remain_len -= trb_buff_len;
3897                 }
3898
3899                 /* Check TD length */
3900                 if (running_total != td_len) {
3901                         xhci_err(xhci, "ISOC TD length unmatch\n");
3902                         ret = -EINVAL;
3903                         goto cleanup;
3904                 }
3905         }
3906
3907         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3908                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3909                         usb_amd_quirk_pll_disable();
3910         }
3911         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3912
3913         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3914                         start_cycle, start_trb);
3915         return 0;
3916 cleanup:
3917         /* Clean up a partially enqueued isoc transfer. */
3918
3919         for (i--; i >= 0; i--)
3920                 list_del_init(&urb_priv->td[i]->td_list);
3921
3922         /* Use the first TD as a temporary variable to turn the TDs we've queued
3923          * into No-ops with a software-owned cycle bit. That way the hardware
3924          * won't accidentally start executing bogus TDs when we partially
3925          * overwrite them.  td->first_trb and td->start_seg are already set.
3926          */
3927         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3928         /* Every TRB except the first & last will have its cycle bit flipped. */
3929         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3930
3931         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3932         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3933         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3934         ep_ring->cycle_state = start_cycle;
3935         ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3936         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3937         return ret;
3938 }
3939
3940 /*
3941  * Check transfer ring to guarantee there is enough room for the urb.
3942  * Update ISO URB start_frame and interval.
3943  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3944  * update the urb->start_frame by now.
3945  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3946  */
3947 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3948                 struct urb *urb, int slot_id, unsigned int ep_index)
3949 {
3950         struct xhci_virt_device *xdev;
3951         struct xhci_ring *ep_ring;
3952         struct xhci_ep_ctx *ep_ctx;
3953         int start_frame;
3954         int xhci_interval;
3955         int ep_interval;
3956         int num_tds, num_trbs, i;
3957         int ret;
3958
3959         xdev = xhci->devs[slot_id];
3960         ep_ring = xdev->eps[ep_index].ring;
3961         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3962
3963         num_trbs = 0;
3964         num_tds = urb->number_of_packets;
3965         for (i = 0; i < num_tds; i++)
3966                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3967
3968         /* Check the ring to guarantee there is enough room for the whole urb.
3969          * Do not insert any td of the urb to the ring if the check failed.
3970          */
3971         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3972                            num_trbs, mem_flags);
3973         if (ret)
3974                 return ret;
3975
3976         start_frame = readl(&xhci->run_regs->microframe_index);
3977         start_frame &= 0x3fff;
3978
3979         urb->start_frame = start_frame;
3980         if (urb->dev->speed == USB_SPEED_LOW ||
3981                         urb->dev->speed == USB_SPEED_FULL)
3982                 urb->start_frame >>= 3;
3983
3984         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3985         ep_interval = urb->interval;
3986         /* Convert to microframes */
3987         if (urb->dev->speed == USB_SPEED_LOW ||
3988                         urb->dev->speed == USB_SPEED_FULL)
3989                 ep_interval *= 8;
3990         /* FIXME change this to a warning and a suggestion to use the new API
3991          * to set the polling interval (once the API is added).
3992          */
3993         if (xhci_interval != ep_interval) {
3994                 dev_dbg_ratelimited(&urb->dev->dev,
3995                                 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3996                                 ep_interval, ep_interval == 1 ? "" : "s",
3997                                 xhci_interval, xhci_interval == 1 ? "" : "s");
3998                 urb->interval = xhci_interval;
3999                 /* Convert back to frames for LS/FS devices */
4000                 if (urb->dev->speed == USB_SPEED_LOW ||
4001                                 urb->dev->speed == USB_SPEED_FULL)
4002                         urb->interval /= 8;
4003         }
4004         ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4005
4006         return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4007 }
4008
4009 /****           Command Ring Operations         ****/
4010
4011 /* Generic function for queueing a command TRB on the command ring.
4012  * Check to make sure there's room on the command ring for one command TRB.
4013  * Also check that there's room reserved for commands that must not fail.
4014  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4015  * then only check for the number of reserved spots.
4016  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4017  * because the command event handler may want to resubmit a failed command.
4018  */
4019 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
4020                 u32 field3, u32 field4, bool command_must_succeed)
4021 {
4022         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4023         int ret;
4024
4025         if (!command_must_succeed)
4026                 reserved_trbs++;
4027
4028         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4029                         reserved_trbs, GFP_ATOMIC);
4030         if (ret < 0) {
4031                 xhci_err(xhci, "ERR: No room for command on command ring\n");
4032                 if (command_must_succeed)
4033                         xhci_err(xhci, "ERR: Reserved TRB counting for "
4034                                         "unfailable commands failed.\n");
4035                 return ret;
4036         }
4037         queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4038                         field4 | xhci->cmd_ring->cycle_state);
4039         return 0;
4040 }
4041
4042 /* Queue a slot enable or disable request on the command ring */
4043 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
4044 {
4045         return queue_command(xhci, 0, 0, 0,
4046                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4047 }
4048
4049 /* Queue an address device command TRB */
4050 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4051                               u32 slot_id, enum xhci_setup_dev setup)
4052 {
4053         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4054                         upper_32_bits(in_ctx_ptr), 0,
4055                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4056                         | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4057 }
4058
4059 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
4060                 u32 field1, u32 field2, u32 field3, u32 field4)
4061 {
4062         return queue_command(xhci, field1, field2, field3, field4, false);
4063 }
4064
4065 /* Queue a reset device command TRB */
4066 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
4067 {
4068         return queue_command(xhci, 0, 0, 0,
4069                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4070                         false);
4071 }
4072
4073 /* Queue a configure endpoint command TRB */
4074 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4075                 u32 slot_id, bool command_must_succeed)
4076 {
4077         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4078                         upper_32_bits(in_ctx_ptr), 0,
4079                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4080                         command_must_succeed);
4081 }
4082
4083 /* Queue an evaluate context command TRB */
4084 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
4085                 u32 slot_id, bool command_must_succeed)
4086 {
4087         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
4088                         upper_32_bits(in_ctx_ptr), 0,
4089                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4090                         command_must_succeed);
4091 }
4092
4093 /*
4094  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4095  * activity on an endpoint that is about to be suspended.
4096  */
4097 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
4098                 unsigned int ep_index, int suspend)
4099 {
4100         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4101         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4102         u32 type = TRB_TYPE(TRB_STOP_RING);
4103         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4104
4105         return queue_command(xhci, 0, 0, 0,
4106                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
4107 }
4108
4109 /* Set Transfer Ring Dequeue Pointer command.
4110  * This should not be used for endpoints that have streams enabled.
4111  */
4112 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
4113                 unsigned int ep_index, unsigned int stream_id,
4114                 struct xhci_segment *deq_seg,
4115                 union xhci_trb *deq_ptr, u32 cycle_state)
4116 {
4117         dma_addr_t addr;
4118         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4119         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4120         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4121         u32 type = TRB_TYPE(TRB_SET_DEQ);
4122         struct xhci_virt_ep *ep;
4123
4124         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
4125         if (addr == 0) {
4126                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4127                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4128                                 deq_seg, deq_ptr);
4129                 return 0;
4130         }
4131         ep = &xhci->devs[slot_id]->eps[ep_index];
4132         if ((ep->ep_state & SET_DEQ_PENDING)) {
4133                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4134                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4135                 return 0;
4136         }
4137         ep->queued_deq_seg = deq_seg;
4138         ep->queued_deq_ptr = deq_ptr;
4139         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4140                         upper_32_bits(addr), trb_stream_id,
4141                         trb_slot_id | trb_ep_index | type, false);
4142 }
4143
4144 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4145                 unsigned int ep_index)
4146 {
4147         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4148         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4149         u32 type = TRB_TYPE(TRB_RESET_EP);
4150
4151         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4152                         false);
4153 }