Pileus Git - ~andy/linux/blob - drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         unsigned int                    gis_shift;
  63         int                             type;           /* SAB82532 version     */
  64
  65         /* Setting configuration bits while the transmitter is active
  66          * can cause garbage characters to get emitted by the chip.
  67          * Therefore, we cache such writes here and do the real register
  68          * write the next time the transmitter becomes idle.
  69          */
  70         unsigned int                    cached_ebrg;
  71         unsigned char                   cached_mode;
  72         unsigned char                   cached_pvr;
  73         unsigned char                   cached_dafo;
  74 };
  75
  76 /*
  77  * This assumes you have a 29.4912 MHz clock for your UART.
  78  */
  79 #define SAB_BASE_BAUD ( 29491200 / 16 )
  80
  81 static char *sab82532_version[16] = {
  82         "V1.0", "V2.0", "V3.2", "V(0x03)",
  83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  86 };
  87
  88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  90
  91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  92 #define SAB82532_XMIT_FIFO_SIZE 32
  93
  94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  95 {
  96         int timeout = up->tec_timeout;
  97
  98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  99                 udelay(1);
 100 }
 101
 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 103 {
 104         int timeout = up->cec_timeout;
 105
 106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 107                 udelay(1);
 108 }
 109
 110 static struct tty_port *
 111 receive_chars(struct uart_sunsab_port *up,
 112               union sab82532_irq_status *stat)
 113 {
 114         struct tty_port *port = NULL;
 115         unsigned char buf[32];
 116         int saw_console_brk = 0;
 117         int free_fifo = 0;
 118         int count = 0;
 119         int i;
 120
 121         if (up->port.state != NULL)             /* Unopened serial console */
 122                 port = &up->port.state->port;
 123
 124         /* Read number of BYTES (Character + Status) available. */
 125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 126                 count = SAB82532_RECV_FIFO_SIZE;
 127                 free_fifo++;
 128         }
 129
 130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 132                 free_fifo++;
 133         }
 134
 135         /* Issue a FIFO read command in case we where idle. */
 136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 137                 sunsab_cec_wait(up);
 138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 139                 return port;
 140         }
 141
 142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 143                 free_fifo++;
 144
 145         /* Read the FIFO. */
 146         for (i = 0; i < count; i++)
 147                 buf[i] = readb(&up->regs->r.rfifo[i]);
 148
 149         /* Issue Receive Message Complete command. */
 150         if (free_fifo) {
 151                 sunsab_cec_wait(up);
 152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 153         }
 154
 155         /* Count may be zero for BRK, so we check for it here */
 156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 157             (up->port.line == up->port.cons->index))
 158                 saw_console_brk = 1;
 159
 160         for (i = 0; i < count; i++) {
 161                 unsigned char ch = buf[i], flag;
 162
 163                 flag = TTY_NORMAL;
 164                 up->port.icount.rx++;
 165
 166                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 167                                                 SAB82532_ISR0_FERR |
 168                                                 SAB82532_ISR0_RFO)) ||
 169                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 170                         /*
 171                          * For statistics only
 172                          */
 173                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 174                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 175                                                      SAB82532_ISR0_FERR);
 176                                 up->port.icount.brk++;
 177                                 /*
 178                                  * We do the SysRQ and SAK checking
 179                                  * here because otherwise the break
 180                                  * may get masked by ignore_status_mask
 181                                  * or read_status_mask.
 182                                  */
 183                                 if (uart_handle_break(&up->port))
 184                                         continue;
 185                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 186                                 up->port.icount.parity++;
 187                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 188                                 up->port.icount.frame++;
 189                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 190                                 up->port.icount.overrun++;
 191
 192                         /*
 193                          * Mask off conditions which should be ingored.
 194                          */
 195                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 196                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 197
 198                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 199                                 flag = TTY_BREAK;
 200                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 201                                 flag = TTY_PARITY;
 202                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 203                                 flag = TTY_FRAME;
 204                 }
 205
 206                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
 207                         continue;
 208
 209                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 210                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 211                         tty_insert_flip_char(port, ch, flag);
 212                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 213                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 214         }
 215
 216         if (saw_console_brk)
 217                 sun_do_break();
 218
 219         return port;
 220 }
 221
 222 static void sunsab_stop_tx(struct uart_port *);
 223 static void sunsab_tx_idle(struct uart_sunsab_port *);
 224
 225 static void transmit_chars(struct uart_sunsab_port *up,
 226                            union sab82532_irq_status *stat)
 227 {
 228         struct circ_buf *xmit = &up->port.state->xmit;
 229         int i;
 230
 231         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 232                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 233                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 234                 set_bit(SAB82532_ALLS, &up->irqflags);
 235         }
 236
 237 #if 0 /* bde@nwlink.com says this check causes problems */
 238         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 239                 return;
 240 #endif
 241
 242         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 243                 return;
 244
 245         set_bit(SAB82532_XPR, &up->irqflags);
 246         sunsab_tx_idle(up);
 247
 248         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 249                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 250                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 251                 return;
 252         }
 253
 254         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 255         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 256         clear_bit(SAB82532_ALLS, &up->irqflags);
 257
 258         /* Stuff 32 bytes into Transmit FIFO. */
 259         clear_bit(SAB82532_XPR, &up->irqflags);
 260         for (i = 0; i < up->port.fifosize; i++) {
 261                 writeb(xmit->buf[xmit->tail],
 262                        &up->regs->w.xfifo[i]);
 263                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 264                 up->port.icount.tx++;
 265                 if (uart_circ_empty(xmit))
 266                         break;
 267         }
 268
 269         /* Issue a Transmit Frame command. */
 270         sunsab_cec_wait(up);
 271         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 272
 273         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 274                 uart_write_wakeup(&up->port);
 275
 276         if (uart_circ_empty(xmit))
 277                 sunsab_stop_tx(&up->port);
 278 }
 279
 280 static void check_status(struct uart_sunsab_port *up,
 281                          union sab82532_irq_status *stat)
 282 {
 283         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 284                 uart_handle_dcd_change(&up->port,
 285                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 286
 287         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 288                 uart_handle_cts_change(&up->port,
 289                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 290
 291         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 292                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 293                 up->port.icount.dsr++;
 294         }
 295
 296         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 297 }
 298
 299 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 300 {
 301         struct uart_sunsab_port *up = dev_id;
 302         struct tty_port *port = NULL;
 303         union sab82532_irq_status status;
 304         unsigned long flags;
 305         unsigned char gis;
 306
 307         spin_lock_irqsave(&up->port.lock, flags);
 308
 309         status.stat = 0;
 310         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 311         if (gis & 1)
 312                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 313         if (gis & 2)
 314                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 315
 316         if (status.stat) {
 317                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 318                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 319                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 320                         port = receive_chars(up, &status);
 321                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 322                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 323                         check_status(up, &status);
 324                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 325                         transmit_chars(up, &status);
 326         }
 327
 328         spin_unlock_irqrestore(&up->port.lock, flags);
 329
 330         if (port)
 331                 tty_flip_buffer_push(port);
 332
 333         return IRQ_HANDLED;
 334 }
 335
 336 /* port->lock is not held.  */
 337 static unsigned int sunsab_tx_empty(struct uart_port *port)
 338 {
 339         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 340         int ret;
 341
 342         /* Do not need a lock for a state test like this.  */
 343         if (test_bit(SAB82532_ALLS, &up->irqflags))
 344                 ret = TIOCSER_TEMT;
 345         else
 346                 ret = 0;
 347
 348         return ret;
 349 }
 350
 351 /* port->lock held by caller.  */
 352 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 353 {
 354         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 355
 356         if (mctrl & TIOCM_RTS) {
 357                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 358                 up->cached_mode |= SAB82532_MODE_RTS;
 359         } else {
 360                 up->cached_mode |= (SAB82532_MODE_FRTS |
 361                                     SAB82532_MODE_RTS);
 362         }
 363         if (mctrl & TIOCM_DTR) {
 364                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 365         } else {
 366                 up->cached_pvr |= up->pvr_dtr_bit;
 367         }
 368
 369         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 370         if (test_bit(SAB82532_XPR, &up->irqflags))
 371                 sunsab_tx_idle(up);
 372 }
 373
 374 /* port->lock is held by caller and interrupts are disabled.  */
 375 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 376 {
 377         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 378         unsigned char val;
 379         unsigned int result;
 380
 381         result = 0;
 382
 383         val = readb(&up->regs->r.pvr);
 384         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 385
 386         val = readb(&up->regs->r.vstr);
 387         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 388
 389         val = readb(&up->regs->r.star);
 390         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 391
 392         return result;
 393 }
 394
 395 /* port->lock held by caller.  */
 396 static void sunsab_stop_tx(struct uart_port *port)
 397 {
 398         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 399
 400         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 401         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 402 }
 403
 404 /* port->lock held by caller.  */
 405 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 406 {
 407         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 408                 u8 tmp;
 409
 410                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 411                 writeb(up->cached_mode, &up->regs->rw.mode);
 412                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 413                 writeb(up->cached_dafo, &up->regs->w.dafo);
 414
 415                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 416                 tmp = readb(&up->regs->rw.ccr2);
 417                 tmp &= ~0xc0;
 418                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 419                 writeb(tmp, &up->regs->rw.ccr2);
 420         }
 421 }
 422
 423 /* port->lock held by caller.  */
 424 static void sunsab_start_tx(struct uart_port *port)
 425 {
 426         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 427         struct circ_buf *xmit = &up->port.state->xmit;
 428         int i;
 429
 430         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 431         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 432
 433         if (!test_bit(SAB82532_XPR, &up->irqflags))
 434                 return;
 435
 436         clear_bit(SAB82532_ALLS, &up->irqflags);
 437         clear_bit(SAB82532_XPR, &up->irqflags);
 438
 439         for (i = 0; i < up->port.fifosize; i++) {
 440                 writeb(xmit->buf[xmit->tail],
 441                        &up->regs->w.xfifo[i]);
 442                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 443                 up->port.icount.tx++;
 444                 if (uart_circ_empty(xmit))
 445                         break;
 446         }
 447
 448         /* Issue a Transmit Frame command.  */
 449         sunsab_cec_wait(up);
 450         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 451 }
 452
 453 /* port->lock is not held.  */
 454 static void sunsab_send_xchar(struct uart_port *port, char ch)
 455 {
 456         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 457         unsigned long flags;
 458
 459         spin_lock_irqsave(&up->port.lock, flags);
 460
 461         sunsab_tec_wait(up);
 462         writeb(ch, &up->regs->w.tic);
 463
 464         spin_unlock_irqrestore(&up->port.lock, flags);
 465 }
 466
 467 /* port->lock held by caller.  */
 468 static void sunsab_stop_rx(struct uart_port *port)
 469 {
 470         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 471
 472         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 473         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 474 }
 475
 476 /* port->lock held by caller.  */
 477 static void sunsab_enable_ms(struct uart_port *port)
 478 {
 479         /* For now we always receive these interrupts.  */
 480 }
 481
 482 /* port->lock is not held.  */
 483 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 484 {
 485         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 486         unsigned long flags;
 487         unsigned char val;
 488
 489         spin_lock_irqsave(&up->port.lock, flags);
 490
 491         val = up->cached_dafo;
 492         if (break_state)
 493                 val |= SAB82532_DAFO_XBRK;
 494         else
 495                 val &= ~SAB82532_DAFO_XBRK;
 496         up->cached_dafo = val;
 497
 498         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 499         if (test_bit(SAB82532_XPR, &up->irqflags))
 500                 sunsab_tx_idle(up);
 501
 502         spin_unlock_irqrestore(&up->port.lock, flags);
 503 }
 504
 505 /* port->lock is not held.  */
 506 static int sunsab_startup(struct uart_port *port)
 507 {
 508         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 509         unsigned long flags;
 510         unsigned char tmp;
 511         int err = request_irq(up->port.irq, sunsab_interrupt,
 512                               IRQF_SHARED, "sab", up);
 513         if (err)
 514                 return err;
 515
 516         spin_lock_irqsave(&up->port.lock, flags);
 517
 518         /*
 519          * Wait for any commands or immediate characters
 520          */
 521         sunsab_cec_wait(up);
 522         sunsab_tec_wait(up);
 523
 524         /*
 525          * Clear the FIFO buffers.
 526          */
 527         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 528         sunsab_cec_wait(up);
 529         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 530
 531         /*
 532          * Clear the interrupt registers.
 533          */
 534         (void) readb(&up->regs->r.isr0);
 535         (void) readb(&up->regs->r.isr1);
 536
 537         /*
 538          * Now, initialize the UART
 539          */
 540         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 541         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 542                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 543         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 544         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 545                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 546         writeb(0, &up->regs->w.ccr3);
 547         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 548         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 549                            SAB82532_MODE_RAC);
 550         writeb(up->cached_mode, &up->regs->w.mode);
 551         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 552
 553         tmp = readb(&up->regs->rw.ccr0);
 554         tmp |= SAB82532_CCR0_PU;        /* power-up */
 555         writeb(tmp, &up->regs->rw.ccr0);
 556
 557         /*
 558          * Finally, enable interrupts
 559          */
 560         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 561                                SAB82532_IMR0_PLLA);
 562         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 563         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 564                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 565                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 566                                SAB82532_IMR1_XPR);
 567         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 568         set_bit(SAB82532_ALLS, &up->irqflags);
 569         set_bit(SAB82532_XPR, &up->irqflags);
 570
 571         spin_unlock_irqrestore(&up->port.lock, flags);
 572
 573         return 0;
 574 }
 575
 576 /* port->lock is not held.  */
 577 static void sunsab_shutdown(struct uart_port *port)
 578 {
 579         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 580         unsigned long flags;
 581
 582         spin_lock_irqsave(&up->port.lock, flags);
 583
 584         /* Disable Interrupts */
 585         up->interrupt_mask0 = 0xff;
 586         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 587         up->interrupt_mask1 = 0xff;
 588         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 589
 590         /* Disable break condition */
 591         up->cached_dafo = readb(&up->regs->rw.dafo);
 592         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 593         writeb(up->cached_dafo, &up->regs->rw.dafo);
 594
 595         /* Disable Receiver */
 596         up->cached_mode &= ~SAB82532_MODE_RAC;
 597         writeb(up->cached_mode, &up->regs->rw.mode);
 598
 599         /*
 600          * XXX FIXME
 601          *
 602          * If the chip is powered down here the system hangs/crashes during
 603          * reboot or shutdown.  This needs to be investigated further,
 604          * similar behaviour occurs in 2.4 when the driver is configured
 605          * as a module only.  One hint may be that data is sometimes
 606          * transmitted at 9600 baud during shutdown (regardless of the
 607          * speed the chip was configured for when the port was open).
 608          */
 609 #if 0
 610         /* Power Down */
 611         tmp = readb(&up->regs->rw.ccr0);
 612         tmp &= ~SAB82532_CCR0_PU;
 613         writeb(tmp, &up->regs->rw.ccr0);
 614 #endif
 615
 616         spin_unlock_irqrestore(&up->port.lock, flags);
 617         free_irq(up->port.irq, up);
 618 }
 619
 620 /*
 621  * This is used to figure out the divisor speeds.
 622  *
 623  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 624  *
 625  * with               0 <= N < 64 and 0 <= M < 16
 626  */
 627
 628 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 629 {
 630         int     n, m;
 631
 632         if (baud == 0) {
 633                 *n_ret = 0;
 634                 *m_ret = 0;
 635                 return;
 636         }
 637
 638         /*
 639          * We scale numbers by 10 so that we get better accuracy
 640          * without having to use floating point.  Here we increment m
 641          * until n is within the valid range.
 642          */
 643         n = (SAB_BASE_BAUD * 10) / baud;
 644         m = 0;
 645         while (n >= 640) {
 646                 n = n / 2;
 647                 m++;
 648         }
 649         n = (n+5) / 10;
 650         /*
 651          * We try very hard to avoid speeds with M == 0 since they may
 652          * not work correctly for XTAL frequences above 10 MHz.
 653          */
 654         if ((m == 0) && ((n & 1) == 0)) {
 655                 n = n / 2;
 656                 m++;
 657         }
 658         *n_ret = n - 1;
 659         *m_ret = m;
 660 }
 661
 662 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 663 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 664                                   unsigned int iflag, unsigned int baud,
 665                                   unsigned int quot)
 666 {
 667         unsigned char dafo;
 668         int bits, n, m;
 669
 670         /* Byte size and parity */
 671         switch (cflag & CSIZE) {
 672               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 673               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 674               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 675               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 676               /* Never happens, but GCC is too dumb to figure it out */
 677               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 678         }
 679
 680         if (cflag & CSTOPB) {
 681                 dafo |= SAB82532_DAFO_STOP;
 682                 bits++;
 683         }
 684
 685         if (cflag & PARENB) {
 686                 dafo |= SAB82532_DAFO_PARE;
 687                 bits++;
 688         }
 689
 690         if (cflag & PARODD) {
 691                 dafo |= SAB82532_DAFO_PAR_ODD;
 692         } else {
 693                 dafo |= SAB82532_DAFO_PAR_EVEN;
 694         }
 695         up->cached_dafo = dafo;
 696
 697         calc_ebrg(baud, &n, &m);
 698
 699         up->cached_ebrg = n | (m << 6);
 700
 701         up->tec_timeout = (10 * 1000000) / baud;
 702         up->cec_timeout = up->tec_timeout >> 2;
 703
 704         /* CTS flow control flags */
 705         /* We encode read_status_mask and ignore_status_mask like so:
 706          *
 707          * ---------------------
 708          * | ... | ISR1 | ISR0 |
 709          * ---------------------
 710          *  ..    15   8 7    0
 711          */
 712
 713         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 714                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 715                                      SAB82532_ISR0_CDSC);
 716         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 717                                       SAB82532_ISR1_ALLS |
 718                                       SAB82532_ISR1_XPR) << 8;
 719         if (iflag & INPCK)
 720                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 721                                               SAB82532_ISR0_FERR);
 722         if (iflag & (BRKINT | PARMRK))
 723                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 724
 725         /*
 726          * Characteres to ignore
 727          */
 728         up->port.ignore_status_mask = 0;
 729         if (iflag & IGNPAR)
 730                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 731                                                 SAB82532_ISR0_FERR);
 732         if (iflag & IGNBRK) {
 733                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 734                 /*
 735                  * If we're ignoring parity and break indicators,
 736                  * ignore overruns too (for real raw support).
 737                  */
 738                 if (iflag & IGNPAR)
 739                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 740         }
 741
 742         /*
 743          * ignore all characters if CREAD is not set
 744          */
 745         if ((cflag & CREAD) == 0)
 746                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 747                                                 SAB82532_ISR0_TCD);
 748
 749         uart_update_timeout(&up->port, cflag,
 750                             (up->port.uartclk / (16 * quot)));
 751
 752         /* Now schedule a register update when the chip's
 753          * transmitter is idle.
 754          */
 755         up->cached_mode |= SAB82532_MODE_RAC;
 756         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 757         if (test_bit(SAB82532_XPR, &up->irqflags))
 758                 sunsab_tx_idle(up);
 759 }
 760
 761 /* port->lock is not held.  */
 762 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 763                                struct ktermios *old)
 764 {
 765         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 766         unsigned long flags;
 767         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 768         unsigned int quot = uart_get_divisor(port, baud);
 769
 770         spin_lock_irqsave(&up->port.lock, flags);
 771         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 772         spin_unlock_irqrestore(&up->port.lock, flags);
 773 }
 774
 775 static const char *sunsab_type(struct uart_port *port)
 776 {
 777         struct uart_sunsab_port *up = (void *)port;
 778         static char buf[36];
 779
 780         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 781         return buf;
 782 }
 783
 784 static void sunsab_release_port(struct uart_port *port)
 785 {
 786 }
 787
 788 static int sunsab_request_port(struct uart_port *port)
 789 {
 790         return 0;
 791 }
 792
 793 static void sunsab_config_port(struct uart_port *port, int flags)
 794 {
 795 }
 796
 797 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 798 {
 799         return -EINVAL;
 800 }
 801
 802 static struct uart_ops sunsab_pops = {
 803         .tx_empty       = sunsab_tx_empty,
 804         .set_mctrl      = sunsab_set_mctrl,
 805         .get_mctrl      = sunsab_get_mctrl,
 806         .stop_tx        = sunsab_stop_tx,
 807         .start_tx       = sunsab_start_tx,
 808         .send_xchar     = sunsab_send_xchar,
 809         .stop_rx        = sunsab_stop_rx,
 810         .enable_ms      = sunsab_enable_ms,
 811         .break_ctl      = sunsab_break_ctl,
 812         .startup        = sunsab_startup,
 813         .shutdown       = sunsab_shutdown,
 814         .set_termios    = sunsab_set_termios,
 815         .type           = sunsab_type,
 816         .release_port   = sunsab_release_port,
 817         .request_port   = sunsab_request_port,
 818         .config_port    = sunsab_config_port,
 819         .verify_port    = sunsab_verify_port,
 820 };
 821
 822 static struct uart_driver sunsab_reg = {
 823         .owner                  = THIS_MODULE,
 824         .driver_name            = "sunsab",
 825         .dev_name               = "ttyS",
 826         .major                  = TTY_MAJOR,
 827 };
 828
 829 static struct uart_sunsab_port *sunsab_ports;
 830
 831 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 832
 833 static void sunsab_console_putchar(struct uart_port *port, int c)
 834 {
 835         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 836
 837         sunsab_tec_wait(up);
 838         writeb(c, &up->regs->w.tic);
 839 }
 840
 841 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 842 {
 843         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 844         unsigned long flags;
 845         int locked = 1;
 846
 847         local_irq_save(flags);
 848         if (up->port.sysrq) {
 849                 locked = 0;
 850         } else if (oops_in_progress) {
 851                 locked = spin_trylock(&up->port.lock);
 852         } else
 853                 spin_lock(&up->port.lock);
 854
 855         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 856         sunsab_tec_wait(up);
 857
 858         if (locked)
 859                 spin_unlock(&up->port.lock);
 860         local_irq_restore(flags);
 861 }
 862
 863 static int sunsab_console_setup(struct console *con, char *options)
 864 {
 865         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 866         unsigned long flags;
 867         unsigned int baud, quot;
 868
 869         /*
 870          * The console framework calls us for each and every port
 871          * registered. Defer the console setup until the requested
 872          * port has been properly discovered. A bit of a hack,
 873          * though...
 874          */
 875         if (up->port.type != PORT_SUNSAB)
 876                 return -1;
 877
 878         printk("Console: ttyS%d (SAB82532)\n",
 879                (sunsab_reg.minor - 64) + con->index);
 880
 881         sunserial_console_termios(con, up->port.dev->of_node);
 882
 883         switch (con->cflag & CBAUD) {
 884         case B150: baud = 150; break;
 885         case B300: baud = 300; break;
 886         case B600: baud = 600; break;
 887         case B1200: baud = 1200; break;
 888         case B2400: baud = 2400; break;
 889         case B4800: baud = 4800; break;
 890         default: case B9600: baud = 9600; break;
 891         case B19200: baud = 19200; break;
 892         case B38400: baud = 38400; break;
 893         case B57600: baud = 57600; break;
 894         case B115200: baud = 115200; break;
 895         case B230400: baud = 230400; break;
 896         case B460800: baud = 460800; break;
 897         }
 898
 899         /*
 900          * Temporary fix.
 901          */
 902         spin_lock_init(&up->port.lock);
 903
 904         /*
 905          * Initialize the hardware
 906          */
 907         sunsab_startup(&up->port);
 908
 909         spin_lock_irqsave(&up->port.lock, flags);
 910
 911         /*
 912          * Finally, enable interrupts
 913          */
 914         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 915                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 916         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 917         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 918                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 919                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 920                                 SAB82532_IMR1_XPR;
 921         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 922
 923         quot = uart_get_divisor(&up->port, baud);
 924         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 925         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 926
 927         spin_unlock_irqrestore(&up->port.lock, flags);
 928
 929         return 0;
 930 }
 931
 932 static struct console sunsab_console = {
 933         .name   =       "ttyS",
 934         .write  =       sunsab_console_write,
 935         .device =       uart_console_device,
 936         .setup  =       sunsab_console_setup,
 937         .flags  =       CON_PRINTBUFFER,
 938         .index  =       -1,
 939         .data   =       &sunsab_reg,
 940 };
 941
 942 static inline struct console *SUNSAB_CONSOLE(void)
 943 {
 944         return &sunsab_console;
 945 }
 946 #else
 947 #define SUNSAB_CONSOLE()        (NULL)
 948 #define sunsab_console_init()   do { } while (0)
 949 #endif
 950
 951 static int sunsab_init_one(struct uart_sunsab_port *up,
 952                                      struct platform_device *op,
 953                                      unsigned long offset,
 954                                      int line)
 955 {
 956         up->port.line = line;
 957         up->port.dev = &op->dev;
 958
 959         up->port.mapbase = op->resource[0].start + offset;
 960         up->port.membase = of_ioremap(&op->resource[0], offset,
 961                                       sizeof(union sab82532_async_regs),
 962                                       "sab");
 963         if (!up->port.membase)
 964                 return -ENOMEM;
 965         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 966
 967         up->port.irq = op->archdata.irqs[0];
 968
 969         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 970         up->port.iotype = UPIO_MEM;
 971
 972         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 973
 974         up->port.ops = &sunsab_pops;
 975         up->port.type = PORT_SUNSAB;
 976         up->port.uartclk = SAB_BASE_BAUD;
 977
 978         up->type = readb(&up->regs->r.vstr) & 0x0f;
 979         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 980         writeb(0xff, &up->regs->w.pim);
 981         if ((up->port.line & 0x1) == 0) {
 982                 up->pvr_dsr_bit = (1 << 0);
 983                 up->pvr_dtr_bit = (1 << 1);
 984                 up->gis_shift = 2;
 985         } else {
 986                 up->pvr_dsr_bit = (1 << 3);
 987                 up->pvr_dtr_bit = (1 << 2);
 988                 up->gis_shift = 0;
 989         }
 990         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
 991         writeb(up->cached_pvr, &up->regs->w.pvr);
 992         up->cached_mode = readb(&up->regs->rw.mode);
 993         up->cached_mode |= SAB82532_MODE_FRTS;
 994         writeb(up->cached_mode, &up->regs->rw.mode);
 995         up->cached_mode |= SAB82532_MODE_RTS;
 996         writeb(up->cached_mode, &up->regs->rw.mode);
 997
 998         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
 999         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1000
1001         return 0;
1002 }
1003
1004 static int sab_probe(struct platform_device *op)
1005 {
1006         static int inst;
1007         struct uart_sunsab_port *up;
1008         int err;
1009
1010         up = &sunsab_ports[inst * 2];
1011
1012         err = sunsab_init_one(&up[0], op,
1013                               0,
1014                               (inst * 2) + 0);
1015         if (err)
1016                 goto out;
1017
1018         err = sunsab_init_one(&up[1], op,
1019                               sizeof(union sab82532_async_regs),
1020                               (inst * 2) + 1);
1021         if (err)
1022                 goto out1;
1023
1024         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1025                                 &sunsab_reg, up[0].port.line,
1026                                 false);
1027
1028         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1029                                 &sunsab_reg, up[1].port.line,
1030                                 false);
1031
1032         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1033         if (err)
1034                 goto out2;
1035
1036         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1037         if (err)
1038                 goto out3;
1039
1040         platform_set_drvdata(op, &up[0]);
1041
1042         inst++;
1043
1044         return 0;
1045
1046 out3:
1047         uart_remove_one_port(&sunsab_reg, &up[0].port);
1048 out2:
1049         of_iounmap(&op->resource[0],
1050                    up[1].port.membase,
1051                    sizeof(union sab82532_async_regs));
1052 out1:
1053         of_iounmap(&op->resource[0],
1054                    up[0].port.membase,
1055                    sizeof(union sab82532_async_regs));
1056 out:
1057         return err;
1058 }
1059
1060 static int sab_remove(struct platform_device *op)
1061 {
1062         struct uart_sunsab_port *up = platform_get_drvdata(op);
1063
1064         uart_remove_one_port(&sunsab_reg, &up[1].port);
1065         uart_remove_one_port(&sunsab_reg, &up[0].port);
1066         of_iounmap(&op->resource[0],
1067                    up[1].port.membase,
1068                    sizeof(union sab82532_async_regs));
1069         of_iounmap(&op->resource[0],
1070                    up[0].port.membase,
1071                    sizeof(union sab82532_async_regs));
1072
1073         return 0;
1074 }
1075
1076 static const struct of_device_id sab_match[] = {
1077         {
1078                 .name = "se",
1079         },
1080         {
1081                 .name = "serial",
1082                 .compatible = "sab82532",
1083         },
1084         {},
1085 };
1086 MODULE_DEVICE_TABLE(of, sab_match);
1087
1088 static struct platform_driver sab_driver = {
1089         .driver = {
1090                 .name = "sab",
1091                 .owner = THIS_MODULE,
1092                 .of_match_table = sab_match,
1093         },
1094         .probe          = sab_probe,
1095         .remove         = sab_remove,
1096 };
1097
1098 static int __init sunsab_init(void)
1099 {
1100         struct device_node *dp;
1101         int err;
1102         int num_channels = 0;
1103
1104         for_each_node_by_name(dp, "se")
1105                 num_channels += 2;
1106         for_each_node_by_name(dp, "serial") {
1107                 if (of_device_is_compatible(dp, "sab82532"))
1108                         num_channels += 2;
1109         }
1110
1111         if (num_channels) {
1112                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1113                                        num_channels, GFP_KERNEL);
1114                 if (!sunsab_ports)
1115                         return -ENOMEM;
1116
1117                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1118                 if (err) {
1119                         kfree(sunsab_ports);
1120                         sunsab_ports = NULL;
1121
1122                         return err;
1123                 }
1124         }
1125
1126         return platform_driver_register(&sab_driver);
1127 }
1128
1129 static void __exit sunsab_exit(void)
1130 {
1131         platform_driver_unregister(&sab_driver);
1132         if (sunsab_reg.nr) {
1133                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1134         }
1135
1136         kfree(sunsab_ports);
1137         sunsab_ports = NULL;
1138 }
1139
1140 module_init(sunsab_init);
1141 module_exit(sunsab_exit);
1142
1143 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1144 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1145 MODULE_LICENSE("GPL");