Pileus Git - ~andy/linux/blob - drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/gpio.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/platform_data/serial-omap.h>
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 #define OMAP_MAX_HSUART_PORTS   6
  50
  51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  52
  53 #define OMAP_UART_REV_42 0x0402
  54 #define OMAP_UART_REV_46 0x0406
  55 #define OMAP_UART_REV_52 0x0502
  56 #define OMAP_UART_REV_63 0x0603
  57
  58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  59
  60 /* Feature flags */
  61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  62
  63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  65
  66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  67
  68 /* SCR register bitmasks */
  69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  72
  73 /* FCR register bitmasks */
  74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  76
  77 /* MVR register bitmasks */
  78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  79
  80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  83
  84 #define OMAP_UART_MVR_MAJ_MASK          0x700
  85 #define OMAP_UART_MVR_MAJ_SHIFT         8
  86 #define OMAP_UART_MVR_MIN_MASK          0x3f
  87
  88 #define OMAP_UART_DMA_CH_FREE   -1
  89
  90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  91 #define OMAP_MODE13X_SPEED      230400
  92
  93 /* WER = 0x7F
  94  * Enable module level wakeup in WER reg
  95  */
  96 #define OMAP_UART_WER_MOD_WKUP  0X7F
  97
  98 /* Enable XON/XOFF flow control on output */
  99 #define OMAP_UART_SW_TX         0x08
 100
 101 /* Enable XON/XOFF flow control on input */
 102 #define OMAP_UART_SW_RX         0x02
 103
 104 #define OMAP_UART_SW_CLR        0xF0
 105
 106 #define OMAP_UART_TCR_TRIG      0x0F
 107
 108 struct uart_omap_dma {
 109         u8                      uart_dma_tx;
 110         u8                      uart_dma_rx;
 111         int                     rx_dma_channel;
 112         int                     tx_dma_channel;
 113         dma_addr_t              rx_buf_dma_phys;
 114         dma_addr_t              tx_buf_dma_phys;
 115         unsigned int            uart_base;
 116         /*
 117          * Buffer for rx dma.It is not required for tx because the buffer
 118          * comes from port structure.
 119          */
 120         unsigned char           *rx_buf;
 121         unsigned int            prev_rx_dma_pos;
 122         int                     tx_buf_size;
 123         int                     tx_dma_used;
 124         int                     rx_dma_used;
 125         spinlock_t              tx_lock;
 126         spinlock_t              rx_lock;
 127         /* timer to poll activity on rx dma */
 128         struct timer_list       rx_timer;
 129         unsigned int            rx_buf_size;
 130         unsigned int            rx_poll_rate;
 131         unsigned int            rx_timeout;
 132 };
 133
 134 struct uart_omap_port {
 135         struct uart_port        port;
 136         struct uart_omap_dma    uart_dma;
 137         struct device           *dev;
 138         int                     wakeirq;
 139
 140         unsigned char           ier;
 141         unsigned char           lcr;
 142         unsigned char           mcr;
 143         unsigned char           fcr;
 144         unsigned char           efr;
 145         unsigned char           dll;
 146         unsigned char           dlh;
 147         unsigned char           mdr1;
 148         unsigned char           scr;
 149         unsigned char           wer;
 150
 151         int                     use_dma;
 152         /*
 153          * Some bits in registers are cleared on a read, so they must
 154          * be saved whenever the register is read but the bits will not
 155          * be immediately processed.
 156          */
 157         unsigned int            lsr_break_flag;
 158         unsigned char           msr_saved_flags;
 159         char                    name[20];
 160         unsigned long           port_activity;
 161         int                     context_loss_cnt;
 162         u32                     errata;
 163         u8                      wakeups_enabled;
 164         u32                     features;
 165
 166         int                     DTR_gpio;
 167         int                     DTR_inverted;
 168         int                     DTR_active;
 169
 170         struct serial_rs485     rs485;
 171         int                     rts_gpio;
 172
 173         struct pm_qos_request   pm_qos_request;
 174         u32                     latency;
 175         u32                     calc_latency;
 176         struct work_struct      qos_work;
 177         bool                    is_suspending;
 178 };
 179
 180 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 181
 182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 183
 184 /* Forward declaration of functions */
 185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 186
 187 static struct workqueue_struct *serial_omap_uart_wq;
 188
 189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 190 {
 191         offset <<= up->port.regshift;
 192         return readw(up->port.membase + offset);
 193 }
 194
 195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 196 {
 197         offset <<= up->port.regshift;
 198         writew(value, up->port.membase + offset);
 199 }
 200
 201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 202 {
 203         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 204         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 205                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 206         serial_out(up, UART_FCR, 0);
 207 }
 208
 209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 210 {
 211         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 212
 213         if (!pdata || !pdata->get_context_loss_count)
 214                 return -EINVAL;
 215
 216         return pdata->get_context_loss_count(up->dev);
 217 }
 218
 219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
 220                                        bool enable)
 221 {
 222         if (!up->wakeirq)
 223                 return;
 224
 225         if (enable)
 226                 enable_irq(up->wakeirq);
 227         else
 228                 disable_irq(up->wakeirq);
 229 }
 230
 231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 232 {
 233         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 234
 235         serial_omap_enable_wakeirq(up, enable);
 236         if (!pdata || !pdata->enable_wakeup)
 237                 return;
 238
 239         pdata->enable_wakeup(up->dev, enable);
 240 }
 241
 242 /*
 243  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 244  * @port: uart port info
 245  * @baud: baudrate for which mode needs to be determined
 246  *
 247  * Returns true if baud rate is MODE16X and false if MODE13X
 248  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 249  * and Error Rates" determines modes not for all common baud rates.
 250  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 251  * table it's determined as 13x.
 252  */
 253 static bool
 254 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 255 {
 256         unsigned int n13 = port->uartclk / (13 * baud);
 257         unsigned int n16 = port->uartclk / (16 * baud);
 258         int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
 259         int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
 260         if (baudAbsDiff13 < 0)
 261                 baudAbsDiff13 = -baudAbsDiff13;
 262         if (baudAbsDiff16 < 0)
 263                 baudAbsDiff16 = -baudAbsDiff16;
 264
 265         return (baudAbsDiff13 >= baudAbsDiff16);
 266 }
 267
 268 /*
 269  * serial_omap_get_divisor - calculate divisor value
 270  * @port: uart port info
 271  * @baud: baudrate for which divisor needs to be calculated.
 272  */
 273 static unsigned int
 274 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 275 {
 276         unsigned int mode;
 277
 278         if (!serial_omap_baud_is_mode16(port, baud))
 279                 mode = 13;
 280         else
 281                 mode = 16;
 282         return port->uartclk/(mode * baud);
 283 }
 284
 285 static void serial_omap_enable_ms(struct uart_port *port)
 286 {
 287         struct uart_omap_port *up = to_uart_omap_port(port);
 288
 289         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 290
 291         pm_runtime_get_sync(up->dev);
 292         up->ier |= UART_IER_MSI;
 293         serial_out(up, UART_IER, up->ier);
 294         pm_runtime_mark_last_busy(up->dev);
 295         pm_runtime_put_autosuspend(up->dev);
 296 }
 297
 298 static void serial_omap_stop_tx(struct uart_port *port)
 299 {
 300         struct uart_omap_port *up = to_uart_omap_port(port);
 301         int res;
 302
 303         pm_runtime_get_sync(up->dev);
 304
 305         /* Handle RS-485 */
 306         if (up->rs485.flags & SER_RS485_ENABLED) {
 307                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 308                         /* THR interrupt is fired when both TX FIFO and TX
 309                          * shift register are empty. This means there's nothing
 310                          * left to transmit now, so make sure the THR interrupt
 311                          * is fired when TX FIFO is below the trigger level,
 312                          * disable THR interrupts and toggle the RS-485 GPIO
 313                          * data direction pin if needed.
 314                          */
 315                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 316                         serial_out(up, UART_OMAP_SCR, up->scr);
 317                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
 318                         if (gpio_get_value(up->rts_gpio) != res) {
 319                                 if (up->rs485.delay_rts_after_send > 0)
 320                                         mdelay(up->rs485.delay_rts_after_send);
 321                                 gpio_set_value(up->rts_gpio, res);
 322                         }
 323                 } else {
 324                         /* We're asked to stop, but there's still stuff in the
 325                          * UART FIFO, so make sure the THR interrupt is fired
 326                          * when both TX FIFO and TX shift register are empty.
 327                          * The next THR interrupt (if no transmission is started
 328                          * in the meantime) will indicate the end of a
 329                          * transmission. Therefore we _don't_ disable THR
 330                          * interrupts in this situation.
 331                          */
 332                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 333                         serial_out(up, UART_OMAP_SCR, up->scr);
 334                         return;
 335                 }
 336         }
 337
 338         if (up->ier & UART_IER_THRI) {
 339                 up->ier &= ~UART_IER_THRI;
 340                 serial_out(up, UART_IER, up->ier);
 341         }
 342
 343         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 344             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
 345                 up->ier = UART_IER_RLSI | UART_IER_RDI;
 346                 serial_out(up, UART_IER, up->ier);
 347         }
 348
 349         pm_runtime_mark_last_busy(up->dev);
 350         pm_runtime_put_autosuspend(up->dev);
 351 }
 352
 353 static void serial_omap_stop_rx(struct uart_port *port)
 354 {
 355         struct uart_omap_port *up = to_uart_omap_port(port);
 356
 357         pm_runtime_get_sync(up->dev);
 358         up->ier &= ~UART_IER_RLSI;
 359         up->port.read_status_mask &= ~UART_LSR_DR;
 360         serial_out(up, UART_IER, up->ier);
 361         pm_runtime_mark_last_busy(up->dev);
 362         pm_runtime_put_autosuspend(up->dev);
 363 }
 364
 365 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 366 {
 367         struct circ_buf *xmit = &up->port.state->xmit;
 368         int count;
 369
 370         if (up->port.x_char) {
 371                 serial_out(up, UART_TX, up->port.x_char);
 372                 up->port.icount.tx++;
 373                 up->port.x_char = 0;
 374                 return;
 375         }
 376         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 377                 serial_omap_stop_tx(&up->port);
 378                 return;
 379         }
 380         count = up->port.fifosize / 4;
 381         do {
 382                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 383                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 384                 up->port.icount.tx++;
 385                 if (uart_circ_empty(xmit))
 386                         break;
 387         } while (--count > 0);
 388
 389         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 390                 spin_unlock(&up->port.lock);
 391                 uart_write_wakeup(&up->port);
 392                 spin_lock(&up->port.lock);
 393         }
 394
 395         if (uart_circ_empty(xmit))
 396                 serial_omap_stop_tx(&up->port);
 397 }
 398
 399 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 400 {
 401         if (!(up->ier & UART_IER_THRI)) {
 402                 up->ier |= UART_IER_THRI;
 403                 serial_out(up, UART_IER, up->ier);
 404         }
 405 }
 406
 407 static void serial_omap_start_tx(struct uart_port *port)
 408 {
 409         struct uart_omap_port *up = to_uart_omap_port(port);
 410         int res;
 411
 412         pm_runtime_get_sync(up->dev);
 413
 414         /* Handle RS-485 */
 415         if (up->rs485.flags & SER_RS485_ENABLED) {
 416                 /* Fire THR interrupts when FIFO is below trigger level */
 417                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 418                 serial_out(up, UART_OMAP_SCR, up->scr);
 419
 420                 /* if rts not already enabled */
 421                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 422                 if (gpio_get_value(up->rts_gpio) != res) {
 423                         gpio_set_value(up->rts_gpio, res);
 424                         if (up->rs485.delay_rts_before_send > 0)
 425                                 mdelay(up->rs485.delay_rts_before_send);
 426                 }
 427         }
 428
 429         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 430             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
 431                 serial_omap_stop_rx(port);
 432
 433         serial_omap_enable_ier_thri(up);
 434         pm_runtime_mark_last_busy(up->dev);
 435         pm_runtime_put_autosuspend(up->dev);
 436 }
 437
 438 static void serial_omap_throttle(struct uart_port *port)
 439 {
 440         struct uart_omap_port *up = to_uart_omap_port(port);
 441         unsigned long flags;
 442
 443         pm_runtime_get_sync(up->dev);
 444         spin_lock_irqsave(&up->port.lock, flags);
 445         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 446         serial_out(up, UART_IER, up->ier);
 447         spin_unlock_irqrestore(&up->port.lock, flags);
 448         pm_runtime_mark_last_busy(up->dev);
 449         pm_runtime_put_autosuspend(up->dev);
 450 }
 451
 452 static void serial_omap_unthrottle(struct uart_port *port)
 453 {
 454         struct uart_omap_port *up = to_uart_omap_port(port);
 455         unsigned long flags;
 456
 457         pm_runtime_get_sync(up->dev);
 458         spin_lock_irqsave(&up->port.lock, flags);
 459         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 460         serial_out(up, UART_IER, up->ier);
 461         spin_unlock_irqrestore(&up->port.lock, flags);
 462         pm_runtime_mark_last_busy(up->dev);
 463         pm_runtime_put_autosuspend(up->dev);
 464 }
 465
 466 static unsigned int check_modem_status(struct uart_omap_port *up)
 467 {
 468         unsigned int status;
 469
 470         status = serial_in(up, UART_MSR);
 471         status |= up->msr_saved_flags;
 472         up->msr_saved_flags = 0;
 473         if ((status & UART_MSR_ANY_DELTA) == 0)
 474                 return status;
 475
 476         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 477             up->port.state != NULL) {
 478                 if (status & UART_MSR_TERI)
 479                         up->port.icount.rng++;
 480                 if (status & UART_MSR_DDSR)
 481                         up->port.icount.dsr++;
 482                 if (status & UART_MSR_DDCD)
 483                         uart_handle_dcd_change
 484                                 (&up->port, status & UART_MSR_DCD);
 485                 if (status & UART_MSR_DCTS)
 486                         uart_handle_cts_change
 487                                 (&up->port, status & UART_MSR_CTS);
 488                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 489         }
 490
 491         return status;
 492 }
 493
 494 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 495 {
 496         unsigned int flag;
 497         unsigned char ch = 0;
 498
 499         if (likely(lsr & UART_LSR_DR))
 500                 ch = serial_in(up, UART_RX);
 501
 502         up->port.icount.rx++;
 503         flag = TTY_NORMAL;
 504
 505         if (lsr & UART_LSR_BI) {
 506                 flag = TTY_BREAK;
 507                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 508                 up->port.icount.brk++;
 509                 /*
 510                  * We do the SysRQ and SAK checking
 511                  * here because otherwise the break
 512                  * may get masked by ignore_status_mask
 513                  * or read_status_mask.
 514                  */
 515                 if (uart_handle_break(&up->port))
 516                         return;
 517
 518         }
 519
 520         if (lsr & UART_LSR_PE) {
 521                 flag = TTY_PARITY;
 522                 up->port.icount.parity++;
 523         }
 524
 525         if (lsr & UART_LSR_FE) {
 526                 flag = TTY_FRAME;
 527                 up->port.icount.frame++;
 528         }
 529
 530         if (lsr & UART_LSR_OE)
 531                 up->port.icount.overrun++;
 532
 533 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 534         if (up->port.line == up->port.cons->index) {
 535                 /* Recover the break flag from console xmit */
 536                 lsr |= up->lsr_break_flag;
 537         }
 538 #endif
 539         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 540 }
 541
 542 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 543 {
 544         unsigned char ch = 0;
 545         unsigned int flag;
 546
 547         if (!(lsr & UART_LSR_DR))
 548                 return;
 549
 550         ch = serial_in(up, UART_RX);
 551         flag = TTY_NORMAL;
 552         up->port.icount.rx++;
 553
 554         if (uart_handle_sysrq_char(&up->port, ch))
 555                 return;
 556
 557         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 558 }
 559
 560 /**
 561  * serial_omap_irq() - This handles the interrupt from one port
 562  * @irq: uart port irq number
 563  * @dev_id: uart port info
 564  */
 565 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 566 {
 567         struct uart_omap_port *up = dev_id;
 568         unsigned int iir, lsr;
 569         unsigned int type;
 570         irqreturn_t ret = IRQ_NONE;
 571         int max_count = 256;
 572
 573         spin_lock(&up->port.lock);
 574         pm_runtime_get_sync(up->dev);
 575
 576         do {
 577                 iir = serial_in(up, UART_IIR);
 578                 if (iir & UART_IIR_NO_INT)
 579                         break;
 580
 581                 ret = IRQ_HANDLED;
 582                 lsr = serial_in(up, UART_LSR);
 583
 584                 /* extract IRQ type from IIR register */
 585                 type = iir & 0x3e;
 586
 587                 switch (type) {
 588                 case UART_IIR_MSI:
 589                         check_modem_status(up);
 590                         break;
 591                 case UART_IIR_THRI:
 592                         transmit_chars(up, lsr);
 593                         break;
 594                 case UART_IIR_RX_TIMEOUT:
 595                         /* FALLTHROUGH */
 596                 case UART_IIR_RDI:
 597                         serial_omap_rdi(up, lsr);
 598                         break;
 599                 case UART_IIR_RLSI:
 600                         serial_omap_rlsi(up, lsr);
 601                         break;
 602                 case UART_IIR_CTS_RTS_DSR:
 603                         /* simply try again */
 604                         break;
 605                 case UART_IIR_XOFF:
 606                         /* FALLTHROUGH */
 607                 default:
 608                         break;
 609                 }
 610         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 611
 612         spin_unlock(&up->port.lock);
 613
 614         tty_flip_buffer_push(&up->port.state->port);
 615
 616         pm_runtime_mark_last_busy(up->dev);
 617         pm_runtime_put_autosuspend(up->dev);
 618         up->port_activity = jiffies;
 619
 620         return ret;
 621 }
 622
 623 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 624 {
 625         struct uart_omap_port *up = to_uart_omap_port(port);
 626         unsigned long flags = 0;
 627         unsigned int ret = 0;
 628
 629         pm_runtime_get_sync(up->dev);
 630         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 631         spin_lock_irqsave(&up->port.lock, flags);
 632         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 633         spin_unlock_irqrestore(&up->port.lock, flags);
 634         pm_runtime_mark_last_busy(up->dev);
 635         pm_runtime_put_autosuspend(up->dev);
 636         return ret;
 637 }
 638
 639 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 640 {
 641         struct uart_omap_port *up = to_uart_omap_port(port);
 642         unsigned int status;
 643         unsigned int ret = 0;
 644
 645         pm_runtime_get_sync(up->dev);
 646         status = check_modem_status(up);
 647         pm_runtime_mark_last_busy(up->dev);
 648         pm_runtime_put_autosuspend(up->dev);
 649
 650         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 651
 652         if (status & UART_MSR_DCD)
 653                 ret |= TIOCM_CAR;
 654         if (status & UART_MSR_RI)
 655                 ret |= TIOCM_RNG;
 656         if (status & UART_MSR_DSR)
 657                 ret |= TIOCM_DSR;
 658         if (status & UART_MSR_CTS)
 659                 ret |= TIOCM_CTS;
 660         return ret;
 661 }
 662
 663 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 664 {
 665         struct uart_omap_port *up = to_uart_omap_port(port);
 666         unsigned char mcr = 0, old_mcr;
 667
 668         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 669         if (mctrl & TIOCM_RTS)
 670                 mcr |= UART_MCR_RTS;
 671         if (mctrl & TIOCM_DTR)
 672                 mcr |= UART_MCR_DTR;
 673         if (mctrl & TIOCM_OUT1)
 674                 mcr |= UART_MCR_OUT1;
 675         if (mctrl & TIOCM_OUT2)
 676                 mcr |= UART_MCR_OUT2;
 677         if (mctrl & TIOCM_LOOP)
 678                 mcr |= UART_MCR_LOOP;
 679
 680         pm_runtime_get_sync(up->dev);
 681         old_mcr = serial_in(up, UART_MCR);
 682         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 683                      UART_MCR_DTR | UART_MCR_RTS);
 684         up->mcr = old_mcr | mcr;
 685         serial_out(up, UART_MCR, up->mcr);
 686         pm_runtime_mark_last_busy(up->dev);
 687         pm_runtime_put_autosuspend(up->dev);
 688
 689         if (gpio_is_valid(up->DTR_gpio) &&
 690             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 691                 up->DTR_active = !up->DTR_active;
 692                 if (gpio_cansleep(up->DTR_gpio))
 693                         schedule_work(&up->qos_work);
 694                 else
 695                         gpio_set_value(up->DTR_gpio,
 696                                        up->DTR_active != up->DTR_inverted);
 697         }
 698 }
 699
 700 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 701 {
 702         struct uart_omap_port *up = to_uart_omap_port(port);
 703         unsigned long flags = 0;
 704
 705         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 706         pm_runtime_get_sync(up->dev);
 707         spin_lock_irqsave(&up->port.lock, flags);
 708         if (break_state == -1)
 709                 up->lcr |= UART_LCR_SBC;
 710         else
 711                 up->lcr &= ~UART_LCR_SBC;
 712         serial_out(up, UART_LCR, up->lcr);
 713         spin_unlock_irqrestore(&up->port.lock, flags);
 714         pm_runtime_mark_last_busy(up->dev);
 715         pm_runtime_put_autosuspend(up->dev);
 716 }
 717
 718 static int serial_omap_startup(struct uart_port *port)
 719 {
 720         struct uart_omap_port *up = to_uart_omap_port(port);
 721         unsigned long flags = 0;
 722         int retval;
 723
 724         /*
 725          * Allocate the IRQ
 726          */
 727         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 728                                 up->name, up);
 729         if (retval)
 730                 return retval;
 731
 732         /* Optional wake-up IRQ */
 733         if (up->wakeirq) {
 734                 retval = request_irq(up->wakeirq, serial_omap_irq,
 735                                      up->port.irqflags, up->name, up);
 736                 if (retval) {
 737                         free_irq(up->port.irq, up);
 738                         return retval;
 739                 }
 740                 disable_irq(up->wakeirq);
 741         } else {
 742                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
 743                          up->port.line);
 744         }
 745
 746         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 747
 748         pm_runtime_get_sync(up->dev);
 749         /*
 750          * Clear the FIFO buffers and disable them.
 751          * (they will be reenabled in set_termios())
 752          */
 753         serial_omap_clear_fifos(up);
 754         /* For Hardware flow control */
 755         serial_out(up, UART_MCR, UART_MCR_RTS);
 756
 757         /*
 758          * Clear the interrupt registers.
 759          */
 760         (void) serial_in(up, UART_LSR);
 761         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 762                 (void) serial_in(up, UART_RX);
 763         (void) serial_in(up, UART_IIR);
 764         (void) serial_in(up, UART_MSR);
 765
 766         /*
 767          * Now, initialize the UART
 768          */
 769         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 770         spin_lock_irqsave(&up->port.lock, flags);
 771         /*
 772          * Most PC uarts need OUT2 raised to enable interrupts.
 773          */
 774         up->port.mctrl |= TIOCM_OUT2;
 775         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 776         spin_unlock_irqrestore(&up->port.lock, flags);
 777
 778         up->msr_saved_flags = 0;
 779         /*
 780          * Finally, enable interrupts. Note: Modem status interrupts
 781          * are set via set_termios(), which will be occurring imminently
 782          * anyway, so we don't enable them here.
 783          */
 784         up->ier = UART_IER_RLSI | UART_IER_RDI;
 785         serial_out(up, UART_IER, up->ier);
 786
 787         /* Enable module level wake up */
 788         up->wer = OMAP_UART_WER_MOD_WKUP;
 789         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 790                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 791
 792         serial_out(up, UART_OMAP_WER, up->wer);
 793
 794         pm_runtime_mark_last_busy(up->dev);
 795         pm_runtime_put_autosuspend(up->dev);
 796         up->port_activity = jiffies;
 797         return 0;
 798 }
 799
 800 static void serial_omap_shutdown(struct uart_port *port)
 801 {
 802         struct uart_omap_port *up = to_uart_omap_port(port);
 803         unsigned long flags = 0;
 804
 805         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 806
 807         pm_runtime_get_sync(up->dev);
 808         /*
 809          * Disable interrupts from this port
 810          */
 811         up->ier = 0;
 812         serial_out(up, UART_IER, 0);
 813
 814         spin_lock_irqsave(&up->port.lock, flags);
 815         up->port.mctrl &= ~TIOCM_OUT2;
 816         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 817         spin_unlock_irqrestore(&up->port.lock, flags);
 818
 819         /*
 820          * Disable break condition and FIFOs
 821          */
 822         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 823         serial_omap_clear_fifos(up);
 824
 825         /*
 826          * Read data port to reset things, and then free the irq
 827          */
 828         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 829                 (void) serial_in(up, UART_RX);
 830
 831         pm_runtime_mark_last_busy(up->dev);
 832         pm_runtime_put_autosuspend(up->dev);
 833         free_irq(up->port.irq, up);
 834         if (up->wakeirq)
 835                 free_irq(up->wakeirq, up);
 836 }
 837
 838 static void serial_omap_uart_qos_work(struct work_struct *work)
 839 {
 840         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 841                                                 qos_work);
 842
 843         pm_qos_update_request(&up->pm_qos_request, up->latency);
 844         if (gpio_is_valid(up->DTR_gpio))
 845                 gpio_set_value_cansleep(up->DTR_gpio,
 846                                         up->DTR_active != up->DTR_inverted);
 847 }
 848
 849 static void
 850 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 851                         struct ktermios *old)
 852 {
 853         struct uart_omap_port *up = to_uart_omap_port(port);
 854         unsigned char cval = 0;
 855         unsigned long flags = 0;
 856         unsigned int baud, quot;
 857
 858         switch (termios->c_cflag & CSIZE) {
 859         case CS5:
 860                 cval = UART_LCR_WLEN5;
 861                 break;
 862         case CS6:
 863                 cval = UART_LCR_WLEN6;
 864                 break;
 865         case CS7:
 866                 cval = UART_LCR_WLEN7;
 867                 break;
 868         default:
 869         case CS8:
 870                 cval = UART_LCR_WLEN8;
 871                 break;
 872         }
 873
 874         if (termios->c_cflag & CSTOPB)
 875                 cval |= UART_LCR_STOP;
 876         if (termios->c_cflag & PARENB)
 877                 cval |= UART_LCR_PARITY;
 878         if (!(termios->c_cflag & PARODD))
 879                 cval |= UART_LCR_EPAR;
 880         if (termios->c_cflag & CMSPAR)
 881                 cval |= UART_LCR_SPAR;
 882
 883         /*
 884          * Ask the core to calculate the divisor for us.
 885          */
 886
 887         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 888         quot = serial_omap_get_divisor(port, baud);
 889
 890         /* calculate wakeup latency constraint */
 891         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 892         up->latency = up->calc_latency;
 893         schedule_work(&up->qos_work);
 894
 895         up->dll = quot & 0xff;
 896         up->dlh = quot >> 8;
 897         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 898
 899         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 900                         UART_FCR_ENABLE_FIFO;
 901
 902         /*
 903          * Ok, we're now changing the port state. Do it with
 904          * interrupts disabled.
 905          */
 906         pm_runtime_get_sync(up->dev);
 907         spin_lock_irqsave(&up->port.lock, flags);
 908
 909         /*
 910          * Update the per-port timeout.
 911          */
 912         uart_update_timeout(port, termios->c_cflag, baud);
 913
 914         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 915         if (termios->c_iflag & INPCK)
 916                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 917         if (termios->c_iflag & (BRKINT | PARMRK))
 918                 up->port.read_status_mask |= UART_LSR_BI;
 919
 920         /*
 921          * Characters to ignore
 922          */
 923         up->port.ignore_status_mask = 0;
 924         if (termios->c_iflag & IGNPAR)
 925                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 926         if (termios->c_iflag & IGNBRK) {
 927                 up->port.ignore_status_mask |= UART_LSR_BI;
 928                 /*
 929                  * If we're ignoring parity and break indicators,
 930                  * ignore overruns too (for real raw support).
 931                  */
 932                 if (termios->c_iflag & IGNPAR)
 933                         up->port.ignore_status_mask |= UART_LSR_OE;
 934         }
 935
 936         /*
 937          * ignore all characters if CREAD is not set
 938          */
 939         if ((termios->c_cflag & CREAD) == 0)
 940                 up->port.ignore_status_mask |= UART_LSR_DR;
 941
 942         /*
 943          * Modem status interrupts
 944          */
 945         up->ier &= ~UART_IER_MSI;
 946         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 947                 up->ier |= UART_IER_MSI;
 948         serial_out(up, UART_IER, up->ier);
 949         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 950         up->lcr = cval;
 951         up->scr = 0;
 952
 953         /* FIFOs and DMA Settings */
 954
 955         /* FCR can be changed only when the
 956          * baud clock is not running
 957          * DLL_REG and DLH_REG set to 0.
 958          */
 959         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 960         serial_out(up, UART_DLL, 0);
 961         serial_out(up, UART_DLM, 0);
 962         serial_out(up, UART_LCR, 0);
 963
 964         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 965
 966         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 967         up->efr &= ~UART_EFR_SCD;
 968         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 969
 970         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 971         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 972         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 973         /* FIFO ENABLE, DMA MODE */
 974
 975         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 976         /*
 977          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 978          * sets Enables the granularity of 1 for TRIGGER RX
 979          * level. Along with setting RX FIFO trigger level
 980          * to 1 (as noted below, 16 characters) and TLR[3:0]
 981          * to zero this will result RX FIFO threshold level
 982          * to 1 character, instead of 16 as noted in comment
 983          * below.
 984          */
 985
 986         /* Set receive FIFO threshold to 16 characters and
 987          * transmit FIFO threshold to 32 spaces
 988          */
 989         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 990         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 991         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 992                 UART_FCR_ENABLE_FIFO;
 993
 994         serial_out(up, UART_FCR, up->fcr);
 995         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 996
 997         serial_out(up, UART_OMAP_SCR, up->scr);
 998
 999         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
1000         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001         serial_out(up, UART_MCR, up->mcr);
1002         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1003         serial_out(up, UART_EFR, up->efr);
1004         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1005
1006         /* Protocol, Baud Rate, and Interrupt Settings */
1007
1008         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1009                 serial_omap_mdr1_errataset(up, up->mdr1);
1010         else
1011                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1012
1013         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1014         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1015
1016         serial_out(up, UART_LCR, 0);
1017         serial_out(up, UART_IER, 0);
1018         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1019
1020         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1021         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1022
1023         serial_out(up, UART_LCR, 0);
1024         serial_out(up, UART_IER, up->ier);
1025         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1026
1027         serial_out(up, UART_EFR, up->efr);
1028         serial_out(up, UART_LCR, cval);
1029
1030         if (!serial_omap_baud_is_mode16(port, baud))
1031                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1032         else
1033                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1034
1035         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1036                 serial_omap_mdr1_errataset(up, up->mdr1);
1037         else
1038                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1039
1040         /* Configure flow control */
1041         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1042
1043         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1044         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1045         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1046
1047         /* Enable access to TCR/TLR */
1048         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1049         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1050         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1051
1052         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1053
1054         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1055                 /* Enable AUTORTS and AUTOCTS */
1056                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1057
1058                 /* Ensure MCR RTS is asserted */
1059                 up->mcr |= UART_MCR_RTS;
1060         } else {
1061                 /* Disable AUTORTS and AUTOCTS */
1062                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1063         }
1064
1065         if (up->port.flags & UPF_SOFT_FLOW) {
1066                 /* clear SW control mode bits */
1067                 up->efr &= OMAP_UART_SW_CLR;
1068
1069                 /*
1070                  * IXON Flag:
1071                  * Enable XON/XOFF flow control on input.
1072                  * Receiver compares XON1, XOFF1.
1073                  */
1074                 if (termios->c_iflag & IXON)
1075                         up->efr |= OMAP_UART_SW_RX;
1076
1077                 /*
1078                  * IXOFF Flag:
1079                  * Enable XON/XOFF flow control on output.
1080                  * Transmit XON1, XOFF1
1081                  */
1082                 if (termios->c_iflag & IXOFF)
1083                         up->efr |= OMAP_UART_SW_TX;
1084
1085                 /*
1086                  * IXANY Flag:
1087                  * Enable any character to restart output.
1088                  * Operation resumes after receiving any
1089                  * character after recognition of the XOFF character
1090                  */
1091                 if (termios->c_iflag & IXANY)
1092                         up->mcr |= UART_MCR_XONANY;
1093                 else
1094                         up->mcr &= ~UART_MCR_XONANY;
1095         }
1096         serial_out(up, UART_MCR, up->mcr);
1097         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1098         serial_out(up, UART_EFR, up->efr);
1099         serial_out(up, UART_LCR, up->lcr);
1100
1101         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1102
1103         spin_unlock_irqrestore(&up->port.lock, flags);
1104         pm_runtime_mark_last_busy(up->dev);
1105         pm_runtime_put_autosuspend(up->dev);
1106         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1107 }
1108
1109 static void
1110 serial_omap_pm(struct uart_port *port, unsigned int state,
1111                unsigned int oldstate)
1112 {
1113         struct uart_omap_port *up = to_uart_omap_port(port);
1114         unsigned char efr;
1115
1116         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1117
1118         pm_runtime_get_sync(up->dev);
1119         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1120         efr = serial_in(up, UART_EFR);
1121         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1122         serial_out(up, UART_LCR, 0);
1123
1124         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1125         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1126         serial_out(up, UART_EFR, efr);
1127         serial_out(up, UART_LCR, 0);
1128
1129         if (!device_may_wakeup(up->dev)) {
1130                 if (!state)
1131                         pm_runtime_forbid(up->dev);
1132                 else
1133                         pm_runtime_allow(up->dev);
1134         }
1135
1136         pm_runtime_mark_last_busy(up->dev);
1137         pm_runtime_put_autosuspend(up->dev);
1138 }
1139
1140 static void serial_omap_release_port(struct uart_port *port)
1141 {
1142         dev_dbg(port->dev, "serial_omap_release_port+\n");
1143 }
1144
1145 static int serial_omap_request_port(struct uart_port *port)
1146 {
1147         dev_dbg(port->dev, "serial_omap_request_port+\n");
1148         return 0;
1149 }
1150
1151 static void serial_omap_config_port(struct uart_port *port, int flags)
1152 {
1153         struct uart_omap_port *up = to_uart_omap_port(port);
1154
1155         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1156                                                         up->port.line);
1157         up->port.type = PORT_OMAP;
1158         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1159 }
1160
1161 static int
1162 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1163 {
1164         /* we don't want the core code to modify any port params */
1165         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1166         return -EINVAL;
1167 }
1168
1169 static const char *
1170 serial_omap_type(struct uart_port *port)
1171 {
1172         struct uart_omap_port *up = to_uart_omap_port(port);
1173
1174         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1175         return up->name;
1176 }
1177
1178 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1179
1180 static inline void wait_for_xmitr(struct uart_omap_port *up)
1181 {
1182         unsigned int status, tmout = 10000;
1183
1184         /* Wait up to 10ms for the character(s) to be sent. */
1185         do {
1186                 status = serial_in(up, UART_LSR);
1187
1188                 if (status & UART_LSR_BI)
1189                         up->lsr_break_flag = UART_LSR_BI;
1190
1191                 if (--tmout == 0)
1192                         break;
1193                 udelay(1);
1194         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1195
1196         /* Wait up to 1s for flow control if necessary */
1197         if (up->port.flags & UPF_CONS_FLOW) {
1198                 tmout = 1000000;
1199                 for (tmout = 1000000; tmout; tmout--) {
1200                         unsigned int msr = serial_in(up, UART_MSR);
1201
1202                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1203                         if (msr & UART_MSR_CTS)
1204                                 break;
1205
1206                         udelay(1);
1207                 }
1208         }
1209 }
1210
1211 #ifdef CONFIG_CONSOLE_POLL
1212
1213 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1214 {
1215         struct uart_omap_port *up = to_uart_omap_port(port);
1216
1217         pm_runtime_get_sync(up->dev);
1218         wait_for_xmitr(up);
1219         serial_out(up, UART_TX, ch);
1220         pm_runtime_mark_last_busy(up->dev);
1221         pm_runtime_put_autosuspend(up->dev);
1222 }
1223
1224 static int serial_omap_poll_get_char(struct uart_port *port)
1225 {
1226         struct uart_omap_port *up = to_uart_omap_port(port);
1227         unsigned int status;
1228
1229         pm_runtime_get_sync(up->dev);
1230         status = serial_in(up, UART_LSR);
1231         if (!(status & UART_LSR_DR)) {
1232                 status = NO_POLL_CHAR;
1233                 goto out;
1234         }
1235
1236         status = serial_in(up, UART_RX);
1237
1238 out:
1239         pm_runtime_mark_last_busy(up->dev);
1240         pm_runtime_put_autosuspend(up->dev);
1241
1242         return status;
1243 }
1244
1245 #endif /* CONFIG_CONSOLE_POLL */
1246
1247 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1248
1249 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1250
1251 static struct uart_driver serial_omap_reg;
1252
1253 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1254 {
1255         struct uart_omap_port *up = to_uart_omap_port(port);
1256
1257         wait_for_xmitr(up);
1258         serial_out(up, UART_TX, ch);
1259 }
1260
1261 static void
1262 serial_omap_console_write(struct console *co, const char *s,
1263                 unsigned int count)
1264 {
1265         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1266         unsigned long flags;
1267         unsigned int ier;
1268         int locked = 1;
1269
1270         pm_runtime_get_sync(up->dev);
1271
1272         local_irq_save(flags);
1273         if (up->port.sysrq)
1274                 locked = 0;
1275         else if (oops_in_progress)
1276                 locked = spin_trylock(&up->port.lock);
1277         else
1278                 spin_lock(&up->port.lock);
1279
1280         /*
1281          * First save the IER then disable the interrupts
1282          */
1283         ier = serial_in(up, UART_IER);
1284         serial_out(up, UART_IER, 0);
1285
1286         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1287
1288         /*
1289          * Finally, wait for transmitter to become empty
1290          * and restore the IER
1291          */
1292         wait_for_xmitr(up);
1293         serial_out(up, UART_IER, ier);
1294         /*
1295          * The receive handling will happen properly because the
1296          * receive ready bit will still be set; it is not cleared
1297          * on read.  However, modem control will not, we must
1298          * call it if we have saved something in the saved flags
1299          * while processing with interrupts off.
1300          */
1301         if (up->msr_saved_flags)
1302                 check_modem_status(up);
1303
1304         pm_runtime_mark_last_busy(up->dev);
1305         pm_runtime_put_autosuspend(up->dev);
1306         if (locked)
1307                 spin_unlock(&up->port.lock);
1308         local_irq_restore(flags);
1309 }
1310
1311 static int __init
1312 serial_omap_console_setup(struct console *co, char *options)
1313 {
1314         struct uart_omap_port *up;
1315         int baud = 115200;
1316         int bits = 8;
1317         int parity = 'n';
1318         int flow = 'n';
1319
1320         if (serial_omap_console_ports[co->index] == NULL)
1321                 return -ENODEV;
1322         up = serial_omap_console_ports[co->index];
1323
1324         if (options)
1325                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1326
1327         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1328 }
1329
1330 static struct console serial_omap_console = {
1331         .name           = OMAP_SERIAL_NAME,
1332         .write          = serial_omap_console_write,
1333         .device         = uart_console_device,
1334         .setup          = serial_omap_console_setup,
1335         .flags          = CON_PRINTBUFFER,
1336         .index          = -1,
1337         .data           = &serial_omap_reg,
1338 };
1339
1340 static void serial_omap_add_console_port(struct uart_omap_port *up)
1341 {
1342         serial_omap_console_ports[up->port.line] = up;
1343 }
1344
1345 #define OMAP_CONSOLE    (&serial_omap_console)
1346
1347 #else
1348
1349 #define OMAP_CONSOLE    NULL
1350
1351 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1352 {}
1353
1354 #endif
1355
1356 /* Enable or disable the rs485 support */
1357 static void
1358 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1359 {
1360         struct uart_omap_port *up = to_uart_omap_port(port);
1361         unsigned long flags;
1362         unsigned int mode;
1363         int val;
1364
1365         pm_runtime_get_sync(up->dev);
1366         spin_lock_irqsave(&up->port.lock, flags);
1367
1368         /* Disable interrupts from this port */
1369         mode = up->ier;
1370         up->ier = 0;
1371         serial_out(up, UART_IER, 0);
1372
1373         /* store new config */
1374         up->rs485 = *rs485conf;
1375
1376         /*
1377          * Just as a precaution, only allow rs485
1378          * to be enabled if the gpio pin is valid
1379          */
1380         if (gpio_is_valid(up->rts_gpio)) {
1381                 /* enable / disable rts */
1382                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1383                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1384                 val = (up->rs485.flags & val) ? 1 : 0;
1385                 gpio_set_value(up->rts_gpio, val);
1386         } else
1387                 up->rs485.flags &= ~SER_RS485_ENABLED;
1388
1389         /* Enable interrupts */
1390         up->ier = mode;
1391         serial_out(up, UART_IER, up->ier);
1392
1393         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1394          * TX FIFO is below the trigger level.
1395          */
1396         if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1397             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1398                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1399                 serial_out(up, UART_OMAP_SCR, up->scr);
1400         }
1401
1402         spin_unlock_irqrestore(&up->port.lock, flags);
1403         pm_runtime_mark_last_busy(up->dev);
1404         pm_runtime_put_autosuspend(up->dev);
1405 }
1406
1407 static int
1408 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1409 {
1410         struct serial_rs485 rs485conf;
1411
1412         switch (cmd) {
1413         case TIOCSRS485:
1414                 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1415                                         sizeof(rs485conf)))
1416                         return -EFAULT;
1417
1418                 serial_omap_config_rs485(port, &rs485conf);
1419                 break;
1420
1421         case TIOCGRS485:
1422                 if (copy_to_user((struct serial_rs485 *) arg,
1423                                         &(to_uart_omap_port(port)->rs485),
1424                                         sizeof(rs485conf)))
1425                         return -EFAULT;
1426                 break;
1427
1428         default:
1429                 return -ENOIOCTLCMD;
1430         }
1431         return 0;
1432 }
1433
1434
1435 static struct uart_ops serial_omap_pops = {
1436         .tx_empty       = serial_omap_tx_empty,
1437         .set_mctrl      = serial_omap_set_mctrl,
1438         .get_mctrl      = serial_omap_get_mctrl,
1439         .stop_tx        = serial_omap_stop_tx,
1440         .start_tx       = serial_omap_start_tx,
1441         .throttle       = serial_omap_throttle,
1442         .unthrottle     = serial_omap_unthrottle,
1443         .stop_rx        = serial_omap_stop_rx,
1444         .enable_ms      = serial_omap_enable_ms,
1445         .break_ctl      = serial_omap_break_ctl,
1446         .startup        = serial_omap_startup,
1447         .shutdown       = serial_omap_shutdown,
1448         .set_termios    = serial_omap_set_termios,
1449         .pm             = serial_omap_pm,
1450         .type           = serial_omap_type,
1451         .release_port   = serial_omap_release_port,
1452         .request_port   = serial_omap_request_port,
1453         .config_port    = serial_omap_config_port,
1454         .verify_port    = serial_omap_verify_port,
1455         .ioctl          = serial_omap_ioctl,
1456 #ifdef CONFIG_CONSOLE_POLL
1457         .poll_put_char  = serial_omap_poll_put_char,
1458         .poll_get_char  = serial_omap_poll_get_char,
1459 #endif
1460 };
1461
1462 static struct uart_driver serial_omap_reg = {
1463         .owner          = THIS_MODULE,
1464         .driver_name    = "OMAP-SERIAL",
1465         .dev_name       = OMAP_SERIAL_NAME,
1466         .nr             = OMAP_MAX_HSUART_PORTS,
1467         .cons           = OMAP_CONSOLE,
1468 };
1469
1470 #ifdef CONFIG_PM_SLEEP
1471 static int serial_omap_prepare(struct device *dev)
1472 {
1473         struct uart_omap_port *up = dev_get_drvdata(dev);
1474
1475         up->is_suspending = true;
1476
1477         return 0;
1478 }
1479
1480 static void serial_omap_complete(struct device *dev)
1481 {
1482         struct uart_omap_port *up = dev_get_drvdata(dev);
1483
1484         up->is_suspending = false;
1485 }
1486
1487 static int serial_omap_suspend(struct device *dev)
1488 {
1489         struct uart_omap_port *up = dev_get_drvdata(dev);
1490
1491         uart_suspend_port(&serial_omap_reg, &up->port);
1492         flush_work(&up->qos_work);
1493
1494         return 0;
1495 }
1496
1497 static int serial_omap_resume(struct device *dev)
1498 {
1499         struct uart_omap_port *up = dev_get_drvdata(dev);
1500
1501         uart_resume_port(&serial_omap_reg, &up->port);
1502
1503         return 0;
1504 }
1505 #else
1506 #define serial_omap_prepare NULL
1507 #define serial_omap_complete NULL
1508 #endif /* CONFIG_PM_SLEEP */
1509
1510 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1511 {
1512         u32 mvr, scheme;
1513         u16 revision, major, minor;
1514
1515         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1516
1517         /* Check revision register scheme */
1518         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1519
1520         switch (scheme) {
1521         case 0: /* Legacy Scheme: OMAP2/3 */
1522                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1523                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1524                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1525                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1526                 break;
1527         case 1:
1528                 /* New Scheme: OMAP4+ */
1529                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1530                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1531                                         OMAP_UART_MVR_MAJ_SHIFT;
1532                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1533                 break;
1534         default:
1535                 dev_warn(up->dev,
1536                         "Unknown %s revision, defaulting to highest\n",
1537                         up->name);
1538                 /* highest possible revision */
1539                 major = 0xff;
1540                 minor = 0xff;
1541         }
1542
1543         /* normalize revision for the driver */
1544         revision = UART_BUILD_REVISION(major, minor);
1545
1546         switch (revision) {
1547         case OMAP_UART_REV_46:
1548                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1549                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1550                 break;
1551         case OMAP_UART_REV_52:
1552                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1553                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1554                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1555                 break;
1556         case OMAP_UART_REV_63:
1557                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1558                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1559                 break;
1560         default:
1561                 break;
1562         }
1563 }
1564
1565 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1566 {
1567         struct omap_uart_port_info *omap_up_info;
1568
1569         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1570         if (!omap_up_info)
1571                 return NULL; /* out of memory */
1572
1573         of_property_read_u32(dev->of_node, "clock-frequency",
1574                                          &omap_up_info->uartclk);
1575         return omap_up_info;
1576 }
1577
1578 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1579                                    struct device_node *np)
1580 {
1581         struct serial_rs485 *rs485conf = &up->rs485;
1582         u32 rs485_delay[2];
1583         enum of_gpio_flags flags;
1584         int ret;
1585
1586         rs485conf->flags = 0;
1587         up->rts_gpio = -EINVAL;
1588
1589         if (!np)
1590                 return 0;
1591
1592         if (of_property_read_bool(np, "rs485-rts-active-high"))
1593                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1594         else
1595                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1596
1597         /* check for tx enable gpio */
1598         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1599         if (gpio_is_valid(up->rts_gpio)) {
1600                 ret = gpio_request(up->rts_gpio, "omap-serial");
1601                 if (ret < 0)
1602                         return ret;
1603                 ret = gpio_direction_output(up->rts_gpio,
1604                                             flags & SER_RS485_RTS_AFTER_SEND);
1605                 if (ret < 0)
1606                         return ret;
1607         } else
1608                 up->rts_gpio = -EINVAL;
1609
1610         if (of_property_read_u32_array(np, "rs485-rts-delay",
1611                                     rs485_delay, 2) == 0) {
1612                 rs485conf->delay_rts_before_send = rs485_delay[0];
1613                 rs485conf->delay_rts_after_send = rs485_delay[1];
1614         }
1615
1616         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1617                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1618
1619         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1620                 rs485conf->flags |= SER_RS485_ENABLED;
1621
1622         return 0;
1623 }
1624
1625 static int serial_omap_probe(struct platform_device *pdev)
1626 {
1627         struct uart_omap_port   *up;
1628         struct resource         *mem, *irq;
1629         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1630         int ret, uartirq = 0, wakeirq = 0;
1631
1632         /* The optional wakeirq may be specified in the board dts file */
1633         if (pdev->dev.of_node) {
1634                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1635                 if (!uartirq)
1636                         return -EPROBE_DEFER;
1637                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1638                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1639                 pdev->dev.platform_data = omap_up_info;
1640         } else {
1641                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1642                 if (!irq) {
1643                         dev_err(&pdev->dev, "no irq resource?\n");
1644                         return -ENODEV;
1645                 }
1646                 uartirq = irq->start;
1647         }
1648
1649         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1650         if (!mem) {
1651                 dev_err(&pdev->dev, "no mem resource?\n");
1652                 return -ENODEV;
1653         }
1654
1655         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1656                                 pdev->dev.driver->name)) {
1657                 dev_err(&pdev->dev, "memory region already claimed\n");
1658                 return -EBUSY;
1659         }
1660
1661         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1662             omap_up_info->DTR_present) {
1663                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1664                 if (ret < 0)
1665                         return ret;
1666                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1667                                             omap_up_info->DTR_inverted);
1668                 if (ret < 0)
1669                         return ret;
1670         }
1671
1672         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1673         if (!up)
1674                 return -ENOMEM;
1675
1676         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1677             omap_up_info->DTR_present) {
1678                 up->DTR_gpio = omap_up_info->DTR_gpio;
1679                 up->DTR_inverted = omap_up_info->DTR_inverted;
1680         } else
1681                 up->DTR_gpio = -EINVAL;
1682         up->DTR_active = 0;
1683
1684         up->dev = &pdev->dev;
1685         up->port.dev = &pdev->dev;
1686         up->port.type = PORT_OMAP;
1687         up->port.iotype = UPIO_MEM;
1688         up->port.irq = uartirq;
1689         up->wakeirq = wakeirq;
1690
1691         up->port.regshift = 2;
1692         up->port.fifosize = 64;
1693         up->port.ops = &serial_omap_pops;
1694
1695         if (pdev->dev.of_node)
1696                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1697         else
1698                 up->port.line = pdev->id;
1699
1700         if (up->port.line < 0) {
1701                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1702                                                                 up->port.line);
1703                 ret = -ENODEV;
1704                 goto err_port_line;
1705         }
1706
1707         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1708         if (ret < 0)
1709                 goto err_rs485;
1710
1711         sprintf(up->name, "OMAP UART%d", up->port.line);
1712         up->port.mapbase = mem->start;
1713         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1714                                                 resource_size(mem));
1715         if (!up->port.membase) {
1716                 dev_err(&pdev->dev, "can't ioremap UART\n");
1717                 ret = -ENOMEM;
1718                 goto err_ioremap;
1719         }
1720
1721         up->port.flags = omap_up_info->flags;
1722         up->port.uartclk = omap_up_info->uartclk;
1723         if (!up->port.uartclk) {
1724                 up->port.uartclk = DEFAULT_CLK_SPEED;
1725                 dev_warn(&pdev->dev,
1726                          "No clock speed specified: using default: %d\n",
1727                          DEFAULT_CLK_SPEED);
1728         }
1729
1730         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1731         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1732         pm_qos_add_request(&up->pm_qos_request,
1733                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1734         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1735         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1736
1737         platform_set_drvdata(pdev, up);
1738         if (omap_up_info->autosuspend_timeout == 0)
1739                 omap_up_info->autosuspend_timeout = -1;
1740         device_init_wakeup(up->dev, true);
1741         pm_runtime_use_autosuspend(&pdev->dev);
1742         pm_runtime_set_autosuspend_delay(&pdev->dev,
1743                         omap_up_info->autosuspend_timeout);
1744
1745         pm_runtime_irq_safe(&pdev->dev);
1746         pm_runtime_enable(&pdev->dev);
1747
1748         pm_runtime_get_sync(&pdev->dev);
1749
1750         omap_serial_fill_features_erratas(up);
1751
1752         ui[up->port.line] = up;
1753         serial_omap_add_console_port(up);
1754
1755         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1756         if (ret != 0)
1757                 goto err_add_port;
1758
1759         pm_runtime_mark_last_busy(up->dev);
1760         pm_runtime_put_autosuspend(up->dev);
1761         return 0;
1762
1763 err_add_port:
1764         pm_runtime_put(&pdev->dev);
1765         pm_runtime_disable(&pdev->dev);
1766 err_ioremap:
1767 err_rs485:
1768 err_port_line:
1769         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1770                                 pdev->id, __func__, ret);
1771         return ret;
1772 }
1773
1774 static int serial_omap_remove(struct platform_device *dev)
1775 {
1776         struct uart_omap_port *up = platform_get_drvdata(dev);
1777
1778         pm_runtime_put_sync(up->dev);
1779         pm_runtime_disable(up->dev);
1780         uart_remove_one_port(&serial_omap_reg, &up->port);
1781         pm_qos_remove_request(&up->pm_qos_request);
1782
1783         return 0;
1784 }
1785
1786 /*
1787  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1788  * The access to uart register after MDR1 Access
1789  * causes UART to corrupt data.
1790  *
1791  * Need a delay =
1792  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1793  * give 10 times as much
1794  */
1795 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1796 {
1797         u8 timeout = 255;
1798
1799         serial_out(up, UART_OMAP_MDR1, mdr1);
1800         udelay(2);
1801         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1802                         UART_FCR_CLEAR_RCVR);
1803         /*
1804          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1805          * TX_FIFO_E bit is 1.
1806          */
1807         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1808                                 (UART_LSR_THRE | UART_LSR_DR))) {
1809                 timeout--;
1810                 if (!timeout) {
1811                         /* Should *never* happen. we warn and carry on */
1812                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1813                                                 serial_in(up, UART_LSR));
1814                         break;
1815                 }
1816                 udelay(1);
1817         }
1818 }
1819
1820 #ifdef CONFIG_PM_RUNTIME
1821 static void serial_omap_restore_context(struct uart_omap_port *up)
1822 {
1823         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1824                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1825         else
1826                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1827
1828         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1829         serial_out(up, UART_EFR, UART_EFR_ECB);
1830         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1831         serial_out(up, UART_IER, 0x0);
1832         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1833         serial_out(up, UART_DLL, up->dll);
1834         serial_out(up, UART_DLM, up->dlh);
1835         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1836         serial_out(up, UART_IER, up->ier);
1837         serial_out(up, UART_FCR, up->fcr);
1838         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1839         serial_out(up, UART_MCR, up->mcr);
1840         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1841         serial_out(up, UART_OMAP_SCR, up->scr);
1842         serial_out(up, UART_EFR, up->efr);
1843         serial_out(up, UART_LCR, up->lcr);
1844         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1845                 serial_omap_mdr1_errataset(up, up->mdr1);
1846         else
1847                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1848         serial_out(up, UART_OMAP_WER, up->wer);
1849 }
1850
1851 static int serial_omap_runtime_suspend(struct device *dev)
1852 {
1853         struct uart_omap_port *up = dev_get_drvdata(dev);
1854
1855         if (!up)
1856                 return -EINVAL;
1857
1858         /*
1859         * When using 'no_console_suspend', the console UART must not be
1860         * suspended. Since driver suspend is managed by runtime suspend,
1861         * preventing runtime suspend (by returning error) will keep device
1862         * active during suspend.
1863         */
1864         if (up->is_suspending && !console_suspend_enabled &&
1865             uart_console(&up->port))
1866                 return -EBUSY;
1867
1868         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1869
1870         if (device_may_wakeup(dev)) {
1871                 if (!up->wakeups_enabled) {
1872                         serial_omap_enable_wakeup(up, true);
1873                         up->wakeups_enabled = true;
1874                 }
1875         } else {
1876                 if (up->wakeups_enabled) {
1877                         serial_omap_enable_wakeup(up, false);
1878                         up->wakeups_enabled = false;
1879                 }
1880         }
1881
1882         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1883         schedule_work(&up->qos_work);
1884
1885         return 0;
1886 }
1887
1888 static int serial_omap_runtime_resume(struct device *dev)
1889 {
1890         struct uart_omap_port *up = dev_get_drvdata(dev);
1891
1892         int loss_cnt = serial_omap_get_context_loss_count(up);
1893
1894         if (loss_cnt < 0) {
1895                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1896                         loss_cnt);
1897                 serial_omap_restore_context(up);
1898         } else if (up->context_loss_cnt != loss_cnt) {
1899                 serial_omap_restore_context(up);
1900         }
1901         up->latency = up->calc_latency;
1902         schedule_work(&up->qos_work);
1903
1904         return 0;
1905 }
1906 #endif
1907
1908 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1909         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1910         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1911                                 serial_omap_runtime_resume, NULL)
1912         .prepare        = serial_omap_prepare,
1913         .complete       = serial_omap_complete,
1914 };
1915
1916 #if defined(CONFIG_OF)
1917 static const struct of_device_id omap_serial_of_match[] = {
1918         { .compatible = "ti,omap2-uart" },
1919         { .compatible = "ti,omap3-uart" },
1920         { .compatible = "ti,omap4-uart" },
1921         {},
1922 };
1923 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1924 #endif
1925
1926 static struct platform_driver serial_omap_driver = {
1927         .probe          = serial_omap_probe,
1928         .remove         = serial_omap_remove,
1929         .driver         = {
1930                 .name   = DRIVER_NAME,
1931                 .pm     = &serial_omap_dev_pm_ops,
1932                 .of_match_table = of_match_ptr(omap_serial_of_match),
1933         },
1934 };
1935
1936 static int __init serial_omap_init(void)
1937 {
1938         int ret;
1939
1940         ret = uart_register_driver(&serial_omap_reg);
1941         if (ret != 0)
1942                 return ret;
1943         ret = platform_driver_register(&serial_omap_driver);
1944         if (ret != 0)
1945                 uart_unregister_driver(&serial_omap_reg);
1946         return ret;
1947 }
1948
1949 static void __exit serial_omap_exit(void)
1950 {
1951         platform_driver_unregister(&serial_omap_driver);
1952         uart_unregister_driver(&serial_omap_reg);
1953 }
1954
1955 module_init(serial_omap_init);
1956 module_exit(serial_omap_exit);
1957
1958 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1959 MODULE_LICENSE("GPL");
1960 MODULE_AUTHOR("Texas Instruments Inc");