Pileus Git - ~andy/linux/blob - drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/of_irq.h>
  43 #include <linux/gpio.h>
  44 #include <linux/of_gpio.h>
  45 #include <linux/platform_data/serial-omap.h>
  46
  47 #include <dt-bindings/gpio/gpio.h>
  48
  49 #define OMAP_MAX_HSUART_PORTS   6
  50
  51 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  52
  53 #define OMAP_UART_REV_42 0x0402
  54 #define OMAP_UART_REV_46 0x0406
  55 #define OMAP_UART_REV_52 0x0502
  56 #define OMAP_UART_REV_63 0x0603
  57
  58 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  59
  60 /* Feature flags */
  61 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  62
  63 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  64 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  65
  66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  67
  68 /* SCR register bitmasks */
  69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  71 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  72
  73 /* FCR register bitmasks */
  74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  76
  77 /* MVR register bitmasks */
  78 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  79
  80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  82 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  83
  84 #define OMAP_UART_MVR_MAJ_MASK          0x700
  85 #define OMAP_UART_MVR_MAJ_SHIFT         8
  86 #define OMAP_UART_MVR_MIN_MASK          0x3f
  87
  88 #define OMAP_UART_DMA_CH_FREE   -1
  89
  90 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  91 #define OMAP_MODE13X_SPEED      230400
  92
  93 /* WER = 0x7F
  94  * Enable module level wakeup in WER reg
  95  */
  96 #define OMAP_UART_WER_MOD_WKUP  0X7F
  97
  98 /* Enable XON/XOFF flow control on output */
  99 #define OMAP_UART_SW_TX         0x08
 100
 101 /* Enable XON/XOFF flow control on input */
 102 #define OMAP_UART_SW_RX         0x02
 103
 104 #define OMAP_UART_SW_CLR        0xF0
 105
 106 #define OMAP_UART_TCR_TRIG      0x0F
 107
 108 struct uart_omap_dma {
 109         u8                      uart_dma_tx;
 110         u8                      uart_dma_rx;
 111         int                     rx_dma_channel;
 112         int                     tx_dma_channel;
 113         dma_addr_t              rx_buf_dma_phys;
 114         dma_addr_t              tx_buf_dma_phys;
 115         unsigned int            uart_base;
 116         /*
 117          * Buffer for rx dma.It is not required for tx because the buffer
 118          * comes from port structure.
 119          */
 120         unsigned char           *rx_buf;
 121         unsigned int            prev_rx_dma_pos;
 122         int                     tx_buf_size;
 123         int                     tx_dma_used;
 124         int                     rx_dma_used;
 125         spinlock_t              tx_lock;
 126         spinlock_t              rx_lock;
 127         /* timer to poll activity on rx dma */
 128         struct timer_list       rx_timer;
 129         unsigned int            rx_buf_size;
 130         unsigned int            rx_poll_rate;
 131         unsigned int            rx_timeout;
 132 };
 133
 134 struct uart_omap_port {
 135         struct uart_port        port;
 136         struct uart_omap_dma    uart_dma;
 137         struct device           *dev;
 138         int                     wakeirq;
 139
 140         unsigned char           ier;
 141         unsigned char           lcr;
 142         unsigned char           mcr;
 143         unsigned char           fcr;
 144         unsigned char           efr;
 145         unsigned char           dll;
 146         unsigned char           dlh;
 147         unsigned char           mdr1;
 148         unsigned char           scr;
 149         unsigned char           wer;
 150
 151         int                     use_dma;
 152         /*
 153          * Some bits in registers are cleared on a read, so they must
 154          * be saved whenever the register is read but the bits will not
 155          * be immediately processed.
 156          */
 157         unsigned int            lsr_break_flag;
 158         unsigned char           msr_saved_flags;
 159         char                    name[20];
 160         unsigned long           port_activity;
 161         int                     context_loss_cnt;
 162         u32                     errata;
 163         u8                      wakeups_enabled;
 164         u32                     features;
 165
 166         int                     DTR_gpio;
 167         int                     DTR_inverted;
 168         int                     DTR_active;
 169
 170         struct serial_rs485     rs485;
 171         int                     rts_gpio;
 172
 173         struct pm_qos_request   pm_qos_request;
 174         u32                     latency;
 175         u32                     calc_latency;
 176         struct work_struct      qos_work;
 177         bool                    is_suspending;
 178 };
 179
 180 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 181
 182 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 183
 184 /* Forward declaration of functions */
 185 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 186
 187 static struct workqueue_struct *serial_omap_uart_wq;
 188
 189 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 190 {
 191         offset <<= up->port.regshift;
 192         return readw(up->port.membase + offset);
 193 }
 194
 195 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 196 {
 197         offset <<= up->port.regshift;
 198         writew(value, up->port.membase + offset);
 199 }
 200
 201 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 202 {
 203         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 204         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 205                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 206         serial_out(up, UART_FCR, 0);
 207 }
 208
 209 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 210 {
 211         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 212
 213         if (!pdata || !pdata->get_context_loss_count)
 214                 return -EINVAL;
 215
 216         return pdata->get_context_loss_count(up->dev);
 217 }
 218
 219 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
 220                                        bool enable)
 221 {
 222         if (!up->wakeirq)
 223                 return;
 224
 225         if (enable)
 226                 enable_irq(up->wakeirq);
 227         else
 228                 disable_irq(up->wakeirq);
 229 }
 230
 231 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 232 {
 233         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 234
 235         serial_omap_enable_wakeirq(up, enable);
 236         if (!pdata || !pdata->enable_wakeup)
 237                 return;
 238
 239         pdata->enable_wakeup(up->dev, enable);
 240 }
 241
 242 /*
 243  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 244  * @port: uart port info
 245  * @baud: baudrate for which mode needs to be determined
 246  *
 247  * Returns true if baud rate is MODE16X and false if MODE13X
 248  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 249  * and Error Rates" determines modes not for all common baud rates.
 250  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 251  * table it's determined as 13x.
 252  */
 253 static bool
 254 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 255 {
 256         unsigned int n13 = port->uartclk / (13 * baud);
 257         unsigned int n16 = port->uartclk / (16 * baud);
 258         int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
 259         int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
 260         if (baudAbsDiff13 < 0)
 261                 baudAbsDiff13 = -baudAbsDiff13;
 262         if (baudAbsDiff16 < 0)
 263                 baudAbsDiff16 = -baudAbsDiff16;
 264
 265         return (baudAbsDiff13 >= baudAbsDiff16);
 266 }
 267
 268 /*
 269  * serial_omap_get_divisor - calculate divisor value
 270  * @port: uart port info
 271  * @baud: baudrate for which divisor needs to be calculated.
 272  */
 273 static unsigned int
 274 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 275 {
 276         unsigned int mode;
 277
 278         if (!serial_omap_baud_is_mode16(port, baud))
 279                 mode = 13;
 280         else
 281                 mode = 16;
 282         return port->uartclk/(mode * baud);
 283 }
 284
 285 static void serial_omap_enable_ms(struct uart_port *port)
 286 {
 287         struct uart_omap_port *up = to_uart_omap_port(port);
 288
 289         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 290
 291         pm_runtime_get_sync(up->dev);
 292         up->ier |= UART_IER_MSI;
 293         serial_out(up, UART_IER, up->ier);
 294         pm_runtime_mark_last_busy(up->dev);
 295         pm_runtime_put_autosuspend(up->dev);
 296 }
 297
 298 static void serial_omap_stop_tx(struct uart_port *port)
 299 {
 300         struct uart_omap_port *up = to_uart_omap_port(port);
 301         int res;
 302
 303         pm_runtime_get_sync(up->dev);
 304
 305         /* Handle RS-485 */
 306         if (up->rs485.flags & SER_RS485_ENABLED) {
 307                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 308                         /* THR interrupt is fired when both TX FIFO and TX
 309                          * shift register are empty. This means there's nothing
 310                          * left to transmit now, so make sure the THR interrupt
 311                          * is fired when TX FIFO is below the trigger level,
 312                          * disable THR interrupts and toggle the RS-485 GPIO
 313                          * data direction pin if needed.
 314                          */
 315                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 316                         serial_out(up, UART_OMAP_SCR, up->scr);
 317                         res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
 318                         if (gpio_get_value(up->rts_gpio) != res) {
 319                                 if (up->rs485.delay_rts_after_send > 0)
 320                                         mdelay(up->rs485.delay_rts_after_send);
 321                                 gpio_set_value(up->rts_gpio, res);
 322                         }
 323                 } else {
 324                         /* We're asked to stop, but there's still stuff in the
 325                          * UART FIFO, so make sure the THR interrupt is fired
 326                          * when both TX FIFO and TX shift register are empty.
 327                          * The next THR interrupt (if no transmission is started
 328                          * in the meantime) will indicate the end of a
 329                          * transmission. Therefore we _don't_ disable THR
 330                          * interrupts in this situation.
 331                          */
 332                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 333                         serial_out(up, UART_OMAP_SCR, up->scr);
 334                         return;
 335                 }
 336         }
 337
 338         if (up->ier & UART_IER_THRI) {
 339                 up->ier &= ~UART_IER_THRI;
 340                 serial_out(up, UART_IER, up->ier);
 341         }
 342
 343         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 344             !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
 345                 up->ier = UART_IER_RLSI | UART_IER_RDI;
 346                 serial_out(up, UART_IER, up->ier);
 347         }
 348
 349         pm_runtime_mark_last_busy(up->dev);
 350         pm_runtime_put_autosuspend(up->dev);
 351 }
 352
 353 static void serial_omap_stop_rx(struct uart_port *port)
 354 {
 355         struct uart_omap_port *up = to_uart_omap_port(port);
 356
 357         pm_runtime_get_sync(up->dev);
 358         up->ier &= ~UART_IER_RLSI;
 359         up->port.read_status_mask &= ~UART_LSR_DR;
 360         serial_out(up, UART_IER, up->ier);
 361         pm_runtime_mark_last_busy(up->dev);
 362         pm_runtime_put_autosuspend(up->dev);
 363 }
 364
 365 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 366 {
 367         struct circ_buf *xmit = &up->port.state->xmit;
 368         int count;
 369
 370         if (up->port.x_char) {
 371                 serial_out(up, UART_TX, up->port.x_char);
 372                 up->port.icount.tx++;
 373                 up->port.x_char = 0;
 374                 return;
 375         }
 376         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 377                 serial_omap_stop_tx(&up->port);
 378                 return;
 379         }
 380         count = up->port.fifosize / 4;
 381         do {
 382                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 383                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 384                 up->port.icount.tx++;
 385                 if (uart_circ_empty(xmit))
 386                         break;
 387         } while (--count > 0);
 388
 389         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 390                 spin_unlock(&up->port.lock);
 391                 uart_write_wakeup(&up->port);
 392                 spin_lock(&up->port.lock);
 393         }
 394
 395         if (uart_circ_empty(xmit))
 396                 serial_omap_stop_tx(&up->port);
 397 }
 398
 399 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 400 {
 401         if (!(up->ier & UART_IER_THRI)) {
 402                 up->ier |= UART_IER_THRI;
 403                 serial_out(up, UART_IER, up->ier);
 404         }
 405 }
 406
 407 static void serial_omap_start_tx(struct uart_port *port)
 408 {
 409         struct uart_omap_port *up = to_uart_omap_port(port);
 410         int res;
 411
 412         pm_runtime_get_sync(up->dev);
 413
 414         /* Handle RS-485 */
 415         if (up->rs485.flags & SER_RS485_ENABLED) {
 416                 /* Fire THR interrupts when FIFO is below trigger level */
 417                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 418                 serial_out(up, UART_OMAP_SCR, up->scr);
 419
 420                 /* if rts not already enabled */
 421                 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 422                 if (gpio_get_value(up->rts_gpio) != res) {
 423                         gpio_set_value(up->rts_gpio, res);
 424                         if (up->rs485.delay_rts_before_send > 0)
 425                                 mdelay(up->rs485.delay_rts_before_send);
 426                 }
 427         }
 428
 429         if ((up->rs485.flags & SER_RS485_ENABLED) &&
 430             !(up->rs485.flags & SER_RS485_RX_DURING_TX))
 431                 serial_omap_stop_rx(port);
 432
 433         serial_omap_enable_ier_thri(up);
 434         pm_runtime_mark_last_busy(up->dev);
 435         pm_runtime_put_autosuspend(up->dev);
 436 }
 437
 438 static void serial_omap_throttle(struct uart_port *port)
 439 {
 440         struct uart_omap_port *up = to_uart_omap_port(port);
 441         unsigned long flags;
 442
 443         pm_runtime_get_sync(up->dev);
 444         spin_lock_irqsave(&up->port.lock, flags);
 445         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 446         serial_out(up, UART_IER, up->ier);
 447         spin_unlock_irqrestore(&up->port.lock, flags);
 448         pm_runtime_mark_last_busy(up->dev);
 449         pm_runtime_put_autosuspend(up->dev);
 450 }
 451
 452 static void serial_omap_unthrottle(struct uart_port *port)
 453 {
 454         struct uart_omap_port *up = to_uart_omap_port(port);
 455         unsigned long flags;
 456
 457         pm_runtime_get_sync(up->dev);
 458         spin_lock_irqsave(&up->port.lock, flags);
 459         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 460         serial_out(up, UART_IER, up->ier);
 461         spin_unlock_irqrestore(&up->port.lock, flags);
 462         pm_runtime_mark_last_busy(up->dev);
 463         pm_runtime_put_autosuspend(up->dev);
 464 }
 465
 466 static unsigned int check_modem_status(struct uart_omap_port *up)
 467 {
 468         unsigned int status;
 469
 470         status = serial_in(up, UART_MSR);
 471         status |= up->msr_saved_flags;
 472         up->msr_saved_flags = 0;
 473         if ((status & UART_MSR_ANY_DELTA) == 0)
 474                 return status;
 475
 476         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 477             up->port.state != NULL) {
 478                 if (status & UART_MSR_TERI)
 479                         up->port.icount.rng++;
 480                 if (status & UART_MSR_DDSR)
 481                         up->port.icount.dsr++;
 482                 if (status & UART_MSR_DDCD)
 483                         uart_handle_dcd_change
 484                                 (&up->port, status & UART_MSR_DCD);
 485                 if (status & UART_MSR_DCTS)
 486                         uart_handle_cts_change
 487                                 (&up->port, status & UART_MSR_CTS);
 488                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 489         }
 490
 491         return status;
 492 }
 493
 494 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 495 {
 496         unsigned int flag;
 497         unsigned char ch = 0;
 498
 499         if (likely(lsr & UART_LSR_DR))
 500                 ch = serial_in(up, UART_RX);
 501
 502         up->port.icount.rx++;
 503         flag = TTY_NORMAL;
 504
 505         if (lsr & UART_LSR_BI) {
 506                 flag = TTY_BREAK;
 507                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 508                 up->port.icount.brk++;
 509                 /*
 510                  * We do the SysRQ and SAK checking
 511                  * here because otherwise the break
 512                  * may get masked by ignore_status_mask
 513                  * or read_status_mask.
 514                  */
 515                 if (uart_handle_break(&up->port))
 516                         return;
 517
 518         }
 519
 520         if (lsr & UART_LSR_PE) {
 521                 flag = TTY_PARITY;
 522                 up->port.icount.parity++;
 523         }
 524
 525         if (lsr & UART_LSR_FE) {
 526                 flag = TTY_FRAME;
 527                 up->port.icount.frame++;
 528         }
 529
 530         if (lsr & UART_LSR_OE)
 531                 up->port.icount.overrun++;
 532
 533 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 534         if (up->port.line == up->port.cons->index) {
 535                 /* Recover the break flag from console xmit */
 536                 lsr |= up->lsr_break_flag;
 537         }
 538 #endif
 539         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 540 }
 541
 542 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 543 {
 544         unsigned char ch = 0;
 545         unsigned int flag;
 546
 547         if (!(lsr & UART_LSR_DR))
 548                 return;
 549
 550         ch = serial_in(up, UART_RX);
 551         flag = TTY_NORMAL;
 552         up->port.icount.rx++;
 553
 554         if (uart_handle_sysrq_char(&up->port, ch))
 555                 return;
 556
 557         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 558 }
 559
 560 /**
 561  * serial_omap_irq() - This handles the interrupt from one port
 562  * @irq: uart port irq number
 563  * @dev_id: uart port info
 564  */
 565 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 566 {
 567         struct uart_omap_port *up = dev_id;
 568         unsigned int iir, lsr;
 569         unsigned int type;
 570         irqreturn_t ret = IRQ_NONE;
 571         int max_count = 256;
 572
 573         spin_lock(&up->port.lock);
 574         pm_runtime_get_sync(up->dev);
 575
 576         do {
 577                 iir = serial_in(up, UART_IIR);
 578                 if (iir & UART_IIR_NO_INT)
 579                         break;
 580
 581                 ret = IRQ_HANDLED;
 582                 lsr = serial_in(up, UART_LSR);
 583
 584                 /* extract IRQ type from IIR register */
 585                 type = iir & 0x3e;
 586
 587                 switch (type) {
 588                 case UART_IIR_MSI:
 589                         check_modem_status(up);
 590                         break;
 591                 case UART_IIR_THRI:
 592                         transmit_chars(up, lsr);
 593                         break;
 594                 case UART_IIR_RX_TIMEOUT:
 595                         /* FALLTHROUGH */
 596                 case UART_IIR_RDI:
 597                         serial_omap_rdi(up, lsr);
 598                         break;
 599                 case UART_IIR_RLSI:
 600                         serial_omap_rlsi(up, lsr);
 601                         break;
 602                 case UART_IIR_CTS_RTS_DSR:
 603                         /* simply try again */
 604                         break;
 605                 case UART_IIR_XOFF:
 606                         /* FALLTHROUGH */
 607                 default:
 608                         break;
 609                 }
 610         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 611
 612         spin_unlock(&up->port.lock);
 613
 614         tty_flip_buffer_push(&up->port.state->port);
 615
 616         pm_runtime_mark_last_busy(up->dev);
 617         pm_runtime_put_autosuspend(up->dev);
 618         up->port_activity = jiffies;
 619
 620         return ret;
 621 }
 622
 623 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 624 {
 625         struct uart_omap_port *up = to_uart_omap_port(port);
 626         unsigned long flags = 0;
 627         unsigned int ret = 0;
 628
 629         pm_runtime_get_sync(up->dev);
 630         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 631         spin_lock_irqsave(&up->port.lock, flags);
 632         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 633         spin_unlock_irqrestore(&up->port.lock, flags);
 634         pm_runtime_mark_last_busy(up->dev);
 635         pm_runtime_put_autosuspend(up->dev);
 636         return ret;
 637 }
 638
 639 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 640 {
 641         struct uart_omap_port *up = to_uart_omap_port(port);
 642         unsigned int status;
 643         unsigned int ret = 0;
 644
 645         pm_runtime_get_sync(up->dev);
 646         status = check_modem_status(up);
 647         pm_runtime_mark_last_busy(up->dev);
 648         pm_runtime_put_autosuspend(up->dev);
 649
 650         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 651
 652         if (status & UART_MSR_DCD)
 653                 ret |= TIOCM_CAR;
 654         if (status & UART_MSR_RI)
 655                 ret |= TIOCM_RNG;
 656         if (status & UART_MSR_DSR)
 657                 ret |= TIOCM_DSR;
 658         if (status & UART_MSR_CTS)
 659                 ret |= TIOCM_CTS;
 660         return ret;
 661 }
 662
 663 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 664 {
 665         struct uart_omap_port *up = to_uart_omap_port(port);
 666         unsigned char mcr = 0, old_mcr;
 667
 668         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 669         if (mctrl & TIOCM_RTS)
 670                 mcr |= UART_MCR_RTS;
 671         if (mctrl & TIOCM_DTR)
 672                 mcr |= UART_MCR_DTR;
 673         if (mctrl & TIOCM_OUT1)
 674                 mcr |= UART_MCR_OUT1;
 675         if (mctrl & TIOCM_OUT2)
 676                 mcr |= UART_MCR_OUT2;
 677         if (mctrl & TIOCM_LOOP)
 678                 mcr |= UART_MCR_LOOP;
 679
 680         pm_runtime_get_sync(up->dev);
 681         old_mcr = serial_in(up, UART_MCR);
 682         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 683                      UART_MCR_DTR | UART_MCR_RTS);
 684         up->mcr = old_mcr | mcr;
 685         serial_out(up, UART_MCR, up->mcr);
 686         pm_runtime_mark_last_busy(up->dev);
 687         pm_runtime_put_autosuspend(up->dev);
 688
 689         if (gpio_is_valid(up->DTR_gpio) &&
 690             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 691                 up->DTR_active = !up->DTR_active;
 692                 if (gpio_cansleep(up->DTR_gpio))
 693                         schedule_work(&up->qos_work);
 694                 else
 695                         gpio_set_value(up->DTR_gpio,
 696                                        up->DTR_active != up->DTR_inverted);
 697         }
 698 }
 699
 700 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 701 {
 702         struct uart_omap_port *up = to_uart_omap_port(port);
 703         unsigned long flags = 0;
 704
 705         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 706         pm_runtime_get_sync(up->dev);
 707         spin_lock_irqsave(&up->port.lock, flags);
 708         if (break_state == -1)
 709                 up->lcr |= UART_LCR_SBC;
 710         else
 711                 up->lcr &= ~UART_LCR_SBC;
 712         serial_out(up, UART_LCR, up->lcr);
 713         spin_unlock_irqrestore(&up->port.lock, flags);
 714         pm_runtime_mark_last_busy(up->dev);
 715         pm_runtime_put_autosuspend(up->dev);
 716 }
 717
 718 static int serial_omap_startup(struct uart_port *port)
 719 {
 720         struct uart_omap_port *up = to_uart_omap_port(port);
 721         unsigned long flags = 0;
 722         int retval;
 723
 724         /*
 725          * Allocate the IRQ
 726          */
 727         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 728                                 up->name, up);
 729         if (retval)
 730                 return retval;
 731
 732         /* Optional wake-up IRQ */
 733         if (up->wakeirq) {
 734                 retval = request_irq(up->wakeirq, serial_omap_irq,
 735                                      up->port.irqflags, up->name, up);
 736                 if (retval) {
 737                         free_irq(up->port.irq, up);
 738                         return retval;
 739                 }
 740                 disable_irq(up->wakeirq);
 741         }
 742
 743         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 744
 745         pm_runtime_get_sync(up->dev);
 746         /*
 747          * Clear the FIFO buffers and disable them.
 748          * (they will be reenabled in set_termios())
 749          */
 750         serial_omap_clear_fifos(up);
 751         /* For Hardware flow control */
 752         serial_out(up, UART_MCR, UART_MCR_RTS);
 753
 754         /*
 755          * Clear the interrupt registers.
 756          */
 757         (void) serial_in(up, UART_LSR);
 758         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 759                 (void) serial_in(up, UART_RX);
 760         (void) serial_in(up, UART_IIR);
 761         (void) serial_in(up, UART_MSR);
 762
 763         /*
 764          * Now, initialize the UART
 765          */
 766         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 767         spin_lock_irqsave(&up->port.lock, flags);
 768         /*
 769          * Most PC uarts need OUT2 raised to enable interrupts.
 770          */
 771         up->port.mctrl |= TIOCM_OUT2;
 772         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 773         spin_unlock_irqrestore(&up->port.lock, flags);
 774
 775         up->msr_saved_flags = 0;
 776         /*
 777          * Finally, enable interrupts. Note: Modem status interrupts
 778          * are set via set_termios(), which will be occurring imminently
 779          * anyway, so we don't enable them here.
 780          */
 781         up->ier = UART_IER_RLSI | UART_IER_RDI;
 782         serial_out(up, UART_IER, up->ier);
 783
 784         /* Enable module level wake up */
 785         up->wer = OMAP_UART_WER_MOD_WKUP;
 786         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 787                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 788
 789         serial_out(up, UART_OMAP_WER, up->wer);
 790
 791         pm_runtime_mark_last_busy(up->dev);
 792         pm_runtime_put_autosuspend(up->dev);
 793         up->port_activity = jiffies;
 794         return 0;
 795 }
 796
 797 static void serial_omap_shutdown(struct uart_port *port)
 798 {
 799         struct uart_omap_port *up = to_uart_omap_port(port);
 800         unsigned long flags = 0;
 801
 802         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 803
 804         pm_runtime_get_sync(up->dev);
 805         /*
 806          * Disable interrupts from this port
 807          */
 808         up->ier = 0;
 809         serial_out(up, UART_IER, 0);
 810
 811         spin_lock_irqsave(&up->port.lock, flags);
 812         up->port.mctrl &= ~TIOCM_OUT2;
 813         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 814         spin_unlock_irqrestore(&up->port.lock, flags);
 815
 816         /*
 817          * Disable break condition and FIFOs
 818          */
 819         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 820         serial_omap_clear_fifos(up);
 821
 822         /*
 823          * Read data port to reset things, and then free the irq
 824          */
 825         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 826                 (void) serial_in(up, UART_RX);
 827
 828         pm_runtime_mark_last_busy(up->dev);
 829         pm_runtime_put_autosuspend(up->dev);
 830         free_irq(up->port.irq, up);
 831         if (up->wakeirq)
 832                 free_irq(up->wakeirq, up);
 833 }
 834
 835 static void serial_omap_uart_qos_work(struct work_struct *work)
 836 {
 837         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 838                                                 qos_work);
 839
 840         pm_qos_update_request(&up->pm_qos_request, up->latency);
 841         if (gpio_is_valid(up->DTR_gpio))
 842                 gpio_set_value_cansleep(up->DTR_gpio,
 843                                         up->DTR_active != up->DTR_inverted);
 844 }
 845
 846 static void
 847 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 848                         struct ktermios *old)
 849 {
 850         struct uart_omap_port *up = to_uart_omap_port(port);
 851         unsigned char cval = 0;
 852         unsigned long flags = 0;
 853         unsigned int baud, quot;
 854
 855         switch (termios->c_cflag & CSIZE) {
 856         case CS5:
 857                 cval = UART_LCR_WLEN5;
 858                 break;
 859         case CS6:
 860                 cval = UART_LCR_WLEN6;
 861                 break;
 862         case CS7:
 863                 cval = UART_LCR_WLEN7;
 864                 break;
 865         default:
 866         case CS8:
 867                 cval = UART_LCR_WLEN8;
 868                 break;
 869         }
 870
 871         if (termios->c_cflag & CSTOPB)
 872                 cval |= UART_LCR_STOP;
 873         if (termios->c_cflag & PARENB)
 874                 cval |= UART_LCR_PARITY;
 875         if (!(termios->c_cflag & PARODD))
 876                 cval |= UART_LCR_EPAR;
 877         if (termios->c_cflag & CMSPAR)
 878                 cval |= UART_LCR_SPAR;
 879
 880         /*
 881          * Ask the core to calculate the divisor for us.
 882          */
 883
 884         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 885         quot = serial_omap_get_divisor(port, baud);
 886
 887         /* calculate wakeup latency constraint */
 888         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 889         up->latency = up->calc_latency;
 890         schedule_work(&up->qos_work);
 891
 892         up->dll = quot & 0xff;
 893         up->dlh = quot >> 8;
 894         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 895
 896         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 897                         UART_FCR_ENABLE_FIFO;
 898
 899         /*
 900          * Ok, we're now changing the port state. Do it with
 901          * interrupts disabled.
 902          */
 903         pm_runtime_get_sync(up->dev);
 904         spin_lock_irqsave(&up->port.lock, flags);
 905
 906         /*
 907          * Update the per-port timeout.
 908          */
 909         uart_update_timeout(port, termios->c_cflag, baud);
 910
 911         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 912         if (termios->c_iflag & INPCK)
 913                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 914         if (termios->c_iflag & (BRKINT | PARMRK))
 915                 up->port.read_status_mask |= UART_LSR_BI;
 916
 917         /*
 918          * Characters to ignore
 919          */
 920         up->port.ignore_status_mask = 0;
 921         if (termios->c_iflag & IGNPAR)
 922                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 923         if (termios->c_iflag & IGNBRK) {
 924                 up->port.ignore_status_mask |= UART_LSR_BI;
 925                 /*
 926                  * If we're ignoring parity and break indicators,
 927                  * ignore overruns too (for real raw support).
 928                  */
 929                 if (termios->c_iflag & IGNPAR)
 930                         up->port.ignore_status_mask |= UART_LSR_OE;
 931         }
 932
 933         /*
 934          * ignore all characters if CREAD is not set
 935          */
 936         if ((termios->c_cflag & CREAD) == 0)
 937                 up->port.ignore_status_mask |= UART_LSR_DR;
 938
 939         /*
 940          * Modem status interrupts
 941          */
 942         up->ier &= ~UART_IER_MSI;
 943         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 944                 up->ier |= UART_IER_MSI;
 945         serial_out(up, UART_IER, up->ier);
 946         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 947         up->lcr = cval;
 948         up->scr = 0;
 949
 950         /* FIFOs and DMA Settings */
 951
 952         /* FCR can be changed only when the
 953          * baud clock is not running
 954          * DLL_REG and DLH_REG set to 0.
 955          */
 956         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 957         serial_out(up, UART_DLL, 0);
 958         serial_out(up, UART_DLM, 0);
 959         serial_out(up, UART_LCR, 0);
 960
 961         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 962
 963         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 964         up->efr &= ~UART_EFR_SCD;
 965         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 966
 967         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 968         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 969         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 970         /* FIFO ENABLE, DMA MODE */
 971
 972         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 973         /*
 974          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 975          * sets Enables the granularity of 1 for TRIGGER RX
 976          * level. Along with setting RX FIFO trigger level
 977          * to 1 (as noted below, 16 characters) and TLR[3:0]
 978          * to zero this will result RX FIFO threshold level
 979          * to 1 character, instead of 16 as noted in comment
 980          * below.
 981          */
 982
 983         /* Set receive FIFO threshold to 16 characters and
 984          * transmit FIFO threshold to 32 spaces
 985          */
 986         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 987         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 988         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 989                 UART_FCR_ENABLE_FIFO;
 990
 991         serial_out(up, UART_FCR, up->fcr);
 992         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 993
 994         serial_out(up, UART_OMAP_SCR, up->scr);
 995
 996         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 997         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 998         serial_out(up, UART_MCR, up->mcr);
 999         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1000         serial_out(up, UART_EFR, up->efr);
1001         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1002
1003         /* Protocol, Baud Rate, and Interrupt Settings */
1004
1005         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1006                 serial_omap_mdr1_errataset(up, up->mdr1);
1007         else
1008                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1009
1010         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1011         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1012
1013         serial_out(up, UART_LCR, 0);
1014         serial_out(up, UART_IER, 0);
1015         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1016
1017         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
1018         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
1019
1020         serial_out(up, UART_LCR, 0);
1021         serial_out(up, UART_IER, up->ier);
1022         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1023
1024         serial_out(up, UART_EFR, up->efr);
1025         serial_out(up, UART_LCR, cval);
1026
1027         if (!serial_omap_baud_is_mode16(port, baud))
1028                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1029         else
1030                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1031
1032         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1033                 serial_omap_mdr1_errataset(up, up->mdr1);
1034         else
1035                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1036
1037         /* Configure flow control */
1038         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1039
1040         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1041         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1042         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1043
1044         /* Enable access to TCR/TLR */
1045         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1046         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1047         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1048
1049         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1050
1051         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1052                 /* Enable AUTORTS and AUTOCTS */
1053                 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1054
1055                 /* Ensure MCR RTS is asserted */
1056                 up->mcr |= UART_MCR_RTS;
1057         } else {
1058                 /* Disable AUTORTS and AUTOCTS */
1059                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1060         }
1061
1062         if (up->port.flags & UPF_SOFT_FLOW) {
1063                 /* clear SW control mode bits */
1064                 up->efr &= OMAP_UART_SW_CLR;
1065
1066                 /*
1067                  * IXON Flag:
1068                  * Enable XON/XOFF flow control on input.
1069                  * Receiver compares XON1, XOFF1.
1070                  */
1071                 if (termios->c_iflag & IXON)
1072                         up->efr |= OMAP_UART_SW_RX;
1073
1074                 /*
1075                  * IXOFF Flag:
1076                  * Enable XON/XOFF flow control on output.
1077                  * Transmit XON1, XOFF1
1078                  */
1079                 if (termios->c_iflag & IXOFF)
1080                         up->efr |= OMAP_UART_SW_TX;
1081
1082                 /*
1083                  * IXANY Flag:
1084                  * Enable any character to restart output.
1085                  * Operation resumes after receiving any
1086                  * character after recognition of the XOFF character
1087                  */
1088                 if (termios->c_iflag & IXANY)
1089                         up->mcr |= UART_MCR_XONANY;
1090                 else
1091                         up->mcr &= ~UART_MCR_XONANY;
1092         }
1093         serial_out(up, UART_MCR, up->mcr);
1094         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1095         serial_out(up, UART_EFR, up->efr);
1096         serial_out(up, UART_LCR, up->lcr);
1097
1098         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1099
1100         spin_unlock_irqrestore(&up->port.lock, flags);
1101         pm_runtime_mark_last_busy(up->dev);
1102         pm_runtime_put_autosuspend(up->dev);
1103         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1104 }
1105
1106 static void
1107 serial_omap_pm(struct uart_port *port, unsigned int state,
1108                unsigned int oldstate)
1109 {
1110         struct uart_omap_port *up = to_uart_omap_port(port);
1111         unsigned char efr;
1112
1113         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1114
1115         pm_runtime_get_sync(up->dev);
1116         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1117         efr = serial_in(up, UART_EFR);
1118         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1119         serial_out(up, UART_LCR, 0);
1120
1121         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1122         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1123         serial_out(up, UART_EFR, efr);
1124         serial_out(up, UART_LCR, 0);
1125
1126         if (!device_may_wakeup(up->dev)) {
1127                 if (!state)
1128                         pm_runtime_forbid(up->dev);
1129                 else
1130                         pm_runtime_allow(up->dev);
1131         }
1132
1133         pm_runtime_mark_last_busy(up->dev);
1134         pm_runtime_put_autosuspend(up->dev);
1135 }
1136
1137 static void serial_omap_release_port(struct uart_port *port)
1138 {
1139         dev_dbg(port->dev, "serial_omap_release_port+\n");
1140 }
1141
1142 static int serial_omap_request_port(struct uart_port *port)
1143 {
1144         dev_dbg(port->dev, "serial_omap_request_port+\n");
1145         return 0;
1146 }
1147
1148 static void serial_omap_config_port(struct uart_port *port, int flags)
1149 {
1150         struct uart_omap_port *up = to_uart_omap_port(port);
1151
1152         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1153                                                         up->port.line);
1154         up->port.type = PORT_OMAP;
1155         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1156 }
1157
1158 static int
1159 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1160 {
1161         /* we don't want the core code to modify any port params */
1162         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1163         return -EINVAL;
1164 }
1165
1166 static const char *
1167 serial_omap_type(struct uart_port *port)
1168 {
1169         struct uart_omap_port *up = to_uart_omap_port(port);
1170
1171         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1172         return up->name;
1173 }
1174
1175 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1176
1177 static inline void wait_for_xmitr(struct uart_omap_port *up)
1178 {
1179         unsigned int status, tmout = 10000;
1180
1181         /* Wait up to 10ms for the character(s) to be sent. */
1182         do {
1183                 status = serial_in(up, UART_LSR);
1184
1185                 if (status & UART_LSR_BI)
1186                         up->lsr_break_flag = UART_LSR_BI;
1187
1188                 if (--tmout == 0)
1189                         break;
1190                 udelay(1);
1191         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1192
1193         /* Wait up to 1s for flow control if necessary */
1194         if (up->port.flags & UPF_CONS_FLOW) {
1195                 tmout = 1000000;
1196                 for (tmout = 1000000; tmout; tmout--) {
1197                         unsigned int msr = serial_in(up, UART_MSR);
1198
1199                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1200                         if (msr & UART_MSR_CTS)
1201                                 break;
1202
1203                         udelay(1);
1204                 }
1205         }
1206 }
1207
1208 #ifdef CONFIG_CONSOLE_POLL
1209
1210 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1211 {
1212         struct uart_omap_port *up = to_uart_omap_port(port);
1213
1214         pm_runtime_get_sync(up->dev);
1215         wait_for_xmitr(up);
1216         serial_out(up, UART_TX, ch);
1217         pm_runtime_mark_last_busy(up->dev);
1218         pm_runtime_put_autosuspend(up->dev);
1219 }
1220
1221 static int serial_omap_poll_get_char(struct uart_port *port)
1222 {
1223         struct uart_omap_port *up = to_uart_omap_port(port);
1224         unsigned int status;
1225
1226         pm_runtime_get_sync(up->dev);
1227         status = serial_in(up, UART_LSR);
1228         if (!(status & UART_LSR_DR)) {
1229                 status = NO_POLL_CHAR;
1230                 goto out;
1231         }
1232
1233         status = serial_in(up, UART_RX);
1234
1235 out:
1236         pm_runtime_mark_last_busy(up->dev);
1237         pm_runtime_put_autosuspend(up->dev);
1238
1239         return status;
1240 }
1241
1242 #endif /* CONFIG_CONSOLE_POLL */
1243
1244 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1245
1246 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1247
1248 static struct uart_driver serial_omap_reg;
1249
1250 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1251 {
1252         struct uart_omap_port *up = to_uart_omap_port(port);
1253
1254         wait_for_xmitr(up);
1255         serial_out(up, UART_TX, ch);
1256 }
1257
1258 static void
1259 serial_omap_console_write(struct console *co, const char *s,
1260                 unsigned int count)
1261 {
1262         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1263         unsigned long flags;
1264         unsigned int ier;
1265         int locked = 1;
1266
1267         pm_runtime_get_sync(up->dev);
1268
1269         local_irq_save(flags);
1270         if (up->port.sysrq)
1271                 locked = 0;
1272         else if (oops_in_progress)
1273                 locked = spin_trylock(&up->port.lock);
1274         else
1275                 spin_lock(&up->port.lock);
1276
1277         /*
1278          * First save the IER then disable the interrupts
1279          */
1280         ier = serial_in(up, UART_IER);
1281         serial_out(up, UART_IER, 0);
1282
1283         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1284
1285         /*
1286          * Finally, wait for transmitter to become empty
1287          * and restore the IER
1288          */
1289         wait_for_xmitr(up);
1290         serial_out(up, UART_IER, ier);
1291         /*
1292          * The receive handling will happen properly because the
1293          * receive ready bit will still be set; it is not cleared
1294          * on read.  However, modem control will not, we must
1295          * call it if we have saved something in the saved flags
1296          * while processing with interrupts off.
1297          */
1298         if (up->msr_saved_flags)
1299                 check_modem_status(up);
1300
1301         pm_runtime_mark_last_busy(up->dev);
1302         pm_runtime_put_autosuspend(up->dev);
1303         if (locked)
1304                 spin_unlock(&up->port.lock);
1305         local_irq_restore(flags);
1306 }
1307
1308 static int __init
1309 serial_omap_console_setup(struct console *co, char *options)
1310 {
1311         struct uart_omap_port *up;
1312         int baud = 115200;
1313         int bits = 8;
1314         int parity = 'n';
1315         int flow = 'n';
1316
1317         if (serial_omap_console_ports[co->index] == NULL)
1318                 return -ENODEV;
1319         up = serial_omap_console_ports[co->index];
1320
1321         if (options)
1322                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1323
1324         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1325 }
1326
1327 static struct console serial_omap_console = {
1328         .name           = OMAP_SERIAL_NAME,
1329         .write          = serial_omap_console_write,
1330         .device         = uart_console_device,
1331         .setup          = serial_omap_console_setup,
1332         .flags          = CON_PRINTBUFFER,
1333         .index          = -1,
1334         .data           = &serial_omap_reg,
1335 };
1336
1337 static void serial_omap_add_console_port(struct uart_omap_port *up)
1338 {
1339         serial_omap_console_ports[up->port.line] = up;
1340 }
1341
1342 #define OMAP_CONSOLE    (&serial_omap_console)
1343
1344 #else
1345
1346 #define OMAP_CONSOLE    NULL
1347
1348 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1349 {}
1350
1351 #endif
1352
1353 /* Enable or disable the rs485 support */
1354 static void
1355 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1356 {
1357         struct uart_omap_port *up = to_uart_omap_port(port);
1358         unsigned long flags;
1359         unsigned int mode;
1360         int val;
1361
1362         pm_runtime_get_sync(up->dev);
1363         spin_lock_irqsave(&up->port.lock, flags);
1364
1365         /* Disable interrupts from this port */
1366         mode = up->ier;
1367         up->ier = 0;
1368         serial_out(up, UART_IER, 0);
1369
1370         /* store new config */
1371         up->rs485 = *rs485conf;
1372
1373         /*
1374          * Just as a precaution, only allow rs485
1375          * to be enabled if the gpio pin is valid
1376          */
1377         if (gpio_is_valid(up->rts_gpio)) {
1378                 /* enable / disable rts */
1379                 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1380                         SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1381                 val = (up->rs485.flags & val) ? 1 : 0;
1382                 gpio_set_value(up->rts_gpio, val);
1383         } else
1384                 up->rs485.flags &= ~SER_RS485_ENABLED;
1385
1386         /* Enable interrupts */
1387         up->ier = mode;
1388         serial_out(up, UART_IER, up->ier);
1389
1390         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1391          * TX FIFO is below the trigger level.
1392          */
1393         if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1394             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1395                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1396                 serial_out(up, UART_OMAP_SCR, up->scr);
1397         }
1398
1399         spin_unlock_irqrestore(&up->port.lock, flags);
1400         pm_runtime_mark_last_busy(up->dev);
1401         pm_runtime_put_autosuspend(up->dev);
1402 }
1403
1404 static int
1405 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1406 {
1407         struct serial_rs485 rs485conf;
1408
1409         switch (cmd) {
1410         case TIOCSRS485:
1411                 if (copy_from_user(&rs485conf, (struct serial_rs485 *) arg,
1412                                         sizeof(rs485conf)))
1413                         return -EFAULT;
1414
1415                 serial_omap_config_rs485(port, &rs485conf);
1416                 break;
1417
1418         case TIOCGRS485:
1419                 if (copy_to_user((struct serial_rs485 *) arg,
1420                                         &(to_uart_omap_port(port)->rs485),
1421                                         sizeof(rs485conf)))
1422                         return -EFAULT;
1423                 break;
1424
1425         default:
1426                 return -ENOIOCTLCMD;
1427         }
1428         return 0;
1429 }
1430
1431
1432 static struct uart_ops serial_omap_pops = {
1433         .tx_empty       = serial_omap_tx_empty,
1434         .set_mctrl      = serial_omap_set_mctrl,
1435         .get_mctrl      = serial_omap_get_mctrl,
1436         .stop_tx        = serial_omap_stop_tx,
1437         .start_tx       = serial_omap_start_tx,
1438         .throttle       = serial_omap_throttle,
1439         .unthrottle     = serial_omap_unthrottle,
1440         .stop_rx        = serial_omap_stop_rx,
1441         .enable_ms      = serial_omap_enable_ms,
1442         .break_ctl      = serial_omap_break_ctl,
1443         .startup        = serial_omap_startup,
1444         .shutdown       = serial_omap_shutdown,
1445         .set_termios    = serial_omap_set_termios,
1446         .pm             = serial_omap_pm,
1447         .type           = serial_omap_type,
1448         .release_port   = serial_omap_release_port,
1449         .request_port   = serial_omap_request_port,
1450         .config_port    = serial_omap_config_port,
1451         .verify_port    = serial_omap_verify_port,
1452         .ioctl          = serial_omap_ioctl,
1453 #ifdef CONFIG_CONSOLE_POLL
1454         .poll_put_char  = serial_omap_poll_put_char,
1455         .poll_get_char  = serial_omap_poll_get_char,
1456 #endif
1457 };
1458
1459 static struct uart_driver serial_omap_reg = {
1460         .owner          = THIS_MODULE,
1461         .driver_name    = "OMAP-SERIAL",
1462         .dev_name       = OMAP_SERIAL_NAME,
1463         .nr             = OMAP_MAX_HSUART_PORTS,
1464         .cons           = OMAP_CONSOLE,
1465 };
1466
1467 #ifdef CONFIG_PM_SLEEP
1468 static int serial_omap_prepare(struct device *dev)
1469 {
1470         struct uart_omap_port *up = dev_get_drvdata(dev);
1471
1472         up->is_suspending = true;
1473
1474         return 0;
1475 }
1476
1477 static void serial_omap_complete(struct device *dev)
1478 {
1479         struct uart_omap_port *up = dev_get_drvdata(dev);
1480
1481         up->is_suspending = false;
1482 }
1483
1484 static int serial_omap_suspend(struct device *dev)
1485 {
1486         struct uart_omap_port *up = dev_get_drvdata(dev);
1487
1488         uart_suspend_port(&serial_omap_reg, &up->port);
1489         flush_work(&up->qos_work);
1490
1491         return 0;
1492 }
1493
1494 static int serial_omap_resume(struct device *dev)
1495 {
1496         struct uart_omap_port *up = dev_get_drvdata(dev);
1497
1498         uart_resume_port(&serial_omap_reg, &up->port);
1499
1500         return 0;
1501 }
1502 #else
1503 #define serial_omap_prepare NULL
1504 #define serial_omap_complete NULL
1505 #endif /* CONFIG_PM_SLEEP */
1506
1507 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1508 {
1509         u32 mvr, scheme;
1510         u16 revision, major, minor;
1511
1512         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1513
1514         /* Check revision register scheme */
1515         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1516
1517         switch (scheme) {
1518         case 0: /* Legacy Scheme: OMAP2/3 */
1519                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1520                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1521                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1522                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1523                 break;
1524         case 1:
1525                 /* New Scheme: OMAP4+ */
1526                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1527                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1528                                         OMAP_UART_MVR_MAJ_SHIFT;
1529                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1530                 break;
1531         default:
1532                 dev_warn(up->dev,
1533                         "Unknown %s revision, defaulting to highest\n",
1534                         up->name);
1535                 /* highest possible revision */
1536                 major = 0xff;
1537                 minor = 0xff;
1538         }
1539
1540         /* normalize revision for the driver */
1541         revision = UART_BUILD_REVISION(major, minor);
1542
1543         switch (revision) {
1544         case OMAP_UART_REV_46:
1545                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1546                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1547                 break;
1548         case OMAP_UART_REV_52:
1549                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1550                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1551                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1552                 break;
1553         case OMAP_UART_REV_63:
1554                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1555                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1556                 break;
1557         default:
1558                 break;
1559         }
1560 }
1561
1562 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1563 {
1564         struct omap_uart_port_info *omap_up_info;
1565
1566         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1567         if (!omap_up_info)
1568                 return NULL; /* out of memory */
1569
1570         of_property_read_u32(dev->of_node, "clock-frequency",
1571                                          &omap_up_info->uartclk);
1572         return omap_up_info;
1573 }
1574
1575 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1576                                    struct device_node *np)
1577 {
1578         struct serial_rs485 *rs485conf = &up->rs485;
1579         u32 rs485_delay[2];
1580         enum of_gpio_flags flags;
1581         int ret;
1582
1583         rs485conf->flags = 0;
1584         up->rts_gpio = -EINVAL;
1585
1586         if (!np)
1587                 return 0;
1588
1589         if (of_property_read_bool(np, "rs485-rts-active-high"))
1590                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1591         else
1592                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1593
1594         /* check for tx enable gpio */
1595         up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1596         if (gpio_is_valid(up->rts_gpio)) {
1597                 ret = gpio_request(up->rts_gpio, "omap-serial");
1598                 if (ret < 0)
1599                         return ret;
1600                 ret = gpio_direction_output(up->rts_gpio,
1601                                             flags & SER_RS485_RTS_AFTER_SEND);
1602                 if (ret < 0)
1603                         return ret;
1604         } else if (up->rts_gpio == -EPROBE_DEFER) {
1605                 return -EPROBE_DEFER;
1606         } else {
1607                 up->rts_gpio = -EINVAL;
1608         }
1609
1610         if (of_property_read_u32_array(np, "rs485-rts-delay",
1611                                     rs485_delay, 2) == 0) {
1612                 rs485conf->delay_rts_before_send = rs485_delay[0];
1613                 rs485conf->delay_rts_after_send = rs485_delay[1];
1614         }
1615
1616         if (of_property_read_bool(np, "rs485-rx-during-tx"))
1617                 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1618
1619         if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1620                 rs485conf->flags |= SER_RS485_ENABLED;
1621
1622         return 0;
1623 }
1624
1625 static int serial_omap_probe(struct platform_device *pdev)
1626 {
1627         struct uart_omap_port   *up;
1628         struct resource         *mem, *irq;
1629         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1630         int ret, uartirq = 0, wakeirq = 0;
1631
1632         /* The optional wakeirq may be specified in the board dts file */
1633         if (pdev->dev.of_node) {
1634                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1635                 if (!uartirq)
1636                         return -EPROBE_DEFER;
1637                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1638                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1639                 pdev->dev.platform_data = omap_up_info;
1640         } else {
1641                 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1642                 if (!irq) {
1643                         dev_err(&pdev->dev, "no irq resource?\n");
1644                         return -ENODEV;
1645                 }
1646                 uartirq = irq->start;
1647         }
1648
1649         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1650         if (!mem) {
1651                 dev_err(&pdev->dev, "no mem resource?\n");
1652                 return -ENODEV;
1653         }
1654
1655         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1656                                 pdev->dev.driver->name)) {
1657                 dev_err(&pdev->dev, "memory region already claimed\n");
1658                 return -EBUSY;
1659         }
1660
1661         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1662             omap_up_info->DTR_present) {
1663                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1664                 if (ret < 0)
1665                         return ret;
1666                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1667                                             omap_up_info->DTR_inverted);
1668                 if (ret < 0)
1669                         return ret;
1670         }
1671
1672         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1673         if (!up)
1674                 return -ENOMEM;
1675
1676         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1677             omap_up_info->DTR_present) {
1678                 up->DTR_gpio = omap_up_info->DTR_gpio;
1679                 up->DTR_inverted = omap_up_info->DTR_inverted;
1680         } else
1681                 up->DTR_gpio = -EINVAL;
1682         up->DTR_active = 0;
1683
1684         up->dev = &pdev->dev;
1685         up->port.dev = &pdev->dev;
1686         up->port.type = PORT_OMAP;
1687         up->port.iotype = UPIO_MEM;
1688         up->port.irq = uartirq;
1689         up->wakeirq = wakeirq;
1690         if (!up->wakeirq)
1691                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1692                          up->port.line);
1693
1694         up->port.regshift = 2;
1695         up->port.fifosize = 64;
1696         up->port.ops = &serial_omap_pops;
1697
1698         if (pdev->dev.of_node)
1699                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1700         else
1701                 up->port.line = pdev->id;
1702
1703         if (up->port.line < 0) {
1704                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1705                                                                 up->port.line);
1706                 ret = -ENODEV;
1707                 goto err_port_line;
1708         }
1709
1710         ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1711         if (ret < 0)
1712                 goto err_rs485;
1713
1714         sprintf(up->name, "OMAP UART%d", up->port.line);
1715         up->port.mapbase = mem->start;
1716         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1717                                                 resource_size(mem));
1718         if (!up->port.membase) {
1719                 dev_err(&pdev->dev, "can't ioremap UART\n");
1720                 ret = -ENOMEM;
1721                 goto err_ioremap;
1722         }
1723
1724         up->port.flags = omap_up_info->flags;
1725         up->port.uartclk = omap_up_info->uartclk;
1726         if (!up->port.uartclk) {
1727                 up->port.uartclk = DEFAULT_CLK_SPEED;
1728                 dev_warn(&pdev->dev,
1729                          "No clock speed specified: using default: %d\n",
1730                          DEFAULT_CLK_SPEED);
1731         }
1732
1733         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1734         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1735         pm_qos_add_request(&up->pm_qos_request,
1736                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1737         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1738         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1739
1740         platform_set_drvdata(pdev, up);
1741         if (omap_up_info->autosuspend_timeout == 0)
1742                 omap_up_info->autosuspend_timeout = -1;
1743         device_init_wakeup(up->dev, true);
1744         pm_runtime_use_autosuspend(&pdev->dev);
1745         pm_runtime_set_autosuspend_delay(&pdev->dev,
1746                         omap_up_info->autosuspend_timeout);
1747
1748         pm_runtime_irq_safe(&pdev->dev);
1749         pm_runtime_enable(&pdev->dev);
1750
1751         pm_runtime_get_sync(&pdev->dev);
1752
1753         omap_serial_fill_features_erratas(up);
1754
1755         ui[up->port.line] = up;
1756         serial_omap_add_console_port(up);
1757
1758         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1759         if (ret != 0)
1760                 goto err_add_port;
1761
1762         pm_runtime_mark_last_busy(up->dev);
1763         pm_runtime_put_autosuspend(up->dev);
1764         return 0;
1765
1766 err_add_port:
1767         pm_runtime_put(&pdev->dev);
1768         pm_runtime_disable(&pdev->dev);
1769 err_ioremap:
1770 err_rs485:
1771 err_port_line:
1772         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1773                                 pdev->id, __func__, ret);
1774         return ret;
1775 }
1776
1777 static int serial_omap_remove(struct platform_device *dev)
1778 {
1779         struct uart_omap_port *up = platform_get_drvdata(dev);
1780
1781         pm_runtime_put_sync(up->dev);
1782         pm_runtime_disable(up->dev);
1783         uart_remove_one_port(&serial_omap_reg, &up->port);
1784         pm_qos_remove_request(&up->pm_qos_request);
1785
1786         return 0;
1787 }
1788
1789 /*
1790  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1791  * The access to uart register after MDR1 Access
1792  * causes UART to corrupt data.
1793  *
1794  * Need a delay =
1795  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1796  * give 10 times as much
1797  */
1798 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1799 {
1800         u8 timeout = 255;
1801
1802         serial_out(up, UART_OMAP_MDR1, mdr1);
1803         udelay(2);
1804         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1805                         UART_FCR_CLEAR_RCVR);
1806         /*
1807          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1808          * TX_FIFO_E bit is 1.
1809          */
1810         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1811                                 (UART_LSR_THRE | UART_LSR_DR))) {
1812                 timeout--;
1813                 if (!timeout) {
1814                         /* Should *never* happen. we warn and carry on */
1815                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1816                                                 serial_in(up, UART_LSR));
1817                         break;
1818                 }
1819                 udelay(1);
1820         }
1821 }
1822
1823 #ifdef CONFIG_PM_RUNTIME
1824 static void serial_omap_restore_context(struct uart_omap_port *up)
1825 {
1826         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1827                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1828         else
1829                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1830
1831         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1832         serial_out(up, UART_EFR, UART_EFR_ECB);
1833         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1834         serial_out(up, UART_IER, 0x0);
1835         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1836         serial_out(up, UART_DLL, up->dll);
1837         serial_out(up, UART_DLM, up->dlh);
1838         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1839         serial_out(up, UART_IER, up->ier);
1840         serial_out(up, UART_FCR, up->fcr);
1841         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1842         serial_out(up, UART_MCR, up->mcr);
1843         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1844         serial_out(up, UART_OMAP_SCR, up->scr);
1845         serial_out(up, UART_EFR, up->efr);
1846         serial_out(up, UART_LCR, up->lcr);
1847         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1848                 serial_omap_mdr1_errataset(up, up->mdr1);
1849         else
1850                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1851         serial_out(up, UART_OMAP_WER, up->wer);
1852 }
1853
1854 static int serial_omap_runtime_suspend(struct device *dev)
1855 {
1856         struct uart_omap_port *up = dev_get_drvdata(dev);
1857
1858         if (!up)
1859                 return -EINVAL;
1860
1861         /*
1862         * When using 'no_console_suspend', the console UART must not be
1863         * suspended. Since driver suspend is managed by runtime suspend,
1864         * preventing runtime suspend (by returning error) will keep device
1865         * active during suspend.
1866         */
1867         if (up->is_suspending && !console_suspend_enabled &&
1868             uart_console(&up->port))
1869                 return -EBUSY;
1870
1871         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1872
1873         if (device_may_wakeup(dev)) {
1874                 if (!up->wakeups_enabled) {
1875                         serial_omap_enable_wakeup(up, true);
1876                         up->wakeups_enabled = true;
1877                 }
1878         } else {
1879                 if (up->wakeups_enabled) {
1880                         serial_omap_enable_wakeup(up, false);
1881                         up->wakeups_enabled = false;
1882                 }
1883         }
1884
1885         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1886         schedule_work(&up->qos_work);
1887
1888         return 0;
1889 }
1890
1891 static int serial_omap_runtime_resume(struct device *dev)
1892 {
1893         struct uart_omap_port *up = dev_get_drvdata(dev);
1894
1895         int loss_cnt = serial_omap_get_context_loss_count(up);
1896
1897         if (loss_cnt < 0) {
1898                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1899                         loss_cnt);
1900                 serial_omap_restore_context(up);
1901         } else if (up->context_loss_cnt != loss_cnt) {
1902                 serial_omap_restore_context(up);
1903         }
1904         up->latency = up->calc_latency;
1905         schedule_work(&up->qos_work);
1906
1907         return 0;
1908 }
1909 #endif
1910
1911 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1912         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1913         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1914                                 serial_omap_runtime_resume, NULL)
1915         .prepare        = serial_omap_prepare,
1916         .complete       = serial_omap_complete,
1917 };
1918
1919 #if defined(CONFIG_OF)
1920 static const struct of_device_id omap_serial_of_match[] = {
1921         { .compatible = "ti,omap2-uart" },
1922         { .compatible = "ti,omap3-uart" },
1923         { .compatible = "ti,omap4-uart" },
1924         {},
1925 };
1926 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1927 #endif
1928
1929 static struct platform_driver serial_omap_driver = {
1930         .probe          = serial_omap_probe,
1931         .remove         = serial_omap_remove,
1932         .driver         = {
1933                 .name   = DRIVER_NAME,
1934                 .pm     = &serial_omap_dev_pm_ops,
1935                 .of_match_table = of_match_ptr(omap_serial_of_match),
1936         },
1937 };
1938
1939 static int __init serial_omap_init(void)
1940 {
1941         int ret;
1942
1943         ret = uart_register_driver(&serial_omap_reg);
1944         if (ret != 0)
1945                 return ret;
1946         ret = platform_driver_register(&serial_omap_driver);
1947         if (ret != 0)
1948                 uart_unregister_driver(&serial_omap_reg);
1949         return ret;
1950 }
1951
1952 static void __exit serial_omap_exit(void)
1953 {
1954         platform_driver_unregister(&serial_omap_driver);
1955         uart_unregister_driver(&serial_omap_reg);
1956 }
1957
1958 module_init(serial_omap_init);
1959 module_exit(serial_omap_exit);
1960
1961 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1962 MODULE_LICENSE("GPL");
1963 MODULE_AUTHOR("Texas Instruments Inc");