Pileus Git - ~andy/linux/blob - drivers/spi/spi-s3c64xx.c

   1 /*
   2  * Copyright (C) 2009 Samsung Electronics Ltd.
   3  *      Jaswinder Singh <jassi.brar@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/workqueue.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/dmaengine.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/gpio.h>
  32 #include <linux/of.h>
  33 #include <linux/of_gpio.h>
  34
  35 #include <linux/platform_data/spi-s3c64xx.h>
  36
  37 #ifdef CONFIG_S3C_DMA
  38 #include <mach/dma.h>
  39 #endif
  40
  41 #define MAX_SPI_PORTS           3
  42 #define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  43
  44 /* Registers and bit-fields */
  45
  46 #define S3C64XX_SPI_CH_CFG              0x00
  47 #define S3C64XX_SPI_CLK_CFG             0x04
  48 #define S3C64XX_SPI_MODE_CFG    0x08
  49 #define S3C64XX_SPI_SLAVE_SEL   0x0C
  50 #define S3C64XX_SPI_INT_EN              0x10
  51 #define S3C64XX_SPI_STATUS              0x14
  52 #define S3C64XX_SPI_TX_DATA             0x18
  53 #define S3C64XX_SPI_RX_DATA             0x1C
  54 #define S3C64XX_SPI_PACKET_CNT  0x20
  55 #define S3C64XX_SPI_PENDING_CLR 0x24
  56 #define S3C64XX_SPI_SWAP_CFG    0x28
  57 #define S3C64XX_SPI_FB_CLK              0x2C
  58
  59 #define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  60 #define S3C64XX_SPI_CH_SW_RST           (1<<5)
  61 #define S3C64XX_SPI_CH_SLAVE            (1<<4)
  62 #define S3C64XX_SPI_CPOL_L              (1<<3)
  63 #define S3C64XX_SPI_CPHA_B              (1<<2)
  64 #define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  65 #define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  66
  67 #define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  68 #define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  69 #define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  70 #define S3C64XX_SPI_PSR_MASK            0xff
  71
  72 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  73 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  74 #define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  75 #define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  76 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  77 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  78 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  79 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  80 #define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  81 #define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  82 #define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  83
  84 #define S3C64XX_SPI_SLAVE_AUTO                  (1<<1)
  85 #define S3C64XX_SPI_SLAVE_SIG_INACT             (1<<0)
  86
  87 #define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  88 #define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  89 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  90 #define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  91 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  92 #define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  93 #define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  94
  95 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  96 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR  (1<<4)
  97 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  98 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR  (1<<2)
  99 #define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
 100 #define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
 101
 102 #define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
 103
 104 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
 105 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
 106 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
 107 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
 108 #define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
 109
 110 #define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
 111 #define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
 112 #define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
 113 #define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
 114 #define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 115 #define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 116 #define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 117 #define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 118
 119 #define S3C64XX_SPI_FBCLK_MSK           (3<<0)
 120
 121 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 122 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 123                                 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 124 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 125 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 126                                         FIFO_LVL_MASK(i))
 127
 128 #define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 129 #define S3C64XX_SPI_TRAILCNT_OFF        19
 130
 131 #define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 132
 133 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 134 #define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 135
 136 #define RXBUSY    (1<<2)
 137 #define TXBUSY    (1<<3)
 138
 139 struct s3c64xx_spi_dma_data {
 140         struct dma_chan *ch;
 141         enum dma_transfer_direction direction;
 142         unsigned int dmach;
 143 };
 144
 145 /**
 146  * struct s3c64xx_spi_info - SPI Controller hardware info
 147  * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 148  * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 149  * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 150  * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 151  * @clk_from_cmu: True, if the controller does not include a clock mux and
 152  *      prescaler unit.
 153  *
 154  * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 155  * differ in some aspects such as the size of the fifo and spi bus clock
 156  * setup. Such differences are specified to the driver using this structure
 157  * which is provided as driver data to the driver.
 158  */
 159 struct s3c64xx_spi_port_config {
 160         int     fifo_lvl_mask[MAX_SPI_PORTS];
 161         int     rx_lvl_offset;
 162         int     tx_st_done;
 163         int     quirks;
 164         bool    high_speed;
 165         bool    clk_from_cmu;
 166 };
 167
 168 /**
 169  * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 170  * @clk: Pointer to the spi clock.
 171  * @src_clk: Pointer to the clock used to generate SPI signals.
 172  * @master: Pointer to the SPI Protocol master.
 173  * @cntrlr_info: Platform specific data for the controller this driver manages.
 174  * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
 175  * @lock: Controller specific lock.
 176  * @state: Set of FLAGS to indicate status.
 177  * @rx_dmach: Controller's DMA channel for Rx.
 178  * @tx_dmach: Controller's DMA channel for Tx.
 179  * @sfr_start: BUS address of SPI controller regs.
 180  * @regs: Pointer to ioremap'ed controller registers.
 181  * @irq: interrupt
 182  * @xfer_completion: To indicate completion of xfer task.
 183  * @cur_mode: Stores the active configuration of the controller.
 184  * @cur_bpw: Stores the active bits per word settings.
 185  * @cur_speed: Stores the active xfer clock speed.
 186  */
 187 struct s3c64xx_spi_driver_data {
 188         void __iomem                    *regs;
 189         struct clk                      *clk;
 190         struct clk                      *src_clk;
 191         struct platform_device          *pdev;
 192         struct spi_master               *master;
 193         struct s3c64xx_spi_info  *cntrlr_info;
 194         struct spi_device               *tgl_spi;
 195         spinlock_t                      lock;
 196         unsigned long                   sfr_start;
 197         struct completion               xfer_completion;
 198         unsigned                        state;
 199         unsigned                        cur_mode, cur_bpw;
 200         unsigned                        cur_speed;
 201         struct s3c64xx_spi_dma_data     rx_dma;
 202         struct s3c64xx_spi_dma_data     tx_dma;
 203 #ifdef CONFIG_S3C_DMA
 204         struct samsung_dma_ops          *ops;
 205 #endif
 206         struct s3c64xx_spi_port_config  *port_conf;
 207         unsigned int                    port_id;
 208         bool                            cs_gpio;
 209 };
 210
 211 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 212 {
 213         void __iomem *regs = sdd->regs;
 214         unsigned long loops;
 215         u32 val;
 216
 217         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 218
 219         val = readl(regs + S3C64XX_SPI_CH_CFG);
 220         val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 221         writel(val, regs + S3C64XX_SPI_CH_CFG);
 222
 223         val = readl(regs + S3C64XX_SPI_CH_CFG);
 224         val |= S3C64XX_SPI_CH_SW_RST;
 225         val &= ~S3C64XX_SPI_CH_HS_EN;
 226         writel(val, regs + S3C64XX_SPI_CH_CFG);
 227
 228         /* Flush TxFIFO*/
 229         loops = msecs_to_loops(1);
 230         do {
 231                 val = readl(regs + S3C64XX_SPI_STATUS);
 232         } while (TX_FIFO_LVL(val, sdd) && loops--);
 233
 234         if (loops == 0)
 235                 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 236
 237         /* Flush RxFIFO*/
 238         loops = msecs_to_loops(1);
 239         do {
 240                 val = readl(regs + S3C64XX_SPI_STATUS);
 241                 if (RX_FIFO_LVL(val, sdd))
 242                         readl(regs + S3C64XX_SPI_RX_DATA);
 243                 else
 244                         break;
 245         } while (loops--);
 246
 247         if (loops == 0)
 248                 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 249
 250         val = readl(regs + S3C64XX_SPI_CH_CFG);
 251         val &= ~S3C64XX_SPI_CH_SW_RST;
 252         writel(val, regs + S3C64XX_SPI_CH_CFG);
 253
 254         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 255         val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 256         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 257 }
 258
 259 static void s3c64xx_spi_dmacb(void *data)
 260 {
 261         struct s3c64xx_spi_driver_data *sdd;
 262         struct s3c64xx_spi_dma_data *dma = data;
 263         unsigned long flags;
 264
 265         if (dma->direction == DMA_DEV_TO_MEM)
 266                 sdd = container_of(data,
 267                         struct s3c64xx_spi_driver_data, rx_dma);
 268         else
 269                 sdd = container_of(data,
 270                         struct s3c64xx_spi_driver_data, tx_dma);
 271
 272         spin_lock_irqsave(&sdd->lock, flags);
 273
 274         if (dma->direction == DMA_DEV_TO_MEM) {
 275                 sdd->state &= ~RXBUSY;
 276                 if (!(sdd->state & TXBUSY))
 277                         complete(&sdd->xfer_completion);
 278         } else {
 279                 sdd->state &= ~TXBUSY;
 280                 if (!(sdd->state & RXBUSY))
 281                         complete(&sdd->xfer_completion);
 282         }
 283
 284         spin_unlock_irqrestore(&sdd->lock, flags);
 285 }
 286
 287 #ifdef CONFIG_S3C_DMA
 288 /* FIXME: remove this section once arch/arm/mach-s3c64xx uses dmaengine */
 289
 290 static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
 291         .name = "samsung-spi-dma",
 292 };
 293
 294 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 295                                         unsigned len, dma_addr_t buf)
 296 {
 297         struct s3c64xx_spi_driver_data *sdd;
 298         struct samsung_dma_prep info;
 299         struct samsung_dma_config config;
 300
 301         if (dma->direction == DMA_DEV_TO_MEM) {
 302                 sdd = container_of((void *)dma,
 303                         struct s3c64xx_spi_driver_data, rx_dma);
 304                 config.direction = sdd->rx_dma.direction;
 305                 config.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 306                 config.width = sdd->cur_bpw / 8;
 307                 sdd->ops->config((enum dma_ch)sdd->rx_dma.ch, &config);
 308         } else {
 309                 sdd = container_of((void *)dma,
 310                         struct s3c64xx_spi_driver_data, tx_dma);
 311                 config.direction =  sdd->tx_dma.direction;
 312                 config.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 313                 config.width = sdd->cur_bpw / 8;
 314                 sdd->ops->config((enum dma_ch)sdd->tx_dma.ch, &config);
 315         }
 316
 317         info.cap = DMA_SLAVE;
 318         info.len = len;
 319         info.fp = s3c64xx_spi_dmacb;
 320         info.fp_param = dma;
 321         info.direction = dma->direction;
 322         info.buf = buf;
 323
 324         sdd->ops->prepare((enum dma_ch)dma->ch, &info);
 325         sdd->ops->trigger((enum dma_ch)dma->ch);
 326 }
 327
 328 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
 329 {
 330         struct samsung_dma_req req;
 331         struct device *dev = &sdd->pdev->dev;
 332
 333         sdd->ops = samsung_dma_get_ops();
 334
 335         req.cap = DMA_SLAVE;
 336         req.client = &s3c64xx_spi_dma_client;
 337
 338         sdd->rx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 339                                         sdd->rx_dma.dmach, &req, dev, "rx");
 340         sdd->tx_dma.ch = (struct dma_chan *)(unsigned long)sdd->ops->request(
 341                                         sdd->tx_dma.dmach, &req, dev, "tx");
 342
 343         return 1;
 344 }
 345
 346 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 347 {
 348         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 349
 350         /*
 351          * If DMA resource was not available during
 352          * probe, no need to continue with dma requests
 353          * else Acquire DMA channels
 354          */
 355         while (!is_polling(sdd) && !acquire_dma(sdd))
 356                 usleep_range(10000, 11000);
 357
 358         return 0;
 359 }
 360
 361 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 362 {
 363         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 364
 365         /* Free DMA channels */
 366         if (!is_polling(sdd)) {
 367                 sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
 368                                         &s3c64xx_spi_dma_client);
 369                 sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
 370                                         &s3c64xx_spi_dma_client);
 371         }
 372
 373         return 0;
 374 }
 375
 376 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 377                                  struct s3c64xx_spi_dma_data *dma)
 378 {
 379         sdd->ops->stop((enum dma_ch)dma->ch);
 380 }
 381 #else
 382
 383 static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
 384                                         unsigned len, dma_addr_t buf)
 385 {
 386         struct s3c64xx_spi_driver_data *sdd;
 387         struct dma_slave_config config;
 388         struct dma_async_tx_descriptor *desc;
 389
 390         memset(&config, 0, sizeof(config));
 391
 392         if (dma->direction == DMA_DEV_TO_MEM) {
 393                 sdd = container_of((void *)dma,
 394                         struct s3c64xx_spi_driver_data, rx_dma);
 395                 config.direction = dma->direction;
 396                 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 397                 config.src_addr_width = sdd->cur_bpw / 8;
 398                 config.src_maxburst = 1;
 399                 dmaengine_slave_config(dma->ch, &config);
 400         } else {
 401                 sdd = container_of((void *)dma,
 402                         struct s3c64xx_spi_driver_data, tx_dma);
 403                 config.direction = dma->direction;
 404                 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 405                 config.dst_addr_width = sdd->cur_bpw / 8;
 406                 config.dst_maxburst = 1;
 407                 dmaengine_slave_config(dma->ch, &config);
 408         }
 409
 410         desc = dmaengine_prep_slave_single(dma->ch, buf, len,
 411                                         dma->direction, DMA_PREP_INTERRUPT);
 412
 413         desc->callback = s3c64xx_spi_dmacb;
 414         desc->callback_param = dma;
 415
 416         dmaengine_submit(desc);
 417         dma_async_issue_pending(dma->ch);
 418 }
 419
 420 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 421 {
 422         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 423         dma_filter_fn filter = sdd->cntrlr_info->filter;
 424         struct device *dev = &sdd->pdev->dev;
 425         dma_cap_mask_t mask;
 426         int ret;
 427
 428         if (!is_polling(sdd)) {
 429                 dma_cap_zero(mask);
 430                 dma_cap_set(DMA_SLAVE, mask);
 431
 432                 /* Acquire DMA channels */
 433                 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 434                                    (void *)sdd->rx_dma.dmach, dev, "rx");
 435                 if (!sdd->rx_dma.ch) {
 436                         dev_err(dev, "Failed to get RX DMA channel\n");
 437                         ret = -EBUSY;
 438                         goto out;
 439                 }
 440
 441                 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
 442                                    (void *)sdd->tx_dma.dmach, dev, "tx");
 443                 if (!sdd->tx_dma.ch) {
 444                         dev_err(dev, "Failed to get TX DMA channel\n");
 445                         ret = -EBUSY;
 446                         goto out_rx;
 447                 }
 448         }
 449
 450         ret = pm_runtime_get_sync(&sdd->pdev->dev);
 451         if (ret < 0) {
 452                 dev_err(dev, "Failed to enable device: %d\n", ret);
 453                 goto out_tx;
 454         }
 455
 456         return 0;
 457
 458 out_tx:
 459         dma_release_channel(sdd->tx_dma.ch);
 460 out_rx:
 461         dma_release_channel(sdd->rx_dma.ch);
 462 out:
 463         return ret;
 464 }
 465
 466 static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
 467 {
 468         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 469
 470         /* Free DMA channels */
 471         if (!is_polling(sdd)) {
 472                 dma_release_channel(sdd->rx_dma.ch);
 473                 dma_release_channel(sdd->tx_dma.ch);
 474         }
 475
 476         pm_runtime_put(&sdd->pdev->dev);
 477         return 0;
 478 }
 479
 480 static void s3c64xx_spi_dma_stop(struct s3c64xx_spi_driver_data *sdd,
 481                                  struct s3c64xx_spi_dma_data *dma)
 482 {
 483         dmaengine_terminate_all(dma->ch);
 484 }
 485 #endif
 486
 487 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 488                                 struct spi_device *spi,
 489                                 struct spi_transfer *xfer, int dma_mode)
 490 {
 491         void __iomem *regs = sdd->regs;
 492         u32 modecfg, chcfg;
 493
 494         modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 495         modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 496
 497         chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 498         chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 499
 500         if (dma_mode) {
 501                 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 502         } else {
 503                 /* Always shift in data in FIFO, even if xfer is Tx only,
 504                  * this helps setting PCKT_CNT value for generating clocks
 505                  * as exactly needed.
 506                  */
 507                 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 508                 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 509                                         | S3C64XX_SPI_PACKET_CNT_EN,
 510                                         regs + S3C64XX_SPI_PACKET_CNT);
 511         }
 512
 513         if (xfer->tx_buf != NULL) {
 514                 sdd->state |= TXBUSY;
 515                 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 516                 if (dma_mode) {
 517                         modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 518                         prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
 519                 } else {
 520                         switch (sdd->cur_bpw) {
 521                         case 32:
 522                                 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 523                                         xfer->tx_buf, xfer->len / 4);
 524                                 break;
 525                         case 16:
 526                                 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 527                                         xfer->tx_buf, xfer->len / 2);
 528                                 break;
 529                         default:
 530                                 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 531                                         xfer->tx_buf, xfer->len);
 532                                 break;
 533                         }
 534                 }
 535         }
 536
 537         if (xfer->rx_buf != NULL) {
 538                 sdd->state |= RXBUSY;
 539
 540                 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 541                                         && !(sdd->cur_mode & SPI_CPHA))
 542                         chcfg |= S3C64XX_SPI_CH_HS_EN;
 543
 544                 if (dma_mode) {
 545                         modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 546                         chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 547                         writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 548                                         | S3C64XX_SPI_PACKET_CNT_EN,
 549                                         regs + S3C64XX_SPI_PACKET_CNT);
 550                         prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
 551                 }
 552         }
 553
 554         writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 555         writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 556 }
 557
 558 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
 559                                                 struct spi_device *spi)
 560 {
 561         if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
 562                 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
 563                         /* Deselect the last toggled device */
 564                         if (spi->cs_gpio >= 0)
 565                                 gpio_set_value(spi->cs_gpio,
 566                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 567                 }
 568                 sdd->tgl_spi = NULL;
 569         }
 570
 571         if (spi->cs_gpio >= 0)
 572                 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 1 : 0);
 573 }
 574
 575 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 576                                         int timeout_ms)
 577 {
 578         void __iomem *regs = sdd->regs;
 579         unsigned long val = 1;
 580         u32 status;
 581
 582         /* max fifo depth available */
 583         u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 584
 585         if (timeout_ms)
 586                 val = msecs_to_loops(timeout_ms);
 587
 588         do {
 589                 status = readl(regs + S3C64XX_SPI_STATUS);
 590         } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 591
 592         /* return the actual received data length */
 593         return RX_FIFO_LVL(status, sdd);
 594 }
 595
 596 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
 597                                 struct spi_transfer *xfer, int dma_mode)
 598 {
 599         void __iomem *regs = sdd->regs;
 600         unsigned long val;
 601         int ms;
 602
 603         /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 604         ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 605         ms += 10; /* some tolerance */
 606
 607         if (dma_mode) {
 608                 val = msecs_to_jiffies(ms) + 10;
 609                 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 610         } else {
 611                 u32 status;
 612                 val = msecs_to_loops(ms);
 613                 do {
 614                         status = readl(regs + S3C64XX_SPI_STATUS);
 615                 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 616         }
 617
 618         if (dma_mode) {
 619                 u32 status;
 620
 621                 /*
 622                  * If the previous xfer was completed within timeout, then
 623                  * proceed further else return -EIO.
 624                  * DmaTx returns after simply writing data in the FIFO,
 625                  * w/o waiting for real transmission on the bus to finish.
 626                  * DmaRx returns only after Dma read data from FIFO which
 627                  * needs bus transmission to finish, so we don't worry if
 628                  * Xfer involved Rx(with or without Tx).
 629                  */
 630                 if (val && !xfer->rx_buf) {
 631                         val = msecs_to_loops(10);
 632                         status = readl(regs + S3C64XX_SPI_STATUS);
 633                         while ((TX_FIFO_LVL(status, sdd)
 634                                 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 635                                         && --val) {
 636                                 cpu_relax();
 637                                 status = readl(regs + S3C64XX_SPI_STATUS);
 638                         }
 639
 640                 }
 641
 642                 /* If timed out while checking rx/tx status return error */
 643                 if (!val)
 644                         return -EIO;
 645         } else {
 646                 int loops;
 647                 u32 cpy_len;
 648                 u8 *buf;
 649
 650                 /* If it was only Tx */
 651                 if (!xfer->rx_buf) {
 652                         sdd->state &= ~TXBUSY;
 653                         return 0;
 654                 }
 655
 656                 /*
 657                  * If the receive length is bigger than the controller fifo
 658                  * size, calculate the loops and read the fifo as many times.
 659                  * loops = length / max fifo size (calculated by using the
 660                  * fifo mask).
 661                  * For any size less than the fifo size the below code is
 662                  * executed atleast once.
 663                  */
 664                 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 665                 buf = xfer->rx_buf;
 666                 do {
 667                         /* wait for data to be received in the fifo */
 668                         cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 669                                                 (loops ? ms : 0));
 670
 671                         switch (sdd->cur_bpw) {
 672                         case 32:
 673                                 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 674                                         buf, cpy_len / 4);
 675                                 break;
 676                         case 16:
 677                                 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 678                                         buf, cpy_len / 2);
 679                                 break;
 680                         default:
 681                                 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 682                                         buf, cpy_len);
 683                                 break;
 684                         }
 685
 686                         buf = buf + cpy_len;
 687                 } while (loops--);
 688                 sdd->state &= ~RXBUSY;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
 695                                                 struct spi_device *spi)
 696 {
 697         if (sdd->tgl_spi == spi)
 698                 sdd->tgl_spi = NULL;
 699
 700         if (spi->cs_gpio >= 0)
 701                 gpio_set_value(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 702 }
 703
 704 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 705 {
 706         void __iomem *regs = sdd->regs;
 707         u32 val;
 708
 709         /* Disable Clock */
 710         if (sdd->port_conf->clk_from_cmu) {
 711                 clk_disable_unprepare(sdd->src_clk);
 712         } else {
 713                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 714                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 715                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 716         }
 717
 718         /* Set Polarity and Phase */
 719         val = readl(regs + S3C64XX_SPI_CH_CFG);
 720         val &= ~(S3C64XX_SPI_CH_SLAVE |
 721                         S3C64XX_SPI_CPOL_L |
 722                         S3C64XX_SPI_CPHA_B);
 723
 724         if (sdd->cur_mode & SPI_CPOL)
 725                 val |= S3C64XX_SPI_CPOL_L;
 726
 727         if (sdd->cur_mode & SPI_CPHA)
 728                 val |= S3C64XX_SPI_CPHA_B;
 729
 730         writel(val, regs + S3C64XX_SPI_CH_CFG);
 731
 732         /* Set Channel & DMA Mode */
 733         val = readl(regs + S3C64XX_SPI_MODE_CFG);
 734         val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 735                         | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 736
 737         switch (sdd->cur_bpw) {
 738         case 32:
 739                 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 740                 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 741                 break;
 742         case 16:
 743                 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 744                 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 745                 break;
 746         default:
 747                 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 748                 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 749                 break;
 750         }
 751
 752         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 753
 754         if (sdd->port_conf->clk_from_cmu) {
 755                 /* Configure Clock */
 756                 /* There is half-multiplier before the SPI */
 757                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 758                 /* Enable Clock */
 759                 clk_prepare_enable(sdd->src_clk);
 760         } else {
 761                 /* Configure Clock */
 762                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 763                 val &= ~S3C64XX_SPI_PSR_MASK;
 764                 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 765                                 & S3C64XX_SPI_PSR_MASK);
 766                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 767
 768                 /* Enable Clock */
 769                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
 770                 val |= S3C64XX_SPI_ENCLK_ENABLE;
 771                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
 772         }
 773 }
 774
 775 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 776
 777 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
 778                                                 struct spi_message *msg)
 779 {
 780         struct device *dev = &sdd->pdev->dev;
 781         struct spi_transfer *xfer;
 782
 783         if (is_polling(sdd) || msg->is_dma_mapped)
 784                 return 0;
 785
 786         /* First mark all xfer unmapped */
 787         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 788                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 789                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 790         }
 791
 792         /* Map until end or first fail */
 793         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 794
 795                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 796                         continue;
 797
 798                 if (xfer->tx_buf != NULL) {
 799                         xfer->tx_dma = dma_map_single(dev,
 800                                         (void *)xfer->tx_buf, xfer->len,
 801                                         DMA_TO_DEVICE);
 802                         if (dma_mapping_error(dev, xfer->tx_dma)) {
 803                                 dev_err(dev, "dma_map_single Tx failed\n");
 804                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 805                                 return -ENOMEM;
 806                         }
 807                 }
 808
 809                 if (xfer->rx_buf != NULL) {
 810                         xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
 811                                                 xfer->len, DMA_FROM_DEVICE);
 812                         if (dma_mapping_error(dev, xfer->rx_dma)) {
 813                                 dev_err(dev, "dma_map_single Rx failed\n");
 814                                 dma_unmap_single(dev, xfer->tx_dma,
 815                                                 xfer->len, DMA_TO_DEVICE);
 816                                 xfer->tx_dma = XFER_DMAADDR_INVALID;
 817                                 xfer->rx_dma = XFER_DMAADDR_INVALID;
 818                                 return -ENOMEM;
 819                         }
 820                 }
 821         }
 822
 823         return 0;
 824 }
 825
 826 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
 827                                                 struct spi_message *msg)
 828 {
 829         struct device *dev = &sdd->pdev->dev;
 830         struct spi_transfer *xfer;
 831
 832         if (is_polling(sdd) || msg->is_dma_mapped)
 833                 return;
 834
 835         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 836
 837                 if (xfer->len <= ((FIFO_LVL_MASK(sdd) >> 1) + 1))
 838                         continue;
 839
 840                 if (xfer->rx_buf != NULL
 841                                 && xfer->rx_dma != XFER_DMAADDR_INVALID)
 842                         dma_unmap_single(dev, xfer->rx_dma,
 843                                                 xfer->len, DMA_FROM_DEVICE);
 844
 845                 if (xfer->tx_buf != NULL
 846                                 && xfer->tx_dma != XFER_DMAADDR_INVALID)
 847                         dma_unmap_single(dev, xfer->tx_dma,
 848                                                 xfer->len, DMA_TO_DEVICE);
 849         }
 850 }
 851
 852 static int s3c64xx_spi_prepare_message(struct spi_master *master,
 853                                        struct spi_message *msg)
 854 {
 855         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 856         struct spi_device *spi = msg->spi;
 857         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 858
 859         /* If Master's(controller) state differs from that needed by Slave */
 860         if (sdd->cur_speed != spi->max_speed_hz
 861                         || sdd->cur_mode != spi->mode
 862                         || sdd->cur_bpw != spi->bits_per_word) {
 863                 sdd->cur_bpw = spi->bits_per_word;
 864                 sdd->cur_speed = spi->max_speed_hz;
 865                 sdd->cur_mode = spi->mode;
 866                 s3c64xx_spi_config(sdd);
 867         }
 868
 869         /* Map all the transfers if needed */
 870         if (s3c64xx_spi_map_mssg(sdd, msg)) {
 871                 dev_err(&spi->dev,
 872                         "Xfer: Unable to map message buffers!\n");
 873                 return -ENOMEM;
 874         }
 875
 876         /* Configure feedback delay */
 877         writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 878
 879         return 0;
 880 }
 881
 882 static int s3c64xx_spi_transfer_one(struct spi_master *master,
 883                                     struct spi_device *spi,
 884                                     struct spi_transfer *xfer)
 885 {
 886         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 887         int status;
 888         u32 speed;
 889         u8 bpw;
 890         unsigned long flags;
 891         int use_dma;
 892
 893         reinit_completion(&sdd->xfer_completion);
 894
 895         /* Only BPW and Speed may change across transfers */
 896         bpw = xfer->bits_per_word;
 897         speed = xfer->speed_hz ? : spi->max_speed_hz;
 898
 899         if (xfer->len % (bpw / 8)) {
 900                 dev_err(&spi->dev,
 901                         "Xfer length(%u) not a multiple of word size(%u)\n",
 902                         xfer->len, bpw / 8);
 903                 return -EIO;
 904         }
 905
 906         if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 907                 sdd->cur_bpw = bpw;
 908                 sdd->cur_speed = speed;
 909                 s3c64xx_spi_config(sdd);
 910         }
 911
 912         /* Polling method for xfers not bigger than FIFO capacity */
 913         use_dma = 0;
 914         if (!is_polling(sdd) &&
 915             (sdd->rx_dma.ch && sdd->tx_dma.ch &&
 916              (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
 917                 use_dma = 1;
 918
 919         spin_lock_irqsave(&sdd->lock, flags);
 920
 921         /* Pending only which is to be done */
 922         sdd->state &= ~RXBUSY;
 923         sdd->state &= ~TXBUSY;
 924
 925         enable_datapath(sdd, spi, xfer, use_dma);
 926
 927         /* Start the signals */
 928         writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
 929
 930         spin_unlock_irqrestore(&sdd->lock, flags);
 931
 932         status = wait_for_xfer(sdd, xfer, use_dma);
 933
 934         if (status) {
 935                 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
 936                         xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 937                         (sdd->state & RXBUSY) ? 'f' : 'p',
 938                         (sdd->state & TXBUSY) ? 'f' : 'p',
 939                         xfer->len);
 940
 941                 if (use_dma) {
 942                         if (xfer->tx_buf != NULL
 943                             && (sdd->state & TXBUSY))
 944                                 s3c64xx_spi_dma_stop(sdd, &sdd->tx_dma);
 945                         if (xfer->rx_buf != NULL
 946                             && (sdd->state & RXBUSY))
 947                                 s3c64xx_spi_dma_stop(sdd, &sdd->rx_dma);
 948                 }
 949         } else {
 950                 flush_fifo(sdd);
 951         }
 952
 953         return status;
 954 }
 955
 956 static int s3c64xx_spi_unprepare_message(struct spi_master *master,
 957                                             struct spi_message *msg)
 958 {
 959         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 960
 961         s3c64xx_spi_unmap_mssg(sdd, msg);
 962
 963         return 0;
 964 }
 965
 966 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 967                                 struct spi_device *spi)
 968 {
 969         struct s3c64xx_spi_csinfo *cs;
 970         struct device_node *slave_np, *data_np = NULL;
 971         struct s3c64xx_spi_driver_data *sdd;
 972         u32 fb_delay = 0;
 973
 974         sdd = spi_master_get_devdata(spi->master);
 975         slave_np = spi->dev.of_node;
 976         if (!slave_np) {
 977                 dev_err(&spi->dev, "device node not found\n");
 978                 return ERR_PTR(-EINVAL);
 979         }
 980
 981         data_np = of_get_child_by_name(slave_np, "controller-data");
 982         if (!data_np) {
 983                 dev_err(&spi->dev, "child node 'controller-data' not found\n");
 984                 return ERR_PTR(-EINVAL);
 985         }
 986
 987         cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 988         if (!cs) {
 989                 dev_err(&spi->dev, "could not allocate memory for controller data\n");
 990                 of_node_put(data_np);
 991                 return ERR_PTR(-ENOMEM);
 992         }
 993
 994         /* The CS line is asserted/deasserted by the gpio pin */
 995         if (sdd->cs_gpio)
 996                 cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
 997
 998         if (!gpio_is_valid(cs->line)) {
 999                 dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
1000                 kfree(cs);
1001                 of_node_put(data_np);
1002                 return ERR_PTR(-EINVAL);
1003         }
1004
1005         of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
1006         cs->fb_delay = fb_delay;
1007         of_node_put(data_np);
1008         return cs;
1009 }
1010
1011 /*
1012  * Here we only check the validity of requested configuration
1013  * and save the configuration in a local data-structure.
1014  * The controller is actually configured only just before we
1015  * get a message to transfer.
1016  */
1017 static int s3c64xx_spi_setup(struct spi_device *spi)
1018 {
1019         struct s3c64xx_spi_csinfo *cs = spi->controller_data;
1020         struct s3c64xx_spi_driver_data *sdd;
1021         struct s3c64xx_spi_info *sci;
1022         int err;
1023
1024         sdd = spi_master_get_devdata(spi->master);
1025         if (!cs && spi->dev.of_node) {
1026                 cs = s3c64xx_get_slave_ctrldata(spi);
1027                 spi->controller_data = cs;
1028         }
1029
1030         if (IS_ERR_OR_NULL(cs)) {
1031                 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
1032                 return -ENODEV;
1033         }
1034
1035         if (!spi_get_ctldata(spi)) {
1036                 /* Request gpio only if cs line is asserted by gpio pins */
1037                 if (sdd->cs_gpio) {
1038                         err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
1039                                         dev_name(&spi->dev));
1040                         if (err) {
1041                                 dev_err(&spi->dev,
1042                                         "Failed to get /CS gpio [%d]: %d\n",
1043                                         cs->line, err);
1044                                 goto err_gpio_req;
1045                         }
1046
1047                         spi->cs_gpio = cs->line;
1048                 }
1049
1050                 spi_set_ctldata(spi, cs);
1051         }
1052
1053         sci = sdd->cntrlr_info;
1054
1055         pm_runtime_get_sync(&sdd->pdev->dev);
1056
1057         /* Check if we can provide the requested rate */
1058         if (!sdd->port_conf->clk_from_cmu) {
1059                 u32 psr, speed;
1060
1061                 /* Max possible */
1062                 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
1063
1064                 if (spi->max_speed_hz > speed)
1065                         spi->max_speed_hz = speed;
1066
1067                 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
1068                 psr &= S3C64XX_SPI_PSR_MASK;
1069                 if (psr == S3C64XX_SPI_PSR_MASK)
1070                         psr--;
1071
1072                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1073                 if (spi->max_speed_hz < speed) {
1074                         if (psr+1 < S3C64XX_SPI_PSR_MASK) {
1075                                 psr++;
1076                         } else {
1077                                 err = -EINVAL;
1078                                 goto setup_exit;
1079                         }
1080                 }
1081
1082                 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
1083                 if (spi->max_speed_hz >= speed) {
1084                         spi->max_speed_hz = speed;
1085                 } else {
1086                         dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
1087                                 spi->max_speed_hz);
1088                         err = -EINVAL;
1089                         goto setup_exit;
1090                 }
1091         }
1092
1093         pm_runtime_put(&sdd->pdev->dev);
1094         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1095         disable_cs(sdd, spi);
1096         return 0;
1097
1098 setup_exit:
1099         pm_runtime_put(&sdd->pdev->dev);
1100         /* setup() returns with device de-selected */
1101         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1102         disable_cs(sdd, spi);
1103
1104         gpio_free(cs->line);
1105         spi_set_ctldata(spi, NULL);
1106
1107 err_gpio_req:
1108         if (spi->dev.of_node)
1109                 kfree(cs);
1110
1111         return err;
1112 }
1113
1114 static void s3c64xx_spi_cleanup(struct spi_device *spi)
1115 {
1116         struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
1117         struct s3c64xx_spi_driver_data *sdd;
1118
1119         sdd = spi_master_get_devdata(spi->master);
1120         if (spi->cs_gpio) {
1121                 gpio_free(spi->cs_gpio);
1122                 if (spi->dev.of_node)
1123                         kfree(cs);
1124         }
1125         spi_set_ctldata(spi, NULL);
1126 }
1127
1128 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
1129 {
1130         struct s3c64xx_spi_driver_data *sdd = data;
1131         struct spi_master *spi = sdd->master;
1132         unsigned int val, clr = 0;
1133
1134         val = readl(sdd->regs + S3C64XX_SPI_STATUS);
1135
1136         if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
1137                 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
1138                 dev_err(&spi->dev, "RX overrun\n");
1139         }
1140         if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
1141                 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
1142                 dev_err(&spi->dev, "RX underrun\n");
1143         }
1144         if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
1145                 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
1146                 dev_err(&spi->dev, "TX overrun\n");
1147         }
1148         if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
1149                 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1150                 dev_err(&spi->dev, "TX underrun\n");
1151         }
1152
1153         /* Clear the pending irq by setting and then clearing it */
1154         writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1155         writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
1156
1157         return IRQ_HANDLED;
1158 }
1159
1160 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
1161 {
1162         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1163         void __iomem *regs = sdd->regs;
1164         unsigned int val;
1165
1166         sdd->cur_speed = 0;
1167
1168         writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
1169
1170         /* Disable Interrupts - we use Polling if not DMA mode */
1171         writel(0, regs + S3C64XX_SPI_INT_EN);
1172
1173         if (!sdd->port_conf->clk_from_cmu)
1174                 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
1175                                 regs + S3C64XX_SPI_CLK_CFG);
1176         writel(0, regs + S3C64XX_SPI_MODE_CFG);
1177         writel(0, regs + S3C64XX_SPI_PACKET_CNT);
1178
1179         /* Clear any irq pending bits, should set and clear the bits */
1180         val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1181                 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1182                 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1183                 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1184         writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1185         writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1186
1187         writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1188
1189         val = readl(regs + S3C64XX_SPI_MODE_CFG);
1190         val &= ~S3C64XX_SPI_MODE_4BURST;
1191         val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1192         val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1193         writel(val, regs + S3C64XX_SPI_MODE_CFG);
1194
1195         flush_fifo(sdd);
1196 }
1197
1198 #ifdef CONFIG_OF
1199 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1200 {
1201         struct s3c64xx_spi_info *sci;
1202         u32 temp;
1203
1204         sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1205         if (!sci) {
1206                 dev_err(dev, "memory allocation for spi_info failed\n");
1207                 return ERR_PTR(-ENOMEM);
1208         }
1209
1210         if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1211                 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1212                 sci->src_clk_nr = 0;
1213         } else {
1214                 sci->src_clk_nr = temp;
1215         }
1216
1217         if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1218                 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1219                 sci->num_cs = 1;
1220         } else {
1221                 sci->num_cs = temp;
1222         }
1223
1224         return sci;
1225 }
1226 #else
1227 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1228 {
1229         return dev_get_platdata(dev);
1230 }
1231 #endif
1232
1233 static const struct of_device_id s3c64xx_spi_dt_match[];
1234
1235 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1236                                                 struct platform_device *pdev)
1237 {
1238 #ifdef CONFIG_OF
1239         if (pdev->dev.of_node) {
1240                 const struct of_device_id *match;
1241                 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1242                 return (struct s3c64xx_spi_port_config *)match->data;
1243         }
1244 #endif
1245         return (struct s3c64xx_spi_port_config *)
1246                          platform_get_device_id(pdev)->driver_data;
1247 }
1248
1249 static int s3c64xx_spi_probe(struct platform_device *pdev)
1250 {
1251         struct resource *mem_res;
1252         struct resource *res;
1253         struct s3c64xx_spi_driver_data *sdd;
1254         struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1255         struct spi_master *master;
1256         int ret, irq;
1257         char clk_name[16];
1258
1259         if (!sci && pdev->dev.of_node) {
1260                 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1261                 if (IS_ERR(sci))
1262                         return PTR_ERR(sci);
1263         }
1264
1265         if (!sci) {
1266                 dev_err(&pdev->dev, "platform_data missing!\n");
1267                 return -ENODEV;
1268         }
1269
1270         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1271         if (mem_res == NULL) {
1272                 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1273                 return -ENXIO;
1274         }
1275
1276         irq = platform_get_irq(pdev, 0);
1277         if (irq < 0) {
1278                 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1279                 return irq;
1280         }
1281
1282         master = spi_alloc_master(&pdev->dev,
1283                                 sizeof(struct s3c64xx_spi_driver_data));
1284         if (master == NULL) {
1285                 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1286                 return -ENOMEM;
1287         }
1288
1289         platform_set_drvdata(pdev, master);
1290
1291         sdd = spi_master_get_devdata(master);
1292         sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1293         sdd->master = master;
1294         sdd->cntrlr_info = sci;
1295         sdd->pdev = pdev;
1296         sdd->sfr_start = mem_res->start;
1297         sdd->cs_gpio = true;
1298         if (pdev->dev.of_node) {
1299                 if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
1300                         sdd->cs_gpio = false;
1301
1302                 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1303                 if (ret < 0) {
1304                         dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1305                                 ret);
1306                         goto err0;
1307                 }
1308                 sdd->port_id = ret;
1309         } else {
1310                 sdd->port_id = pdev->id;
1311         }
1312
1313         sdd->cur_bpw = 8;
1314
1315         if (!sdd->pdev->dev.of_node) {
1316                 res = platform_get_resource(pdev, IORESOURCE_DMA,  0);
1317                 if (!res) {
1318                         dev_warn(&pdev->dev, "Unable to get SPI tx dma resource. Switching to poll mode\n");
1319                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1320                 } else
1321                         sdd->tx_dma.dmach = res->start;
1322
1323                 res = platform_get_resource(pdev, IORESOURCE_DMA,  1);
1324                 if (!res) {
1325                         dev_warn(&pdev->dev, "Unable to get SPI rx dma resource. Switching to poll mode\n");
1326                         sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1327                 } else
1328                         sdd->rx_dma.dmach = res->start;
1329         }
1330
1331         sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1332         sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1333
1334         master->dev.of_node = pdev->dev.of_node;
1335         master->bus_num = sdd->port_id;
1336         master->setup = s3c64xx_spi_setup;
1337         master->cleanup = s3c64xx_spi_cleanup;
1338         master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1339         master->prepare_message = s3c64xx_spi_prepare_message;
1340         master->transfer_one = s3c64xx_spi_transfer_one;
1341         master->unprepare_message = s3c64xx_spi_unprepare_message;
1342         master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1343         master->num_chipselect = sci->num_cs;
1344         master->dma_alignment = 8;
1345         master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1346                                         SPI_BPW_MASK(8);
1347         /* the spi->mode bits understood by this driver: */
1348         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1349         master->auto_runtime_pm = true;
1350
1351         sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1352         if (IS_ERR(sdd->regs)) {
1353                 ret = PTR_ERR(sdd->regs);
1354                 goto err0;
1355         }
1356
1357         if (sci->cfg_gpio && sci->cfg_gpio()) {
1358                 dev_err(&pdev->dev, "Unable to config gpio\n");
1359                 ret = -EBUSY;
1360                 goto err0;
1361         }
1362
1363         /* Setup clocks */
1364         sdd->clk = devm_clk_get(&pdev->dev, "spi");
1365         if (IS_ERR(sdd->clk)) {
1366                 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1367                 ret = PTR_ERR(sdd->clk);
1368                 goto err0;
1369         }
1370
1371         if (clk_prepare_enable(sdd->clk)) {
1372                 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1373                 ret = -EBUSY;
1374                 goto err0;
1375         }
1376
1377         sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1378         sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1379         if (IS_ERR(sdd->src_clk)) {
1380                 dev_err(&pdev->dev,
1381                         "Unable to acquire clock '%s'\n", clk_name);
1382                 ret = PTR_ERR(sdd->src_clk);
1383                 goto err2;
1384         }
1385
1386         if (clk_prepare_enable(sdd->src_clk)) {
1387                 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1388                 ret = -EBUSY;
1389                 goto err2;
1390         }
1391
1392         /* Setup Deufult Mode */
1393         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1394
1395         spin_lock_init(&sdd->lock);
1396         init_completion(&sdd->xfer_completion);
1397
1398         ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1399                                 "spi-s3c64xx", sdd);
1400         if (ret != 0) {
1401                 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1402                         irq, ret);
1403                 goto err3;
1404         }
1405
1406         writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1407                S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1408                sdd->regs + S3C64XX_SPI_INT_EN);
1409
1410         pm_runtime_set_active(&pdev->dev);
1411         pm_runtime_enable(&pdev->dev);
1412
1413         ret = devm_spi_register_master(&pdev->dev, master);
1414         if (ret != 0) {
1415                 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1416                 goto err3;
1417         }
1418
1419         dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1420                                         sdd->port_id, master->num_chipselect);
1421         dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tDMA=[Rx-%d, Tx-%d]\n",
1422                                         mem_res,
1423                                         sdd->rx_dma.dmach, sdd->tx_dma.dmach);
1424
1425         return 0;
1426
1427 err3:
1428         clk_disable_unprepare(sdd->src_clk);
1429 err2:
1430         clk_disable_unprepare(sdd->clk);
1431 err0:
1432         spi_master_put(master);
1433
1434         return ret;
1435 }
1436
1437 static int s3c64xx_spi_remove(struct platform_device *pdev)
1438 {
1439         struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1440         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1441
1442         pm_runtime_disable(&pdev->dev);
1443
1444         writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1445
1446         clk_disable_unprepare(sdd->src_clk);
1447
1448         clk_disable_unprepare(sdd->clk);
1449
1450         return 0;
1451 }
1452
1453 #ifdef CONFIG_PM_SLEEP
1454 static int s3c64xx_spi_suspend(struct device *dev)
1455 {
1456         struct spi_master *master = dev_get_drvdata(dev);
1457         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1458
1459         int ret = spi_master_suspend(master);
1460         if (ret)
1461                 return ret;
1462
1463         if (!pm_runtime_suspended(dev)) {
1464                 clk_disable_unprepare(sdd->clk);
1465                 clk_disable_unprepare(sdd->src_clk);
1466         }
1467
1468         sdd->cur_speed = 0; /* Output Clock is stopped */
1469
1470         return 0;
1471 }
1472
1473 static int s3c64xx_spi_resume(struct device *dev)
1474 {
1475         struct spi_master *master = dev_get_drvdata(dev);
1476         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1477         struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1478
1479         if (sci->cfg_gpio)
1480                 sci->cfg_gpio();
1481
1482         if (!pm_runtime_suspended(dev)) {
1483                 clk_prepare_enable(sdd->src_clk);
1484                 clk_prepare_enable(sdd->clk);
1485         }
1486
1487         s3c64xx_spi_hwinit(sdd, sdd->port_id);
1488
1489         return spi_master_resume(master);
1490 }
1491 #endif /* CONFIG_PM_SLEEP */
1492
1493 #ifdef CONFIG_PM_RUNTIME
1494 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1495 {
1496         struct spi_master *master = dev_get_drvdata(dev);
1497         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1498
1499         clk_disable_unprepare(sdd->clk);
1500         clk_disable_unprepare(sdd->src_clk);
1501
1502         return 0;
1503 }
1504
1505 static int s3c64xx_spi_runtime_resume(struct device *dev)
1506 {
1507         struct spi_master *master = dev_get_drvdata(dev);
1508         struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1509         int ret;
1510
1511         ret = clk_prepare_enable(sdd->src_clk);
1512         if (ret != 0)
1513                 return ret;
1514
1515         ret = clk_prepare_enable(sdd->clk);
1516         if (ret != 0) {
1517                 clk_disable_unprepare(sdd->src_clk);
1518                 return ret;
1519         }
1520
1521         return 0;
1522 }
1523 #endif /* CONFIG_PM_RUNTIME */
1524
1525 static const struct dev_pm_ops s3c64xx_spi_pm = {
1526         SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1527         SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1528                            s3c64xx_spi_runtime_resume, NULL)
1529 };
1530
1531 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1532         .fifo_lvl_mask  = { 0x7f },
1533         .rx_lvl_offset  = 13,
1534         .tx_st_done     = 21,
1535         .high_speed     = true,
1536 };
1537
1538 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1539         .fifo_lvl_mask  = { 0x7f, 0x7F },
1540         .rx_lvl_offset  = 13,
1541         .tx_st_done     = 21,
1542 };
1543
1544 static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1545         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1546         .rx_lvl_offset  = 15,
1547         .tx_st_done     = 25,
1548 };
1549
1550 static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1551         .fifo_lvl_mask  = { 0x7f, 0x7F },
1552         .rx_lvl_offset  = 13,
1553         .tx_st_done     = 21,
1554         .high_speed     = true,
1555 };
1556
1557 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1558         .fifo_lvl_mask  = { 0x1ff, 0x7F },
1559         .rx_lvl_offset  = 15,
1560         .tx_st_done     = 25,
1561         .high_speed     = true,
1562 };
1563
1564 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1565         .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1566         .rx_lvl_offset  = 15,
1567         .tx_st_done     = 25,
1568         .high_speed     = true,
1569         .clk_from_cmu   = true,
1570 };
1571
1572 static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1573         .fifo_lvl_mask  = { 0x1ff },
1574         .rx_lvl_offset  = 15,
1575         .tx_st_done     = 25,
1576         .high_speed     = true,
1577         .clk_from_cmu   = true,
1578         .quirks         = S3C64XX_SPI_QUIRK_POLL,
1579 };
1580
1581 static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1582         {
1583                 .name           = "s3c2443-spi",
1584                 .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1585         }, {
1586                 .name           = "s3c6410-spi",
1587                 .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1588         }, {
1589                 .name           = "s5p64x0-spi",
1590                 .driver_data    = (kernel_ulong_t)&s5p64x0_spi_port_config,
1591         }, {
1592                 .name           = "s5pc100-spi",
1593                 .driver_data    = (kernel_ulong_t)&s5pc100_spi_port_config,
1594         }, {
1595                 .name           = "s5pv210-spi",
1596                 .driver_data    = (kernel_ulong_t)&s5pv210_spi_port_config,
1597         }, {
1598                 .name           = "exynos4210-spi",
1599                 .driver_data    = (kernel_ulong_t)&exynos4_spi_port_config,
1600         },
1601         { },
1602 };
1603
1604 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1605         { .compatible = "samsung,s3c2443-spi",
1606                         .data = (void *)&s3c2443_spi_port_config,
1607         },
1608         { .compatible = "samsung,s3c6410-spi",
1609                         .data = (void *)&s3c6410_spi_port_config,
1610         },
1611         { .compatible = "samsung,s5pc100-spi",
1612                         .data = (void *)&s5pc100_spi_port_config,
1613         },
1614         { .compatible = "samsung,s5pv210-spi",
1615                         .data = (void *)&s5pv210_spi_port_config,
1616         },
1617         { .compatible = "samsung,exynos4210-spi",
1618                         .data = (void *)&exynos4_spi_port_config,
1619         },
1620         { .compatible = "samsung,exynos5440-spi",
1621                         .data = (void *)&exynos5440_spi_port_config,
1622         },
1623         { },
1624 };
1625 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1626
1627 static struct platform_driver s3c64xx_spi_driver = {
1628         .driver = {
1629                 .name   = "s3c64xx-spi",
1630                 .owner = THIS_MODULE,
1631                 .pm = &s3c64xx_spi_pm,
1632                 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1633         },
1634         .probe = s3c64xx_spi_probe,
1635         .remove = s3c64xx_spi_remove,
1636         .id_table = s3c64xx_spi_driver_ids,
1637 };
1638 MODULE_ALIAS("platform:s3c64xx-spi");
1639
1640 module_platform_driver(s3c64xx_spi_driver);
1641
1642 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1643 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1644 MODULE_LICENSE("GPL");