Pileus Git - ~andy/linux/blob - drivers/pinctrl/pinctrl-sunxi.c

   1 /*
   2  * Allwinner A1X SoCs pinctrl driver.
   3  *
   4  * Copyright (C) 2012 Maxime Ripard
   5  *
   6  * Maxime Ripard <maxime.ripard@free-electrons.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/io.h>
  14 #include <linux/clk.h>
  15 #include <linux/gpio.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/pinctrl/pinctrl.h>
  26 #include <linux/pinctrl/pinconf-generic.h>
  27 #include <linux/pinctrl/pinmux.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30
  31 #include "core.h"
  32 #include "pinctrl-sunxi.h"
  33 #include "pinctrl-sunxi-pins.h"
  34
  35 static struct sunxi_pinctrl_group *
  36 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
  37 {
  38         int i;
  39
  40         for (i = 0; i < pctl->ngroups; i++) {
  41                 struct sunxi_pinctrl_group *grp = pctl->groups + i;
  42
  43                 if (!strcmp(grp->name, group))
  44                         return grp;
  45         }
  46
  47         return NULL;
  48 }
  49
  50 static struct sunxi_pinctrl_function *
  51 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
  52                                     const char *name)
  53 {
  54         struct sunxi_pinctrl_function *func = pctl->functions;
  55         int i;
  56
  57         for (i = 0; i < pctl->nfunctions; i++) {
  58                 if (!func[i].name)
  59                         break;
  60
  61                 if (!strcmp(func[i].name, name))
  62                         return func + i;
  63         }
  64
  65         return NULL;
  66 }
  67
  68 static struct sunxi_desc_function *
  69 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
  70                                          const char *pin_name,
  71                                          const char *func_name)
  72 {
  73         int i;
  74
  75         for (i = 0; i < pctl->desc->npins; i++) {
  76                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
  77
  78                 if (!strcmp(pin->pin.name, pin_name)) {
  79                         struct sunxi_desc_function *func = pin->functions;
  80
  81                         while (func->name) {
  82                                 if (!strcmp(func->name, func_name))
  83                                         return func;
  84
  85                                 func++;
  86                         }
  87                 }
  88         }
  89
  90         return NULL;
  91 }
  92
  93 static struct sunxi_desc_function *
  94 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
  95                                         const u16 pin_num,
  96                                         const char *func_name)
  97 {
  98         int i;
  99
 100         for (i = 0; i < pctl->desc->npins; i++) {
 101                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 102
 103                 if (pin->pin.number == pin_num) {
 104                         struct sunxi_desc_function *func = pin->functions;
 105
 106                         while (func->name) {
 107                                 if (!strcmp(func->name, func_name))
 108                                         return func;
 109
 110                                 func++;
 111                         }
 112                 }
 113         }
 114
 115         return NULL;
 116 }
 117
 118 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
 119 {
 120         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 121
 122         return pctl->ngroups;
 123 }
 124
 125 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
 126                                               unsigned group)
 127 {
 128         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 129
 130         return pctl->groups[group].name;
 131 }
 132
 133 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
 134                                       unsigned group,
 135                                       const unsigned **pins,
 136                                       unsigned *num_pins)
 137 {
 138         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 139
 140         *pins = (unsigned *)&pctl->groups[group].pin;
 141         *num_pins = 1;
 142
 143         return 0;
 144 }
 145
 146 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 147                                       struct device_node *node,
 148                                       struct pinctrl_map **map,
 149                                       unsigned *num_maps)
 150 {
 151         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 152         unsigned long *pinconfig;
 153         struct property *prop;
 154         const char *function;
 155         const char *group;
 156         int ret, nmaps, i = 0;
 157         u32 val;
 158
 159         *map = NULL;
 160         *num_maps = 0;
 161
 162         ret = of_property_read_string(node, "allwinner,function", &function);
 163         if (ret) {
 164                 dev_err(pctl->dev,
 165                         "missing allwinner,function property in node %s\n",
 166                         node->name);
 167                 return -EINVAL;
 168         }
 169
 170         nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
 171         if (nmaps < 0) {
 172                 dev_err(pctl->dev,
 173                         "missing allwinner,pins property in node %s\n",
 174                         node->name);
 175                 return -EINVAL;
 176         }
 177
 178         *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
 179         if (!*map)
 180                 return -ENOMEM;
 181
 182         of_property_for_each_string(node, "allwinner,pins", prop, group) {
 183                 struct sunxi_pinctrl_group *grp =
 184                         sunxi_pinctrl_find_group_by_name(pctl, group);
 185                 int j = 0, configlen = 0;
 186
 187                 if (!grp) {
 188                         dev_err(pctl->dev, "unknown pin %s", group);
 189                         continue;
 190                 }
 191
 192                 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
 193                                                               grp->name,
 194                                                               function)) {
 195                         dev_err(pctl->dev, "unsupported function %s on pin %s",
 196                                 function, group);
 197                         continue;
 198                 }
 199
 200                 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
 201                 (*map)[i].data.mux.group = group;
 202                 (*map)[i].data.mux.function = function;
 203
 204                 i++;
 205
 206                 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
 207                 (*map)[i].data.configs.group_or_pin = group;
 208
 209                 if (of_find_property(node, "allwinner,drive", NULL))
 210                         configlen++;
 211                 if (of_find_property(node, "allwinner,pull", NULL))
 212                         configlen++;
 213
 214                 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
 215
 216                 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
 217                         u16 strength = (val + 1) * 10;
 218                         pinconfig[j++] =
 219                                 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
 220                                                          strength);
 221                 }
 222
 223                 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
 224                         enum pin_config_param pull = PIN_CONFIG_END;
 225                         if (val == 1)
 226                                 pull = PIN_CONFIG_BIAS_PULL_UP;
 227                         else if (val == 2)
 228                                 pull = PIN_CONFIG_BIAS_PULL_DOWN;
 229                         pinconfig[j++] = pinconf_to_config_packed(pull, 0);
 230                 }
 231
 232                 (*map)[i].data.configs.configs = pinconfig;
 233                 (*map)[i].data.configs.num_configs = configlen;
 234
 235                 i++;
 236         }
 237
 238         *num_maps = nmaps;
 239
 240         return 0;
 241 }
 242
 243 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
 244                                     struct pinctrl_map *map,
 245                                     unsigned num_maps)
 246 {
 247         int i;
 248
 249         for (i = 0; i < num_maps; i++) {
 250                 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
 251                         kfree(map[i].data.configs.configs);
 252         }
 253
 254         kfree(map);
 255 }
 256
 257 static const struct pinctrl_ops sunxi_pctrl_ops = {
 258         .dt_node_to_map         = sunxi_pctrl_dt_node_to_map,
 259         .dt_free_map            = sunxi_pctrl_dt_free_map,
 260         .get_groups_count       = sunxi_pctrl_get_groups_count,
 261         .get_group_name         = sunxi_pctrl_get_group_name,
 262         .get_group_pins         = sunxi_pctrl_get_group_pins,
 263 };
 264
 265 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
 266                                  unsigned group,
 267                                  unsigned long *config)
 268 {
 269         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 270
 271         *config = pctl->groups[group].config;
 272
 273         return 0;
 274 }
 275
 276 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
 277                                  unsigned group,
 278                                  unsigned long *configs,
 279                                  unsigned num_configs)
 280 {
 281         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 282         struct sunxi_pinctrl_group *g = &pctl->groups[group];
 283         unsigned long flags;
 284         u32 val, mask;
 285         u16 strength;
 286         u8 dlevel;
 287         int i;
 288
 289         spin_lock_irqsave(&pctl->lock, flags);
 290
 291         for (i = 0; i < num_configs; i++) {
 292                 switch (pinconf_to_config_param(configs[i])) {
 293                 case PIN_CONFIG_DRIVE_STRENGTH:
 294                         strength = pinconf_to_config_argument(configs[i]);
 295                         if (strength > 40) {
 296                                 spin_unlock_irqrestore(&pctl->lock, flags);
 297                                 return -EINVAL;
 298                         }
 299                         /*
 300                          * We convert from mA to what the register expects:
 301                          *   0: 10mA
 302                          *   1: 20mA
 303                          *   2: 30mA
 304                          *   3: 40mA
 305                          */
 306                         dlevel = strength / 10 - 1;
 307                         val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
 308                         mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
 309                         writel((val & ~mask)
 310                                 | dlevel << sunxi_dlevel_offset(g->pin),
 311                                 pctl->membase + sunxi_dlevel_reg(g->pin));
 312                         break;
 313                 case PIN_CONFIG_BIAS_PULL_UP:
 314                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 315                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 316                         writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
 317                                 pctl->membase + sunxi_pull_reg(g->pin));
 318                         break;
 319                 case PIN_CONFIG_BIAS_PULL_DOWN:
 320                         val = readl(pctl->membase + sunxi_pull_reg(g->pin));
 321                         mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
 322                         writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
 323                                 pctl->membase + sunxi_pull_reg(g->pin));
 324                         break;
 325                 default:
 326                         break;
 327                 }
 328                 /* cache the config value */
 329                 g->config = configs[i];
 330         } /* for each config */
 331
 332         spin_unlock_irqrestore(&pctl->lock, flags);
 333
 334         return 0;
 335 }
 336
 337 static const struct pinconf_ops sunxi_pconf_ops = {
 338         .pin_config_group_get   = sunxi_pconf_group_get,
 339         .pin_config_group_set   = sunxi_pconf_group_set,
 340 };
 341
 342 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 343 {
 344         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 345
 346         return pctl->nfunctions;
 347 }
 348
 349 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
 350                                            unsigned function)
 351 {
 352         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 353
 354         return pctl->functions[function].name;
 355 }
 356
 357 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 358                                      unsigned function,
 359                                      const char * const **groups,
 360                                      unsigned * const num_groups)
 361 {
 362         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 363
 364         *groups = pctl->functions[function].groups;
 365         *num_groups = pctl->functions[function].ngroups;
 366
 367         return 0;
 368 }
 369
 370 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
 371                                  unsigned pin,
 372                                  u8 config)
 373 {
 374         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 375         unsigned long flags;
 376         u32 val, mask;
 377
 378         spin_lock_irqsave(&pctl->lock, flags);
 379
 380         val = readl(pctl->membase + sunxi_mux_reg(pin));
 381         mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
 382         writel((val & ~mask) | config << sunxi_mux_offset(pin),
 383                 pctl->membase + sunxi_mux_reg(pin));
 384
 385         spin_unlock_irqrestore(&pctl->lock, flags);
 386 }
 387
 388 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
 389                             unsigned function,
 390                             unsigned group)
 391 {
 392         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 393         struct sunxi_pinctrl_group *g = pctl->groups + group;
 394         struct sunxi_pinctrl_function *func = pctl->functions + function;
 395         struct sunxi_desc_function *desc =
 396                 sunxi_pinctrl_desc_find_function_by_name(pctl,
 397                                                          g->name,
 398                                                          func->name);
 399
 400         if (!desc)
 401                 return -EINVAL;
 402
 403         sunxi_pmx_set(pctldev, g->pin, desc->muxval);
 404
 405         return 0;
 406 }
 407
 408 static int
 409 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 410                         struct pinctrl_gpio_range *range,
 411                         unsigned offset,
 412                         bool input)
 413 {
 414         struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 415         struct sunxi_desc_function *desc;
 416         const char *func;
 417
 418         if (input)
 419                 func = "gpio_in";
 420         else
 421                 func = "gpio_out";
 422
 423         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
 424         if (!desc)
 425                 return -EINVAL;
 426
 427         sunxi_pmx_set(pctldev, offset, desc->muxval);
 428
 429         return 0;
 430 }
 431
 432 static const struct pinmux_ops sunxi_pmx_ops = {
 433         .get_functions_count    = sunxi_pmx_get_funcs_cnt,
 434         .get_function_name      = sunxi_pmx_get_func_name,
 435         .get_function_groups    = sunxi_pmx_get_func_groups,
 436         .enable                 = sunxi_pmx_enable,
 437         .gpio_set_direction     = sunxi_pmx_gpio_set_direction,
 438 };
 439
 440 static struct pinctrl_desc sunxi_pctrl_desc = {
 441         .confops        = &sunxi_pconf_ops,
 442         .pctlops        = &sunxi_pctrl_ops,
 443         .pmxops         = &sunxi_pmx_ops,
 444 };
 445
 446 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
 447 {
 448         return pinctrl_request_gpio(chip->base + offset);
 449 }
 450
 451 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
 452 {
 453         pinctrl_free_gpio(chip->base + offset);
 454 }
 455
 456 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
 457                                         unsigned offset)
 458 {
 459         return pinctrl_gpio_direction_input(chip->base + offset);
 460 }
 461
 462 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 463 {
 464         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 465
 466         u32 reg = sunxi_data_reg(offset);
 467         u8 index = sunxi_data_offset(offset);
 468         u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 469
 470         return val;
 471 }
 472
 473 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
 474                                 unsigned offset, int value)
 475 {
 476         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 477         u32 reg = sunxi_data_reg(offset);
 478         u8 index = sunxi_data_offset(offset);
 479         unsigned long flags;
 480         u32 regval;
 481
 482         spin_lock_irqsave(&pctl->lock, flags);
 483
 484         regval = readl(pctl->membase + reg);
 485
 486         if (value)
 487                 regval |= BIT(index);
 488         else
 489                 regval &= ~(BIT(index));
 490
 491         writel(regval, pctl->membase + reg);
 492
 493         spin_unlock_irqrestore(&pctl->lock, flags);
 494 }
 495
 496 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
 497                                         unsigned offset, int value)
 498 {
 499         sunxi_pinctrl_gpio_set(chip, offset, value);
 500         return pinctrl_gpio_direction_output(chip->base + offset);
 501 }
 502
 503 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
 504                                 const struct of_phandle_args *gpiospec,
 505                                 u32 *flags)
 506 {
 507         int pin, base;
 508
 509         base = PINS_PER_BANK * gpiospec->args[0];
 510         pin = base + gpiospec->args[1];
 511
 512         if (pin > (gc->base + gc->ngpio))
 513                 return -EINVAL;
 514
 515         if (flags)
 516                 *flags = gpiospec->args[2];
 517
 518         return pin;
 519 }
 520
 521 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 522 {
 523         struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
 524         struct sunxi_desc_function *desc;
 525
 526         if (offset >= chip->ngpio)
 527                 return -ENXIO;
 528
 529         desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
 530         if (!desc)
 531                 return -EINVAL;
 532
 533         pctl->irq_array[desc->irqnum] = offset;
 534
 535         dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
 536                 chip->label, offset + chip->base, desc->irqnum);
 537
 538         return irq_find_mapping(pctl->domain, desc->irqnum);
 539 }
 540
 541 static struct gpio_chip sunxi_pinctrl_gpio_chip = {
 542         .owner                  = THIS_MODULE,
 543         .request                = sunxi_pinctrl_gpio_request,
 544         .free                   = sunxi_pinctrl_gpio_free,
 545         .direction_input        = sunxi_pinctrl_gpio_direction_input,
 546         .direction_output       = sunxi_pinctrl_gpio_direction_output,
 547         .get                    = sunxi_pinctrl_gpio_get,
 548         .set                    = sunxi_pinctrl_gpio_set,
 549         .of_xlate               = sunxi_pinctrl_gpio_of_xlate,
 550         .to_irq                 = sunxi_pinctrl_gpio_to_irq,
 551         .of_gpio_n_cells        = 3,
 552         .can_sleep              = false,
 553 };
 554
 555 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
 556                                       unsigned int type)
 557 {
 558         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 559         u32 reg = sunxi_irq_cfg_reg(d->hwirq);
 560         u8 index = sunxi_irq_cfg_offset(d->hwirq);
 561         unsigned long flags;
 562         u32 regval;
 563         u8 mode;
 564
 565         switch (type) {
 566         case IRQ_TYPE_EDGE_RISING:
 567                 mode = IRQ_EDGE_RISING;
 568                 break;
 569         case IRQ_TYPE_EDGE_FALLING:
 570                 mode = IRQ_EDGE_FALLING;
 571                 break;
 572         case IRQ_TYPE_EDGE_BOTH:
 573                 mode = IRQ_EDGE_BOTH;
 574                 break;
 575         case IRQ_TYPE_LEVEL_HIGH:
 576                 mode = IRQ_LEVEL_HIGH;
 577                 break;
 578         case IRQ_TYPE_LEVEL_LOW:
 579                 mode = IRQ_LEVEL_LOW;
 580                 break;
 581         default:
 582                 return -EINVAL;
 583         }
 584
 585         spin_lock_irqsave(&pctl->lock, flags);
 586
 587         regval = readl(pctl->membase + reg);
 588         regval &= ~(IRQ_CFG_IRQ_MASK << index);
 589         writel(regval | (mode << index), pctl->membase + reg);
 590
 591         spin_unlock_irqrestore(&pctl->lock, flags);
 592
 593         return 0;
 594 }
 595
 596 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
 597 {
 598         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 599         u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
 600         u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
 601         u32 status_reg = sunxi_irq_status_reg(d->hwirq);
 602         u8 status_idx = sunxi_irq_status_offset(d->hwirq);
 603         unsigned long flags;
 604         u32 val;
 605
 606         spin_lock_irqsave(&pctl->lock, flags);
 607
 608         /* Mask the IRQ */
 609         val = readl(pctl->membase + ctrl_reg);
 610         writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
 611
 612         /* Clear the IRQ */
 613         writel(1 << status_idx, pctl->membase + status_reg);
 614
 615         spin_unlock_irqrestore(&pctl->lock, flags);
 616 }
 617
 618 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
 619 {
 620         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 621         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 622         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 623         unsigned long flags;
 624         u32 val;
 625
 626         spin_lock_irqsave(&pctl->lock, flags);
 627
 628         /* Mask the IRQ */
 629         val = readl(pctl->membase + reg);
 630         writel(val & ~(1 << idx), pctl->membase + reg);
 631
 632         spin_unlock_irqrestore(&pctl->lock, flags);
 633 }
 634
 635 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
 636 {
 637         struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
 638         struct sunxi_desc_function *func;
 639         u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
 640         u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
 641         unsigned long flags;
 642         u32 val;
 643
 644         func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
 645                                                        pctl->irq_array[d->hwirq],
 646                                                        "irq");
 647
 648         /* Change muxing to INT mode */
 649         sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
 650
 651         spin_lock_irqsave(&pctl->lock, flags);
 652
 653         /* Unmask the IRQ */
 654         val = readl(pctl->membase + reg);
 655         writel(val | (1 << idx), pctl->membase + reg);
 656
 657         spin_unlock_irqrestore(&pctl->lock, flags);
 658 }
 659
 660 static struct irq_chip sunxi_pinctrl_irq_chip = {
 661         .irq_mask       = sunxi_pinctrl_irq_mask,
 662         .irq_mask_ack   = sunxi_pinctrl_irq_mask_ack,
 663         .irq_unmask     = sunxi_pinctrl_irq_unmask,
 664         .irq_set_type   = sunxi_pinctrl_irq_set_type,
 665 };
 666
 667 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
 668 {
 669         struct irq_chip *chip = irq_get_chip(irq);
 670         struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
 671         const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
 672
 673         /* Clear all interrupts */
 674         writel(reg, pctl->membase + IRQ_STATUS_REG);
 675
 676         if (reg) {
 677                 int irqoffset;
 678
 679                 chained_irq_enter(chip, desc);
 680                 for_each_set_bit(irqoffset, &reg, SUNXI_IRQ_NUMBER) {
 681                         int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
 682                         generic_handle_irq(pin_irq);
 683                 }
 684                 chained_irq_exit(chip, desc);
 685         }
 686 }
 687
 688 static struct of_device_id sunxi_pinctrl_match[] = {
 689         { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
 690         { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
 691         { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
 692         { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
 693         { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
 694         {}
 695 };
 696 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
 697
 698 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
 699                                         const char *name)
 700 {
 701         struct sunxi_pinctrl_function *func = pctl->functions;
 702
 703         while (func->name) {
 704                 /* function already there */
 705                 if (strcmp(func->name, name) == 0) {
 706                         func->ngroups++;
 707                         return -EEXIST;
 708                 }
 709                 func++;
 710         }
 711
 712         func->name = name;
 713         func->ngroups = 1;
 714
 715         pctl->nfunctions++;
 716
 717         return 0;
 718 }
 719
 720 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
 721 {
 722         struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
 723         int i;
 724
 725         pctl->ngroups = pctl->desc->npins;
 726
 727         /* Allocate groups */
 728         pctl->groups = devm_kzalloc(&pdev->dev,
 729                                     pctl->ngroups * sizeof(*pctl->groups),
 730                                     GFP_KERNEL);
 731         if (!pctl->groups)
 732                 return -ENOMEM;
 733
 734         for (i = 0; i < pctl->desc->npins; i++) {
 735                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 736                 struct sunxi_pinctrl_group *group = pctl->groups + i;
 737
 738                 group->name = pin->pin.name;
 739                 group->pin = pin->pin.number;
 740         }
 741
 742         /*
 743          * We suppose that we won't have any more functions than pins,
 744          * we'll reallocate that later anyway
 745          */
 746         pctl->functions = devm_kzalloc(&pdev->dev,
 747                                 pctl->desc->npins * sizeof(*pctl->functions),
 748                                 GFP_KERNEL);
 749         if (!pctl->functions)
 750                 return -ENOMEM;
 751
 752         /* Count functions and their associated groups */
 753         for (i = 0; i < pctl->desc->npins; i++) {
 754                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 755                 struct sunxi_desc_function *func = pin->functions;
 756
 757                 while (func->name) {
 758                         sunxi_pinctrl_add_function(pctl, func->name);
 759                         func++;
 760                 }
 761         }
 762
 763         pctl->functions = krealloc(pctl->functions,
 764                                 pctl->nfunctions * sizeof(*pctl->functions),
 765                                 GFP_KERNEL);
 766
 767         for (i = 0; i < pctl->desc->npins; i++) {
 768                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 769                 struct sunxi_desc_function *func = pin->functions;
 770
 771                 while (func->name) {
 772                         struct sunxi_pinctrl_function *func_item;
 773                         const char **func_grp;
 774
 775                         func_item = sunxi_pinctrl_find_function_by_name(pctl,
 776                                                                         func->name);
 777                         if (!func_item)
 778                                 return -EINVAL;
 779
 780                         if (!func_item->groups) {
 781                                 func_item->groups =
 782                                         devm_kzalloc(&pdev->dev,
 783                                                      func_item->ngroups * sizeof(*func_item->groups),
 784                                                      GFP_KERNEL);
 785                                 if (!func_item->groups)
 786                                         return -ENOMEM;
 787                         }
 788
 789                         func_grp = func_item->groups;
 790                         while (*func_grp)
 791                                 func_grp++;
 792
 793                         *func_grp = pin->pin.name;
 794                         func++;
 795                 }
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int sunxi_pinctrl_probe(struct platform_device *pdev)
 802 {
 803         struct device_node *node = pdev->dev.of_node;
 804         const struct of_device_id *device;
 805         struct pinctrl_pin_desc *pins;
 806         struct sunxi_pinctrl *pctl;
 807         int i, ret, last_pin;
 808         struct clk *clk;
 809
 810         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
 811         if (!pctl)
 812                 return -ENOMEM;
 813         platform_set_drvdata(pdev, pctl);
 814
 815         spin_lock_init(&pctl->lock);
 816
 817         pctl->membase = of_iomap(node, 0);
 818         if (!pctl->membase)
 819                 return -ENOMEM;
 820
 821         device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
 822         if (!device)
 823                 return -ENODEV;
 824
 825         pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
 826
 827         ret = sunxi_pinctrl_build_state(pdev);
 828         if (ret) {
 829                 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
 830                 return ret;
 831         }
 832
 833         pins = devm_kzalloc(&pdev->dev,
 834                             pctl->desc->npins * sizeof(*pins),
 835                             GFP_KERNEL);
 836         if (!pins)
 837                 return -ENOMEM;
 838
 839         for (i = 0; i < pctl->desc->npins; i++)
 840                 pins[i] = pctl->desc->pins[i].pin;
 841
 842         sunxi_pctrl_desc.name = dev_name(&pdev->dev);
 843         sunxi_pctrl_desc.owner = THIS_MODULE;
 844         sunxi_pctrl_desc.pins = pins;
 845         sunxi_pctrl_desc.npins = pctl->desc->npins;
 846         pctl->dev = &pdev->dev;
 847         pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
 848                                           &pdev->dev, pctl);
 849         if (!pctl->pctl_dev) {
 850                 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
 851                 return -EINVAL;
 852         }
 853
 854         pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
 855         if (!pctl->chip) {
 856                 ret = -ENOMEM;
 857                 goto pinctrl_error;
 858         }
 859
 860         last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
 861         pctl->chip = &sunxi_pinctrl_gpio_chip;
 862         pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
 863         pctl->chip->label = dev_name(&pdev->dev);
 864         pctl->chip->dev = &pdev->dev;
 865         pctl->chip->base = 0;
 866
 867         ret = gpiochip_add(pctl->chip);
 868         if (ret)
 869                 goto pinctrl_error;
 870
 871         for (i = 0; i < pctl->desc->npins; i++) {
 872                 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
 873
 874                 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
 875                                              pin->pin.number,
 876                                              pin->pin.number, 1);
 877                 if (ret)
 878                         goto gpiochip_error;
 879         }
 880
 881         clk = devm_clk_get(&pdev->dev, NULL);
 882         if (IS_ERR(clk)) {
 883                 ret = PTR_ERR(clk);
 884                 goto gpiochip_error;
 885         }
 886
 887         clk_prepare_enable(clk);
 888
 889         pctl->irq = irq_of_parse_and_map(node, 0);
 890         if (!pctl->irq) {
 891                 ret = -EINVAL;
 892                 goto gpiochip_error;
 893         }
 894
 895         pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
 896                                              &irq_domain_simple_ops, NULL);
 897         if (!pctl->domain) {
 898                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
 899                 ret = -ENOMEM;
 900                 goto gpiochip_error;
 901         }
 902
 903         for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
 904                 int irqno = irq_create_mapping(pctl->domain, i);
 905
 906                 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
 907                                          handle_simple_irq);
 908                 irq_set_chip_data(irqno, pctl);
 909         };
 910
 911         irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
 912         irq_set_handler_data(pctl->irq, pctl);
 913
 914         dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
 915
 916         return 0;
 917
 918 gpiochip_error:
 919         if (gpiochip_remove(pctl->chip))
 920                 dev_err(&pdev->dev, "failed to remove gpio chip\n");
 921 pinctrl_error:
 922         pinctrl_unregister(pctl->pctl_dev);
 923         return ret;
 924 }
 925
 926 static struct platform_driver sunxi_pinctrl_driver = {
 927         .probe = sunxi_pinctrl_probe,
 928         .driver = {
 929                 .name = "sunxi-pinctrl",
 930                 .owner = THIS_MODULE,
 931                 .of_match_table = sunxi_pinctrl_match,
 932         },
 933 };
 934 module_platform_driver(sunxi_pinctrl_driver);
 935
 936 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
 937 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
 938 MODULE_LICENSE("GPL");