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[~andy/linux] / drivers / net / usb / r8152.c
1 /*
2  *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * version 2 as published by the Free Software Foundation.
7  *
8  */
9
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24
25 /* Version Information */
26 #define DRIVER_VERSION "v1.04.0 (2014/01/15)"
27 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
28 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
29 #define MODULENAME "r8152"
30
31 #define R8152_PHY_ID            32
32
33 #define PLA_IDR                 0xc000
34 #define PLA_RCR                 0xc010
35 #define PLA_RMS                 0xc016
36 #define PLA_RXFIFO_CTRL0        0xc0a0
37 #define PLA_RXFIFO_CTRL1        0xc0a4
38 #define PLA_RXFIFO_CTRL2        0xc0a8
39 #define PLA_FMC                 0xc0b4
40 #define PLA_CFG_WOL             0xc0b6
41 #define PLA_TEREDO_CFG          0xc0bc
42 #define PLA_MAR                 0xcd00
43 #define PLA_BACKUP              0xd000
44 #define PAL_BDC_CR              0xd1a0
45 #define PLA_TEREDO_TIMER        0xd2cc
46 #define PLA_REALWOW_TIMER       0xd2e8
47 #define PLA_LEDSEL              0xdd90
48 #define PLA_LED_FEATURE         0xdd92
49 #define PLA_PHYAR               0xde00
50 #define PLA_BOOT_CTRL           0xe004
51 #define PLA_GPHY_INTR_IMR       0xe022
52 #define PLA_EEE_CR              0xe040
53 #define PLA_EEEP_CR             0xe080
54 #define PLA_MAC_PWR_CTRL        0xe0c0
55 #define PLA_MAC_PWR_CTRL2       0xe0ca
56 #define PLA_MAC_PWR_CTRL3       0xe0cc
57 #define PLA_MAC_PWR_CTRL4       0xe0ce
58 #define PLA_WDT6_CTRL           0xe428
59 #define PLA_TCR0                0xe610
60 #define PLA_TCR1                0xe612
61 #define PLA_TXFIFO_CTRL         0xe618
62 #define PLA_RSTTELLY            0xe800
63 #define PLA_CR                  0xe813
64 #define PLA_CRWECR              0xe81c
65 #define PLA_CONFIG5             0xe822
66 #define PLA_PHY_PWR             0xe84c
67 #define PLA_OOB_CTRL            0xe84f
68 #define PLA_CPCR                0xe854
69 #define PLA_MISC_0              0xe858
70 #define PLA_MISC_1              0xe85a
71 #define PLA_OCP_GPHY_BASE       0xe86c
72 #define PLA_TELLYCNT            0xe890
73 #define PLA_SFF_STS_7           0xe8de
74 #define PLA_PHYSTATUS           0xe908
75 #define PLA_BP_BA               0xfc26
76 #define PLA_BP_0                0xfc28
77 #define PLA_BP_1                0xfc2a
78 #define PLA_BP_2                0xfc2c
79 #define PLA_BP_3                0xfc2e
80 #define PLA_BP_4                0xfc30
81 #define PLA_BP_5                0xfc32
82 #define PLA_BP_6                0xfc34
83 #define PLA_BP_7                0xfc36
84 #define PLA_BP_EN               0xfc38
85
86 #define USB_U2P3_CTRL           0xb460
87 #define USB_DEV_STAT            0xb808
88 #define USB_USB_CTRL            0xd406
89 #define USB_PHY_CTRL            0xd408
90 #define USB_TX_AGG              0xd40a
91 #define USB_RX_BUF_TH           0xd40c
92 #define USB_USB_TIMER           0xd428
93 #define USB_RX_EARLY_AGG        0xd42c
94 #define USB_PM_CTRL_STATUS      0xd432
95 #define USB_TX_DMA              0xd434
96 #define USB_TOLERANCE           0xd490
97 #define USB_LPM_CTRL            0xd41a
98 #define USB_UPS_CTRL            0xd800
99 #define USB_MISC_0              0xd81a
100 #define USB_POWER_CUT           0xd80a
101 #define USB_AFE_CTRL2           0xd824
102 #define USB_WDT11_CTRL          0xe43c
103 #define USB_BP_BA               0xfc26
104 #define USB_BP_0                0xfc28
105 #define USB_BP_1                0xfc2a
106 #define USB_BP_2                0xfc2c
107 #define USB_BP_3                0xfc2e
108 #define USB_BP_4                0xfc30
109 #define USB_BP_5                0xfc32
110 #define USB_BP_6                0xfc34
111 #define USB_BP_7                0xfc36
112 #define USB_BP_EN               0xfc38
113
114 /* OCP Registers */
115 #define OCP_ALDPS_CONFIG        0x2010
116 #define OCP_EEE_CONFIG1         0x2080
117 #define OCP_EEE_CONFIG2         0x2092
118 #define OCP_EEE_CONFIG3         0x2094
119 #define OCP_BASE_MII            0xa400
120 #define OCP_EEE_AR              0xa41a
121 #define OCP_EEE_DATA            0xa41c
122 #define OCP_PHY_STATUS          0xa420
123 #define OCP_POWER_CFG           0xa430
124 #define OCP_EEE_CFG             0xa432
125 #define OCP_SRAM_ADDR           0xa436
126 #define OCP_SRAM_DATA           0xa438
127 #define OCP_DOWN_SPEED          0xa442
128 #define OCP_EEE_CFG2            0xa5d0
129 #define OCP_ADC_CFG             0xbc06
130
131 /* SRAM Register */
132 #define SRAM_LPF_CFG            0x8012
133 #define SRAM_10M_AMP1           0x8080
134 #define SRAM_10M_AMP2           0x8082
135 #define SRAM_IMPEDANCE          0x8084
136
137 /* PLA_RCR */
138 #define RCR_AAP                 0x00000001
139 #define RCR_APM                 0x00000002
140 #define RCR_AM                  0x00000004
141 #define RCR_AB                  0x00000008
142 #define RCR_ACPT_ALL            (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
143
144 /* PLA_RXFIFO_CTRL0 */
145 #define RXFIFO_THR1_NORMAL      0x00080002
146 #define RXFIFO_THR1_OOB         0x01800003
147
148 /* PLA_RXFIFO_CTRL1 */
149 #define RXFIFO_THR2_FULL        0x00000060
150 #define RXFIFO_THR2_HIGH        0x00000038
151 #define RXFIFO_THR2_OOB         0x0000004a
152 #define RXFIFO_THR2_NORMAL      0x00a0
153
154 /* PLA_RXFIFO_CTRL2 */
155 #define RXFIFO_THR3_FULL        0x00000078
156 #define RXFIFO_THR3_HIGH        0x00000048
157 #define RXFIFO_THR3_OOB         0x0000005a
158 #define RXFIFO_THR3_NORMAL      0x0110
159
160 /* PLA_TXFIFO_CTRL */
161 #define TXFIFO_THR_NORMAL       0x00400008
162 #define TXFIFO_THR_NORMAL2      0x01000008
163
164 /* PLA_FMC */
165 #define FMC_FCR_MCU_EN          0x0001
166
167 /* PLA_EEEP_CR */
168 #define EEEP_CR_EEEP_TX         0x0002
169
170 /* PLA_WDT6_CTRL */
171 #define WDT6_SET_MODE           0x0010
172
173 /* PLA_TCR0 */
174 #define TCR0_TX_EMPTY           0x0800
175 #define TCR0_AUTO_FIFO          0x0080
176
177 /* PLA_TCR1 */
178 #define VERSION_MASK            0x7cf0
179
180 /* PLA_CR */
181 #define CR_RST                  0x10
182 #define CR_RE                   0x08
183 #define CR_TE                   0x04
184
185 /* PLA_CRWECR */
186 #define CRWECR_NORAML           0x00
187 #define CRWECR_CONFIG           0xc0
188
189 /* PLA_OOB_CTRL */
190 #define NOW_IS_OOB              0x80
191 #define TXFIFO_EMPTY            0x20
192 #define RXFIFO_EMPTY            0x10
193 #define LINK_LIST_READY         0x02
194 #define DIS_MCU_CLROOB          0x01
195 #define FIFO_EMPTY              (TXFIFO_EMPTY | RXFIFO_EMPTY)
196
197 /* PLA_MISC_1 */
198 #define RXDY_GATED_EN           0x0008
199
200 /* PLA_SFF_STS_7 */
201 #define RE_INIT_LL              0x8000
202 #define MCU_BORW_EN             0x4000
203
204 /* PLA_CPCR */
205 #define CPCR_RX_VLAN            0x0040
206
207 /* PLA_CFG_WOL */
208 #define MAGIC_EN                0x0001
209
210 /* PLA_TEREDO_CFG */
211 #define TEREDO_SEL              0x8000
212 #define TEREDO_WAKE_MASK        0x7f00
213 #define TEREDO_RS_EVENT_MASK    0x00fe
214 #define OOB_TEREDO_EN           0x0001
215
216 /* PAL_BDC_CR */
217 #define ALDPS_PROXY_MODE        0x0001
218
219 /* PLA_CONFIG5 */
220 #define LAN_WAKE_EN             0x0002
221
222 /* PLA_LED_FEATURE */
223 #define LED_MODE_MASK           0x0700
224
225 /* PLA_PHY_PWR */
226 #define TX_10M_IDLE_EN          0x0080
227 #define PFM_PWM_SWITCH          0x0040
228
229 /* PLA_MAC_PWR_CTRL */
230 #define D3_CLK_GATED_EN         0x00004000
231 #define MCU_CLK_RATIO           0x07010f07
232 #define MCU_CLK_RATIO_MASK      0x0f0f0f0f
233 #define ALDPS_SPDWN_RATIO       0x0f87
234
235 /* PLA_MAC_PWR_CTRL2 */
236 #define EEE_SPDWN_RATIO         0x8007
237
238 /* PLA_MAC_PWR_CTRL3 */
239 #define PKT_AVAIL_SPDWN_EN      0x0100
240 #define SUSPEND_SPDWN_EN        0x0004
241 #define U1U2_SPDWN_EN           0x0002
242 #define L1_SPDWN_EN             0x0001
243
244 /* PLA_MAC_PWR_CTRL4 */
245 #define PWRSAVE_SPDWN_EN        0x1000
246 #define RXDV_SPDWN_EN           0x0800
247 #define TX10MIDLE_EN            0x0100
248 #define TP100_SPDWN_EN          0x0020
249 #define TP500_SPDWN_EN          0x0010
250 #define TP1000_SPDWN_EN         0x0008
251 #define EEE_SPDWN_EN            0x0001
252
253 /* PLA_GPHY_INTR_IMR */
254 #define GPHY_STS_MSK            0x0001
255 #define SPEED_DOWN_MSK          0x0002
256 #define SPDWN_RXDV_MSK          0x0004
257 #define SPDWN_LINKCHG_MSK       0x0008
258
259 /* PLA_PHYAR */
260 #define PHYAR_FLAG              0x80000000
261
262 /* PLA_EEE_CR */
263 #define EEE_RX_EN               0x0001
264 #define EEE_TX_EN               0x0002
265
266 /* PLA_BOOT_CTRL */
267 #define AUTOLOAD_DONE           0x0002
268
269 /* USB_DEV_STAT */
270 #define STAT_SPEED_MASK         0x0006
271 #define STAT_SPEED_HIGH         0x0000
272 #define STAT_SPEED_FULL         0x0001
273
274 /* USB_TX_AGG */
275 #define TX_AGG_MAX_THRESHOLD    0x03
276
277 /* USB_RX_BUF_TH */
278 #define RX_THR_SUPPER           0x0c350180
279 #define RX_THR_HIGH             0x7a120180
280 #define RX_THR_SLOW             0xffff0180
281
282 /* USB_TX_DMA */
283 #define TEST_MODE_DISABLE       0x00000001
284 #define TX_SIZE_ADJUST1         0x00000100
285
286 /* USB_UPS_CTRL */
287 #define POWER_CUT               0x0100
288
289 /* USB_PM_CTRL_STATUS */
290 #define RESUME_INDICATE         0x0001
291
292 /* USB_USB_CTRL */
293 #define RX_AGG_DISABLE          0x0010
294
295 /* USB_U2P3_CTRL */
296 #define U2P3_ENABLE             0x0001
297
298 /* USB_POWER_CUT */
299 #define PWR_EN                  0x0001
300 #define PHASE2_EN               0x0008
301
302 /* USB_MISC_0 */
303 #define PCUT_STATUS             0x0001
304
305 /* USB_RX_EARLY_AGG */
306 #define EARLY_AGG_SUPPER        0x0e832981
307 #define EARLY_AGG_HIGH          0x0e837a12
308 #define EARLY_AGG_SLOW          0x0e83ffff
309
310 /* USB_WDT11_CTRL */
311 #define TIMER11_EN              0x0001
312
313 /* USB_LPM_CTRL */
314 #define LPM_TIMER_MASK          0x0c
315 #define LPM_TIMER_500MS         0x04    /* 500 ms */
316 #define LPM_TIMER_500US         0x0c    /* 500 us */
317
318 /* USB_AFE_CTRL2 */
319 #define SEN_VAL_MASK            0xf800
320 #define SEN_VAL_NORMAL          0xa000
321 #define SEL_RXIDLE              0x0100
322
323 /* OCP_ALDPS_CONFIG */
324 #define ENPWRSAVE               0x8000
325 #define ENPDNPS                 0x0200
326 #define LINKENA                 0x0100
327 #define DIS_SDSAVE              0x0010
328
329 /* OCP_PHY_STATUS */
330 #define PHY_STAT_MASK           0x0007
331 #define PHY_STAT_LAN_ON         3
332 #define PHY_STAT_PWRDN          5
333
334 /* OCP_POWER_CFG */
335 #define EEE_CLKDIV_EN           0x8000
336 #define EN_ALDPS                0x0004
337 #define EN_10M_PLLOFF           0x0001
338
339 /* OCP_EEE_CONFIG1 */
340 #define RG_TXLPI_MSK_HFDUP      0x8000
341 #define RG_MATCLR_EN            0x4000
342 #define EEE_10_CAP              0x2000
343 #define EEE_NWAY_EN             0x1000
344 #define TX_QUIET_EN             0x0200
345 #define RX_QUIET_EN             0x0100
346 #define SDRISETIME              0x0010  /* bit 4 ~ 6 */
347 #define RG_RXLPI_MSK_HFDUP      0x0008
348 #define SDFALLTIME              0x0007  /* bit 0 ~ 2 */
349
350 /* OCP_EEE_CONFIG2 */
351 #define RG_LPIHYS_NUM           0x7000  /* bit 12 ~ 15 */
352 #define RG_DACQUIET_EN          0x0400
353 #define RG_LDVQUIET_EN          0x0200
354 #define RG_CKRSEL               0x0020
355 #define RG_EEEPRG_EN            0x0010
356
357 /* OCP_EEE_CONFIG3 */
358 #define FST_SNR_EYE_R           0x1500  /* bit 7 ~ 15 */
359 #define RG_LFS_SEL              0x0060  /* bit 6 ~ 5 */
360 #define MSK_PH                  0x0006  /* bit 0 ~ 3 */
361
362 /* OCP_EEE_AR */
363 /* bit[15:14] function */
364 #define FUN_ADDR                0x0000
365 #define FUN_DATA                0x4000
366 /* bit[4:0] device addr */
367 #define DEVICE_ADDR             0x0007
368
369 /* OCP_EEE_DATA */
370 #define EEE_ADDR                0x003C
371 #define EEE_DATA                0x0002
372
373 /* OCP_EEE_CFG */
374 #define CTAP_SHORT_EN           0x0040
375 #define EEE10_EN                0x0010
376
377 /* OCP_DOWN_SPEED */
378 #define EN_10M_BGOFF            0x0080
379
380 /* OCP_EEE_CFG2 */
381 #define MY1000_EEE              0x0004
382 #define MY100_EEE               0x0002
383
384 /* OCP_ADC_CFG */
385 #define CKADSEL_L               0x0100
386 #define ADC_EN                  0x0080
387 #define EN_EMI_L                0x0040
388
389 /* SRAM_LPF_CFG */
390 #define LPF_AUTO_TUNE           0x8000
391
392 /* SRAM_10M_AMP1 */
393 #define GDAC_IB_UPALL           0x0008
394
395 /* SRAM_10M_AMP2 */
396 #define AMP_DN                  0x0200
397
398 /* SRAM_IMPEDANCE */
399 #define RX_DRIVING_MASK         0x6000
400
401 enum rtl_register_content {
402         _1000bps        = 0x10,
403         _100bps         = 0x08,
404         _10bps          = 0x04,
405         LINK_STATUS     = 0x02,
406         FULL_DUP        = 0x01,
407 };
408
409 #define RTL8152_MAX_TX          10
410 #define RTL8152_MAX_RX          10
411 #define INTBUFSIZE              2
412 #define CRC_SIZE                4
413 #define TX_ALIGN                4
414 #define RX_ALIGN                8
415
416 #define INTR_LINK               0x0004
417
418 #define RTL8152_REQT_READ       0xc0
419 #define RTL8152_REQT_WRITE      0x40
420 #define RTL8152_REQ_GET_REGS    0x05
421 #define RTL8152_REQ_SET_REGS    0x05
422
423 #define BYTE_EN_DWORD           0xff
424 #define BYTE_EN_WORD            0x33
425 #define BYTE_EN_BYTE            0x11
426 #define BYTE_EN_SIX_BYTES       0x3f
427 #define BYTE_EN_START_MASK      0x0f
428 #define BYTE_EN_END_MASK        0xf0
429
430 #define RTL8152_RMS             (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
431 #define RTL8152_TX_TIMEOUT      (HZ)
432
433 /* rtl8152 flags */
434 enum rtl8152_flags {
435         RTL8152_UNPLUG = 0,
436         RTL8152_SET_RX_MODE,
437         WORK_ENABLE,
438         RTL8152_LINK_CHG,
439 };
440
441 /* Define these values to match your device */
442 #define VENDOR_ID_REALTEK               0x0bda
443 #define PRODUCT_ID_RTL8152              0x8152
444 #define PRODUCT_ID_RTL8153              0x8153
445
446 #define VENDOR_ID_SAMSUNG               0x04e8
447 #define PRODUCT_ID_SAMSUNG              0xa101
448
449 #define MCU_TYPE_PLA                    0x0100
450 #define MCU_TYPE_USB                    0x0000
451
452 #define REALTEK_USB_DEVICE(vend, prod)  \
453         USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
454
455 struct rx_desc {
456         __le32 opts1;
457 #define RX_LEN_MASK                     0x7fff
458         __le32 opts2;
459         __le32 opts3;
460         __le32 opts4;
461         __le32 opts5;
462         __le32 opts6;
463 };
464
465 struct tx_desc {
466         __le32 opts1;
467 #define TX_FS                   (1 << 31) /* First segment of a packet */
468 #define TX_LS                   (1 << 30) /* Final segment of a packet */
469 #define TX_LEN_MASK             0x3ffff
470
471         __le32 opts2;
472 #define UDP_CS                  (1 << 31) /* Calculate UDP/IP checksum */
473 #define TCP_CS                  (1 << 30) /* Calculate TCP/IP checksum */
474 #define IPV4_CS                 (1 << 29) /* Calculate IPv4 checksum */
475 #define IPV6_CS                 (1 << 28) /* Calculate IPv6 checksum */
476 };
477
478 struct r8152;
479
480 struct rx_agg {
481         struct list_head list;
482         struct urb *urb;
483         struct r8152 *context;
484         void *buffer;
485         void *head;
486 };
487
488 struct tx_agg {
489         struct list_head list;
490         struct urb *urb;
491         struct r8152 *context;
492         void *buffer;
493         void *head;
494         u32 skb_num;
495         u32 skb_len;
496 };
497
498 struct r8152 {
499         unsigned long flags;
500         struct usb_device *udev;
501         struct tasklet_struct tl;
502         struct usb_interface *intf;
503         struct net_device *netdev;
504         struct urb *intr_urb;
505         struct tx_agg tx_info[RTL8152_MAX_TX];
506         struct rx_agg rx_info[RTL8152_MAX_RX];
507         struct list_head rx_done, tx_free;
508         struct sk_buff_head tx_queue;
509         spinlock_t rx_lock, tx_lock;
510         struct delayed_work schedule;
511         struct mii_if_info mii;
512
513         struct rtl_ops {
514                 void (*init)(struct r8152 *);
515                 int (*enable)(struct r8152 *);
516                 void (*disable)(struct r8152 *);
517                 void (*down)(struct r8152 *);
518                 void (*unload)(struct r8152 *);
519         } rtl_ops;
520
521         int intr_interval;
522         u32 msg_enable;
523         u32 tx_qlen;
524         u16 ocp_base;
525         u8 *intr_buff;
526         u8 version;
527         u8 speed;
528 };
529
530 enum rtl_version {
531         RTL_VER_UNKNOWN = 0,
532         RTL_VER_01,
533         RTL_VER_02,
534         RTL_VER_03,
535         RTL_VER_04,
536         RTL_VER_05,
537         RTL_VER_MAX
538 };
539
540 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
541  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
542  */
543 static const int multicast_filter_limit = 32;
544 static unsigned int rx_buf_sz = 16384;
545
546 static
547 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
548 {
549         int ret;
550         void *tmp;
551
552         tmp = kmalloc(size, GFP_KERNEL);
553         if (!tmp)
554                 return -ENOMEM;
555
556         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
557                                RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
558                                value, index, tmp, size, 500);
559
560         memcpy(data, tmp, size);
561         kfree(tmp);
562
563         return ret;
564 }
565
566 static
567 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
568 {
569         int ret;
570         void *tmp;
571
572         tmp = kmalloc(size, GFP_KERNEL);
573         if (!tmp)
574                 return -ENOMEM;
575
576         memcpy(tmp, data, size);
577
578         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
579                                RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
580                                value, index, tmp, size, 500);
581
582         kfree(tmp);
583         return ret;
584 }
585
586 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
587                                 void *data, u16 type)
588 {
589         u16 limit = 64;
590         int ret = 0;
591
592         if (test_bit(RTL8152_UNPLUG, &tp->flags))
593                 return -ENODEV;
594
595         /* both size and indix must be 4 bytes align */
596         if ((size & 3) || !size || (index & 3) || !data)
597                 return -EPERM;
598
599         if ((u32)index + (u32)size > 0xffff)
600                 return -EPERM;
601
602         while (size) {
603                 if (size > limit) {
604                         ret = get_registers(tp, index, type, limit, data);
605                         if (ret < 0)
606                                 break;
607
608                         index += limit;
609                         data += limit;
610                         size -= limit;
611                 } else {
612                         ret = get_registers(tp, index, type, size, data);
613                         if (ret < 0)
614                                 break;
615
616                         index += size;
617                         data += size;
618                         size = 0;
619                         break;
620                 }
621         }
622
623         return ret;
624 }
625
626 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
627                                 u16 size, void *data, u16 type)
628 {
629         int ret;
630         u16 byteen_start, byteen_end, byen;
631         u16 limit = 512;
632
633         if (test_bit(RTL8152_UNPLUG, &tp->flags))
634                 return -ENODEV;
635
636         /* both size and indix must be 4 bytes align */
637         if ((size & 3) || !size || (index & 3) || !data)
638                 return -EPERM;
639
640         if ((u32)index + (u32)size > 0xffff)
641                 return -EPERM;
642
643         byteen_start = byteen & BYTE_EN_START_MASK;
644         byteen_end = byteen & BYTE_EN_END_MASK;
645
646         byen = byteen_start | (byteen_start << 4);
647         ret = set_registers(tp, index, type | byen, 4, data);
648         if (ret < 0)
649                 goto error1;
650
651         index += 4;
652         data += 4;
653         size -= 4;
654
655         if (size) {
656                 size -= 4;
657
658                 while (size) {
659                         if (size > limit) {
660                                 ret = set_registers(tp, index,
661                                         type | BYTE_EN_DWORD,
662                                         limit, data);
663                                 if (ret < 0)
664                                         goto error1;
665
666                                 index += limit;
667                                 data += limit;
668                                 size -= limit;
669                         } else {
670                                 ret = set_registers(tp, index,
671                                         type | BYTE_EN_DWORD,
672                                         size, data);
673                                 if (ret < 0)
674                                         goto error1;
675
676                                 index += size;
677                                 data += size;
678                                 size = 0;
679                                 break;
680                         }
681                 }
682
683                 byen = byteen_end | (byteen_end >> 4);
684                 ret = set_registers(tp, index, type | byen, 4, data);
685                 if (ret < 0)
686                         goto error1;
687         }
688
689 error1:
690         return ret;
691 }
692
693 static inline
694 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
695 {
696         return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
697 }
698
699 static inline
700 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
701 {
702         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
703 }
704
705 static inline
706 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
707 {
708         return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
709 }
710
711 static inline
712 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
713 {
714         return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
715 }
716
717 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
718 {
719         __le32 data;
720
721         generic_ocp_read(tp, index, sizeof(data), &data, type);
722
723         return __le32_to_cpu(data);
724 }
725
726 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
727 {
728         __le32 tmp = __cpu_to_le32(data);
729
730         generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
731 }
732
733 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
734 {
735         u32 data;
736         __le32 tmp;
737         u8 shift = index & 2;
738
739         index &= ~3;
740
741         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
742
743         data = __le32_to_cpu(tmp);
744         data >>= (shift * 8);
745         data &= 0xffff;
746
747         return (u16)data;
748 }
749
750 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
751 {
752         u32 mask = 0xffff;
753         __le32 tmp;
754         u16 byen = BYTE_EN_WORD;
755         u8 shift = index & 2;
756
757         data &= mask;
758
759         if (index & 2) {
760                 byen <<= shift;
761                 mask <<= (shift * 8);
762                 data <<= (shift * 8);
763                 index &= ~3;
764         }
765
766         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
767
768         data |= __le32_to_cpu(tmp) & ~mask;
769         tmp = __cpu_to_le32(data);
770
771         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
772 }
773
774 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
775 {
776         u32 data;
777         __le32 tmp;
778         u8 shift = index & 3;
779
780         index &= ~3;
781
782         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
783
784         data = __le32_to_cpu(tmp);
785         data >>= (shift * 8);
786         data &= 0xff;
787
788         return (u8)data;
789 }
790
791 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
792 {
793         u32 mask = 0xff;
794         __le32 tmp;
795         u16 byen = BYTE_EN_BYTE;
796         u8 shift = index & 3;
797
798         data &= mask;
799
800         if (index & 3) {
801                 byen <<= shift;
802                 mask <<= (shift * 8);
803                 data <<= (shift * 8);
804                 index &= ~3;
805         }
806
807         generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
808
809         data |= __le32_to_cpu(tmp) & ~mask;
810         tmp = __cpu_to_le32(data);
811
812         generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
813 }
814
815 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
816 {
817         u16 ocp_base, ocp_index;
818
819         ocp_base = addr & 0xf000;
820         if (ocp_base != tp->ocp_base) {
821                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
822                 tp->ocp_base = ocp_base;
823         }
824
825         ocp_index = (addr & 0x0fff) | 0xb000;
826         return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
827 }
828
829 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
830 {
831         u16 ocp_base, ocp_index;
832
833         ocp_base = addr & 0xf000;
834         if (ocp_base != tp->ocp_base) {
835                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
836                 tp->ocp_base = ocp_base;
837         }
838
839         ocp_index = (addr & 0x0fff) | 0xb000;
840         ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
841 }
842
843 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
844 {
845         ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
846 }
847
848 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
849 {
850         return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
851 }
852
853 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
854 {
855         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
856         ocp_reg_write(tp, OCP_SRAM_DATA, data);
857 }
858
859 static u16 sram_read(struct r8152 *tp, u16 addr)
860 {
861         ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
862         return ocp_reg_read(tp, OCP_SRAM_DATA);
863 }
864
865 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
866 {
867         struct r8152 *tp = netdev_priv(netdev);
868
869         if (phy_id != R8152_PHY_ID)
870                 return -EINVAL;
871
872         return r8152_mdio_read(tp, reg);
873 }
874
875 static
876 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
877 {
878         struct r8152 *tp = netdev_priv(netdev);
879
880         if (phy_id != R8152_PHY_ID)
881                 return;
882
883         r8152_mdio_write(tp, reg, val);
884 }
885
886 static
887 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
888
889 static inline void set_ethernet_addr(struct r8152 *tp)
890 {
891         struct net_device *dev = tp->netdev;
892         u8 node_id[8] = {0};
893
894         if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0)
895                 netif_notice(tp, probe, dev, "inet addr fail\n");
896         else {
897                 memcpy(dev->dev_addr, node_id, dev->addr_len);
898                 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
899         }
900 }
901
902 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
903 {
904         struct r8152 *tp = netdev_priv(netdev);
905         struct sockaddr *addr = p;
906
907         if (!is_valid_ether_addr(addr->sa_data))
908                 return -EADDRNOTAVAIL;
909
910         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
911
912         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
913         pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
914         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
915
916         return 0;
917 }
918
919 static struct net_device_stats *rtl8152_get_stats(struct net_device *dev)
920 {
921         return &dev->stats;
922 }
923
924 static void read_bulk_callback(struct urb *urb)
925 {
926         struct net_device *netdev;
927         unsigned long flags;
928         int status = urb->status;
929         struct rx_agg *agg;
930         struct r8152 *tp;
931         int result;
932
933         agg = urb->context;
934         if (!agg)
935                 return;
936
937         tp = agg->context;
938         if (!tp)
939                 return;
940
941         if (test_bit(RTL8152_UNPLUG, &tp->flags))
942                 return;
943
944         if (!test_bit(WORK_ENABLE, &tp->flags))
945                 return;
946
947         netdev = tp->netdev;
948
949         /* When link down, the driver would cancel all bulks. */
950         /* This avoid the re-submitting bulk */
951         if (!netif_carrier_ok(netdev))
952                 return;
953
954         switch (status) {
955         case 0:
956                 if (urb->actual_length < ETH_ZLEN)
957                         break;
958
959                 spin_lock_irqsave(&tp->rx_lock, flags);
960                 list_add_tail(&agg->list, &tp->rx_done);
961                 spin_unlock_irqrestore(&tp->rx_lock, flags);
962                 tasklet_schedule(&tp->tl);
963                 return;
964         case -ESHUTDOWN:
965                 set_bit(RTL8152_UNPLUG, &tp->flags);
966                 netif_device_detach(tp->netdev);
967                 return;
968         case -ENOENT:
969                 return; /* the urb is in unlink state */
970         case -ETIME:
971                 if (net_ratelimit())
972                         netdev_warn(netdev, "maybe reset is needed?\n");
973                 break;
974         default:
975                 if (net_ratelimit())
976                         netdev_warn(netdev, "Rx status %d\n", status);
977                 break;
978         }
979
980         result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
981         if (result == -ENODEV) {
982                 netif_device_detach(tp->netdev);
983         } else if (result) {
984                 spin_lock_irqsave(&tp->rx_lock, flags);
985                 list_add_tail(&agg->list, &tp->rx_done);
986                 spin_unlock_irqrestore(&tp->rx_lock, flags);
987                 tasklet_schedule(&tp->tl);
988         }
989 }
990
991 static void write_bulk_callback(struct urb *urb)
992 {
993         struct net_device_stats *stats;
994         unsigned long flags;
995         struct tx_agg *agg;
996         struct r8152 *tp;
997         int status = urb->status;
998
999         agg = urb->context;
1000         if (!agg)
1001                 return;
1002
1003         tp = agg->context;
1004         if (!tp)
1005                 return;
1006
1007         stats = rtl8152_get_stats(tp->netdev);
1008         if (status) {
1009                 if (net_ratelimit())
1010                         netdev_warn(tp->netdev, "Tx status %d\n", status);
1011                 stats->tx_errors += agg->skb_num;
1012         } else {
1013                 stats->tx_packets += agg->skb_num;
1014                 stats->tx_bytes += agg->skb_len;
1015         }
1016
1017         spin_lock_irqsave(&tp->tx_lock, flags);
1018         list_add_tail(&agg->list, &tp->tx_free);
1019         spin_unlock_irqrestore(&tp->tx_lock, flags);
1020
1021         if (!netif_carrier_ok(tp->netdev))
1022                 return;
1023
1024         if (!test_bit(WORK_ENABLE, &tp->flags))
1025                 return;
1026
1027         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1028                 return;
1029
1030         if (!skb_queue_empty(&tp->tx_queue))
1031                 tasklet_schedule(&tp->tl);
1032 }
1033
1034 static void intr_callback(struct urb *urb)
1035 {
1036         struct r8152 *tp;
1037         __le16 *d;
1038         int status = urb->status;
1039         int res;
1040
1041         tp = urb->context;
1042         if (!tp)
1043                 return;
1044
1045         if (!test_bit(WORK_ENABLE, &tp->flags))
1046                 return;
1047
1048         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1049                 return;
1050
1051         switch (status) {
1052         case 0:                 /* success */
1053                 break;
1054         case -ECONNRESET:       /* unlink */
1055         case -ESHUTDOWN:
1056                 netif_device_detach(tp->netdev);
1057         case -ENOENT:
1058                 return;
1059         case -EOVERFLOW:
1060                 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1061                 goto resubmit;
1062         /* -EPIPE:  should clear the halt */
1063         default:
1064                 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1065                 goto resubmit;
1066         }
1067
1068         d = urb->transfer_buffer;
1069         if (INTR_LINK & __le16_to_cpu(d[0])) {
1070                 if (!(tp->speed & LINK_STATUS)) {
1071                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1072                         schedule_delayed_work(&tp->schedule, 0);
1073                 }
1074         } else {
1075                 if (tp->speed & LINK_STATUS) {
1076                         set_bit(RTL8152_LINK_CHG, &tp->flags);
1077                         schedule_delayed_work(&tp->schedule, 0);
1078                 }
1079         }
1080
1081 resubmit:
1082         res = usb_submit_urb(urb, GFP_ATOMIC);
1083         if (res == -ENODEV)
1084                 netif_device_detach(tp->netdev);
1085         else if (res)
1086                 netif_err(tp, intr, tp->netdev,
1087                           "can't resubmit intr, status %d\n", res);
1088 }
1089
1090 static inline void *rx_agg_align(void *data)
1091 {
1092         return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1093 }
1094
1095 static inline void *tx_agg_align(void *data)
1096 {
1097         return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1098 }
1099
1100 static void free_all_mem(struct r8152 *tp)
1101 {
1102         int i;
1103
1104         for (i = 0; i < RTL8152_MAX_RX; i++) {
1105                 usb_free_urb(tp->rx_info[i].urb);
1106                 tp->rx_info[i].urb = NULL;
1107
1108                 kfree(tp->rx_info[i].buffer);
1109                 tp->rx_info[i].buffer = NULL;
1110                 tp->rx_info[i].head = NULL;
1111         }
1112
1113         for (i = 0; i < RTL8152_MAX_TX; i++) {
1114                 usb_free_urb(tp->tx_info[i].urb);
1115                 tp->tx_info[i].urb = NULL;
1116
1117                 kfree(tp->tx_info[i].buffer);
1118                 tp->tx_info[i].buffer = NULL;
1119                 tp->tx_info[i].head = NULL;
1120         }
1121
1122         usb_free_urb(tp->intr_urb);
1123         tp->intr_urb = NULL;
1124
1125         kfree(tp->intr_buff);
1126         tp->intr_buff = NULL;
1127 }
1128
1129 static int alloc_all_mem(struct r8152 *tp)
1130 {
1131         struct net_device *netdev = tp->netdev;
1132         struct usb_interface *intf = tp->intf;
1133         struct usb_host_interface *alt = intf->cur_altsetting;
1134         struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1135         struct urb *urb;
1136         int node, i;
1137         u8 *buf;
1138
1139         node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1140
1141         spin_lock_init(&tp->rx_lock);
1142         spin_lock_init(&tp->tx_lock);
1143         INIT_LIST_HEAD(&tp->rx_done);
1144         INIT_LIST_HEAD(&tp->tx_free);
1145         skb_queue_head_init(&tp->tx_queue);
1146
1147         for (i = 0; i < RTL8152_MAX_RX; i++) {
1148                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1149                 if (!buf)
1150                         goto err1;
1151
1152                 if (buf != rx_agg_align(buf)) {
1153                         kfree(buf);
1154                         buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1155                                            node);
1156                         if (!buf)
1157                                 goto err1;
1158                 }
1159
1160                 urb = usb_alloc_urb(0, GFP_KERNEL);
1161                 if (!urb) {
1162                         kfree(buf);
1163                         goto err1;
1164                 }
1165
1166                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1167                 tp->rx_info[i].context = tp;
1168                 tp->rx_info[i].urb = urb;
1169                 tp->rx_info[i].buffer = buf;
1170                 tp->rx_info[i].head = rx_agg_align(buf);
1171         }
1172
1173         for (i = 0; i < RTL8152_MAX_TX; i++) {
1174                 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1175                 if (!buf)
1176                         goto err1;
1177
1178                 if (buf != tx_agg_align(buf)) {
1179                         kfree(buf);
1180                         buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1181                                            node);
1182                         if (!buf)
1183                                 goto err1;
1184                 }
1185
1186                 urb = usb_alloc_urb(0, GFP_KERNEL);
1187                 if (!urb) {
1188                         kfree(buf);
1189                         goto err1;
1190                 }
1191
1192                 INIT_LIST_HEAD(&tp->tx_info[i].list);
1193                 tp->tx_info[i].context = tp;
1194                 tp->tx_info[i].urb = urb;
1195                 tp->tx_info[i].buffer = buf;
1196                 tp->tx_info[i].head = tx_agg_align(buf);
1197
1198                 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1199         }
1200
1201         tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1202         if (!tp->intr_urb)
1203                 goto err1;
1204
1205         tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1206         if (!tp->intr_buff)
1207                 goto err1;
1208
1209         tp->intr_interval = (int)ep_intr->desc.bInterval;
1210         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1211                      tp->intr_buff, INTBUFSIZE, intr_callback,
1212                      tp, tp->intr_interval);
1213
1214         return 0;
1215
1216 err1:
1217         free_all_mem(tp);
1218         return -ENOMEM;
1219 }
1220
1221 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1222 {
1223         struct tx_agg *agg = NULL;
1224         unsigned long flags;
1225
1226         spin_lock_irqsave(&tp->tx_lock, flags);
1227         if (!list_empty(&tp->tx_free)) {
1228                 struct list_head *cursor;
1229
1230                 cursor = tp->tx_free.next;
1231                 list_del_init(cursor);
1232                 agg = list_entry(cursor, struct tx_agg, list);
1233         }
1234         spin_unlock_irqrestore(&tp->tx_lock, flags);
1235
1236         return agg;
1237 }
1238
1239 static void
1240 r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb)
1241 {
1242         memset(desc, 0, sizeof(*desc));
1243
1244         desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS);
1245
1246         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1247                 __be16 protocol;
1248                 u8 ip_protocol;
1249                 u32 opts2 = 0;
1250
1251                 if (skb->protocol == htons(ETH_P_8021Q))
1252                         protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1253                 else
1254                         protocol = skb->protocol;
1255
1256                 switch (protocol) {
1257                 case htons(ETH_P_IP):
1258                         opts2 |= IPV4_CS;
1259                         ip_protocol = ip_hdr(skb)->protocol;
1260                         break;
1261
1262                 case htons(ETH_P_IPV6):
1263                         opts2 |= IPV6_CS;
1264                         ip_protocol = ipv6_hdr(skb)->nexthdr;
1265                         break;
1266
1267                 default:
1268                         ip_protocol = IPPROTO_RAW;
1269                         break;
1270                 }
1271
1272                 if (ip_protocol == IPPROTO_TCP) {
1273                         opts2 |= TCP_CS;
1274                         opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17;
1275                 } else if (ip_protocol == IPPROTO_UDP) {
1276                         opts2 |= UDP_CS;
1277                 } else {
1278                         WARN_ON_ONCE(1);
1279                 }
1280
1281                 desc->opts2 = cpu_to_le32(opts2);
1282         }
1283 }
1284
1285 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1286 {
1287         int remain;
1288         u8 *tx_data;
1289
1290         tx_data = agg->head;
1291         agg->skb_num = agg->skb_len = 0;
1292         remain = rx_buf_sz;
1293
1294         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1295                 struct tx_desc *tx_desc;
1296                 struct sk_buff *skb;
1297                 unsigned int len;
1298
1299                 skb = skb_dequeue(&tp->tx_queue);
1300                 if (!skb)
1301                         break;
1302
1303                 remain -= sizeof(*tx_desc);
1304                 len = skb->len;
1305                 if (remain < len) {
1306                         skb_queue_head(&tp->tx_queue, skb);
1307                         break;
1308                 }
1309
1310                 tx_data = tx_agg_align(tx_data);
1311                 tx_desc = (struct tx_desc *)tx_data;
1312                 tx_data += sizeof(*tx_desc);
1313
1314                 r8152_tx_csum(tp, tx_desc, skb);
1315                 memcpy(tx_data, skb->data, len);
1316                 agg->skb_num++;
1317                 agg->skb_len += len;
1318                 dev_kfree_skb_any(skb);
1319
1320                 tx_data += len;
1321                 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1322         }
1323
1324         netif_tx_lock(tp->netdev);
1325
1326         if (netif_queue_stopped(tp->netdev) &&
1327             skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1328                 netif_wake_queue(tp->netdev);
1329
1330         netif_tx_unlock(tp->netdev);
1331
1332         usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1333                           agg->head, (int)(tx_data - (u8 *)agg->head),
1334                           (usb_complete_t)write_bulk_callback, agg);
1335
1336         return usb_submit_urb(agg->urb, GFP_ATOMIC);
1337 }
1338
1339 static void rx_bottom(struct r8152 *tp)
1340 {
1341         unsigned long flags;
1342         struct list_head *cursor, *next;
1343
1344         spin_lock_irqsave(&tp->rx_lock, flags);
1345         list_for_each_safe(cursor, next, &tp->rx_done) {
1346                 struct rx_desc *rx_desc;
1347                 struct rx_agg *agg;
1348                 int len_used = 0;
1349                 struct urb *urb;
1350                 u8 *rx_data;
1351                 int ret;
1352
1353                 list_del_init(cursor);
1354                 spin_unlock_irqrestore(&tp->rx_lock, flags);
1355
1356                 agg = list_entry(cursor, struct rx_agg, list);
1357                 urb = agg->urb;
1358                 if (urb->actual_length < ETH_ZLEN)
1359                         goto submit;
1360
1361                 rx_desc = agg->head;
1362                 rx_data = agg->head;
1363                 len_used += sizeof(struct rx_desc);
1364
1365                 while (urb->actual_length > len_used) {
1366                         struct net_device *netdev = tp->netdev;
1367                         struct net_device_stats *stats;
1368                         unsigned int pkt_len;
1369                         struct sk_buff *skb;
1370
1371                         pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1372                         if (pkt_len < ETH_ZLEN)
1373                                 break;
1374
1375                         len_used += pkt_len;
1376                         if (urb->actual_length < len_used)
1377                                 break;
1378
1379                         stats = rtl8152_get_stats(netdev);
1380
1381                         pkt_len -= CRC_SIZE;
1382                         rx_data += sizeof(struct rx_desc);
1383
1384                         skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1385                         if (!skb) {
1386                                 stats->rx_dropped++;
1387                                 break;
1388                         }
1389                         memcpy(skb->data, rx_data, pkt_len);
1390                         skb_put(skb, pkt_len);
1391                         skb->protocol = eth_type_trans(skb, netdev);
1392                         netif_rx(skb);
1393                         stats->rx_packets++;
1394                         stats->rx_bytes += pkt_len;
1395
1396                         rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1397                         rx_desc = (struct rx_desc *)rx_data;
1398                         len_used = (int)(rx_data - (u8 *)agg->head);
1399                         len_used += sizeof(struct rx_desc);
1400                 }
1401
1402 submit:
1403                 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1404                 spin_lock_irqsave(&tp->rx_lock, flags);
1405                 if (ret && ret != -ENODEV) {
1406                         list_add_tail(&agg->list, next);
1407                         tasklet_schedule(&tp->tl);
1408                 }
1409         }
1410         spin_unlock_irqrestore(&tp->rx_lock, flags);
1411 }
1412
1413 static void tx_bottom(struct r8152 *tp)
1414 {
1415         int res;
1416
1417         do {
1418                 struct tx_agg *agg;
1419
1420                 if (skb_queue_empty(&tp->tx_queue))
1421                         break;
1422
1423                 agg = r8152_get_tx_agg(tp);
1424                 if (!agg)
1425                         break;
1426
1427                 res = r8152_tx_agg_fill(tp, agg);
1428                 if (res) {
1429                         struct net_device_stats *stats;
1430                         struct net_device *netdev;
1431                         unsigned long flags;
1432
1433                         netdev = tp->netdev;
1434                         stats = rtl8152_get_stats(netdev);
1435
1436                         if (res == -ENODEV) {
1437                                 netif_device_detach(netdev);
1438                         } else {
1439                                 netif_warn(tp, tx_err, netdev,
1440                                            "failed tx_urb %d\n", res);
1441                                 stats->tx_dropped += agg->skb_num;
1442                                 spin_lock_irqsave(&tp->tx_lock, flags);
1443                                 list_add_tail(&agg->list, &tp->tx_free);
1444                                 spin_unlock_irqrestore(&tp->tx_lock, flags);
1445                         }
1446                 }
1447         } while (res == 0);
1448 }
1449
1450 static void bottom_half(unsigned long data)
1451 {
1452         struct r8152 *tp;
1453
1454         tp = (struct r8152 *)data;
1455
1456         if (test_bit(RTL8152_UNPLUG, &tp->flags))
1457                 return;
1458
1459         if (!test_bit(WORK_ENABLE, &tp->flags))
1460                 return;
1461
1462         /* When link down, the driver would cancel all bulks. */
1463         /* This avoid the re-submitting bulk */
1464         if (!netif_carrier_ok(tp->netdev))
1465                 return;
1466
1467         rx_bottom(tp);
1468         tx_bottom(tp);
1469 }
1470
1471 static
1472 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1473 {
1474         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1475                       agg->head, rx_buf_sz,
1476                       (usb_complete_t)read_bulk_callback, agg);
1477
1478         return usb_submit_urb(agg->urb, mem_flags);
1479 }
1480
1481 static void rtl8152_tx_timeout(struct net_device *netdev)
1482 {
1483         struct r8152 *tp = netdev_priv(netdev);
1484         int i;
1485
1486         netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1487         for (i = 0; i < RTL8152_MAX_TX; i++)
1488                 usb_unlink_urb(tp->tx_info[i].urb);
1489 }
1490
1491 static void rtl8152_set_rx_mode(struct net_device *netdev)
1492 {
1493         struct r8152 *tp = netdev_priv(netdev);
1494
1495         if (tp->speed & LINK_STATUS) {
1496                 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1497                 schedule_delayed_work(&tp->schedule, 0);
1498         }
1499 }
1500
1501 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1502 {
1503         struct r8152 *tp = netdev_priv(netdev);
1504         u32 mc_filter[2];       /* Multicast hash filter */
1505         __le32 tmp[2];
1506         u32 ocp_data;
1507
1508         clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1509         netif_stop_queue(netdev);
1510         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1511         ocp_data &= ~RCR_ACPT_ALL;
1512         ocp_data |= RCR_AB | RCR_APM;
1513
1514         if (netdev->flags & IFF_PROMISC) {
1515                 /* Unconditionally log net taps. */
1516                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1517                 ocp_data |= RCR_AM | RCR_AAP;
1518                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1519         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1520                    (netdev->flags & IFF_ALLMULTI)) {
1521                 /* Too many to filter perfectly -- accept all multicasts. */
1522                 ocp_data |= RCR_AM;
1523                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1524         } else {
1525                 struct netdev_hw_addr *ha;
1526
1527                 mc_filter[1] = mc_filter[0] = 0;
1528                 netdev_for_each_mc_addr(ha, netdev) {
1529                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1530                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1531                         ocp_data |= RCR_AM;
1532                 }
1533         }
1534
1535         tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1536         tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1537
1538         pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1539         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1540         netif_wake_queue(netdev);
1541 }
1542
1543 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1544                                             struct net_device *netdev)
1545 {
1546         struct r8152 *tp = netdev_priv(netdev);
1547
1548         skb_tx_timestamp(skb);
1549
1550         skb_queue_tail(&tp->tx_queue, skb);
1551
1552         if (list_empty(&tp->tx_free) &&
1553             skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1554                 netif_stop_queue(netdev);
1555
1556         if (!list_empty(&tp->tx_free))
1557                 tasklet_schedule(&tp->tl);
1558
1559         return NETDEV_TX_OK;
1560 }
1561
1562 static void r8152b_reset_packet_filter(struct r8152 *tp)
1563 {
1564         u32     ocp_data;
1565
1566         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1567         ocp_data &= ~FMC_FCR_MCU_EN;
1568         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1569         ocp_data |= FMC_FCR_MCU_EN;
1570         ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1571 }
1572
1573 static void rtl8152_nic_reset(struct r8152 *tp)
1574 {
1575         int     i;
1576
1577         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1578
1579         for (i = 0; i < 1000; i++) {
1580                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1581                         break;
1582                 udelay(100);
1583         }
1584 }
1585
1586 static void set_tx_qlen(struct r8152 *tp)
1587 {
1588         struct net_device *netdev = tp->netdev;
1589
1590         tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1591                                    sizeof(struct tx_desc));
1592 }
1593
1594 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1595 {
1596         return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1597 }
1598
1599 static void rtl_set_eee_plus(struct r8152 *tp)
1600 {
1601         u32 ocp_data;
1602         u8 speed;
1603
1604         speed = rtl8152_get_speed(tp);
1605         if (speed & _10bps) {
1606                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1607                 ocp_data |= EEEP_CR_EEEP_TX;
1608                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1609         } else {
1610                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1611                 ocp_data &= ~EEEP_CR_EEEP_TX;
1612                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1613         }
1614 }
1615
1616 static int rtl_enable(struct r8152 *tp)
1617 {
1618         u32 ocp_data;
1619         int i, ret;
1620
1621         r8152b_reset_packet_filter(tp);
1622
1623         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1624         ocp_data |= CR_RE | CR_TE;
1625         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1626
1627         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1628         ocp_data &= ~RXDY_GATED_EN;
1629         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1630
1631         INIT_LIST_HEAD(&tp->rx_done);
1632         ret = 0;
1633         for (i = 0; i < RTL8152_MAX_RX; i++) {
1634                 INIT_LIST_HEAD(&tp->rx_info[i].list);
1635                 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1636         }
1637
1638         return ret;
1639 }
1640
1641 static int rtl8152_enable(struct r8152 *tp)
1642 {
1643         set_tx_qlen(tp);
1644         rtl_set_eee_plus(tp);
1645
1646         return rtl_enable(tp);
1647 }
1648
1649 static void r8153_set_rx_agg(struct r8152 *tp)
1650 {
1651         u8 speed;
1652
1653         speed = rtl8152_get_speed(tp);
1654         if (speed & _1000bps) {
1655                 if (tp->udev->speed == USB_SPEED_SUPER) {
1656                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1657                                         RX_THR_SUPPER);
1658                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1659                                         EARLY_AGG_SUPPER);
1660                 } else {
1661                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1662                                         RX_THR_HIGH);
1663                         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1664                                         EARLY_AGG_HIGH);
1665                 }
1666         } else {
1667                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1668                 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1669                                 EARLY_AGG_SLOW);
1670         }
1671 }
1672
1673 static int rtl8153_enable(struct r8152 *tp)
1674 {
1675         set_tx_qlen(tp);
1676         rtl_set_eee_plus(tp);
1677         r8153_set_rx_agg(tp);
1678
1679         return rtl_enable(tp);
1680 }
1681
1682 static void rtl8152_disable(struct r8152 *tp)
1683 {
1684         struct net_device_stats *stats = rtl8152_get_stats(tp->netdev);
1685         struct sk_buff *skb;
1686         u32 ocp_data;
1687         int i;
1688
1689         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1690         ocp_data &= ~RCR_ACPT_ALL;
1691         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1692
1693         while ((skb = skb_dequeue(&tp->tx_queue))) {
1694                 dev_kfree_skb(skb);
1695                 stats->tx_dropped++;
1696         }
1697
1698         for (i = 0; i < RTL8152_MAX_TX; i++)
1699                 usb_kill_urb(tp->tx_info[i].urb);
1700
1701         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1702         ocp_data |= RXDY_GATED_EN;
1703         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1704
1705         for (i = 0; i < 1000; i++) {
1706                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1707                 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
1708                         break;
1709                 mdelay(1);
1710         }
1711
1712         for (i = 0; i < 1000; i++) {
1713                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
1714                         break;
1715                 mdelay(1);
1716         }
1717
1718         for (i = 0; i < RTL8152_MAX_RX; i++)
1719                 usb_kill_urb(tp->rx_info[i].urb);
1720
1721         rtl8152_nic_reset(tp);
1722 }
1723
1724 static void r8152b_exit_oob(struct r8152 *tp)
1725 {
1726         u32     ocp_data;
1727         int     i;
1728
1729         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1730         ocp_data &= ~RCR_ACPT_ALL;
1731         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1732
1733         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1734         ocp_data |= RXDY_GATED_EN;
1735         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1736
1737         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1738         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
1739
1740         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1741         ocp_data &= ~NOW_IS_OOB;
1742         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1743
1744         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1745         ocp_data &= ~MCU_BORW_EN;
1746         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1747
1748         for (i = 0; i < 1000; i++) {
1749                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1750                 if (ocp_data & LINK_LIST_READY)
1751                         break;
1752                 mdelay(1);
1753         }
1754
1755         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1756         ocp_data |= RE_INIT_LL;
1757         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1758
1759         for (i = 0; i < 1000; i++) {
1760                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1761                 if (ocp_data & LINK_LIST_READY)
1762                         break;
1763                 mdelay(1);
1764         }
1765
1766         rtl8152_nic_reset(tp);
1767
1768         /* rx share fifo credit full threshold */
1769         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
1770
1771         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
1772         ocp_data &= STAT_SPEED_MASK;
1773         if (ocp_data == STAT_SPEED_FULL) {
1774                 /* rx share fifo credit near full threshold */
1775                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1776                                 RXFIFO_THR2_FULL);
1777                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1778                                 RXFIFO_THR3_FULL);
1779         } else {
1780                 /* rx share fifo credit near full threshold */
1781                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
1782                                 RXFIFO_THR2_HIGH);
1783                 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
1784                                 RXFIFO_THR3_HIGH);
1785         }
1786
1787         /* TX share fifo free credit full threshold */
1788         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1789
1790         ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1791         ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
1792         ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
1793                         TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
1794
1795         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1796         ocp_data &= ~CPCR_RX_VLAN;
1797         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1798
1799         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1800
1801         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
1802         ocp_data |= TCR0_AUTO_FIFO;
1803         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
1804 }
1805
1806 static void r8152b_enter_oob(struct r8152 *tp)
1807 {
1808         u32 ocp_data;
1809         int i;
1810
1811         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1812         ocp_data &= ~NOW_IS_OOB;
1813         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1814
1815         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
1816         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
1817         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
1818
1819         rtl8152_disable(tp);
1820
1821         for (i = 0; i < 1000; i++) {
1822                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1823                 if (ocp_data & LINK_LIST_READY)
1824                         break;
1825                 mdelay(1);
1826         }
1827
1828         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1829         ocp_data |= RE_INIT_LL;
1830         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1831
1832         for (i = 0; i < 1000; i++) {
1833                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1834                 if (ocp_data & LINK_LIST_READY)
1835                         break;
1836                 mdelay(1);
1837         }
1838
1839         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
1840
1841         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
1842         ocp_data |= MAGIC_EN;
1843         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
1844
1845         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
1846         ocp_data |= CPCR_RX_VLAN;
1847         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
1848
1849         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
1850         ocp_data |= ALDPS_PROXY_MODE;
1851         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
1852
1853         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1854         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
1855         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1856
1857         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
1858
1859         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1860         ocp_data &= ~RXDY_GATED_EN;
1861         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1862
1863         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1864         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1865         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1866 }
1867
1868 static void r8152b_disable_aldps(struct r8152 *tp)
1869 {
1870         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
1871         msleep(20);
1872 }
1873
1874 static inline void r8152b_enable_aldps(struct r8152 *tp)
1875 {
1876         ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
1877                                             LINKENA | DIS_SDSAVE);
1878 }
1879
1880 static void r8153_hw_phy_cfg(struct r8152 *tp)
1881 {
1882         u32 ocp_data;
1883         u16 data;
1884
1885         ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
1886         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
1887
1888         if (tp->version == RTL_VER_03) {
1889                 data = ocp_reg_read(tp, OCP_EEE_CFG);
1890                 data &= ~CTAP_SHORT_EN;
1891                 ocp_reg_write(tp, OCP_EEE_CFG, data);
1892         }
1893
1894         data = ocp_reg_read(tp, OCP_POWER_CFG);
1895         data |= EEE_CLKDIV_EN;
1896         ocp_reg_write(tp, OCP_POWER_CFG, data);
1897
1898         data = ocp_reg_read(tp, OCP_DOWN_SPEED);
1899         data |= EN_10M_BGOFF;
1900         ocp_reg_write(tp, OCP_DOWN_SPEED, data);
1901         data = ocp_reg_read(tp, OCP_POWER_CFG);
1902         data |= EN_10M_PLLOFF;
1903         ocp_reg_write(tp, OCP_POWER_CFG, data);
1904         data = sram_read(tp, SRAM_IMPEDANCE);
1905         data &= ~RX_DRIVING_MASK;
1906         sram_write(tp, SRAM_IMPEDANCE, data);
1907
1908         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1909         ocp_data |= PFM_PWM_SWITCH;
1910         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1911
1912         data = sram_read(tp, SRAM_LPF_CFG);
1913         data |= LPF_AUTO_TUNE;
1914         sram_write(tp, SRAM_LPF_CFG, data);
1915
1916         data = sram_read(tp, SRAM_10M_AMP1);
1917         data |= GDAC_IB_UPALL;
1918         sram_write(tp, SRAM_10M_AMP1, data);
1919         data = sram_read(tp, SRAM_10M_AMP2);
1920         data |= AMP_DN;
1921         sram_write(tp, SRAM_10M_AMP2, data);
1922 }
1923
1924 static void r8153_u1u2en(struct r8152 *tp, int enable)
1925 {
1926         u8 u1u2[8];
1927
1928         if (enable)
1929                 memset(u1u2, 0xff, sizeof(u1u2));
1930         else
1931                 memset(u1u2, 0x00, sizeof(u1u2));
1932
1933         usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
1934 }
1935
1936 static void r8153_u2p3en(struct r8152 *tp, int enable)
1937 {
1938         u32 ocp_data;
1939
1940         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
1941         if (enable)
1942                 ocp_data |= U2P3_ENABLE;
1943         else
1944                 ocp_data &= ~U2P3_ENABLE;
1945         ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
1946 }
1947
1948 static void r8153_power_cut_en(struct r8152 *tp, int enable)
1949 {
1950         u32 ocp_data;
1951
1952         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
1953         if (enable)
1954                 ocp_data |= PWR_EN | PHASE2_EN;
1955         else
1956                 ocp_data &= ~(PWR_EN | PHASE2_EN);
1957         ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
1958
1959         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1960         ocp_data &= ~PCUT_STATUS;
1961         ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
1962 }
1963
1964 static void r8153_teredo_off(struct r8152 *tp)
1965 {
1966         u32 ocp_data;
1967
1968         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
1969         ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
1970         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
1971
1972         ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
1973         ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
1974         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
1975 }
1976
1977 static void r8153_first_init(struct r8152 *tp)
1978 {
1979         u32 ocp_data;
1980         int i;
1981
1982         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1983         ocp_data |= RXDY_GATED_EN;
1984         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1985
1986         r8153_teredo_off(tp);
1987
1988         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1989         ocp_data &= ~RCR_ACPT_ALL;
1990         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1991
1992         r8153_hw_phy_cfg(tp);
1993
1994         rtl8152_nic_reset(tp);
1995
1996         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1997         ocp_data &= ~NOW_IS_OOB;
1998         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1999
2000         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2001         ocp_data &= ~MCU_BORW_EN;
2002         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2003
2004         for (i = 0; i < 1000; i++) {
2005                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2006                 if (ocp_data & LINK_LIST_READY)
2007                         break;
2008                 mdelay(1);
2009         }
2010
2011         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2012         ocp_data |= RE_INIT_LL;
2013         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2014
2015         for (i = 0; i < 1000; i++) {
2016                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2017                 if (ocp_data & LINK_LIST_READY)
2018                         break;
2019                 mdelay(1);
2020         }
2021
2022         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2023         ocp_data &= ~CPCR_RX_VLAN;
2024         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2025
2026         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2027
2028         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2029         ocp_data |= TCR0_AUTO_FIFO;
2030         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2031
2032         rtl8152_nic_reset(tp);
2033
2034         /* rx share fifo credit full threshold */
2035         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2036         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2037         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2038         /* TX share fifo free credit full threshold */
2039         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2040
2041         /* rx aggregation */
2042         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2043         ocp_data &= ~RX_AGG_DISABLE;
2044         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2045 }
2046
2047 static void r8153_enter_oob(struct r8152 *tp)
2048 {
2049         u32 ocp_data;
2050         int i;
2051
2052         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2053         ocp_data &= ~NOW_IS_OOB;
2054         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2055
2056         rtl8152_disable(tp);
2057
2058         for (i = 0; i < 1000; i++) {
2059                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2060                 if (ocp_data & LINK_LIST_READY)
2061                         break;
2062                 mdelay(1);
2063         }
2064
2065         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2066         ocp_data |= RE_INIT_LL;
2067         ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2068
2069         for (i = 0; i < 1000; i++) {
2070                 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2071                 if (ocp_data & LINK_LIST_READY)
2072                         break;
2073                 mdelay(1);
2074         }
2075
2076         ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2077
2078         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2079         ocp_data |= MAGIC_EN;
2080         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2081
2082         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2083         ocp_data &= ~TEREDO_WAKE_MASK;
2084         ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2085
2086         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2087         ocp_data |= CPCR_RX_VLAN;
2088         ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2089
2090         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2091         ocp_data |= ALDPS_PROXY_MODE;
2092         ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2093
2094         ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2095         ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2096         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2097
2098         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN);
2099
2100         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2101         ocp_data &= ~RXDY_GATED_EN;
2102         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2103
2104         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2105         ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2106         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2107 }
2108
2109 static void r8153_disable_aldps(struct r8152 *tp)
2110 {
2111         u16 data;
2112
2113         data = ocp_reg_read(tp, OCP_POWER_CFG);
2114         data &= ~EN_ALDPS;
2115         ocp_reg_write(tp, OCP_POWER_CFG, data);
2116         msleep(20);
2117 }
2118
2119 static void r8153_enable_aldps(struct r8152 *tp)
2120 {
2121         u16 data;
2122
2123         data = ocp_reg_read(tp, OCP_POWER_CFG);
2124         data |= EN_ALDPS;
2125         ocp_reg_write(tp, OCP_POWER_CFG, data);
2126 }
2127
2128 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2129 {
2130         u16 bmcr, anar, gbcr;
2131         int ret = 0;
2132
2133         cancel_delayed_work_sync(&tp->schedule);
2134         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2135         anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2136                   ADVERTISE_100HALF | ADVERTISE_100FULL);
2137         if (tp->mii.supports_gmii) {
2138                 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2139                 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2140         } else {
2141                 gbcr = 0;
2142         }
2143
2144         if (autoneg == AUTONEG_DISABLE) {
2145                 if (speed == SPEED_10) {
2146                         bmcr = 0;
2147                         anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2148                 } else if (speed == SPEED_100) {
2149                         bmcr = BMCR_SPEED100;
2150                         anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2151                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2152                         bmcr = BMCR_SPEED1000;
2153                         gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2154                 } else {
2155                         ret = -EINVAL;
2156                         goto out;
2157                 }
2158
2159                 if (duplex == DUPLEX_FULL)
2160                         bmcr |= BMCR_FULLDPLX;
2161         } else {
2162                 if (speed == SPEED_10) {
2163                         if (duplex == DUPLEX_FULL)
2164                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2165                         else
2166                                 anar |= ADVERTISE_10HALF;
2167                 } else if (speed == SPEED_100) {
2168                         if (duplex == DUPLEX_FULL) {
2169                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2170                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2171                         } else {
2172                                 anar |= ADVERTISE_10HALF;
2173                                 anar |= ADVERTISE_100HALF;
2174                         }
2175                 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2176                         if (duplex == DUPLEX_FULL) {
2177                                 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2178                                 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2179                                 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2180                         } else {
2181                                 anar |= ADVERTISE_10HALF;
2182                                 anar |= ADVERTISE_100HALF;
2183                                 gbcr |= ADVERTISE_1000HALF;
2184                         }
2185                 } else {
2186                         ret = -EINVAL;
2187                         goto out;
2188                 }
2189
2190                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2191         }
2192
2193         if (tp->mii.supports_gmii)
2194                 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2195
2196         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2197         r8152_mdio_write(tp, MII_BMCR, bmcr);
2198
2199 out:
2200
2201         return ret;
2202 }
2203
2204 static void rtl8152_down(struct r8152 *tp)
2205 {
2206         u32     ocp_data;
2207
2208         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2209         ocp_data &= ~POWER_CUT;
2210         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2211
2212         r8152b_disable_aldps(tp);
2213         r8152b_enter_oob(tp);
2214         r8152b_enable_aldps(tp);
2215 }
2216
2217 static void rtl8153_down(struct r8152 *tp)
2218 {
2219         r8153_u1u2en(tp, 0);
2220         r8153_power_cut_en(tp, 0);
2221         r8153_disable_aldps(tp);
2222         r8153_enter_oob(tp);
2223         r8153_enable_aldps(tp);
2224 }
2225
2226 static void set_carrier(struct r8152 *tp)
2227 {
2228         struct net_device *netdev = tp->netdev;
2229         u8 speed;
2230
2231         clear_bit(RTL8152_LINK_CHG, &tp->flags);
2232         speed = rtl8152_get_speed(tp);
2233
2234         if (speed & LINK_STATUS) {
2235                 if (!(tp->speed & LINK_STATUS)) {
2236                         tp->rtl_ops.enable(tp);
2237                         set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2238                         netif_carrier_on(netdev);
2239                 }
2240         } else {
2241                 if (tp->speed & LINK_STATUS) {
2242                         netif_carrier_off(netdev);
2243                         tasklet_disable(&tp->tl);
2244                         tp->rtl_ops.disable(tp);
2245                         tasklet_enable(&tp->tl);
2246                 }
2247         }
2248         tp->speed = speed;
2249 }
2250
2251 static void rtl_work_func_t(struct work_struct *work)
2252 {
2253         struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2254
2255         if (!test_bit(WORK_ENABLE, &tp->flags))
2256                 goto out1;
2257
2258         if (test_bit(RTL8152_UNPLUG, &tp->flags))
2259                 goto out1;
2260
2261         if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2262                 set_carrier(tp);
2263
2264         if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2265                 _rtl8152_set_rx_mode(tp->netdev);
2266
2267 out1:
2268         return;
2269 }
2270
2271 static int rtl8152_open(struct net_device *netdev)
2272 {
2273         struct r8152 *tp = netdev_priv(netdev);
2274         int res = 0;
2275
2276         rtl8152_set_speed(tp, AUTONEG_ENABLE,
2277                           tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2278                           DUPLEX_FULL);
2279         tp->speed = 0;
2280         netif_carrier_off(netdev);
2281         netif_start_queue(netdev);
2282         set_bit(WORK_ENABLE, &tp->flags);
2283         res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2284         if (res) {
2285                 if (res == -ENODEV)
2286                         netif_device_detach(tp->netdev);
2287                 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2288                            res);
2289         }
2290
2291
2292         return res;
2293 }
2294
2295 static int rtl8152_close(struct net_device *netdev)
2296 {
2297         struct r8152 *tp = netdev_priv(netdev);
2298         int res = 0;
2299
2300         clear_bit(WORK_ENABLE, &tp->flags);
2301         usb_kill_urb(tp->intr_urb);
2302         cancel_delayed_work_sync(&tp->schedule);
2303         netif_stop_queue(netdev);
2304         tasklet_disable(&tp->tl);
2305         tp->rtl_ops.disable(tp);
2306         tasklet_enable(&tp->tl);
2307
2308         return res;
2309 }
2310
2311 static void rtl_clear_bp(struct r8152 *tp)
2312 {
2313         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2314         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2315         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2316         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2317         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2318         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2319         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2320         ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2321         mdelay(3);
2322         ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2323         ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2324 }
2325
2326 static void r8153_clear_bp(struct r8152 *tp)
2327 {
2328         ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2329         ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2330         rtl_clear_bp(tp);
2331 }
2332
2333 static void r8152b_enable_eee(struct r8152 *tp)
2334 {
2335         u32 ocp_data;
2336
2337         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2338         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2339         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2340         ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2341                                            EEE_10_CAP | EEE_NWAY_EN |
2342                                            TX_QUIET_EN | RX_QUIET_EN |
2343                                            SDRISETIME | RG_RXLPI_MSK_HFDUP |
2344                                            SDFALLTIME);
2345         ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2346                                            RG_LDVQUIET_EN | RG_CKRSEL |
2347                                            RG_EEEPRG_EN);
2348         ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2349         ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2350         ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2351         ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2352         ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2353         ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2354 }
2355
2356 static void r8153_enable_eee(struct r8152 *tp)
2357 {
2358         u32 ocp_data;
2359         u16 data;
2360
2361         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2362         ocp_data |= EEE_RX_EN | EEE_TX_EN;
2363         ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2364         data = ocp_reg_read(tp, OCP_EEE_CFG);
2365         data |= EEE10_EN;
2366         ocp_reg_write(tp, OCP_EEE_CFG, data);
2367         data = ocp_reg_read(tp, OCP_EEE_CFG2);
2368         data |= MY1000_EEE | MY100_EEE;
2369         ocp_reg_write(tp, OCP_EEE_CFG2, data);
2370 }
2371
2372 static void r8152b_enable_fc(struct r8152 *tp)
2373 {
2374         u16 anar;
2375
2376         anar = r8152_mdio_read(tp, MII_ADVERTISE);
2377         anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2378         r8152_mdio_write(tp, MII_ADVERTISE, anar);
2379 }
2380
2381 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2382 {
2383         r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE);
2384         r8152b_disable_aldps(tp);
2385 }
2386
2387 static void r8152b_init(struct r8152 *tp)
2388 {
2389         u32 ocp_data;
2390         int i;
2391
2392         rtl_clear_bp(tp);
2393
2394         if (tp->version == RTL_VER_01) {
2395                 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2396                 ocp_data &= ~LED_MODE_MASK;
2397                 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2398         }
2399
2400         r8152b_hw_phy_cfg(tp);
2401
2402         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2403         ocp_data &= ~POWER_CUT;
2404         ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2405
2406         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2407         ocp_data &= ~RESUME_INDICATE;
2408         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2409
2410         r8152b_exit_oob(tp);
2411
2412         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2413         ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2414         ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2415         ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2416         ocp_data &= ~MCU_CLK_RATIO_MASK;
2417         ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2418         ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2419         ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2420                    SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2421         ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2422
2423         r8152b_enable_eee(tp);
2424         r8152b_enable_aldps(tp);
2425         r8152b_enable_fc(tp);
2426
2427         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2428                                        BMCR_ANRESTART);
2429         for (i = 0; i < 100; i++) {
2430                 udelay(100);
2431                 if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET))
2432                         break;
2433         }
2434
2435         /* enable rx aggregation */
2436         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2437         ocp_data &= ~RX_AGG_DISABLE;
2438         ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2439 }
2440
2441 static void r8153_init(struct r8152 *tp)
2442 {
2443         u32 ocp_data;
2444         int i;
2445
2446         r8153_u1u2en(tp, 0);
2447
2448         for (i = 0; i < 500; i++) {
2449                 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2450                     AUTOLOAD_DONE)
2451                         break;
2452                 msleep(20);
2453         }
2454
2455         for (i = 0; i < 500; i++) {
2456                 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2457                 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2458                         break;
2459                 msleep(20);
2460         }
2461
2462         r8153_u2p3en(tp, 0);
2463
2464         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
2465         ocp_data &= ~TIMER11_EN;
2466         ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
2467
2468         r8153_clear_bp(tp);
2469
2470         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2471         ocp_data &= ~LED_MODE_MASK;
2472         ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2473
2474         ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
2475         ocp_data &= ~LPM_TIMER_MASK;
2476         if (tp->udev->speed == USB_SPEED_SUPER)
2477                 ocp_data |= LPM_TIMER_500US;
2478         else
2479                 ocp_data |= LPM_TIMER_500MS;
2480         ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
2481
2482         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
2483         ocp_data &= ~SEN_VAL_MASK;
2484         ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
2485         ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
2486
2487         r8153_power_cut_en(tp, 0);
2488         r8153_u1u2en(tp, 1);
2489
2490         r8153_first_init(tp);
2491
2492         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
2493         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
2494         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2495                        PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2496                        U1U2_SPDWN_EN | L1_SPDWN_EN);
2497         ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2498                        PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2499                        TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
2500                        EEE_SPDWN_EN);
2501
2502         r8153_enable_eee(tp);
2503         r8153_enable_aldps(tp);
2504         r8152b_enable_fc(tp);
2505
2506         r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE |
2507                                        BMCR_ANRESTART);
2508 }
2509
2510 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
2511 {
2512         struct r8152 *tp = usb_get_intfdata(intf);
2513
2514         netif_device_detach(tp->netdev);
2515
2516         if (netif_running(tp->netdev)) {
2517                 clear_bit(WORK_ENABLE, &tp->flags);
2518                 usb_kill_urb(tp->intr_urb);
2519                 cancel_delayed_work_sync(&tp->schedule);
2520                 tasklet_disable(&tp->tl);
2521         }
2522
2523         tp->rtl_ops.down(tp);
2524
2525         return 0;
2526 }
2527
2528 static int rtl8152_resume(struct usb_interface *intf)
2529 {
2530         struct r8152 *tp = usb_get_intfdata(intf);
2531
2532         tp->rtl_ops.init(tp);
2533         netif_device_attach(tp->netdev);
2534         if (netif_running(tp->netdev)) {
2535                 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2536                                 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2537                                 DUPLEX_FULL);
2538                 tp->speed = 0;
2539                 netif_carrier_off(tp->netdev);
2540                 set_bit(WORK_ENABLE, &tp->flags);
2541                 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2542                 tasklet_enable(&tp->tl);
2543         }
2544
2545         return 0;
2546 }
2547
2548 static void rtl8152_get_drvinfo(struct net_device *netdev,
2549                                 struct ethtool_drvinfo *info)
2550 {
2551         struct r8152 *tp = netdev_priv(netdev);
2552
2553         strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
2554         strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
2555         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
2556 }
2557
2558 static
2559 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2560 {
2561         struct r8152 *tp = netdev_priv(netdev);
2562
2563         if (!tp->mii.mdio_read)
2564                 return -EOPNOTSUPP;
2565
2566         return mii_ethtool_gset(&tp->mii, cmd);
2567 }
2568
2569 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2570 {
2571         struct r8152 *tp = netdev_priv(dev);
2572
2573         return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
2574 }
2575
2576 static struct ethtool_ops ops = {
2577         .get_drvinfo = rtl8152_get_drvinfo,
2578         .get_settings = rtl8152_get_settings,
2579         .set_settings = rtl8152_set_settings,
2580         .get_link = ethtool_op_get_link,
2581 };
2582
2583 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2584 {
2585         struct r8152 *tp = netdev_priv(netdev);
2586         struct mii_ioctl_data *data = if_mii(rq);
2587         int res = 0;
2588
2589         switch (cmd) {
2590         case SIOCGMIIPHY:
2591                 data->phy_id = R8152_PHY_ID; /* Internal PHY */
2592                 break;
2593
2594         case SIOCGMIIREG:
2595                 data->val_out = r8152_mdio_read(tp, data->reg_num);
2596                 break;
2597
2598         case SIOCSMIIREG:
2599                 if (!capable(CAP_NET_ADMIN)) {
2600                         res = -EPERM;
2601                         break;
2602                 }
2603                 r8152_mdio_write(tp, data->reg_num, data->val_in);
2604                 break;
2605
2606         default:
2607                 res = -EOPNOTSUPP;
2608         }
2609
2610         return res;
2611 }
2612
2613 static const struct net_device_ops rtl8152_netdev_ops = {
2614         .ndo_open               = rtl8152_open,
2615         .ndo_stop               = rtl8152_close,
2616         .ndo_do_ioctl           = rtl8152_ioctl,
2617         .ndo_start_xmit         = rtl8152_start_xmit,
2618         .ndo_tx_timeout         = rtl8152_tx_timeout,
2619         .ndo_set_rx_mode        = rtl8152_set_rx_mode,
2620         .ndo_set_mac_address    = rtl8152_set_mac_address,
2621
2622         .ndo_change_mtu         = eth_change_mtu,
2623         .ndo_validate_addr      = eth_validate_addr,
2624 };
2625
2626 static void r8152b_get_version(struct r8152 *tp)
2627 {
2628         u32     ocp_data;
2629         u16     version;
2630
2631         ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2632         version = (u16)(ocp_data & VERSION_MASK);
2633
2634         switch (version) {
2635         case 0x4c00:
2636                 tp->version = RTL_VER_01;
2637                 break;
2638         case 0x4c10:
2639                 tp->version = RTL_VER_02;
2640                 break;
2641         case 0x5c00:
2642                 tp->version = RTL_VER_03;
2643                 tp->mii.supports_gmii = 1;
2644                 break;
2645         case 0x5c10:
2646                 tp->version = RTL_VER_04;
2647                 tp->mii.supports_gmii = 1;
2648                 break;
2649         case 0x5c20:
2650                 tp->version = RTL_VER_05;
2651                 tp->mii.supports_gmii = 1;
2652                 break;
2653         default:
2654                 netif_info(tp, probe, tp->netdev,
2655                            "Unknown version 0x%04x\n", version);
2656                 break;
2657         }
2658 }
2659
2660 static void rtl8152_unload(struct r8152 *tp)
2661 {
2662         u32     ocp_data;
2663
2664         if (tp->version != RTL_VER_01) {
2665                 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2666                 ocp_data |= POWER_CUT;
2667                 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2668         }
2669
2670         ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2671         ocp_data &= ~RESUME_INDICATE;
2672         ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2673 }
2674
2675 static void rtl8153_unload(struct r8152 *tp)
2676 {
2677         r8153_power_cut_en(tp, 1);
2678 }
2679
2680 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
2681 {
2682         struct rtl_ops *ops = &tp->rtl_ops;
2683         int ret = -ENODEV;
2684
2685         switch (id->idVendor) {
2686         case VENDOR_ID_REALTEK:
2687                 switch (id->idProduct) {
2688                 case PRODUCT_ID_RTL8152:
2689                         ops->init               = r8152b_init;
2690                         ops->enable             = rtl8152_enable;
2691                         ops->disable            = rtl8152_disable;
2692                         ops->down               = rtl8152_down;
2693                         ops->unload             = rtl8152_unload;
2694                         ret = 0;
2695                         break;
2696                 case PRODUCT_ID_RTL8153:
2697                         ops->init               = r8153_init;
2698                         ops->enable             = rtl8153_enable;
2699                         ops->disable            = rtl8152_disable;
2700                         ops->down               = rtl8153_down;
2701                         ops->unload             = rtl8153_unload;
2702                         ret = 0;
2703                         break;
2704                 default:
2705                         break;
2706                 }
2707                 break;
2708
2709         case VENDOR_ID_SAMSUNG:
2710                 switch (id->idProduct) {
2711                 case PRODUCT_ID_SAMSUNG:
2712                         ops->init               = r8153_init;
2713                         ops->enable             = rtl8153_enable;
2714                         ops->disable            = rtl8152_disable;
2715                         ops->down               = rtl8153_down;
2716                         ops->unload             = rtl8153_unload;
2717                         ret = 0;
2718                         break;
2719                 default:
2720                         break;
2721                 }
2722                 break;
2723
2724         default:
2725                 break;
2726         }
2727
2728         if (ret)
2729                 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
2730
2731         return ret;
2732 }
2733
2734 static int rtl8152_probe(struct usb_interface *intf,
2735                          const struct usb_device_id *id)
2736 {
2737         struct usb_device *udev = interface_to_usbdev(intf);
2738         struct r8152 *tp;
2739         struct net_device *netdev;
2740         int ret;
2741
2742         netdev = alloc_etherdev(sizeof(struct r8152));
2743         if (!netdev) {
2744                 dev_err(&intf->dev, "Out of memory\n");
2745                 return -ENOMEM;
2746         }
2747
2748         SET_NETDEV_DEV(netdev, &intf->dev);
2749         tp = netdev_priv(netdev);
2750         tp->msg_enable = 0x7FFF;
2751
2752         tp->udev = udev;
2753         tp->netdev = netdev;
2754         tp->intf = intf;
2755
2756         ret = rtl_ops_init(tp, id);
2757         if (ret)
2758                 goto out;
2759
2760         tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
2761         INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
2762
2763         netdev->netdev_ops = &rtl8152_netdev_ops;
2764         netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
2765
2766         netdev->features |= NETIF_F_IP_CSUM;
2767         netdev->hw_features = NETIF_F_IP_CSUM;
2768         SET_ETHTOOL_OPS(netdev, &ops);
2769
2770         tp->mii.dev = netdev;
2771         tp->mii.mdio_read = read_mii_word;
2772         tp->mii.mdio_write = write_mii_word;
2773         tp->mii.phy_id_mask = 0x3f;
2774         tp->mii.reg_num_mask = 0x1f;
2775         tp->mii.phy_id = R8152_PHY_ID;
2776         tp->mii.supports_gmii = 0;
2777
2778         r8152b_get_version(tp);
2779         tp->rtl_ops.init(tp);
2780         set_ethernet_addr(tp);
2781
2782         ret = alloc_all_mem(tp);
2783         if (ret)
2784                 goto out;
2785
2786         usb_set_intfdata(intf, tp);
2787
2788         ret = register_netdev(netdev);
2789         if (ret != 0) {
2790                 netif_err(tp, probe, netdev, "couldn't register the device\n");
2791                 goto out1;
2792         }
2793
2794         netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
2795
2796         return 0;
2797
2798 out1:
2799         usb_set_intfdata(intf, NULL);
2800 out:
2801         free_netdev(netdev);
2802         return ret;
2803 }
2804
2805 static void rtl8152_disconnect(struct usb_interface *intf)
2806 {
2807         struct r8152 *tp = usb_get_intfdata(intf);
2808
2809         usb_set_intfdata(intf, NULL);
2810         if (tp) {
2811                 set_bit(RTL8152_UNPLUG, &tp->flags);
2812                 tasklet_kill(&tp->tl);
2813                 unregister_netdev(tp->netdev);
2814                 tp->rtl_ops.unload(tp);
2815                 free_all_mem(tp);
2816                 free_netdev(tp->netdev);
2817         }
2818 }
2819
2820 /* table of devices that work with this driver */
2821 static struct usb_device_id rtl8152_table[] = {
2822         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
2823         {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
2824         {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
2825         {}
2826 };
2827
2828 MODULE_DEVICE_TABLE(usb, rtl8152_table);
2829
2830 static struct usb_driver rtl8152_driver = {
2831         .name =         MODULENAME,
2832         .id_table =     rtl8152_table,
2833         .probe =        rtl8152_probe,
2834         .disconnect =   rtl8152_disconnect,
2835         .suspend =      rtl8152_suspend,
2836         .resume =       rtl8152_resume,
2837         .reset_resume = rtl8152_resume,
2838 };
2839
2840 module_usb_driver(rtl8152_driver);
2841
2842 MODULE_AUTHOR(DRIVER_AUTHOR);
2843 MODULE_DESCRIPTION(DRIVER_DESC);
2844 MODULE_LICENSE("GPL");