2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/of_address.h>
30 #include <linux/phy.h>
31 #include <linux/clk.h>
34 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
35 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
36 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
37 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
38 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
39 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
40 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
41 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
42 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
43 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
44 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
45 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
46 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
47 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
48 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
49 #define MVNETA_PORT_RX_RESET 0x1cc0
50 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
51 #define MVNETA_PHY_ADDR 0x2000
52 #define MVNETA_PHY_ADDR_MASK 0x1f
53 #define MVNETA_MBUS_RETRY 0x2010
54 #define MVNETA_UNIT_INTR_CAUSE 0x2080
55 #define MVNETA_UNIT_CONTROL 0x20B0
56 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
57 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
58 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
59 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
60 #define MVNETA_BASE_ADDR_ENABLE 0x2290
61 #define MVNETA_PORT_CONFIG 0x2400
62 #define MVNETA_UNI_PROMISC_MODE BIT(0)
63 #define MVNETA_DEF_RXQ(q) ((q) << 1)
64 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
65 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
66 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
67 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
68 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
69 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
70 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
71 MVNETA_DEF_RXQ_ARP(q) | \
72 MVNETA_DEF_RXQ_TCP(q) | \
73 MVNETA_DEF_RXQ_UDP(q) | \
74 MVNETA_DEF_RXQ_BPDU(q) | \
75 MVNETA_TX_UNSET_ERR_SUM | \
76 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
77 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
78 #define MVNETA_MAC_ADDR_LOW 0x2414
79 #define MVNETA_MAC_ADDR_HIGH 0x2418
80 #define MVNETA_SDMA_CONFIG 0x241c
81 #define MVNETA_SDMA_BRST_SIZE_16 4
82 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
83 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
84 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
85 #define MVNETA_DESC_SWAP BIT(6)
86 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
87 #define MVNETA_PORT_STATUS 0x2444
88 #define MVNETA_TX_IN_PRGRS BIT(1)
89 #define MVNETA_TX_FIFO_EMPTY BIT(8)
90 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
91 #define MVNETA_SERDES_CFG 0x24A0
92 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
93 #define MVNETA_RGMII_SERDES_PROTO 0x0667
94 #define MVNETA_TYPE_PRIO 0x24bc
95 #define MVNETA_FORCE_UNI BIT(21)
96 #define MVNETA_TXQ_CMD_1 0x24e4
97 #define MVNETA_TXQ_CMD 0x2448
98 #define MVNETA_TXQ_DISABLE_SHIFT 8
99 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
100 #define MVNETA_ACC_MODE 0x2500
101 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
102 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
103 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
104 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
106 /* Exception Interrupt Port/Queue Cause register */
108 #define MVNETA_INTR_NEW_CAUSE 0x25a0
109 #define MVNETA_INTR_NEW_MASK 0x25a4
111 /* bits 0..7 = TXQ SENT, one bit per queue.
112 * bits 8..15 = RXQ OCCUP, one bit per queue.
113 * bits 16..23 = RXQ FREE, one bit per queue.
114 * bit 29 = OLD_REG_SUM, see old reg ?
115 * bit 30 = TX_ERR_SUM, one bit for 4 ports
116 * bit 31 = MISC_SUM, one bit for 4 ports
118 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
119 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
120 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
121 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
123 #define MVNETA_INTR_OLD_CAUSE 0x25a8
124 #define MVNETA_INTR_OLD_MASK 0x25ac
126 /* Data Path Port/Queue Cause Register */
127 #define MVNETA_INTR_MISC_CAUSE 0x25b0
128 #define MVNETA_INTR_MISC_MASK 0x25b4
130 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
131 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
132 #define MVNETA_CAUSE_PTP BIT(4)
134 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
135 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
136 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
137 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
138 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
139 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
140 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
141 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
143 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
144 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
145 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
147 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
148 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
149 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
151 #define MVNETA_INTR_ENABLE 0x25b8
152 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
153 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
155 #define MVNETA_RXQ_CMD 0x2680
156 #define MVNETA_RXQ_DISABLE_SHIFT 8
157 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
158 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
159 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
160 #define MVNETA_GMAC_CTRL_0 0x2c00
161 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
162 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
163 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
164 #define MVNETA_GMAC_CTRL_2 0x2c08
165 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
166 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
167 #define MVNETA_GMAC2_PORT_RESET BIT(6)
168 #define MVNETA_GMAC_STATUS 0x2c10
169 #define MVNETA_GMAC_LINK_UP BIT(0)
170 #define MVNETA_GMAC_SPEED_1000 BIT(1)
171 #define MVNETA_GMAC_SPEED_100 BIT(2)
172 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
173 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
174 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
175 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
176 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
177 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
178 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
179 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
180 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
181 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
182 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
183 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
184 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
185 #define MVNETA_MIB_COUNTERS_BASE 0x3080
186 #define MVNETA_MIB_LATE_COLLISION 0x7c
187 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
188 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
189 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
190 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
191 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
192 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
193 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
194 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
195 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
196 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
197 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
198 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
199 #define MVNETA_PORT_TX_RESET 0x3cf0
200 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
201 #define MVNETA_TX_MTU 0x3e0c
202 #define MVNETA_TX_TOKEN_SIZE 0x3e14
203 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
204 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
205 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
207 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
209 /* Descriptor ring Macros */
210 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
211 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
213 /* Various constants */
216 #define MVNETA_TXDONE_COAL_PKTS 16
217 #define MVNETA_RX_COAL_PKTS 32
218 #define MVNETA_RX_COAL_USEC 100
220 /* Napi polling weight */
221 #define MVNETA_RX_POLL_WEIGHT 64
223 /* The two bytes Marvell header. Either contains a special value used
224 * by Marvell switches when a specific hardware mode is enabled (not
225 * supported by this driver) or is filled automatically by zeroes on
226 * the RX side. Those two bytes being at the front of the Ethernet
227 * header, they allow to have the IP header aligned on a 4 bytes
228 * boundary automatically: the hardware skips those two bytes on its
231 #define MVNETA_MH_SIZE 2
233 #define MVNETA_VLAN_TAG_LEN 4
235 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
236 #define MVNETA_TX_CSUM_MAX_SIZE 9800
237 #define MVNETA_ACC_MODE_EXT 1
239 /* Timeout constants */
240 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
241 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
242 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
244 #define MVNETA_TX_MTU_MAX 0x3ffff
246 /* Max number of Rx descriptors */
247 #define MVNETA_MAX_RXD 128
249 /* Max number of Tx descriptors */
250 #define MVNETA_MAX_TXD 532
252 /* descriptor aligned size */
253 #define MVNETA_DESC_ALIGNED_SIZE 32
255 #define MVNETA_RX_PKT_SIZE(mtu) \
256 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
257 ETH_HLEN + ETH_FCS_LEN, \
258 MVNETA_CPU_D_CACHE_LINE_SIZE)
260 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
262 struct mvneta_pcpu_stats {
263 struct u64_stats_sync syncp;
272 unsigned int frag_size;
274 struct mvneta_rx_queue *rxqs;
275 struct mvneta_tx_queue *txqs;
276 struct net_device *dev;
279 struct napi_struct napi;
289 struct mvneta_pcpu_stats *stats;
291 struct mii_bus *mii_bus;
292 struct phy_device *phy_dev;
293 phy_interface_t phy_interface;
294 struct device_node *phy_node;
300 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
301 * layout of the transmit and reception DMA descriptors, and their
302 * layout is therefore defined by the hardware design
305 #define MVNETA_TX_L3_OFF_SHIFT 0
306 #define MVNETA_TX_IP_HLEN_SHIFT 8
307 #define MVNETA_TX_L4_UDP BIT(16)
308 #define MVNETA_TX_L3_IP6 BIT(17)
309 #define MVNETA_TXD_IP_CSUM BIT(18)
310 #define MVNETA_TXD_Z_PAD BIT(19)
311 #define MVNETA_TXD_L_DESC BIT(20)
312 #define MVNETA_TXD_F_DESC BIT(21)
313 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
314 MVNETA_TXD_L_DESC | \
316 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
317 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
319 #define MVNETA_RXD_ERR_CRC 0x0
320 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
321 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
322 #define MVNETA_RXD_ERR_LEN BIT(18)
323 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
324 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
325 #define MVNETA_RXD_L3_IP4 BIT(25)
326 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
327 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
329 #if defined(__LITTLE_ENDIAN)
330 struct mvneta_tx_desc {
331 u32 command; /* Options used by HW for packet transmitting.*/
332 u16 reserverd1; /* csum_l4 (for future use) */
333 u16 data_size; /* Data size of transmitted packet in bytes */
334 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
335 u32 reserved2; /* hw_cmd - (for future use, PMT) */
336 u32 reserved3[4]; /* Reserved - (for future use) */
339 struct mvneta_rx_desc {
340 u32 status; /* Info about received packet */
341 u16 reserved1; /* pnc_info - (for future use, PnC) */
342 u16 data_size; /* Size of received packet in bytes */
344 u32 buf_phys_addr; /* Physical address of the buffer */
345 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
347 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
348 u16 reserved3; /* prefetch_cmd, for future use */
349 u16 reserved4; /* csum_l4 - (for future use, PnC) */
351 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
352 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
355 struct mvneta_tx_desc {
356 u16 data_size; /* Data size of transmitted packet in bytes */
357 u16 reserverd1; /* csum_l4 (for future use) */
358 u32 command; /* Options used by HW for packet transmitting.*/
359 u32 reserved2; /* hw_cmd - (for future use, PMT) */
360 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
361 u32 reserved3[4]; /* Reserved - (for future use) */
364 struct mvneta_rx_desc {
365 u16 data_size; /* Size of received packet in bytes */
366 u16 reserved1; /* pnc_info - (for future use, PnC) */
367 u32 status; /* Info about received packet */
369 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
370 u32 buf_phys_addr; /* Physical address of the buffer */
372 u16 reserved4; /* csum_l4 - (for future use, PnC) */
373 u16 reserved3; /* prefetch_cmd, for future use */
374 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
376 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
377 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
381 struct mvneta_tx_queue {
382 /* Number of this TX queue, in the range 0-7 */
385 /* Number of TX DMA descriptors in the descriptor ring */
388 /* Number of currently used TX DMA descriptor in the
393 /* Array of transmitted skb */
394 struct sk_buff **tx_skb;
396 /* Index of last TX DMA descriptor that was inserted */
399 /* Index of the TX DMA descriptor to be cleaned up */
404 /* Virtual address of the TX DMA descriptors array */
405 struct mvneta_tx_desc *descs;
407 /* DMA address of the TX DMA descriptors array */
408 dma_addr_t descs_phys;
410 /* Index of the last TX DMA descriptor */
413 /* Index of the next TX DMA descriptor to process */
414 int next_desc_to_proc;
417 struct mvneta_rx_queue {
418 /* rx queue number, in the range 0-7 */
421 /* num of rx descriptors in the rx descriptor ring */
424 /* counter of times when mvneta_refill() failed */
430 /* Virtual address of the RX DMA descriptors array */
431 struct mvneta_rx_desc *descs;
433 /* DMA address of the RX DMA descriptors array */
434 dma_addr_t descs_phys;
436 /* Index of the last RX DMA descriptor */
439 /* Index of the next RX DMA descriptor to process */
440 int next_desc_to_proc;
443 static int rxq_number = 8;
444 static int txq_number = 8;
448 static int rx_copybreak __read_mostly = 256;
450 #define MVNETA_DRIVER_NAME "mvneta"
451 #define MVNETA_DRIVER_VERSION "1.0"
453 /* Utility/helper methods */
455 /* Write helper method */
456 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
458 writel(data, pp->base + offset);
461 /* Read helper method */
462 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
464 return readl(pp->base + offset);
467 /* Increment txq get counter */
468 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
470 txq->txq_get_index++;
471 if (txq->txq_get_index == txq->size)
472 txq->txq_get_index = 0;
475 /* Increment txq put counter */
476 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
478 txq->txq_put_index++;
479 if (txq->txq_put_index == txq->size)
480 txq->txq_put_index = 0;
484 /* Clear all MIB counters */
485 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
490 /* Perform dummy reads from MIB counters */
491 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
492 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
495 /* Get System Network Statistics */
496 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
497 struct rtnl_link_stats64 *stats)
499 struct mvneta_port *pp = netdev_priv(dev);
503 for_each_possible_cpu(cpu) {
504 struct mvneta_pcpu_stats *cpu_stats;
510 cpu_stats = per_cpu_ptr(pp->stats, cpu);
512 start = u64_stats_fetch_begin_bh(&cpu_stats->syncp);
513 rx_packets = cpu_stats->rx_packets;
514 rx_bytes = cpu_stats->rx_bytes;
515 tx_packets = cpu_stats->tx_packets;
516 tx_bytes = cpu_stats->tx_bytes;
517 } while (u64_stats_fetch_retry_bh(&cpu_stats->syncp, start));
519 stats->rx_packets += rx_packets;
520 stats->rx_bytes += rx_bytes;
521 stats->tx_packets += tx_packets;
522 stats->tx_bytes += tx_bytes;
525 stats->rx_errors = dev->stats.rx_errors;
526 stats->rx_dropped = dev->stats.rx_dropped;
528 stats->tx_dropped = dev->stats.tx_dropped;
533 /* Rx descriptors helper methods */
535 /* Checks whether the RX descriptor having this status is both the first
536 * and the last descriptor for the RX packet. Each RX packet is currently
537 * received through a single RX descriptor, so not having each RX
538 * descriptor with its first and last bits set is an error
540 static int mvneta_rxq_desc_is_first_last(u32 status)
542 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
543 MVNETA_RXD_FIRST_LAST_DESC;
546 /* Add number of descriptors ready to receive new packets */
547 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
548 struct mvneta_rx_queue *rxq,
551 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
554 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
555 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
556 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
557 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
558 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
561 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
562 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
565 /* Get number of RX descriptors occupied by received packets */
566 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
567 struct mvneta_rx_queue *rxq)
571 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
572 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
575 /* Update num of rx desc called upon return from rx path or
576 * from mvneta_rxq_drop_pkts().
578 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
579 struct mvneta_rx_queue *rxq,
580 int rx_done, int rx_filled)
584 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
586 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
587 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
591 /* Only 255 descriptors can be added at once */
592 while ((rx_done > 0) || (rx_filled > 0)) {
593 if (rx_done <= 0xff) {
600 if (rx_filled <= 0xff) {
601 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
604 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
607 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
611 /* Get pointer to next RX descriptor to be processed by SW */
612 static struct mvneta_rx_desc *
613 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
615 int rx_desc = rxq->next_desc_to_proc;
617 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
618 prefetch(rxq->descs + rxq->next_desc_to_proc);
619 return rxq->descs + rx_desc;
622 /* Change maximum receive size of the port. */
623 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
627 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
628 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
629 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
630 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
631 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
635 /* Set rx queue offset */
636 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
637 struct mvneta_rx_queue *rxq,
642 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
643 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
646 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
647 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
651 /* Tx descriptors helper methods */
653 /* Update HW with number of TX descriptors to be sent */
654 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
655 struct mvneta_tx_queue *txq,
660 /* Only 255 descriptors can be added at once ; Assume caller
661 * process TX desriptors in quanta less than 256
664 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
667 /* Get pointer to next TX descriptor to be processed (send) by HW */
668 static struct mvneta_tx_desc *
669 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
671 int tx_desc = txq->next_desc_to_proc;
673 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
674 return txq->descs + tx_desc;
677 /* Release the last allocated TX descriptor. Useful to handle DMA
678 * mapping failures in the TX path.
680 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
682 if (txq->next_desc_to_proc == 0)
683 txq->next_desc_to_proc = txq->last_desc - 1;
685 txq->next_desc_to_proc--;
688 /* Set rxq buf size */
689 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
690 struct mvneta_rx_queue *rxq,
695 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
697 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
698 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
700 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
703 /* Disable buffer management (BM) */
704 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
705 struct mvneta_rx_queue *rxq)
709 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
710 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
711 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
714 /* Start the Ethernet port RX and TX activity */
715 static void mvneta_port_up(struct mvneta_port *pp)
720 /* Enable all initialized TXs. */
721 mvneta_mib_counters_clear(pp);
723 for (queue = 0; queue < txq_number; queue++) {
724 struct mvneta_tx_queue *txq = &pp->txqs[queue];
725 if (txq->descs != NULL)
726 q_map |= (1 << queue);
728 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
730 /* Enable all initialized RXQs. */
732 for (queue = 0; queue < rxq_number; queue++) {
733 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
734 if (rxq->descs != NULL)
735 q_map |= (1 << queue);
738 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
741 /* Stop the Ethernet port activity */
742 static void mvneta_port_down(struct mvneta_port *pp)
747 /* Stop Rx port activity. Check port Rx activity. */
748 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
750 /* Issue stop command for active channels only */
752 mvreg_write(pp, MVNETA_RXQ_CMD,
753 val << MVNETA_RXQ_DISABLE_SHIFT);
755 /* Wait for all Rx activity to terminate. */
758 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
760 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
766 val = mvreg_read(pp, MVNETA_RXQ_CMD);
767 } while (val & 0xff);
769 /* Stop Tx port activity. Check port Tx activity. Issue stop
770 * command for active channels only
772 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
775 mvreg_write(pp, MVNETA_TXQ_CMD,
776 (val << MVNETA_TXQ_DISABLE_SHIFT));
778 /* Wait for all Tx activity to terminate. */
781 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
783 "TIMEOUT for TX stopped status=0x%08x\n",
789 /* Check TX Command reg that all Txqs are stopped */
790 val = mvreg_read(pp, MVNETA_TXQ_CMD);
792 } while (val & 0xff);
794 /* Double check to verify that TX FIFO is empty */
797 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
799 "TX FIFO empty timeout status=0x08%x\n",
805 val = mvreg_read(pp, MVNETA_PORT_STATUS);
806 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
807 (val & MVNETA_TX_IN_PRGRS));
812 /* Enable the port by setting the port enable bit of the MAC control register */
813 static void mvneta_port_enable(struct mvneta_port *pp)
818 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
819 val |= MVNETA_GMAC0_PORT_ENABLE;
820 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
823 /* Disable the port and wait for about 200 usec before retuning */
824 static void mvneta_port_disable(struct mvneta_port *pp)
828 /* Reset the Enable bit in the Serial Control Register */
829 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
830 val &= ~MVNETA_GMAC0_PORT_ENABLE;
831 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
836 /* Multicast tables methods */
838 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
839 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
847 val = 0x1 | (queue << 1);
848 val |= (val << 24) | (val << 16) | (val << 8);
851 for (offset = 0; offset <= 0xc; offset += 4)
852 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
855 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
856 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
864 val = 0x1 | (queue << 1);
865 val |= (val << 24) | (val << 16) | (val << 8);
868 for (offset = 0; offset <= 0xfc; offset += 4)
869 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
873 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
874 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
880 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
883 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
884 val = 0x1 | (queue << 1);
885 val |= (val << 24) | (val << 16) | (val << 8);
888 for (offset = 0; offset <= 0xfc; offset += 4)
889 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
892 /* This method sets defaults to the NETA port:
893 * Clears interrupt Cause and Mask registers.
894 * Clears all MAC tables.
895 * Sets defaults to all registers.
896 * Resets RX and TX descriptor rings.
898 * This method can be called after mvneta_port_down() to return the port
899 * settings to defaults.
901 static void mvneta_defaults_set(struct mvneta_port *pp)
907 /* Clear all Cause registers */
908 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
909 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
910 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
912 /* Mask all interrupts */
913 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
914 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
915 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
916 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
918 /* Enable MBUS Retry bit16 */
919 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
921 /* Set CPU queue access map - all CPUs have access to all RX
922 * queues and to all TX queues
924 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
925 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
926 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
927 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
929 /* Reset RX and TX DMAs */
930 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
931 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
933 /* Disable Legacy WRR, Disable EJP, Release from reset */
934 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
935 for (queue = 0; queue < txq_number; queue++) {
936 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
937 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
940 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
941 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
943 /* Set Port Acceleration Mode */
944 val = MVNETA_ACC_MODE_EXT;
945 mvreg_write(pp, MVNETA_ACC_MODE, val);
947 /* Update val of portCfg register accordingly with all RxQueue types */
948 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
949 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
952 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
953 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
955 /* Build PORT_SDMA_CONFIG_REG */
958 /* Default burst size */
959 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
960 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
961 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
963 #if defined(__BIG_ENDIAN)
964 val |= MVNETA_DESC_SWAP;
967 /* Assign port SDMA configuration */
968 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
970 /* Disable PHY polling in hardware, since we're using the
971 * kernel phylib to do this.
973 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
974 val &= ~MVNETA_PHY_POLLING_ENABLE;
975 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
977 mvneta_set_ucast_table(pp, -1);
978 mvneta_set_special_mcast_table(pp, -1);
979 mvneta_set_other_mcast_table(pp, -1);
981 /* Set port interrupt enable register - default enable all */
982 mvreg_write(pp, MVNETA_INTR_ENABLE,
983 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
984 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
987 /* Set max sizes for tx queues */
988 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
994 mtu = max_tx_size * 8;
995 if (mtu > MVNETA_TX_MTU_MAX)
996 mtu = MVNETA_TX_MTU_MAX;
999 val = mvreg_read(pp, MVNETA_TX_MTU);
1000 val &= ~MVNETA_TX_MTU_MAX;
1002 mvreg_write(pp, MVNETA_TX_MTU, val);
1004 /* TX token size and all TXQs token size must be larger that MTU */
1005 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1007 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1010 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1012 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1014 for (queue = 0; queue < txq_number; queue++) {
1015 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1017 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1020 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1022 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1027 /* Set unicast address */
1028 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1031 unsigned int unicast_reg;
1032 unsigned int tbl_offset;
1033 unsigned int reg_offset;
1035 /* Locate the Unicast table entry */
1036 last_nibble = (0xf & last_nibble);
1038 /* offset from unicast tbl base */
1039 tbl_offset = (last_nibble / 4) * 4;
1041 /* offset within the above reg */
1042 reg_offset = last_nibble % 4;
1044 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1047 /* Clear accepts frame bit at specified unicast DA tbl entry */
1048 unicast_reg &= ~(0xff << (8 * reg_offset));
1050 unicast_reg &= ~(0xff << (8 * reg_offset));
1051 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1054 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1057 /* Set mac address */
1058 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1065 mac_l = (addr[4] << 8) | (addr[5]);
1066 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1067 (addr[2] << 8) | (addr[3] << 0);
1069 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1070 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1073 /* Accept frames of this address */
1074 mvneta_set_ucast_addr(pp, addr[5], queue);
1077 /* Set the number of packets that will be received before RX interrupt
1078 * will be generated by HW.
1080 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1081 struct mvneta_rx_queue *rxq, u32 value)
1083 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1084 value | MVNETA_RXQ_NON_OCCUPIED(0));
1085 rxq->pkts_coal = value;
1088 /* Set the time delay in usec before RX interrupt will be generated by
1091 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1092 struct mvneta_rx_queue *rxq, u32 value)
1095 unsigned long clk_rate;
1097 clk_rate = clk_get_rate(pp->clk);
1098 val = (clk_rate / 1000000) * value;
1100 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1101 rxq->time_coal = value;
1104 /* Set threshold for TX_DONE pkts coalescing */
1105 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1106 struct mvneta_tx_queue *txq, u32 value)
1110 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1112 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1113 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1115 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1117 txq->done_pkts_coal = value;
1120 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1121 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1122 u32 phys_addr, u32 cookie)
1124 rx_desc->buf_cookie = cookie;
1125 rx_desc->buf_phys_addr = phys_addr;
1128 /* Decrement sent descriptors counter */
1129 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1130 struct mvneta_tx_queue *txq,
1135 /* Only 255 TX descriptors can be updated at once */
1136 while (sent_desc > 0xff) {
1137 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1138 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1139 sent_desc = sent_desc - 0xff;
1142 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1143 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1146 /* Get number of TX descriptors already sent by HW */
1147 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1148 struct mvneta_tx_queue *txq)
1153 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1154 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1155 MVNETA_TXQ_SENT_DESC_SHIFT;
1160 /* Get number of sent descriptors and decrement counter.
1161 * The number of sent descriptors is returned.
1163 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1164 struct mvneta_tx_queue *txq)
1168 /* Get number of sent descriptors */
1169 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1171 /* Decrement sent descriptors counter */
1173 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1178 /* Set TXQ descriptors fields relevant for CSUM calculation */
1179 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1180 int ip_hdr_len, int l4_proto)
1184 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1185 * G_L4_chk, L4_type; required only for checksum
1188 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1189 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1191 if (l3_proto == swab16(ETH_P_IP))
1192 command |= MVNETA_TXD_IP_CSUM;
1194 command |= MVNETA_TX_L3_IP6;
1196 if (l4_proto == IPPROTO_TCP)
1197 command |= MVNETA_TX_L4_CSUM_FULL;
1198 else if (l4_proto == IPPROTO_UDP)
1199 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1201 command |= MVNETA_TX_L4_CSUM_NOT;
1207 /* Display more error info */
1208 static void mvneta_rx_error(struct mvneta_port *pp,
1209 struct mvneta_rx_desc *rx_desc)
1211 u32 status = rx_desc->status;
1213 if (!mvneta_rxq_desc_is_first_last(status)) {
1215 "bad rx status %08x (buffer oversize), size=%d\n",
1216 status, rx_desc->data_size);
1220 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1221 case MVNETA_RXD_ERR_CRC:
1222 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1223 status, rx_desc->data_size);
1225 case MVNETA_RXD_ERR_OVERRUN:
1226 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1227 status, rx_desc->data_size);
1229 case MVNETA_RXD_ERR_LEN:
1230 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1231 status, rx_desc->data_size);
1233 case MVNETA_RXD_ERR_RESOURCE:
1234 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1235 status, rx_desc->data_size);
1240 /* Handle RX checksum offload based on the descriptor's status */
1241 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1242 struct sk_buff *skb)
1244 if ((status & MVNETA_RXD_L3_IP4) &&
1245 (status & MVNETA_RXD_L4_CSUM_OK)) {
1247 skb->ip_summed = CHECKSUM_UNNECESSARY;
1251 skb->ip_summed = CHECKSUM_NONE;
1254 /* Return tx queue pointer (find last set bit) according to <cause> returned
1255 * form tx_done reg. <cause> must not be null. The return value is always a
1256 * valid queue for matching the first one found in <cause>.
1258 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1261 int queue = fls(cause) - 1;
1263 return &pp->txqs[queue];
1266 /* Free tx queue skbuffs */
1267 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1268 struct mvneta_tx_queue *txq, int num)
1272 for (i = 0; i < num; i++) {
1273 struct mvneta_tx_desc *tx_desc = txq->descs +
1275 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1277 mvneta_txq_inc_get(txq);
1282 dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr,
1283 tx_desc->data_size, DMA_TO_DEVICE);
1284 dev_kfree_skb_any(skb);
1288 /* Handle end of transmission */
1289 static void mvneta_txq_done(struct mvneta_port *pp,
1290 struct mvneta_tx_queue *txq)
1292 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1295 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1299 mvneta_txq_bufs_free(pp, txq, tx_done);
1301 txq->count -= tx_done;
1303 if (netif_tx_queue_stopped(nq)) {
1304 if (txq->size - txq->count >= MAX_SKB_FRAGS + 1)
1305 netif_tx_wake_queue(nq);
1309 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1311 if (likely(pp->frag_size <= PAGE_SIZE))
1312 return netdev_alloc_frag(pp->frag_size);
1314 return kmalloc(pp->frag_size, GFP_ATOMIC);
1317 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1319 if (likely(pp->frag_size <= PAGE_SIZE))
1320 put_page(virt_to_head_page(data));
1325 /* Refill processing */
1326 static int mvneta_rx_refill(struct mvneta_port *pp,
1327 struct mvneta_rx_desc *rx_desc)
1330 dma_addr_t phys_addr;
1333 data = mvneta_frag_alloc(pp);
1337 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1338 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1340 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1341 mvneta_frag_free(pp, data);
1345 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1349 /* Handle tx checksum */
1350 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1352 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1356 if (skb->protocol == htons(ETH_P_IP)) {
1357 struct iphdr *ip4h = ip_hdr(skb);
1359 /* Calculate IPv4 checksum and L4 checksum */
1360 ip_hdr_len = ip4h->ihl;
1361 l4_proto = ip4h->protocol;
1362 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1363 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1365 /* Read l4_protocol from one of IPv6 extra headers */
1366 if (skb_network_header_len(skb) > 0)
1367 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1368 l4_proto = ip6h->nexthdr;
1370 return MVNETA_TX_L4_CSUM_NOT;
1372 return mvneta_txq_desc_csum(skb_network_offset(skb),
1373 skb->protocol, ip_hdr_len, l4_proto);
1376 return MVNETA_TX_L4_CSUM_NOT;
1379 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1382 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1385 int queue = fls(cause >> 8) - 1;
1387 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1390 /* Drop packets received by the RXQ and free buffers */
1391 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1392 struct mvneta_rx_queue *rxq)
1396 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1397 for (i = 0; i < rxq->size; i++) {
1398 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1399 void *data = (void *)rx_desc->buf_cookie;
1401 mvneta_frag_free(pp, data);
1402 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1403 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1407 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1410 /* Main rx processing */
1411 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1412 struct mvneta_rx_queue *rxq)
1414 struct net_device *dev = pp->dev;
1415 int rx_done, rx_filled;
1419 /* Get number of received packets */
1420 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1422 if (rx_todo > rx_done)
1428 /* Fairness NAPI loop */
1429 while (rx_done < rx_todo) {
1430 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1431 struct sk_buff *skb;
1432 unsigned char *data;
1438 rx_status = rx_desc->status;
1439 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1440 data = (unsigned char *)rx_desc->buf_cookie;
1442 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1443 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1445 dev->stats.rx_errors++;
1446 mvneta_rx_error(pp, rx_desc);
1447 /* leave the descriptor untouched */
1451 if (rx_bytes <= rx_copybreak) {
1452 /* better copy a small frame and not unmap the DMA region */
1453 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1455 goto err_drop_frame;
1457 dma_sync_single_range_for_cpu(dev->dev.parent,
1458 rx_desc->buf_phys_addr,
1459 MVNETA_MH_SIZE + NET_SKB_PAD,
1462 memcpy(skb_put(skb, rx_bytes),
1463 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1466 skb->protocol = eth_type_trans(skb, dev);
1467 mvneta_rx_csum(pp, rx_status, skb);
1468 napi_gro_receive(&pp->napi, skb);
1471 rcvd_bytes += rx_bytes;
1473 /* leave the descriptor and buffer untouched */
1477 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1479 goto err_drop_frame;
1481 dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr,
1482 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1485 rcvd_bytes += rx_bytes;
1487 /* Linux processing */
1488 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1489 skb_put(skb, rx_bytes);
1491 skb->protocol = eth_type_trans(skb, dev);
1493 mvneta_rx_csum(pp, rx_status, skb);
1495 napi_gro_receive(&pp->napi, skb);
1497 /* Refill processing */
1498 err = mvneta_rx_refill(pp, rx_desc);
1500 netdev_err(dev, "Linux processing - Can't refill\n");
1507 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1509 u64_stats_update_begin(&stats->syncp);
1510 stats->rx_packets += rcvd_pkts;
1511 stats->rx_bytes += rcvd_bytes;
1512 u64_stats_update_end(&stats->syncp);
1515 /* Update rxq management counters */
1516 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1521 /* Handle tx fragmentation processing */
1522 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1523 struct mvneta_tx_queue *txq)
1525 struct mvneta_tx_desc *tx_desc;
1528 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1529 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1530 void *addr = page_address(frag->page.p) + frag->page_offset;
1532 tx_desc = mvneta_txq_next_desc_get(txq);
1533 tx_desc->data_size = frag->size;
1535 tx_desc->buf_phys_addr =
1536 dma_map_single(pp->dev->dev.parent, addr,
1537 tx_desc->data_size, DMA_TO_DEVICE);
1539 if (dma_mapping_error(pp->dev->dev.parent,
1540 tx_desc->buf_phys_addr)) {
1541 mvneta_txq_desc_put(txq);
1545 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
1546 /* Last descriptor */
1547 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1549 txq->tx_skb[txq->txq_put_index] = skb;
1551 mvneta_txq_inc_put(txq);
1553 /* Descriptor in the middle: Not First, Not Last */
1554 tx_desc->command = 0;
1556 txq->tx_skb[txq->txq_put_index] = NULL;
1557 mvneta_txq_inc_put(txq);
1564 /* Release all descriptors that were used to map fragments of
1565 * this packet, as well as the corresponding DMA mappings
1567 for (i = i - 1; i >= 0; i--) {
1568 tx_desc = txq->descs + i;
1569 dma_unmap_single(pp->dev->dev.parent,
1570 tx_desc->buf_phys_addr,
1573 mvneta_txq_desc_put(txq);
1579 /* Main tx processing */
1580 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1582 struct mvneta_port *pp = netdev_priv(dev);
1583 u16 txq_id = skb_get_queue_mapping(skb);
1584 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1585 struct mvneta_tx_desc *tx_desc;
1586 struct netdev_queue *nq;
1590 if (!netif_running(dev))
1593 frags = skb_shinfo(skb)->nr_frags + 1;
1594 nq = netdev_get_tx_queue(dev, txq_id);
1596 /* Get a descriptor for the first part of the packet */
1597 tx_desc = mvneta_txq_next_desc_get(txq);
1599 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1601 tx_desc->data_size = skb_headlen(skb);
1603 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1606 if (unlikely(dma_mapping_error(dev->dev.parent,
1607 tx_desc->buf_phys_addr))) {
1608 mvneta_txq_desc_put(txq);
1614 /* First and Last descriptor */
1615 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1616 tx_desc->command = tx_cmd;
1617 txq->tx_skb[txq->txq_put_index] = skb;
1618 mvneta_txq_inc_put(txq);
1620 /* First but not Last */
1621 tx_cmd |= MVNETA_TXD_F_DESC;
1622 txq->tx_skb[txq->txq_put_index] = NULL;
1623 mvneta_txq_inc_put(txq);
1624 tx_desc->command = tx_cmd;
1625 /* Continue with other skb fragments */
1626 if (mvneta_tx_frag_process(pp, skb, txq)) {
1627 dma_unmap_single(dev->dev.parent,
1628 tx_desc->buf_phys_addr,
1631 mvneta_txq_desc_put(txq);
1637 txq->count += frags;
1638 mvneta_txq_pend_desc_add(pp, txq, frags);
1640 if (txq->size - txq->count < MAX_SKB_FRAGS + 1)
1641 netif_tx_stop_queue(nq);
1645 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1647 u64_stats_update_begin(&stats->syncp);
1648 stats->tx_packets++;
1649 stats->tx_bytes += skb->len;
1650 u64_stats_update_end(&stats->syncp);
1652 dev->stats.tx_dropped++;
1653 dev_kfree_skb_any(skb);
1656 return NETDEV_TX_OK;
1660 /* Free tx resources, when resetting a port */
1661 static void mvneta_txq_done_force(struct mvneta_port *pp,
1662 struct mvneta_tx_queue *txq)
1665 int tx_done = txq->count;
1667 mvneta_txq_bufs_free(pp, txq, tx_done);
1671 txq->txq_put_index = 0;
1672 txq->txq_get_index = 0;
1675 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1676 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1678 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1680 struct mvneta_tx_queue *txq;
1681 struct netdev_queue *nq;
1683 while (cause_tx_done) {
1684 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1686 nq = netdev_get_tx_queue(pp->dev, txq->id);
1687 __netif_tx_lock(nq, smp_processor_id());
1690 mvneta_txq_done(pp, txq);
1692 __netif_tx_unlock(nq);
1693 cause_tx_done &= ~((1 << txq->id));
1697 /* Compute crc8 of the specified address, using a unique algorithm ,
1698 * according to hw spec, different than generic crc8 algorithm
1700 static int mvneta_addr_crc(unsigned char *addr)
1705 for (i = 0; i < ETH_ALEN; i++) {
1708 crc = (crc ^ addr[i]) << 8;
1709 for (j = 7; j >= 0; j--) {
1710 if (crc & (0x100 << j))
1718 /* This method controls the net device special MAC multicast support.
1719 * The Special Multicast Table for MAC addresses supports MAC of the form
1720 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1721 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1722 * Table entries in the DA-Filter table. This method set the Special
1723 * Multicast Table appropriate entry.
1725 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1726 unsigned char last_byte,
1729 unsigned int smc_table_reg;
1730 unsigned int tbl_offset;
1731 unsigned int reg_offset;
1733 /* Register offset from SMC table base */
1734 tbl_offset = (last_byte / 4);
1735 /* Entry offset within the above reg */
1736 reg_offset = last_byte % 4;
1738 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1742 smc_table_reg &= ~(0xff << (8 * reg_offset));
1744 smc_table_reg &= ~(0xff << (8 * reg_offset));
1745 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1748 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1752 /* This method controls the network device Other MAC multicast support.
1753 * The Other Multicast Table is used for multicast of another type.
1754 * A CRC-8 is used as an index to the Other Multicast Table entries
1755 * in the DA-Filter table.
1756 * The method gets the CRC-8 value from the calling routine and
1757 * sets the Other Multicast Table appropriate entry according to the
1760 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1764 unsigned int omc_table_reg;
1765 unsigned int tbl_offset;
1766 unsigned int reg_offset;
1768 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1769 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1771 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1774 /* Clear accepts frame bit at specified Other DA table entry */
1775 omc_table_reg &= ~(0xff << (8 * reg_offset));
1777 omc_table_reg &= ~(0xff << (8 * reg_offset));
1778 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1781 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1784 /* The network device supports multicast using two tables:
1785 * 1) Special Multicast Table for MAC addresses of the form
1786 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1787 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1788 * Table entries in the DA-Filter table.
1789 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1790 * is used as an index to the Other Multicast Table entries in the
1793 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1796 unsigned char crc_result = 0;
1798 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1799 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1803 crc_result = mvneta_addr_crc(p_addr);
1805 if (pp->mcast_count[crc_result] == 0) {
1806 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1811 pp->mcast_count[crc_result]--;
1812 if (pp->mcast_count[crc_result] != 0) {
1813 netdev_info(pp->dev,
1814 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1815 pp->mcast_count[crc_result], crc_result);
1819 pp->mcast_count[crc_result]++;
1821 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1826 /* Configure Fitering mode of Ethernet port */
1827 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1830 u32 port_cfg_reg, val;
1832 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1834 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
1836 /* Set / Clear UPM bit in port configuration register */
1838 /* Accept all Unicast addresses */
1839 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
1840 val |= MVNETA_FORCE_UNI;
1841 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
1842 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
1844 /* Reject all Unicast addresses */
1845 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
1846 val &= ~MVNETA_FORCE_UNI;
1849 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
1850 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
1853 /* register unicast and multicast addresses */
1854 static void mvneta_set_rx_mode(struct net_device *dev)
1856 struct mvneta_port *pp = netdev_priv(dev);
1857 struct netdev_hw_addr *ha;
1859 if (dev->flags & IFF_PROMISC) {
1860 /* Accept all: Multicast + Unicast */
1861 mvneta_rx_unicast_promisc_set(pp, 1);
1862 mvneta_set_ucast_table(pp, rxq_def);
1863 mvneta_set_special_mcast_table(pp, rxq_def);
1864 mvneta_set_other_mcast_table(pp, rxq_def);
1866 /* Accept single Unicast */
1867 mvneta_rx_unicast_promisc_set(pp, 0);
1868 mvneta_set_ucast_table(pp, -1);
1869 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
1871 if (dev->flags & IFF_ALLMULTI) {
1872 /* Accept all multicast */
1873 mvneta_set_special_mcast_table(pp, rxq_def);
1874 mvneta_set_other_mcast_table(pp, rxq_def);
1876 /* Accept only initialized multicast */
1877 mvneta_set_special_mcast_table(pp, -1);
1878 mvneta_set_other_mcast_table(pp, -1);
1880 if (!netdev_mc_empty(dev)) {
1881 netdev_for_each_mc_addr(ha, dev) {
1882 mvneta_mcast_addr_set(pp, ha->addr,
1890 /* Interrupt handling - the callback for request_irq() */
1891 static irqreturn_t mvneta_isr(int irq, void *dev_id)
1893 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
1895 /* Mask all interrupts */
1896 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
1898 napi_schedule(&pp->napi);
1904 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
1905 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
1906 * Bits 8 -15 of the cause Rx Tx register indicate that are received
1907 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
1908 * Each CPU has its own causeRxTx register
1910 static int mvneta_poll(struct napi_struct *napi, int budget)
1914 unsigned long flags;
1915 struct mvneta_port *pp = netdev_priv(napi->dev);
1917 if (!netif_running(pp->dev)) {
1918 napi_complete(napi);
1922 /* Read cause register */
1923 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) &
1924 (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
1926 /* Release Tx descriptors */
1927 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
1928 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
1929 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
1932 /* For the case where the last mvneta_poll did not process all
1935 cause_rx_tx |= pp->cause_rx_tx;
1936 if (rxq_number > 1) {
1937 while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) {
1939 struct mvneta_rx_queue *rxq;
1940 /* get rx queue number from cause_rx_tx */
1941 rxq = mvneta_rx_policy(pp, cause_rx_tx);
1945 /* process the packet in that rx queue */
1946 count = mvneta_rx(pp, budget, rxq);
1950 /* set off the rx bit of the
1951 * corresponding bit in the cause rx
1952 * tx register, so that next iteration
1953 * will find the next rx queue where
1954 * packets are received on
1956 cause_rx_tx &= ~((1 << rxq->id) << 8);
1960 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
1966 napi_complete(napi);
1967 local_irq_save(flags);
1968 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
1969 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
1970 local_irq_restore(flags);
1973 pp->cause_rx_tx = cause_rx_tx;
1977 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
1978 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
1983 for (i = 0; i < num; i++) {
1984 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
1985 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
1986 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
1987 __func__, rxq->id, i, num);
1992 /* Add this number of RX descriptors as non occupied (ready to
1995 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2000 /* Free all packets pending transmit from all TXQs and reset TX port */
2001 static void mvneta_tx_reset(struct mvneta_port *pp)
2005 /* free the skb's in the hal tx ring */
2006 for (queue = 0; queue < txq_number; queue++)
2007 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2009 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2010 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2013 static void mvneta_rx_reset(struct mvneta_port *pp)
2015 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2016 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2019 /* Rx/Tx queue initialization/cleanup methods */
2021 /* Create a specified RX queue */
2022 static int mvneta_rxq_init(struct mvneta_port *pp,
2023 struct mvneta_rx_queue *rxq)
2026 rxq->size = pp->rx_ring_size;
2028 /* Allocate memory for RX descriptors */
2029 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2030 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2031 &rxq->descs_phys, GFP_KERNEL);
2032 if (rxq->descs == NULL)
2035 BUG_ON(rxq->descs !=
2036 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2038 rxq->last_desc = rxq->size - 1;
2040 /* Set Rx descriptors queue starting address */
2041 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2042 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2045 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2047 /* Set coalescing pkts and time */
2048 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2049 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2051 /* Fill RXQ with buffers from RX pool */
2052 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2053 mvneta_rxq_bm_disable(pp, rxq);
2054 mvneta_rxq_fill(pp, rxq, rxq->size);
2059 /* Cleanup Rx queue */
2060 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2061 struct mvneta_rx_queue *rxq)
2063 mvneta_rxq_drop_pkts(pp, rxq);
2066 dma_free_coherent(pp->dev->dev.parent,
2067 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2073 rxq->next_desc_to_proc = 0;
2074 rxq->descs_phys = 0;
2077 /* Create and initialize a tx queue */
2078 static int mvneta_txq_init(struct mvneta_port *pp,
2079 struct mvneta_tx_queue *txq)
2081 txq->size = pp->tx_ring_size;
2083 /* Allocate memory for TX descriptors */
2084 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2085 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2086 &txq->descs_phys, GFP_KERNEL);
2087 if (txq->descs == NULL)
2090 /* Make sure descriptor address is cache line size aligned */
2091 BUG_ON(txq->descs !=
2092 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2094 txq->last_desc = txq->size - 1;
2096 /* Set maximum bandwidth for enabled TXQs */
2097 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2098 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2100 /* Set Tx descriptors queue starting address */
2101 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2102 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2104 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2105 if (txq->tx_skb == NULL) {
2106 dma_free_coherent(pp->dev->dev.parent,
2107 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2108 txq->descs, txq->descs_phys);
2111 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2116 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2117 static void mvneta_txq_deinit(struct mvneta_port *pp,
2118 struct mvneta_tx_queue *txq)
2123 dma_free_coherent(pp->dev->dev.parent,
2124 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2125 txq->descs, txq->descs_phys);
2129 txq->next_desc_to_proc = 0;
2130 txq->descs_phys = 0;
2132 /* Set minimum bandwidth for disabled TXQs */
2133 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2134 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2136 /* Set Tx descriptors queue starting address and size */
2137 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2138 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2141 /* Cleanup all Tx queues */
2142 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2146 for (queue = 0; queue < txq_number; queue++)
2147 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2150 /* Cleanup all Rx queues */
2151 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2155 for (queue = 0; queue < rxq_number; queue++)
2156 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2160 /* Init all Rx queues */
2161 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2165 for (queue = 0; queue < rxq_number; queue++) {
2166 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2168 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2170 mvneta_cleanup_rxqs(pp);
2178 /* Init all tx queues */
2179 static int mvneta_setup_txqs(struct mvneta_port *pp)
2183 for (queue = 0; queue < txq_number; queue++) {
2184 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2186 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2188 mvneta_cleanup_txqs(pp);
2196 static void mvneta_start_dev(struct mvneta_port *pp)
2198 mvneta_max_rx_size_set(pp, pp->pkt_size);
2199 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2201 /* start the Rx/Tx activity */
2202 mvneta_port_enable(pp);
2204 /* Enable polling on the port */
2205 napi_enable(&pp->napi);
2207 /* Unmask interrupts */
2208 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2209 MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number));
2211 phy_start(pp->phy_dev);
2212 netif_tx_start_all_queues(pp->dev);
2215 static void mvneta_stop_dev(struct mvneta_port *pp)
2217 phy_stop(pp->phy_dev);
2219 napi_disable(&pp->napi);
2221 netif_carrier_off(pp->dev);
2223 mvneta_port_down(pp);
2224 netif_tx_stop_all_queues(pp->dev);
2226 /* Stop the port activity */
2227 mvneta_port_disable(pp);
2229 /* Clear all ethernet port interrupts */
2230 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2231 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2233 /* Mask all ethernet port interrupts */
2234 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2235 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2236 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2238 mvneta_tx_reset(pp);
2239 mvneta_rx_reset(pp);
2242 /* Return positive if MTU is valid */
2243 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2246 netdev_err(dev, "cannot change mtu to less than 68\n");
2250 /* 9676 == 9700 - 20 and rounding to 8 */
2252 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2256 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2257 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2258 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2259 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2265 /* Change the device mtu */
2266 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2268 struct mvneta_port *pp = netdev_priv(dev);
2271 mtu = mvneta_check_mtu_valid(dev, mtu);
2277 if (!netif_running(dev))
2280 /* The interface is running, so we have to force a
2281 * reallocation of the RXQs
2283 mvneta_stop_dev(pp);
2285 mvneta_cleanup_txqs(pp);
2286 mvneta_cleanup_rxqs(pp);
2288 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2289 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2290 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2292 ret = mvneta_setup_rxqs(pp);
2294 netdev_err(pp->dev, "unable to setup rxqs after MTU change\n");
2298 mvneta_setup_txqs(pp);
2300 mvneta_start_dev(pp);
2306 /* Get mac address */
2307 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2309 u32 mac_addr_l, mac_addr_h;
2311 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2312 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2313 addr[0] = (mac_addr_h >> 24) & 0xFF;
2314 addr[1] = (mac_addr_h >> 16) & 0xFF;
2315 addr[2] = (mac_addr_h >> 8) & 0xFF;
2316 addr[3] = mac_addr_h & 0xFF;
2317 addr[4] = (mac_addr_l >> 8) & 0xFF;
2318 addr[5] = mac_addr_l & 0xFF;
2321 /* Handle setting mac address */
2322 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2324 struct mvneta_port *pp = netdev_priv(dev);
2328 if (netif_running(dev))
2331 /* Remove previous address table entry */
2332 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2334 /* Set new addr in hw */
2335 mvneta_mac_addr_set(pp, mac, rxq_def);
2337 /* Set addr in the device */
2338 for (i = 0; i < ETH_ALEN; i++)
2339 dev->dev_addr[i] = mac[i];
2344 static void mvneta_adjust_link(struct net_device *ndev)
2346 struct mvneta_port *pp = netdev_priv(ndev);
2347 struct phy_device *phydev = pp->phy_dev;
2348 int status_change = 0;
2351 if ((pp->speed != phydev->speed) ||
2352 (pp->duplex != phydev->duplex)) {
2355 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2356 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2357 MVNETA_GMAC_CONFIG_GMII_SPEED |
2358 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
2359 MVNETA_GMAC_AN_SPEED_EN |
2360 MVNETA_GMAC_AN_DUPLEX_EN);
2363 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2365 if (phydev->speed == SPEED_1000)
2366 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2368 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2370 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2372 pp->duplex = phydev->duplex;
2373 pp->speed = phydev->speed;
2377 if (phydev->link != pp->link) {
2378 if (!phydev->link) {
2383 pp->link = phydev->link;
2387 if (status_change) {
2389 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2390 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
2391 MVNETA_GMAC_FORCE_LINK_DOWN);
2392 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2394 netdev_info(pp->dev, "link up\n");
2396 mvneta_port_down(pp);
2397 netdev_info(pp->dev, "link down\n");
2402 static int mvneta_mdio_probe(struct mvneta_port *pp)
2404 struct phy_device *phy_dev;
2406 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2409 netdev_err(pp->dev, "could not find the PHY\n");
2413 phy_dev->supported &= PHY_GBIT_FEATURES;
2414 phy_dev->advertising = phy_dev->supported;
2416 pp->phy_dev = phy_dev;
2424 static void mvneta_mdio_remove(struct mvneta_port *pp)
2426 phy_disconnect(pp->phy_dev);
2430 static int mvneta_open(struct net_device *dev)
2432 struct mvneta_port *pp = netdev_priv(dev);
2435 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2437 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2438 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2439 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2441 ret = mvneta_setup_rxqs(pp);
2445 ret = mvneta_setup_txqs(pp);
2447 goto err_cleanup_rxqs;
2449 /* Connect to port interrupt line */
2450 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2451 MVNETA_DRIVER_NAME, pp);
2453 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2454 goto err_cleanup_txqs;
2457 /* In default link is down */
2458 netif_carrier_off(pp->dev);
2460 ret = mvneta_mdio_probe(pp);
2462 netdev_err(dev, "cannot probe MDIO bus\n");
2466 mvneta_start_dev(pp);
2471 free_irq(pp->dev->irq, pp);
2473 mvneta_cleanup_txqs(pp);
2475 mvneta_cleanup_rxqs(pp);
2479 /* Stop the port, free port interrupt line */
2480 static int mvneta_stop(struct net_device *dev)
2482 struct mvneta_port *pp = netdev_priv(dev);
2484 mvneta_stop_dev(pp);
2485 mvneta_mdio_remove(pp);
2486 free_irq(dev->irq, pp);
2487 mvneta_cleanup_rxqs(pp);
2488 mvneta_cleanup_txqs(pp);
2493 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2495 struct mvneta_port *pp = netdev_priv(dev);
2501 ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2503 mvneta_adjust_link(dev);
2508 /* Ethtool methods */
2510 /* Get settings (phy address, speed) for ethtools */
2511 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2513 struct mvneta_port *pp = netdev_priv(dev);
2518 return phy_ethtool_gset(pp->phy_dev, cmd);
2521 /* Set settings (phy address, speed) for ethtools */
2522 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2524 struct mvneta_port *pp = netdev_priv(dev);
2529 return phy_ethtool_sset(pp->phy_dev, cmd);
2532 /* Set interrupt coalescing for ethtools */
2533 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2534 struct ethtool_coalesce *c)
2536 struct mvneta_port *pp = netdev_priv(dev);
2539 for (queue = 0; queue < rxq_number; queue++) {
2540 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2541 rxq->time_coal = c->rx_coalesce_usecs;
2542 rxq->pkts_coal = c->rx_max_coalesced_frames;
2543 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2544 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2547 for (queue = 0; queue < txq_number; queue++) {
2548 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2549 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2550 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2556 /* get coalescing for ethtools */
2557 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2558 struct ethtool_coalesce *c)
2560 struct mvneta_port *pp = netdev_priv(dev);
2562 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2563 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2565 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2570 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2571 struct ethtool_drvinfo *drvinfo)
2573 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2574 sizeof(drvinfo->driver));
2575 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2576 sizeof(drvinfo->version));
2577 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2578 sizeof(drvinfo->bus_info));
2582 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2583 struct ethtool_ringparam *ring)
2585 struct mvneta_port *pp = netdev_priv(netdev);
2587 ring->rx_max_pending = MVNETA_MAX_RXD;
2588 ring->tx_max_pending = MVNETA_MAX_TXD;
2589 ring->rx_pending = pp->rx_ring_size;
2590 ring->tx_pending = pp->tx_ring_size;
2593 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2594 struct ethtool_ringparam *ring)
2596 struct mvneta_port *pp = netdev_priv(dev);
2598 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2600 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2601 ring->rx_pending : MVNETA_MAX_RXD;
2602 pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ?
2603 ring->tx_pending : MVNETA_MAX_TXD;
2605 if (netif_running(dev)) {
2607 if (mvneta_open(dev)) {
2609 "error on opening device after ring param change\n");
2617 static const struct net_device_ops mvneta_netdev_ops = {
2618 .ndo_open = mvneta_open,
2619 .ndo_stop = mvneta_stop,
2620 .ndo_start_xmit = mvneta_tx,
2621 .ndo_set_rx_mode = mvneta_set_rx_mode,
2622 .ndo_set_mac_address = mvneta_set_mac_addr,
2623 .ndo_change_mtu = mvneta_change_mtu,
2624 .ndo_get_stats64 = mvneta_get_stats64,
2625 .ndo_do_ioctl = mvneta_ioctl,
2628 const struct ethtool_ops mvneta_eth_tool_ops = {
2629 .get_link = ethtool_op_get_link,
2630 .get_settings = mvneta_ethtool_get_settings,
2631 .set_settings = mvneta_ethtool_set_settings,
2632 .set_coalesce = mvneta_ethtool_set_coalesce,
2633 .get_coalesce = mvneta_ethtool_get_coalesce,
2634 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2635 .get_ringparam = mvneta_ethtool_get_ringparam,
2636 .set_ringparam = mvneta_ethtool_set_ringparam,
2640 static int mvneta_init(struct mvneta_port *pp, int phy_addr)
2645 mvneta_port_disable(pp);
2647 /* Set port default values */
2648 mvneta_defaults_set(pp);
2650 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
2655 /* Initialize TX descriptor rings */
2656 for (queue = 0; queue < txq_number; queue++) {
2657 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2659 txq->size = pp->tx_ring_size;
2660 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2663 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
2670 /* Create Rx descriptor rings */
2671 for (queue = 0; queue < rxq_number; queue++) {
2672 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2674 rxq->size = pp->rx_ring_size;
2675 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2676 rxq->time_coal = MVNETA_RX_COAL_USEC;
2682 static void mvneta_deinit(struct mvneta_port *pp)
2688 /* platform glue : initialize decoding windows */
2689 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2690 const struct mbus_dram_target_info *dram)
2696 for (i = 0; i < 6; i++) {
2697 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2698 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2701 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2707 for (i = 0; i < dram->num_cs; i++) {
2708 const struct mbus_dram_window *cs = dram->cs + i;
2709 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2710 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2712 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2713 (cs->size - 1) & 0xffff0000);
2715 win_enable &= ~(1 << i);
2716 win_protect |= 3 << (2 * i);
2719 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2722 /* Power up the port */
2723 static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2727 /* MAC Cause register should be cleared */
2728 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2730 if (phy_mode == PHY_INTERFACE_MODE_SGMII)
2731 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
2733 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_RGMII_SERDES_PROTO);
2735 val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2737 val |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2739 /* Cancel Port Reset */
2740 val &= ~MVNETA_GMAC2_PORT_RESET;
2741 mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
2743 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2744 MVNETA_GMAC2_PORT_RESET) != 0)
2748 /* Device initialization routine */
2749 static int mvneta_probe(struct platform_device *pdev)
2751 const struct mbus_dram_target_info *dram_target_info;
2752 struct device_node *dn = pdev->dev.of_node;
2753 struct device_node *phy_node;
2755 struct mvneta_port *pp;
2756 struct net_device *dev;
2757 const char *dt_mac_addr;
2758 char hw_mac_addr[ETH_ALEN];
2759 const char *mac_from;
2764 /* Our multiqueue support is not complete, so for now, only
2765 * allow the usage of the first RX queue
2768 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
2772 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
2776 dev->irq = irq_of_parse_and_map(dn, 0);
2777 if (dev->irq == 0) {
2779 goto err_free_netdev;
2782 phy_node = of_parse_phandle(dn, "phy", 0);
2784 dev_err(&pdev->dev, "no associated PHY\n");
2789 phy_mode = of_get_phy_mode(dn);
2791 dev_err(&pdev->dev, "incorrect phy-mode\n");
2796 dev->tx_queue_len = MVNETA_MAX_TXD;
2797 dev->watchdog_timeo = 5 * HZ;
2798 dev->netdev_ops = &mvneta_netdev_ops;
2800 SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops);
2802 pp = netdev_priv(dev);
2804 pp->weight = MVNETA_RX_POLL_WEIGHT;
2805 pp->phy_node = phy_node;
2806 pp->phy_interface = phy_mode;
2808 pp->clk = devm_clk_get(&pdev->dev, NULL);
2809 if (IS_ERR(pp->clk)) {
2810 err = PTR_ERR(pp->clk);
2814 clk_prepare_enable(pp->clk);
2816 pp->base = of_iomap(dn, 0);
2817 if (pp->base == NULL) {
2822 /* Alloc per-cpu stats */
2823 pp->stats = alloc_percpu(struct mvneta_pcpu_stats);
2829 for_each_possible_cpu(cpu) {
2830 struct mvneta_pcpu_stats *stats;
2831 stats = per_cpu_ptr(pp->stats, cpu);
2832 u64_stats_init(&stats->syncp);
2835 dt_mac_addr = of_get_mac_address(dn);
2837 mac_from = "device tree";
2838 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
2840 mvneta_get_mac_addr(pp, hw_mac_addr);
2841 if (is_valid_ether_addr(hw_mac_addr)) {
2842 mac_from = "hardware";
2843 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
2845 mac_from = "random";
2846 eth_hw_addr_random(dev);
2850 pp->tx_ring_size = MVNETA_MAX_TXD;
2851 pp->rx_ring_size = MVNETA_MAX_RXD;
2854 SET_NETDEV_DEV(dev, &pdev->dev);
2856 err = mvneta_init(pp, phy_addr);
2858 dev_err(&pdev->dev, "can't init eth hal\n");
2859 goto err_free_stats;
2861 mvneta_port_power_up(pp, phy_mode);
2863 dram_target_info = mv_mbus_dram_info();
2864 if (dram_target_info)
2865 mvneta_conf_mbus_windows(pp, dram_target_info);
2867 netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight);
2869 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2870 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2871 dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2872 dev->priv_flags |= IFF_UNICAST_FLT;
2874 err = register_netdev(dev);
2876 dev_err(&pdev->dev, "failed to register\n");
2880 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
2883 platform_set_drvdata(pdev, pp->dev);
2890 free_percpu(pp->stats);
2894 clk_disable_unprepare(pp->clk);
2896 irq_dispose_mapping(dev->irq);
2902 /* Device removal routine */
2903 static int mvneta_remove(struct platform_device *pdev)
2905 struct net_device *dev = platform_get_drvdata(pdev);
2906 struct mvneta_port *pp = netdev_priv(dev);
2908 unregister_netdev(dev);
2910 clk_disable_unprepare(pp->clk);
2911 free_percpu(pp->stats);
2913 irq_dispose_mapping(dev->irq);
2919 static const struct of_device_id mvneta_match[] = {
2920 { .compatible = "marvell,armada-370-neta" },
2923 MODULE_DEVICE_TABLE(of, mvneta_match);
2925 static struct platform_driver mvneta_driver = {
2926 .probe = mvneta_probe,
2927 .remove = mvneta_remove,
2929 .name = MVNETA_DRIVER_NAME,
2930 .of_match_table = mvneta_match,
2934 module_platform_driver(mvneta_driver);
2936 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
2937 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
2938 MODULE_LICENSE("GPL");
2940 module_param(rxq_number, int, S_IRUGO);
2941 module_param(txq_number, int, S_IRUGO);
2943 module_param(rxq_def, int, S_IRUGO);
2944 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);