Pileus Git - ~andy/linux/blob - drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178
 179 /* ETS defines*/
 180 #define DCBX_INVALID_COS                                        (0xFF)
 181
 182 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 183 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 184 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 186 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 187
 188 #define MAX_PACKET_SIZE                                 (9700)
 189 #define MAX_KR_LINK_RETRY                               4
 190
 191 /**********************************************************/
 192 /*                     INTERFACE                          */
 193 /**********************************************************/
 194
 195 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 196         bnx2x_cl45_write(_bp, _phy, \
 197                 (_phy)->def_md_devad, \
 198                 (_bank + (_addr & 0xf)), \
 199                 _val)
 200
 201 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 202         bnx2x_cl45_read(_bp, _phy, \
 203                 (_phy)->def_md_devad, \
 204                 (_bank + (_addr & 0xf)), \
 205                 _val)
 206
 207 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 208 {
 209         u32 val = REG_RD(bp, reg);
 210
 211         val |= bits;
 212         REG_WR(bp, reg, val);
 213         return val;
 214 }
 215
 216 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 217 {
 218         u32 val = REG_RD(bp, reg);
 219
 220         val &= ~bits;
 221         REG_WR(bp, reg, val);
 222         return val;
 223 }
 224
 225 /*
 226  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 227  *                   or link flap can be avoided.
 228  *
 229  * @params:     link parameters
 230  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 231  *         condition code.
 232  */
 233 static int bnx2x_check_lfa(struct link_params *params)
 234 {
 235         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 236         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 237         u32 saved_val, req_val, eee_status;
 238         struct bnx2x *bp = params->bp;
 239
 240         additional_config =
 241                 REG_RD(bp, params->lfa_base +
 242                            offsetof(struct shmem_lfa, additional_config));
 243
 244         /* NOTE: must be first condition checked -
 245         * to verify DCC bit is cleared in any case!
 246         */
 247         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 248                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 249                 REG_WR(bp, params->lfa_base +
 250                            offsetof(struct shmem_lfa, additional_config),
 251                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 252                 return LFA_DCC_LFA_DISABLED;
 253         }
 254
 255         /* Verify that link is up */
 256         link_status = REG_RD(bp, params->shmem_base +
 257                              offsetof(struct shmem_region,
 258                                       port_mb[params->port].link_status));
 259         if (!(link_status & LINK_STATUS_LINK_UP))
 260                 return LFA_LINK_DOWN;
 261
 262         /* if loaded after BOOT from SAN, don't flap the link in any case and
 263          * rely on link set by preboot driver
 264          */
 265         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 266                 return 0;
 267
 268         /* Verify that loopback mode is not set */
 269         if (params->loopback_mode)
 270                 return LFA_LOOPBACK_ENABLED;
 271
 272         /* Verify that MFW supports LFA */
 273         if (!params->lfa_base)
 274                 return LFA_MFW_IS_TOO_OLD;
 275
 276         if (params->num_phys == 3) {
 277                 cfg_size = 2;
 278                 lfa_mask = 0xffffffff;
 279         } else {
 280                 cfg_size = 1;
 281                 lfa_mask = 0xffff;
 282         }
 283
 284         /* Compare Duplex */
 285         saved_val = REG_RD(bp, params->lfa_base +
 286                            offsetof(struct shmem_lfa, req_duplex));
 287         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 288         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 289                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 290                                (saved_val & lfa_mask), (req_val & lfa_mask));
 291                 return LFA_DUPLEX_MISMATCH;
 292         }
 293         /* Compare Flow Control */
 294         saved_val = REG_RD(bp, params->lfa_base +
 295                            offsetof(struct shmem_lfa, req_flow_ctrl));
 296         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 297         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 298                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 299                                (saved_val & lfa_mask), (req_val & lfa_mask));
 300                 return LFA_FLOW_CTRL_MISMATCH;
 301         }
 302         /* Compare Link Speed */
 303         saved_val = REG_RD(bp, params->lfa_base +
 304                            offsetof(struct shmem_lfa, req_line_speed));
 305         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 306         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 307                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 308                                (saved_val & lfa_mask), (req_val & lfa_mask));
 309                 return LFA_LINK_SPEED_MISMATCH;
 310         }
 311
 312         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 313                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 314                                             offsetof(struct shmem_lfa,
 315                                                      speed_cap_mask[cfg_idx]));
 316
 317                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 318                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 319                                        cur_speed_cap_mask,
 320                                        params->speed_cap_mask[cfg_idx]);
 321                         return LFA_SPEED_CAP_MISMATCH;
 322                 }
 323         }
 324
 325         cur_req_fc_auto_adv =
 326                 REG_RD(bp, params->lfa_base +
 327                        offsetof(struct shmem_lfa, additional_config)) &
 328                 REQ_FC_AUTO_ADV_MASK;
 329
 330         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 331                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 332                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 333                 return LFA_FLOW_CTRL_MISMATCH;
 334         }
 335
 336         eee_status = REG_RD(bp, params->shmem2_base +
 337                             offsetof(struct shmem2_region,
 338                                      eee_status[params->port]));
 339
 340         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 341              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 342             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 343              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 344                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 345                                eee_status);
 346                 return LFA_EEE_MISMATCH;
 347         }
 348
 349         /* LFA conditions are met */
 350         return 0;
 351 }
 352 /******************************************************************/
 353 /*                      EPIO/GPIO section                         */
 354 /******************************************************************/
 355 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 356 {
 357         u32 epio_mask, gp_oenable;
 358         *en = 0;
 359         /* Sanity check */
 360         if (epio_pin > 31) {
 361                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 362                 return;
 363         }
 364
 365         epio_mask = 1 << epio_pin;
 366         /* Set this EPIO to output */
 367         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 368         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 369
 370         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 371 }
 372 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 373 {
 374         u32 epio_mask, gp_output, gp_oenable;
 375
 376         /* Sanity check */
 377         if (epio_pin > 31) {
 378                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 379                 return;
 380         }
 381         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 382         epio_mask = 1 << epio_pin;
 383         /* Set this EPIO to output */
 384         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 385         if (en)
 386                 gp_output |= epio_mask;
 387         else
 388                 gp_output &= ~epio_mask;
 389
 390         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 391
 392         /* Set the value for this EPIO */
 393         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 394         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 395 }
 396
 397 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 398 {
 399         if (pin_cfg == PIN_CFG_NA)
 400                 return;
 401         if (pin_cfg >= PIN_CFG_EPIO0) {
 402                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 403         } else {
 404                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 405                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 406                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 407         }
 408 }
 409
 410 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 411 {
 412         if (pin_cfg == PIN_CFG_NA)
 413                 return -EINVAL;
 414         if (pin_cfg >= PIN_CFG_EPIO0) {
 415                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 416         } else {
 417                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 418                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 419                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 420         }
 421         return 0;
 422
 423 }
 424 /******************************************************************/
 425 /*                              ETS section                       */
 426 /******************************************************************/
 427 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 428 {
 429         /* ETS disabled configuration*/
 430         struct bnx2x *bp = params->bp;
 431
 432         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 433
 434         /* mapping between entry  priority to client number (0,1,2 -debug and
 435          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 436          * 3bits client num.
 437          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 438          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 439          */
 440
 441         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 442         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 443          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 444          * COS0 entry, 4 - COS1 entry.
 445          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 446          * bit4   bit3    bit2   bit1     bit0
 447          * MCP and debug are strict
 448          */
 449
 450         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 451         /* defines which entries (clients) are subjected to WFQ arbitration */
 452         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 453         /* For strict priority entries defines the number of consecutive
 454          * slots for the highest priority.
 455          */
 456         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 457         /* mapping between the CREDIT_WEIGHT registers and actual client
 458          * numbers
 459          */
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 463
 464         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 466         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 467         /* ETS mode disable */
 468         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 469         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 470          * weight for COS0/COS1.
 471          */
 472         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 473         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 474         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 475         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 476         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 477         /* Defines the number of consecutive slots for the strict priority */
 478         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 479 }
 480 /******************************************************************************
 481 * Description:
 482 *       Getting min_w_val will be set according to line speed .
 483 *.
 484 ******************************************************************************/
 485 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 486 {
 487         u32 min_w_val = 0;
 488         /* Calculate min_w_val.*/
 489         if (vars->link_up) {
 490                 if (vars->line_speed == SPEED_20000)
 491                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 492                 else
 493                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 494         } else
 495                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 496         /* If the link isn't up (static configuration for example ) The
 497          * link will be according to 20GBPS.
 498          */
 499         return min_w_val;
 500 }
 501 /******************************************************************************
 502 * Description:
 503 *       Getting credit upper bound form min_w_val.
 504 *.
 505 ******************************************************************************/
 506 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 507 {
 508         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 509                                                 MAX_PACKET_SIZE);
 510         return credit_upper_bound;
 511 }
 512 /******************************************************************************
 513 * Description:
 514 *       Set credit upper bound for NIG.
 515 *.
 516 ******************************************************************************/
 517 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 518         const struct link_params *params,
 519         const u32 min_w_val)
 520 {
 521         struct bnx2x *bp = params->bp;
 522         const u8 port = params->port;
 523         const u32 credit_upper_bound =
 524             bnx2x_ets_get_credit_upper_bound(min_w_val);
 525
 526         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 527                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 528         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 529                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 531                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 532         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 533                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 534         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 535                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 536         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 537                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 538
 539         if (!port) {
 540                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 541                         credit_upper_bound);
 542                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 543                         credit_upper_bound);
 544                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 545                         credit_upper_bound);
 546         }
 547 }
 548 /******************************************************************************
 549 * Description:
 550 *       Will return the NIG ETS registers to init values.Except
 551 *       credit_upper_bound.
 552 *       That isn't used in this configuration (No WFQ is enabled) and will be
 553 *       configured acording to spec
 554 *.
 555 ******************************************************************************/
 556 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 557                                         const struct link_vars *vars)
 558 {
 559         struct bnx2x *bp = params->bp;
 560         const u8 port = params->port;
 561         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 562         /* Mapping between entry  priority to client number (0,1,2 -debug and
 563          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 564          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 565          * reset value or init tool
 566          */
 567         if (port) {
 568                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 570         } else {
 571                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 573         }
 574         /* For strict priority entries defines the number of consecutive
 575          * slots for the highest priority.
 576          */
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 578                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 579         /* Mapping between the CREDIT_WEIGHT registers and actual client
 580          * numbers
 581          */
 582         if (port) {
 583                 /*Port 1 has 6 COS*/
 584                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 586         } else {
 587                 /*Port 0 has 9 COS*/
 588                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 589                        0x43210876);
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 591         }
 592
 593         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 594          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 595          * COS0 entry, 4 - COS1 entry.
 596          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 597          * bit4   bit3    bit2   bit1     bit0
 598          * MCP and debug are strict
 599          */
 600         if (port)
 601                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 602         else
 603                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 604         /* defines which entries (clients) are subjected to WFQ arbitration */
 605         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 606                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 607
 608         /* Please notice the register address are note continuous and a
 609          * for here is note appropriate.In 2 port mode port0 only COS0-5
 610          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 611          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 612          * are never used for WFQ
 613          */
 614         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 615                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 616         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 617                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 618         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 619                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 620         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 621                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 622         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 623                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 624         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 625                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 626         if (!port) {
 627                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 630         }
 631
 632         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 633 }
 634 /******************************************************************************
 635 * Description:
 636 *       Set credit upper bound for PBF.
 637 *.
 638 ******************************************************************************/
 639 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 640         const struct link_params *params,
 641         const u32 min_w_val)
 642 {
 643         struct bnx2x *bp = params->bp;
 644         const u32 credit_upper_bound =
 645             bnx2x_ets_get_credit_upper_bound(min_w_val);
 646         const u8 port = params->port;
 647         u32 base_upper_bound = 0;
 648         u8 max_cos = 0;
 649         u8 i = 0;
 650         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 651          * port mode port1 has COS0-2 that can be used for WFQ.
 652          */
 653         if (!port) {
 654                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 655                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 656         } else {
 657                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 658                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 659         }
 660
 661         for (i = 0; i < max_cos; i++)
 662                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 663 }
 664
 665 /******************************************************************************
 666 * Description:
 667 *       Will return the PBF ETS registers to init values.Except
 668 *       credit_upper_bound.
 669 *       That isn't used in this configuration (No WFQ is enabled) and will be
 670 *       configured acording to spec
 671 *.
 672 ******************************************************************************/
 673 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 674 {
 675         struct bnx2x *bp = params->bp;
 676         const u8 port = params->port;
 677         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 678         u8 i = 0;
 679         u32 base_weight = 0;
 680         u8 max_cos = 0;
 681
 682         /* Mapping between entry  priority to client number 0 - COS0
 683          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 684          * TODO_ETS - Should be done by reset value or init tool
 685          */
 686         if (port)
 687                 /*  0x688 (|011|0 10|00 1|000) */
 688                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 689         else
 690                 /*  (10 1|100 |011|0 10|00 1|000) */
 691                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 692
 693         /* TODO_ETS - Should be done by reset value or init tool */
 694         if (port)
 695                 /* 0x688 (|011|0 10|00 1|000)*/
 696                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 697         else
 698         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 699         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 700
 701         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 702                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 703
 704
 705         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 706                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 707
 708         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 709                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 710         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 711          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 712          */
 713         if (!port) {
 714                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 715                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 716         } else {
 717                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 718                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 719         }
 720
 721         for (i = 0; i < max_cos; i++)
 722                 REG_WR(bp, base_weight + (0x4 * i), 0);
 723
 724         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 725 }
 726 /******************************************************************************
 727 * Description:
 728 *       E3B0 disable will return basicly the values to init values.
 729 *.
 730 ******************************************************************************/
 731 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 732                                    const struct link_vars *vars)
 733 {
 734         struct bnx2x *bp = params->bp;
 735
 736         if (!CHIP_IS_E3B0(bp)) {
 737                 DP(NETIF_MSG_LINK,
 738                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 739                 return -EINVAL;
 740         }
 741
 742         bnx2x_ets_e3b0_nig_disabled(params, vars);
 743
 744         bnx2x_ets_e3b0_pbf_disabled(params);
 745
 746         return 0;
 747 }
 748
 749 /******************************************************************************
 750 * Description:
 751 *       Disable will return basicly the values to init values.
 752 *
 753 ******************************************************************************/
 754 int bnx2x_ets_disabled(struct link_params *params,
 755                       struct link_vars *vars)
 756 {
 757         struct bnx2x *bp = params->bp;
 758         int bnx2x_status = 0;
 759
 760         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 761                 bnx2x_ets_e2e3a0_disabled(params);
 762         else if (CHIP_IS_E3B0(bp))
 763                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 764         else {
 765                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 766                 return -EINVAL;
 767         }
 768
 769         return bnx2x_status;
 770 }
 771
 772 /******************************************************************************
 773 * Description
 774 *       Set the COS mappimg to SP and BW until this point all the COS are not
 775 *       set as SP or BW.
 776 ******************************************************************************/
 777 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 778                                   const struct bnx2x_ets_params *ets_params,
 779                                   const u8 cos_sp_bitmap,
 780                                   const u8 cos_bw_bitmap)
 781 {
 782         struct bnx2x *bp = params->bp;
 783         const u8 port = params->port;
 784         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 785         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 786         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 787         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 788
 789         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 790                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 791
 792         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 793                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 794
 795         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 796                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 797                nig_cli_subject2wfq_bitmap);
 798
 799         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 800                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 801                pbf_cli_subject2wfq_bitmap);
 802
 803         return 0;
 804 }
 805
 806 /******************************************************************************
 807 * Description:
 808 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 809 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 810 ******************************************************************************/
 811 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 812                                      const u8 cos_entry,
 813                                      const u32 min_w_val_nig,
 814                                      const u32 min_w_val_pbf,
 815                                      const u16 total_bw,
 816                                      const u8 bw,
 817                                      const u8 port)
 818 {
 819         u32 nig_reg_adress_crd_weight = 0;
 820         u32 pbf_reg_adress_crd_weight = 0;
 821         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 822         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 823         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 824
 825         switch (cos_entry) {
 826         case 0:
 827             nig_reg_adress_crd_weight =
 828                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 829                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 830              pbf_reg_adress_crd_weight = (port) ?
 831                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 832              break;
 833         case 1:
 834              nig_reg_adress_crd_weight = (port) ?
 835                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 836                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 837              pbf_reg_adress_crd_weight = (port) ?
 838                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 839              break;
 840         case 2:
 841              nig_reg_adress_crd_weight = (port) ?
 842                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 843                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 844
 845                  pbf_reg_adress_crd_weight = (port) ?
 846                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 847              break;
 848         case 3:
 849             if (port)
 850                         return -EINVAL;
 851              nig_reg_adress_crd_weight =
 852                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 853              pbf_reg_adress_crd_weight =
 854                  PBF_REG_COS3_WEIGHT_P0;
 855              break;
 856         case 4:
 857             if (port)
 858                 return -EINVAL;
 859              nig_reg_adress_crd_weight =
 860                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 861              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 862              break;
 863         case 5:
 864             if (port)
 865                 return -EINVAL;
 866              nig_reg_adress_crd_weight =
 867                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 868              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 869              break;
 870         }
 871
 872         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 873
 874         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 875
 876         return 0;
 877 }
 878 /******************************************************************************
 879 * Description:
 880 *       Calculate the total BW.A value of 0 isn't legal.
 881 *
 882 ******************************************************************************/
 883 static int bnx2x_ets_e3b0_get_total_bw(
 884         const struct link_params *params,
 885         struct bnx2x_ets_params *ets_params,
 886         u16 *total_bw)
 887 {
 888         struct bnx2x *bp = params->bp;
 889         u8 cos_idx = 0;
 890         u8 is_bw_cos_exist = 0;
 891
 892         *total_bw = 0 ;
 893         /* Calculate total BW requested */
 894         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 895                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 896                         is_bw_cos_exist = 1;
 897                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 898                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 899                                                    "was set to 0\n");
 900                                 /* This is to prevent a state when ramrods
 901                                  * can't be sent
 902                                  */
 903                                 ets_params->cos[cos_idx].params.bw_params.bw
 904                                          = 1;
 905                         }
 906                         *total_bw +=
 907                                 ets_params->cos[cos_idx].params.bw_params.bw;
 908                 }
 909         }
 910
 911         /* Check total BW is valid */
 912         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 913                 if (*total_bw == 0) {
 914                         DP(NETIF_MSG_LINK,
 915                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 916                         return -EINVAL;
 917                 }
 918                 DP(NETIF_MSG_LINK,
 919                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 920                 /* We can handle a case whre the BW isn't 100 this can happen
 921                  * if the TC are joined.
 922                  */
 923         }
 924         return 0;
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Invalidate all the sp_pri_to_cos.
 930 *
 931 ******************************************************************************/
 932 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 933 {
 934         u8 pri = 0;
 935         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 936                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 937 }
 938 /******************************************************************************
 939 * Description:
 940 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 941 *       according to sp_pri_to_cos.
 942 *
 943 ******************************************************************************/
 944 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 945                                             u8 *sp_pri_to_cos, const u8 pri,
 946                                             const u8 cos_entry)
 947 {
 948         struct bnx2x *bp = params->bp;
 949         const u8 port = params->port;
 950         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 951                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 952
 953         if (pri >= max_num_of_cos) {
 954                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 955                    "parameter Illegal strict priority\n");
 956             return -EINVAL;
 957         }
 958
 959         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 960                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 961                                    "parameter There can't be two COS's with "
 962                                    "the same strict pri\n");
 963                 return -EINVAL;
 964         }
 965
 966         sp_pri_to_cos[pri] = cos_entry;
 967         return 0;
 968
 969 }
 970
 971 /******************************************************************************
 972 * Description:
 973 *       Returns the correct value according to COS and priority in
 974 *       the sp_pri_cli register.
 975 *
 976 ******************************************************************************/
 977 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 978                                          const u8 pri_set,
 979                                          const u8 pri_offset,
 980                                          const u8 entry_size)
 981 {
 982         u64 pri_cli_nig = 0;
 983         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 984                                                     (pri_set + pri_offset));
 985
 986         return pri_cli_nig;
 987 }
 988 /******************************************************************************
 989 * Description:
 990 *       Returns the correct value according to COS and priority in the
 991 *       sp_pri_cli register for NIG.
 992 *
 993 ******************************************************************************/
 994 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 995 {
 996         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 997         const u8 nig_cos_offset = 3;
 998         const u8 nig_pri_offset = 3;
 999
1000         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1001                 nig_pri_offset, 4);
1002
1003 }
1004 /******************************************************************************
1005 * Description:
1006 *       Returns the correct value according to COS and priority in the
1007 *       sp_pri_cli register for PBF.
1008 *
1009 ******************************************************************************/
1010 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1011 {
1012         const u8 pbf_cos_offset = 0;
1013         const u8 pbf_pri_offset = 0;
1014
1015         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1016                 pbf_pri_offset, 3);
1017
1018 }
1019
1020 /******************************************************************************
1021 * Description:
1022 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1023 *       according to sp_pri_to_cos.(which COS has higher priority)
1024 *
1025 ******************************************************************************/
1026 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1027                                              u8 *sp_pri_to_cos)
1028 {
1029         struct bnx2x *bp = params->bp;
1030         u8 i = 0;
1031         const u8 port = params->port;
1032         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1033         u64 pri_cli_nig = 0x210;
1034         u32 pri_cli_pbf = 0x0;
1035         u8 pri_set = 0;
1036         u8 pri_bitmask = 0;
1037         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1038                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1039
1040         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1041
1042         /* Set all the strict priority first */
1043         for (i = 0; i < max_num_of_cos; i++) {
1044                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1045                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1046                                 DP(NETIF_MSG_LINK,
1047                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1048                                            "invalid cos entry\n");
1049                                 return -EINVAL;
1050                         }
1051
1052                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1053                             sp_pri_to_cos[i], pri_set);
1054
1055                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1056                             sp_pri_to_cos[i], pri_set);
1057                         pri_bitmask = 1 << sp_pri_to_cos[i];
1058                         /* COS is used remove it from bitmap.*/
1059                         if (!(pri_bitmask & cos_bit_to_set)) {
1060                                 DP(NETIF_MSG_LINK,
1061                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1062                                         "invalid There can't be two COS's with"
1063                                         " the same strict pri\n");
1064                                 return -EINVAL;
1065                         }
1066                         cos_bit_to_set &= ~pri_bitmask;
1067                         pri_set++;
1068                 }
1069         }
1070
1071         /* Set all the Non strict priority i= COS*/
1072         for (i = 0; i < max_num_of_cos; i++) {
1073                 pri_bitmask = 1 << i;
1074                 /* Check if COS was already used for SP */
1075                 if (pri_bitmask & cos_bit_to_set) {
1076                         /* COS wasn't used for SP */
1077                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1078                             i, pri_set);
1079
1080                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1081                             i, pri_set);
1082                         /* COS is used remove it from bitmap.*/
1083                         cos_bit_to_set &= ~pri_bitmask;
1084                         pri_set++;
1085                 }
1086         }
1087
1088         if (pri_set != max_num_of_cos) {
1089                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1090                                    "entries were set\n");
1091                 return -EINVAL;
1092         }
1093
1094         if (port) {
1095                 /* Only 6 usable clients*/
1096                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1097                        (u32)pri_cli_nig);
1098
1099                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1100         } else {
1101                 /* Only 9 usable clients*/
1102                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1103                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1104
1105                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1106                        pri_cli_nig_lsb);
1107                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1108                        pri_cli_nig_msb);
1109
1110                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1111         }
1112         return 0;
1113 }
1114
1115 /******************************************************************************
1116 * Description:
1117 *       Configure the COS to ETS according to BW and SP settings.
1118 ******************************************************************************/
1119 int bnx2x_ets_e3b0_config(const struct link_params *params,
1120                          const struct link_vars *vars,
1121                          struct bnx2x_ets_params *ets_params)
1122 {
1123         struct bnx2x *bp = params->bp;
1124         int bnx2x_status = 0;
1125         const u8 port = params->port;
1126         u16 total_bw = 0;
1127         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1128         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1129         u8 cos_bw_bitmap = 0;
1130         u8 cos_sp_bitmap = 0;
1131         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1132         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1133                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1134         u8 cos_entry = 0;
1135
1136         if (!CHIP_IS_E3B0(bp)) {
1137                 DP(NETIF_MSG_LINK,
1138                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1139                 return -EINVAL;
1140         }
1141
1142         if ((ets_params->num_of_cos > max_num_of_cos)) {
1143                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1144                                    "isn't supported\n");
1145                 return -EINVAL;
1146         }
1147
1148         /* Prepare sp strict priority parameters*/
1149         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1150
1151         /* Prepare BW parameters*/
1152         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1153                                                    &total_bw);
1154         if (bnx2x_status) {
1155                 DP(NETIF_MSG_LINK,
1156                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1157                 return -EINVAL;
1158         }
1159
1160         /* Upper bound is set according to current link speed (min_w_val
1161          * should be the same for upper bound and COS credit val).
1162          */
1163         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1164         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1165
1166
1167         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1168                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1169                         cos_bw_bitmap |= (1 << cos_entry);
1170                         /* The function also sets the BW in HW(not the mappin
1171                          * yet)
1172                          */
1173                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1174                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1175                                 total_bw,
1176                                 ets_params->cos[cos_entry].params.bw_params.bw,
1177                                  port);
1178                 } else if (bnx2x_cos_state_strict ==
1179                         ets_params->cos[cos_entry].state){
1180                         cos_sp_bitmap |= (1 << cos_entry);
1181
1182                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1183                                 params,
1184                                 sp_pri_to_cos,
1185                                 ets_params->cos[cos_entry].params.sp_params.pri,
1186                                 cos_entry);
1187
1188                 } else {
1189                         DP(NETIF_MSG_LINK,
1190                            "bnx2x_ets_e3b0_config cos state not valid\n");
1191                         return -EINVAL;
1192                 }
1193                 if (bnx2x_status) {
1194                         DP(NETIF_MSG_LINK,
1195                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1196                         return bnx2x_status;
1197                 }
1198         }
1199
1200         /* Set SP register (which COS has higher priority) */
1201         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1202                                                          sp_pri_to_cos);
1203
1204         if (bnx2x_status) {
1205                 DP(NETIF_MSG_LINK,
1206                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1207                 return bnx2x_status;
1208         }
1209
1210         /* Set client mapping of BW and strict */
1211         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1212                                               cos_sp_bitmap,
1213                                               cos_bw_bitmap);
1214
1215         if (bnx2x_status) {
1216                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1217                 return bnx2x_status;
1218         }
1219         return 0;
1220 }
1221 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1222 {
1223         /* ETS disabled configuration */
1224         struct bnx2x *bp = params->bp;
1225         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1226         /* Defines which entries (clients) are subjected to WFQ arbitration
1227          * COS0 0x8
1228          * COS1 0x10
1229          */
1230         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1231         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1232          * client numbers (WEIGHT_0 does not actually have to represent
1233          * client 0)
1234          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1235          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1236          */
1237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1238
1239         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1240                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1241         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1242                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1243
1244         /* ETS mode enabled*/
1245         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1246
1247         /* Defines the number of consecutive slots for the strict priority */
1248         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1249         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1250          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1251          * entry, 4 - COS1 entry.
1252          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1253          * bit4   bit3    bit2     bit1    bit0
1254          * MCP and debug are strict
1255          */
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1257
1258         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1259         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1260                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1261         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1262                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1263 }
1264
1265 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1266                         const u32 cos1_bw)
1267 {
1268         /* ETS disabled configuration*/
1269         struct bnx2x *bp = params->bp;
1270         const u32 total_bw = cos0_bw + cos1_bw;
1271         u32 cos0_credit_weight = 0;
1272         u32 cos1_credit_weight = 0;
1273
1274         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1275
1276         if ((!total_bw) ||
1277             (!cos0_bw) ||
1278             (!cos1_bw)) {
1279                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1280                 return;
1281         }
1282
1283         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1284                 total_bw;
1285         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1286                 total_bw;
1287
1288         bnx2x_ets_bw_limit_common(params);
1289
1290         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1292
1293         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1294         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1295 }
1296
1297 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1298 {
1299         /* ETS disabled configuration*/
1300         struct bnx2x *bp = params->bp;
1301         u32 val = 0;
1302
1303         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1304         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1305          * as strict.  Bits 0,1,2 - debug and management entries,
1306          * 3 - COS0 entry, 4 - COS1 entry.
1307          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1308          *  bit4   bit3   bit2      bit1     bit0
1309          * MCP and debug are strict
1310          */
1311         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1312         /* For strict priority entries defines the number of consecutive slots
1313          * for the highest priority.
1314          */
1315         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1316         /* ETS mode disable */
1317         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1318         /* Defines the number of consecutive slots for the strict priority */
1319         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1320
1321         /* Defines the number of consecutive slots for the strict priority */
1322         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1323
1324         /* Mapping between entry  priority to client number (0,1,2 -debug and
1325          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326          * 3bits client num.
1327          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1328          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1329          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1330          */
1331         val = (!strict_cos) ? 0x2318 : 0x22E0;
1332         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1333
1334         return 0;
1335 }
1336
1337 /******************************************************************/
1338 /*                      PFC section                               */
1339 /******************************************************************/
1340 static void bnx2x_update_pfc_xmac(struct link_params *params,
1341                                   struct link_vars *vars,
1342                                   u8 is_lb)
1343 {
1344         struct bnx2x *bp = params->bp;
1345         u32 xmac_base;
1346         u32 pause_val, pfc0_val, pfc1_val;
1347
1348         /* XMAC base adrr */
1349         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1350
1351         /* Initialize pause and pfc registers */
1352         pause_val = 0x18000;
1353         pfc0_val = 0xFFFF8000;
1354         pfc1_val = 0x2;
1355
1356         /* No PFC support */
1357         if (!(params->feature_config_flags &
1358               FEATURE_CONFIG_PFC_ENABLED)) {
1359
1360                 /* RX flow control - Process pause frame in receive direction
1361                  */
1362                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364
1365                 /* TX flow control - Send pause packet when buffer is full */
1366                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1367                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1368         } else {/* PFC support */
1369                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1370                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1371                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1372                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1374                 /* Write pause and PFC registers */
1375                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1376                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1378                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1379
1380         }
1381
1382         /* Write pause and PFC registers */
1383         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1384         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1386
1387
1388         /* Set MAC address for source TX Pause/PFC frames */
1389         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1390                ((params->mac_addr[2] << 24) |
1391                 (params->mac_addr[3] << 16) |
1392                 (params->mac_addr[4] << 8) |
1393                 (params->mac_addr[5])));
1394         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1395                ((params->mac_addr[0] << 8) |
1396                 (params->mac_addr[1])));
1397
1398         udelay(30);
1399 }
1400
1401
1402 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1403                                     u32 pfc_frames_sent[2],
1404                                     u32 pfc_frames_received[2])
1405 {
1406         /* Read pfc statistic */
1407         struct bnx2x *bp = params->bp;
1408         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1409         u32 val_xon = 0;
1410         u32 val_xoff = 0;
1411
1412         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1413
1414         /* PFC received frames */
1415         val_xoff = REG_RD(bp, emac_base +
1416                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1417         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1418         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1419         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1420
1421         pfc_frames_received[0] = val_xon + val_xoff;
1422
1423         /* PFC received sent */
1424         val_xoff = REG_RD(bp, emac_base +
1425                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1426         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1427         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1428         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1429
1430         pfc_frames_sent[0] = val_xon + val_xoff;
1431 }
1432
1433 /* Read pfc statistic*/
1434 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1435                          u32 pfc_frames_sent[2],
1436                          u32 pfc_frames_received[2])
1437 {
1438         /* Read pfc statistic */
1439         struct bnx2x *bp = params->bp;
1440
1441         DP(NETIF_MSG_LINK, "pfc statistic\n");
1442
1443         if (!vars->link_up)
1444                 return;
1445
1446         if (vars->mac_type == MAC_TYPE_EMAC) {
1447                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1448                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1449                                         pfc_frames_received);
1450         }
1451 }
1452 /******************************************************************/
1453 /*                      MAC/PBF section                           */
1454 /******************************************************************/
1455 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1456                                u32 emac_base)
1457 {
1458         u32 new_mode, cur_mode;
1459         u32 clc_cnt;
1460         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1461          * (a value of 49==0x31) and make sure that the AUTO poll is off
1462          */
1463         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1464
1465         if (USES_WARPCORE(bp))
1466                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1467         else
1468                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1469
1470         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1471             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1472                 return;
1473
1474         new_mode = cur_mode &
1475                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1476         new_mode |= clc_cnt;
1477         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1478
1479         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1480            cur_mode, new_mode);
1481         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1482         udelay(40);
1483 }
1484
1485 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1486                                         struct link_params *params)
1487 {
1488         u8 phy_index;
1489         /* Set mdio clock per phy */
1490         for (phy_index = INT_PHY; phy_index < params->num_phys;
1491               phy_index++)
1492                 bnx2x_set_mdio_clk(bp, params->chip_id,
1493                                    params->phy[phy_index].mdio_ctrl);
1494 }
1495
1496 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1497 {
1498         u32 port4mode_ovwr_val;
1499         /* Check 4-port override enabled */
1500         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1501         if (port4mode_ovwr_val & (1<<0)) {
1502                 /* Return 4-port mode override value */
1503                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1504         }
1505         /* Return 4-port mode from input pin */
1506         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1507 }
1508
1509 static void bnx2x_emac_init(struct link_params *params,
1510                             struct link_vars *vars)
1511 {
1512         /* reset and unreset the emac core */
1513         struct bnx2x *bp = params->bp;
1514         u8 port = params->port;
1515         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1516         u32 val;
1517         u16 timeout;
1518
1519         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1520                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1521         udelay(5);
1522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1524
1525         /* init emac - use read-modify-write */
1526         /* self clear reset */
1527         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1528         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1529
1530         timeout = 200;
1531         do {
1532                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1533                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1534                 if (!timeout) {
1535                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1536                         return;
1537                 }
1538                 timeout--;
1539         } while (val & EMAC_MODE_RESET);
1540
1541         bnx2x_set_mdio_emac_per_phy(bp, params);
1542         /* Set mac address */
1543         val = ((params->mac_addr[0] << 8) |
1544                 params->mac_addr[1]);
1545         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1546
1547         val = ((params->mac_addr[2] << 24) |
1548                (params->mac_addr[3] << 16) |
1549                (params->mac_addr[4] << 8) |
1550                 params->mac_addr[5]);
1551         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1552 }
1553
1554 static void bnx2x_set_xumac_nig(struct link_params *params,
1555                                 u16 tx_pause_en,
1556                                 u8 enable)
1557 {
1558         struct bnx2x *bp = params->bp;
1559
1560         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1561                enable);
1562         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1563                enable);
1564         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1565                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1566 }
1567
1568 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1569 {
1570         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1571         u32 val;
1572         struct bnx2x *bp = params->bp;
1573         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1574                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1575                 return;
1576         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1577         if (en)
1578                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1579                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1580         else
1581                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1582                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1583         /* Disable RX and TX */
1584         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1585 }
1586
1587 static void bnx2x_umac_enable(struct link_params *params,
1588                             struct link_vars *vars, u8 lb)
1589 {
1590         u32 val;
1591         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1592         struct bnx2x *bp = params->bp;
1593         /* Reset UMAC */
1594         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1595                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1596         usleep_range(1000, 2000);
1597
1598         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1599                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1600
1601         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1602
1603         /* This register opens the gate for the UMAC despite its name */
1604         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1605
1606         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1607                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1608                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1609                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1610         switch (vars->line_speed) {
1611         case SPEED_10:
1612                 val |= (0<<2);
1613                 break;
1614         case SPEED_100:
1615                 val |= (1<<2);
1616                 break;
1617         case SPEED_1000:
1618                 val |= (2<<2);
1619                 break;
1620         case SPEED_2500:
1621                 val |= (3<<2);
1622                 break;
1623         default:
1624                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1625                                vars->line_speed);
1626                 break;
1627         }
1628         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1629                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1630
1631         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1632                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1633
1634         if (vars->duplex == DUPLEX_HALF)
1635                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1636
1637         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1638         udelay(50);
1639
1640         /* Configure UMAC for EEE */
1641         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1642                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1643                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1644                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1645                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1646         } else {
1647                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1648         }
1649
1650         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1651         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1652                ((params->mac_addr[2] << 24) |
1653                 (params->mac_addr[3] << 16) |
1654                 (params->mac_addr[4] << 8) |
1655                 (params->mac_addr[5])));
1656         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1657                ((params->mac_addr[0] << 8) |
1658                 (params->mac_addr[1])));
1659
1660         /* Enable RX and TX */
1661         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1662         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1663                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1664         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1665         udelay(50);
1666
1667         /* Remove SW Reset */
1668         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1669
1670         /* Check loopback mode */
1671         if (lb)
1672                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1673         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1674
1675         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1676          * length used by the MAC receive logic to check frames.
1677          */
1678         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1679         bnx2x_set_xumac_nig(params,
1680                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1681         vars->mac_type = MAC_TYPE_UMAC;
1682
1683 }
1684
1685 /* Define the XMAC mode */
1686 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1687 {
1688         struct bnx2x *bp = params->bp;
1689         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1690
1691         /* In 4-port mode, need to set the mode only once, so if XMAC is
1692          * already out of reset, it means the mode has already been set,
1693          * and it must not* reset the XMAC again, since it controls both
1694          * ports of the path
1695          */
1696
1697         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1698              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1700             is_port4mode &&
1701             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1702              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1703                 DP(NETIF_MSG_LINK,
1704                    "XMAC already out of reset in 4-port mode\n");
1705                 return;
1706         }
1707
1708         /* Hard reset */
1709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1710                MISC_REGISTERS_RESET_REG_2_XMAC);
1711         usleep_range(1000, 2000);
1712
1713         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1714                MISC_REGISTERS_RESET_REG_2_XMAC);
1715         if (is_port4mode) {
1716                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1717
1718                 /* Set the number of ports on the system side to up to 2 */
1719                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1720
1721                 /* Set the number of ports on the Warp Core to 10G */
1722                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1723         } else {
1724                 /* Set the number of ports on the system side to 1 */
1725                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1726                 if (max_speed == SPEED_10000) {
1727                         DP(NETIF_MSG_LINK,
1728                            "Init XMAC to 10G x 1 port per path\n");
1729                         /* Set the number of ports on the Warp Core to 10G */
1730                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1731                 } else {
1732                         DP(NETIF_MSG_LINK,
1733                            "Init XMAC to 20G x 2 ports per path\n");
1734                         /* Set the number of ports on the Warp Core to 20G */
1735                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1736                 }
1737         }
1738         /* Soft reset */
1739         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1740                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1741         usleep_range(1000, 2000);
1742
1743         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1744                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1745
1746 }
1747
1748 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1749 {
1750         u8 port = params->port;
1751         struct bnx2x *bp = params->bp;
1752         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1753         u32 val;
1754
1755         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1756             MISC_REGISTERS_RESET_REG_2_XMAC) {
1757                 /* Send an indication to change the state in the NIG back to XON
1758                  * Clearing this bit enables the next set of this bit to get
1759                  * rising edge
1760                  */
1761                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1762                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1763                        (pfc_ctrl & ~(1<<1)));
1764                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1765                        (pfc_ctrl | (1<<1)));
1766                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1767                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1768                 if (en)
1769                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1770                 else
1771                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1772                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1773         }
1774 }
1775
1776 static int bnx2x_xmac_enable(struct link_params *params,
1777                              struct link_vars *vars, u8 lb)
1778 {
1779         u32 val, xmac_base;
1780         struct bnx2x *bp = params->bp;
1781         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1782
1783         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1784
1785         bnx2x_xmac_init(params, vars->line_speed);
1786
1787         /* This register determines on which events the MAC will assert
1788          * error on the i/f to the NIG along w/ EOP.
1789          */
1790
1791         /* This register tells the NIG whether to send traffic to UMAC
1792          * or XMAC
1793          */
1794         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1795
1796         /* When XMAC is in XLGMII mode, disable sending idles for fault
1797          * detection.
1798          */
1799         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1800                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1801                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1802                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1803                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1805                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1807         }
1808         /* Set Max packet size */
1809         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1810
1811         /* CRC append for Tx packets */
1812         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1813
1814         /* update PFC */
1815         bnx2x_update_pfc_xmac(params, vars, 0);
1816
1817         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1818                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1819                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1821         } else {
1822                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1823         }
1824
1825         /* Enable TX and RX */
1826         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1827
1828         /* Set MAC in XLGMII mode for dual-mode */
1829         if ((vars->line_speed == SPEED_20000) &&
1830             (params->phy[INT_PHY].supported &
1831              SUPPORTED_20000baseKR2_Full))
1832                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1833
1834         /* Check loopback mode */
1835         if (lb)
1836                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1837         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1838         bnx2x_set_xumac_nig(params,
1839                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1840
1841         vars->mac_type = MAC_TYPE_XMAC;
1842
1843         return 0;
1844 }
1845
1846 static int bnx2x_emac_enable(struct link_params *params,
1847                              struct link_vars *vars, u8 lb)
1848 {
1849         struct bnx2x *bp = params->bp;
1850         u8 port = params->port;
1851         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1852         u32 val;
1853
1854         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1855
1856         /* Disable BMAC */
1857         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1858                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1859
1860         /* enable emac and not bmac */
1861         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1862
1863         /* ASIC */
1864         if (vars->phy_flags & PHY_XGXS_FLAG) {
1865                 u32 ser_lane = ((params->lane_config &
1866                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1867                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1868
1869                 DP(NETIF_MSG_LINK, "XGXS\n");
1870                 /* select the master lanes (out of 0-3) */
1871                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1872                 /* select XGXS */
1873                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1874
1875         } else { /* SerDes */
1876                 DP(NETIF_MSG_LINK, "SerDes\n");
1877                 /* select SerDes */
1878                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1879         }
1880
1881         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1882                       EMAC_RX_MODE_RESET);
1883         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1884                       EMAC_TX_MODE_RESET);
1885
1886                 /* pause enable/disable */
1887                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1888                                EMAC_RX_MODE_FLOW_EN);
1889
1890                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1891                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1892                                 EMAC_TX_MODE_FLOW_EN));
1893                 if (!(params->feature_config_flags &
1894                       FEATURE_CONFIG_PFC_ENABLED)) {
1895                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1896                                 bnx2x_bits_en(bp, emac_base +
1897                                               EMAC_REG_EMAC_RX_MODE,
1898                                               EMAC_RX_MODE_FLOW_EN);
1899
1900                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1901                                 bnx2x_bits_en(bp, emac_base +
1902                                               EMAC_REG_EMAC_TX_MODE,
1903                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1904                                                EMAC_TX_MODE_FLOW_EN));
1905                 } else
1906                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1907                                       EMAC_TX_MODE_FLOW_EN);
1908
1909         /* KEEP_VLAN_TAG, promiscuous */
1910         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1911         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1912
1913         /* Setting this bit causes MAC control frames (except for pause
1914          * frames) to be passed on for processing. This setting has no
1915          * affect on the operation of the pause frames. This bit effects
1916          * all packets regardless of RX Parser packet sorting logic.
1917          * Turn the PFC off to make sure we are in Xon state before
1918          * enabling it.
1919          */
1920         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1921         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923                 /* Enable PFC again */
1924                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1925                         EMAC_REG_RX_PFC_MODE_RX_EN |
1926                         EMAC_REG_RX_PFC_MODE_TX_EN |
1927                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1928
1929                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1930                         ((0x0101 <<
1931                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1932                          (0x00ff <<
1933                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1934                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1935         }
1936         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1937
1938         /* Set Loopback */
1939         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1940         if (lb)
1941                 val |= 0x810;
1942         else
1943                 val &= ~0x810;
1944         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1945
1946         /* Enable emac */
1947         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1948
1949         /* Enable emac for jumbo packets */
1950         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1951                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1952                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1953
1954         /* Strip CRC */
1955         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1956
1957         /* Disable the NIG in/out to the bmac */
1958         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1959         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1961
1962         /* Enable the NIG in/out to the emac */
1963         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1964         val = 0;
1965         if ((params->feature_config_flags &
1966               FEATURE_CONFIG_PFC_ENABLED) ||
1967             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1968                 val = 1;
1969
1970         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1971         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1972
1973         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1974
1975         vars->mac_type = MAC_TYPE_EMAC;
1976         return 0;
1977 }
1978
1979 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1980                                    struct link_vars *vars)
1981 {
1982         u32 wb_data[2];
1983         struct bnx2x *bp = params->bp;
1984         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1985                 NIG_REG_INGRESS_BMAC0_MEM;
1986
1987         u32 val = 0x14;
1988         if ((!(params->feature_config_flags &
1989               FEATURE_CONFIG_PFC_ENABLED)) &&
1990                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1991                 /* Enable BigMAC to react on received Pause packets */
1992                 val |= (1<<5);
1993         wb_data[0] = val;
1994         wb_data[1] = 0;
1995         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1996
1997         /* TX control */
1998         val = 0xc0;
1999         if (!(params->feature_config_flags &
2000               FEATURE_CONFIG_PFC_ENABLED) &&
2001                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2002                 val |= 0x800000;
2003         wb_data[0] = val;
2004         wb_data[1] = 0;
2005         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2006 }
2007
2008 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009                                    struct link_vars *vars,
2010                                    u8 is_lb)
2011 {
2012         /* Set rx control: Strip CRC and enable BigMAC to relay
2013          * control packets to the system as well
2014          */
2015         u32 wb_data[2];
2016         struct bnx2x *bp = params->bp;
2017         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2018                 NIG_REG_INGRESS_BMAC0_MEM;
2019         u32 val = 0x14;
2020
2021         if ((!(params->feature_config_flags &
2022               FEATURE_CONFIG_PFC_ENABLED)) &&
2023                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2024                 /* Enable BigMAC to react on received Pause packets */
2025                 val |= (1<<5);
2026         wb_data[0] = val;
2027         wb_data[1] = 0;
2028         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2029         udelay(30);
2030
2031         /* Tx control */
2032         val = 0xc0;
2033         if (!(params->feature_config_flags &
2034                                 FEATURE_CONFIG_PFC_ENABLED) &&
2035             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2036                 val |= 0x800000;
2037         wb_data[0] = val;
2038         wb_data[1] = 0;
2039         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2040
2041         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2042                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2043                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2044                 wb_data[0] = 0x0;
2045                 wb_data[0] |= (1<<0);  /* RX */
2046                 wb_data[0] |= (1<<1);  /* TX */
2047                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2048                 wb_data[0] |= (1<<3);  /* 8 cos */
2049                 wb_data[0] |= (1<<5);  /* STATS */
2050                 wb_data[1] = 0;
2051                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2052                             wb_data, 2);
2053                 /* Clear the force Xon */
2054                 wb_data[0] &= ~(1<<2);
2055         } else {
2056                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2057                 /* Disable PFC RX & TX & STATS and set 8 COS */
2058                 wb_data[0] = 0x8;
2059                 wb_data[1] = 0;
2060         }
2061
2062         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2063
2064         /* Set Time (based unit is 512 bit time) between automatic
2065          * re-sending of PP packets amd enable automatic re-send of
2066          * Per-Priroity Packet as long as pp_gen is asserted and
2067          * pp_disable is low.
2068          */
2069         val = 0x8000;
2070         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2071                 val |= (1<<16); /* enable automatic re-send */
2072
2073         wb_data[0] = val;
2074         wb_data[1] = 0;
2075         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2076                     wb_data, 2);
2077
2078         /* mac control */
2079         val = 0x3; /* Enable RX and TX */
2080         if (is_lb) {
2081                 val |= 0x4; /* Local loopback */
2082                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2083         }
2084         /* When PFC enabled, Pass pause frames towards the NIG. */
2085         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2086                 val |= ((1<<6)|(1<<5));
2087
2088         wb_data[0] = val;
2089         wb_data[1] = 0;
2090         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2091 }
2092
2093 /******************************************************************************
2094 * Description:
2095 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2096 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2097 ******************************************************************************/
2098 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2099                                            u8 cos_entry,
2100                                            u32 priority_mask, u8 port)
2101 {
2102         u32 nig_reg_rx_priority_mask_add = 0;
2103
2104         switch (cos_entry) {
2105         case 0:
2106              nig_reg_rx_priority_mask_add = (port) ?
2107                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2108                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2109              break;
2110         case 1:
2111             nig_reg_rx_priority_mask_add = (port) ?
2112                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2113                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2114             break;
2115         case 2:
2116             nig_reg_rx_priority_mask_add = (port) ?
2117                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2118                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2119             break;
2120         case 3:
2121             if (port)
2122                 return -EINVAL;
2123             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2124             break;
2125         case 4:
2126             if (port)
2127                 return -EINVAL;
2128             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2129             break;
2130         case 5:
2131             if (port)
2132                 return -EINVAL;
2133             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2134             break;
2135         }
2136
2137         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2138
2139         return 0;
2140 }
2141 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2142 {
2143         struct bnx2x *bp = params->bp;
2144
2145         REG_WR(bp, params->shmem_base +
2146                offsetof(struct shmem_region,
2147                         port_mb[params->port].link_status), link_status);
2148 }
2149
2150 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2151 {
2152         struct bnx2x *bp = params->bp;
2153
2154         if (SHMEM2_HAS(bp, link_attr_sync))
2155                 REG_WR(bp, params->shmem2_base +
2156                        offsetof(struct shmem2_region,
2157                                 link_attr_sync[params->port]), link_attr);
2158 }
2159
2160 static void bnx2x_update_pfc_nig(struct link_params *params,
2161                 struct link_vars *vars,
2162                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2163 {
2164         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2165         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2166         u32 pkt_priority_to_cos = 0;
2167         struct bnx2x *bp = params->bp;
2168         u8 port = params->port;
2169
2170         int set_pfc = params->feature_config_flags &
2171                 FEATURE_CONFIG_PFC_ENABLED;
2172         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2173
2174         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2175          * MAC control frames (that are not pause packets)
2176          * will be forwarded to the XCM.
2177          */
2178         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2179                           NIG_REG_LLH0_XCM_MASK);
2180         /* NIG params will override non PFC params, since it's possible to
2181          * do transition from PFC to SAFC
2182          */
2183         if (set_pfc) {
2184                 pause_enable = 0;
2185                 llfc_out_en = 0;
2186                 llfc_enable = 0;
2187                 if (CHIP_IS_E3(bp))
2188                         ppp_enable = 0;
2189                 else
2190                         ppp_enable = 1;
2191                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2192                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2193                 xcm_out_en = 0;
2194                 hwpfc_enable = 1;
2195         } else  {
2196                 if (nig_params) {
2197                         llfc_out_en = nig_params->llfc_out_en;
2198                         llfc_enable = nig_params->llfc_enable;
2199                         pause_enable = nig_params->pause_enable;
2200                 } else  /* Default non PFC mode - PAUSE */
2201                         pause_enable = 1;
2202
2203                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2204                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2205                 xcm_out_en = 1;
2206         }
2207
2208         if (CHIP_IS_E3(bp))
2209                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2210                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2211         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2212                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2213         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2214                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2215         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2216                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2217
2218         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2219                NIG_REG_PPP_ENABLE_0, ppp_enable);
2220
2221         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2222                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2223
2224         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2225                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2226
2227         /* Output enable for RX_XCM # IF */
2228         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2229                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2230
2231         /* HW PFC TX enable */
2232         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2233                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2234
2235         if (nig_params) {
2236                 u8 i = 0;
2237                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2238
2239                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2240                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2241                 nig_params->rx_cos_priority_mask[i], port);
2242
2243                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2244                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2245                        nig_params->llfc_high_priority_classes);
2246
2247                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2248                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2249                        nig_params->llfc_low_priority_classes);
2250         }
2251         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2252                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2253                pkt_priority_to_cos);
2254 }
2255
2256 int bnx2x_update_pfc(struct link_params *params,
2257                       struct link_vars *vars,
2258                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2259 {
2260         /* The PFC and pause are orthogonal to one another, meaning when
2261          * PFC is enabled, the pause are disabled, and when PFC is
2262          * disabled, pause are set according to the pause result.
2263          */
2264         u32 val;
2265         struct bnx2x *bp = params->bp;
2266         int bnx2x_status = 0;
2267         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2268
2269         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2270                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2271         else
2272                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2273
2274         bnx2x_update_mng(params, vars->link_status);
2275
2276         /* Update NIG params */
2277         bnx2x_update_pfc_nig(params, vars, pfc_params);
2278
2279         if (!vars->link_up)
2280                 return bnx2x_status;
2281
2282         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2283
2284         if (CHIP_IS_E3(bp)) {
2285                 if (vars->mac_type == MAC_TYPE_XMAC)
2286                         bnx2x_update_pfc_xmac(params, vars, 0);
2287         } else {
2288                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2289                 if ((val &
2290                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2291                     == 0) {
2292                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2293                         bnx2x_emac_enable(params, vars, 0);
2294                         return bnx2x_status;
2295                 }
2296                 if (CHIP_IS_E2(bp))
2297                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2298                 else
2299                         bnx2x_update_pfc_bmac1(params, vars);
2300
2301                 val = 0;
2302                 if ((params->feature_config_flags &
2303                      FEATURE_CONFIG_PFC_ENABLED) ||
2304                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2305                         val = 1;
2306                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2307         }
2308         return bnx2x_status;
2309 }
2310
2311 static int bnx2x_bmac1_enable(struct link_params *params,
2312                               struct link_vars *vars,
2313                               u8 is_lb)
2314 {
2315         struct bnx2x *bp = params->bp;
2316         u8 port = params->port;
2317         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2318                                NIG_REG_INGRESS_BMAC0_MEM;
2319         u32 wb_data[2];
2320         u32 val;
2321
2322         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2323
2324         /* XGXS control */
2325         wb_data[0] = 0x3c;
2326         wb_data[1] = 0;
2327         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2328                     wb_data, 2);
2329
2330         /* TX MAC SA */
2331         wb_data[0] = ((params->mac_addr[2] << 24) |
2332                        (params->mac_addr[3] << 16) |
2333                        (params->mac_addr[4] << 8) |
2334                         params->mac_addr[5]);
2335         wb_data[1] = ((params->mac_addr[0] << 8) |
2336                         params->mac_addr[1]);
2337         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2338
2339         /* MAC control */
2340         val = 0x3;
2341         if (is_lb) {
2342                 val |= 0x4;
2343                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2344         }
2345         wb_data[0] = val;
2346         wb_data[1] = 0;
2347         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2348
2349         /* Set rx mtu */
2350         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2351         wb_data[1] = 0;
2352         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2353
2354         bnx2x_update_pfc_bmac1(params, vars);
2355
2356         /* Set tx mtu */
2357         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2358         wb_data[1] = 0;
2359         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2360
2361         /* Set cnt max size */
2362         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2363         wb_data[1] = 0;
2364         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2365
2366         /* Configure SAFC */
2367         wb_data[0] = 0x1000200;
2368         wb_data[1] = 0;
2369         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2370                     wb_data, 2);
2371
2372         return 0;
2373 }
2374
2375 static int bnx2x_bmac2_enable(struct link_params *params,
2376                               struct link_vars *vars,
2377                               u8 is_lb)
2378 {
2379         struct bnx2x *bp = params->bp;
2380         u8 port = params->port;
2381         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2382                                NIG_REG_INGRESS_BMAC0_MEM;
2383         u32 wb_data[2];
2384
2385         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2386
2387         wb_data[0] = 0;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2390         udelay(30);
2391
2392         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2393         wb_data[0] = 0x3c;
2394         wb_data[1] = 0;
2395         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2396                     wb_data, 2);
2397
2398         udelay(30);
2399
2400         /* TX MAC SA */
2401         wb_data[0] = ((params->mac_addr[2] << 24) |
2402                        (params->mac_addr[3] << 16) |
2403                        (params->mac_addr[4] << 8) |
2404                         params->mac_addr[5]);
2405         wb_data[1] = ((params->mac_addr[0] << 8) |
2406                         params->mac_addr[1]);
2407         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2408                     wb_data, 2);
2409
2410         udelay(30);
2411
2412         /* Configure SAFC */
2413         wb_data[0] = 0x1000200;
2414         wb_data[1] = 0;
2415         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2416                     wb_data, 2);
2417         udelay(30);
2418
2419         /* Set RX MTU */
2420         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2421         wb_data[1] = 0;
2422         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2423         udelay(30);
2424
2425         /* Set TX MTU */
2426         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2427         wb_data[1] = 0;
2428         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2429         udelay(30);
2430         /* Set cnt max size */
2431         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2432         wb_data[1] = 0;
2433         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2434         udelay(30);
2435         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2436
2437         return 0;
2438 }
2439
2440 static int bnx2x_bmac_enable(struct link_params *params,
2441                              struct link_vars *vars,
2442                              u8 is_lb, u8 reset_bmac)
2443 {
2444         int rc = 0;
2445         u8 port = params->port;
2446         struct bnx2x *bp = params->bp;
2447         u32 val;
2448         /* Reset and unreset the BigMac */
2449         if (reset_bmac) {
2450                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2451                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2452                 usleep_range(1000, 2000);
2453         }
2454
2455         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2456                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2457
2458         /* Enable access for bmac registers */
2459         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2460
2461         /* Enable BMAC according to BMAC type*/
2462         if (CHIP_IS_E2(bp))
2463                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2464         else
2465                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2466         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2467         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2468         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2469         val = 0;
2470         if ((params->feature_config_flags &
2471               FEATURE_CONFIG_PFC_ENABLED) ||
2472             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2473                 val = 1;
2474         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2475         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2476         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2479         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2480
2481         vars->mac_type = MAC_TYPE_BMAC;
2482         return rc;
2483 }
2484
2485 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2486 {
2487         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2488                         NIG_REG_INGRESS_BMAC0_MEM;
2489         u32 wb_data[2];
2490         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2491
2492         if (CHIP_IS_E2(bp))
2493                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2494         else
2495                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2496         /* Only if the bmac is out of reset */
2497         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2498                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2499             nig_bmac_enable) {
2500                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2501                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2502                 if (en)
2503                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2504                 else
2505                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2506                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2507                 usleep_range(1000, 2000);
2508         }
2509 }
2510
2511 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2512                             u32 line_speed)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u8 port = params->port;
2516         u32 init_crd, crd;
2517         u32 count = 1000;
2518
2519         /* Disable port */
2520         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2521
2522         /* Wait for init credit */
2523         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2524         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2525         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2526
2527         while ((init_crd != crd) && count) {
2528                 usleep_range(5000, 10000);
2529                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2530                 count--;
2531         }
2532         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2533         if (init_crd != crd) {
2534                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2535                           init_crd, crd);
2536                 return -EINVAL;
2537         }
2538
2539         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2540             line_speed == SPEED_10 ||
2541             line_speed == SPEED_100 ||
2542             line_speed == SPEED_1000 ||
2543             line_speed == SPEED_2500) {
2544                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2545                 /* Update threshold */
2546                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2547                 /* Update init credit */
2548                 init_crd = 778;         /* (800-18-4) */
2549
2550         } else {
2551                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2552                               ETH_OVREHEAD)/16;
2553                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2554                 /* Update threshold */
2555                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2556                 /* Update init credit */
2557                 switch (line_speed) {
2558                 case SPEED_10000:
2559                         init_crd = thresh + 553 - 22;
2560                         break;
2561                 default:
2562                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2563                                   line_speed);
2564                         return -EINVAL;
2565                 }
2566         }
2567         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2568         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2569                  line_speed, init_crd);
2570
2571         /* Probe the credit changes */
2572         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2573         usleep_range(5000, 10000);
2574         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2575
2576         /* Enable port */
2577         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2578         return 0;
2579 }
2580
2581 /**
2582  * bnx2x_get_emac_base - retrive emac base address
2583  *
2584  * @bp:                 driver handle
2585  * @mdc_mdio_access:    access type
2586  * @port:               port id
2587  *
2588  * This function selects the MDC/MDIO access (through emac0 or
2589  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2590  * phy has a default access mode, which could also be overridden
2591  * by nvram configuration. This parameter, whether this is the
2592  * default phy configuration, or the nvram overrun
2593  * configuration, is passed here as mdc_mdio_access and selects
2594  * the emac_base for the CL45 read/writes operations
2595  */
2596 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2597                                u32 mdc_mdio_access, u8 port)
2598 {
2599         u32 emac_base = 0;
2600         switch (mdc_mdio_access) {
2601         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2602                 break;
2603         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2604                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2605                         emac_base = GRCBASE_EMAC1;
2606                 else
2607                         emac_base = GRCBASE_EMAC0;
2608                 break;
2609         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2610                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2611                         emac_base = GRCBASE_EMAC0;
2612                 else
2613                         emac_base = GRCBASE_EMAC1;
2614                 break;
2615         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2616                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2617                 break;
2618         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2619                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2620                 break;
2621         default:
2622                 break;
2623         }
2624         return emac_base;
2625
2626 }
2627
2628 /******************************************************************/
2629 /*                      CL22 access functions                     */
2630 /******************************************************************/
2631 static int bnx2x_cl22_write(struct bnx2x *bp,
2632                                        struct bnx2x_phy *phy,
2633                                        u16 reg, u16 val)
2634 {
2635         u32 tmp, mode;
2636         u8 i;
2637         int rc = 0;
2638         /* Switch to CL22 */
2639         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2640         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2641                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2642
2643         /* Address */
2644         tmp = ((phy->addr << 21) | (reg << 16) | val |
2645                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2646                EMAC_MDIO_COMM_START_BUSY);
2647         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2648
2649         for (i = 0; i < 50; i++) {
2650                 udelay(10);
2651
2652                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2653                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2654                         udelay(5);
2655                         break;
2656                 }
2657         }
2658         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2659                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2660                 rc = -EFAULT;
2661         }
2662         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2663         return rc;
2664 }
2665
2666 static int bnx2x_cl22_read(struct bnx2x *bp,
2667                                       struct bnx2x_phy *phy,
2668                                       u16 reg, u16 *ret_val)
2669 {
2670         u32 val, mode;
2671         u16 i;
2672         int rc = 0;
2673
2674         /* Switch to CL22 */
2675         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2676         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2677                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2678
2679         /* Address */
2680         val = ((phy->addr << 21) | (reg << 16) |
2681                EMAC_MDIO_COMM_COMMAND_READ_22 |
2682                EMAC_MDIO_COMM_START_BUSY);
2683         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2684
2685         for (i = 0; i < 50; i++) {
2686                 udelay(10);
2687
2688                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2689                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2690                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2691                         udelay(5);
2692                         break;
2693                 }
2694         }
2695         if (val & EMAC_MDIO_COMM_START_BUSY) {
2696                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2697
2698                 *ret_val = 0;
2699                 rc = -EFAULT;
2700         }
2701         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2702         return rc;
2703 }
2704
2705 /******************************************************************/
2706 /*                      CL45 access functions                     */
2707 /******************************************************************/
2708 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2709                            u8 devad, u16 reg, u16 *ret_val)
2710 {
2711         u32 val;
2712         u16 i;
2713         int rc = 0;
2714         u32 chip_id;
2715         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2716                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2717                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2718                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2719         }
2720
2721         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2722                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2723                               EMAC_MDIO_STATUS_10MB);
2724         /* Address */
2725         val = ((phy->addr << 21) | (devad << 16) | reg |
2726                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2727                EMAC_MDIO_COMM_START_BUSY);
2728         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2729
2730         for (i = 0; i < 50; i++) {
2731                 udelay(10);
2732
2733                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2734                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2735                         udelay(5);
2736                         break;
2737                 }
2738         }
2739         if (val & EMAC_MDIO_COMM_START_BUSY) {
2740                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2741                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2742                 *ret_val = 0;
2743                 rc = -EFAULT;
2744         } else {
2745                 /* Data */
2746                 val = ((phy->addr << 21) | (devad << 16) |
2747                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2748                        EMAC_MDIO_COMM_START_BUSY);
2749                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2750
2751                 for (i = 0; i < 50; i++) {
2752                         udelay(10);
2753
2754                         val = REG_RD(bp, phy->mdio_ctrl +
2755                                      EMAC_REG_EMAC_MDIO_COMM);
2756                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2757                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2758                                 break;
2759                         }
2760                 }
2761                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2762                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2763                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2764                         *ret_val = 0;
2765                         rc = -EFAULT;
2766                 }
2767         }
2768         /* Work around for E3 A0 */
2769         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2770                 phy->flags ^= FLAGS_DUMMY_READ;
2771                 if (phy->flags & FLAGS_DUMMY_READ) {
2772                         u16 temp_val;
2773                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2774                 }
2775         }
2776
2777         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2778                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2779                                EMAC_MDIO_STATUS_10MB);
2780         return rc;
2781 }
2782
2783 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2784                             u8 devad, u16 reg, u16 val)
2785 {
2786         u32 tmp;
2787         u8 i;
2788         int rc = 0;
2789         u32 chip_id;
2790         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2791                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2792                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2793                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2794         }
2795
2796         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2797                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2798                               EMAC_MDIO_STATUS_10MB);
2799
2800         /* Address */
2801         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2802                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2803                EMAC_MDIO_COMM_START_BUSY);
2804         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2805
2806         for (i = 0; i < 50; i++) {
2807                 udelay(10);
2808
2809                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2810                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2811                         udelay(5);
2812                         break;
2813                 }
2814         }
2815         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2816                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2817                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2818                 rc = -EFAULT;
2819         } else {
2820                 /* Data */
2821                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2822                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2823                        EMAC_MDIO_COMM_START_BUSY);
2824                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2825
2826                 for (i = 0; i < 50; i++) {
2827                         udelay(10);
2828
2829                         tmp = REG_RD(bp, phy->mdio_ctrl +
2830                                      EMAC_REG_EMAC_MDIO_COMM);
2831                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2832                                 udelay(5);
2833                                 break;
2834                         }
2835                 }
2836                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2837                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2838                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2839                         rc = -EFAULT;
2840                 }
2841         }
2842         /* Work around for E3 A0 */
2843         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2844                 phy->flags ^= FLAGS_DUMMY_READ;
2845                 if (phy->flags & FLAGS_DUMMY_READ) {
2846                         u16 temp_val;
2847                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2848                 }
2849         }
2850         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2851                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2852                                EMAC_MDIO_STATUS_10MB);
2853         return rc;
2854 }
2855
2856 /******************************************************************/
2857 /*                      EEE section                                */
2858 /******************************************************************/
2859 static u8 bnx2x_eee_has_cap(struct link_params *params)
2860 {
2861         struct bnx2x *bp = params->bp;
2862
2863         if (REG_RD(bp, params->shmem2_base) <=
2864                    offsetof(struct shmem2_region, eee_status[params->port]))
2865                 return 0;
2866
2867         return 1;
2868 }
2869
2870 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2871 {
2872         switch (nvram_mode) {
2873         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2874                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2875                 break;
2876         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2877                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2878                 break;
2879         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2880                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2881                 break;
2882         default:
2883                 *idle_timer = 0;
2884                 break;
2885         }
2886
2887         return 0;
2888 }
2889
2890 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2891 {
2892         switch (idle_timer) {
2893         case EEE_MODE_NVRAM_BALANCED_TIME:
2894                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2895                 break;
2896         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2897                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2898                 break;
2899         case EEE_MODE_NVRAM_LATENCY_TIME:
2900                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2901                 break;
2902         default:
2903                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2904                 break;
2905         }
2906
2907         return 0;
2908 }
2909
2910 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2911 {
2912         u32 eee_mode, eee_idle;
2913         struct bnx2x *bp = params->bp;
2914
2915         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2916                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2917                         /* time value in eee_mode --> used directly*/
2918                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2919                 } else {
2920                         /* hsi value in eee_mode --> time */
2921                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2922                                                     EEE_MODE_NVRAM_MASK,
2923                                                     &eee_idle))
2924                                 return 0;
2925                 }
2926         } else {
2927                 /* hsi values in nvram --> time*/
2928                 eee_mode = ((REG_RD(bp, params->shmem_base +
2929                                     offsetof(struct shmem_region, dev_info.
2930                                     port_feature_config[params->port].
2931                                     eee_power_mode)) &
2932                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2933                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2934
2935                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2936                         return 0;
2937         }
2938
2939         return eee_idle;
2940 }
2941
2942 static int bnx2x_eee_set_timers(struct link_params *params,
2943                                    struct link_vars *vars)
2944 {
2945         u32 eee_idle = 0, eee_mode;
2946         struct bnx2x *bp = params->bp;
2947
2948         eee_idle = bnx2x_eee_calc_timer(params);
2949
2950         if (eee_idle) {
2951                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2952                        eee_idle);
2953         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2954                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2955                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2956                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2957                 return -EINVAL;
2958         }
2959
2960         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2961         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2962                 /* eee_idle in 1u --> eee_status in 16u */
2963                 eee_idle >>= 4;
2964                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2965                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2966         } else {
2967                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2968                         return -EINVAL;
2969                 vars->eee_status |= eee_mode;
2970         }
2971
2972         return 0;
2973 }
2974
2975 static int bnx2x_eee_initial_config(struct link_params *params,
2976                                      struct link_vars *vars, u8 mode)
2977 {
2978         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2979
2980         /* Propogate params' bits --> vars (for migration exposure) */
2981         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2982                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2983         else
2984                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2985
2986         if (params->eee_mode & EEE_MODE_ADV_LPI)
2987                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2988         else
2989                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2990
2991         return bnx2x_eee_set_timers(params, vars);
2992 }
2993
2994 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2995                                 struct link_params *params,
2996                                 struct link_vars *vars)
2997 {
2998         struct bnx2x *bp = params->bp;
2999
3000         /* Make Certain LPI is disabled */
3001         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3002
3003         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3004
3005         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3006
3007         return 0;
3008 }
3009
3010 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3011                                   struct link_params *params,
3012                                   struct link_vars *vars, u8 modes)
3013 {
3014         struct bnx2x *bp = params->bp;
3015         u16 val = 0;
3016
3017         /* Mask events preventing LPI generation */
3018         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3019
3020         if (modes & SHMEM_EEE_10G_ADV) {
3021                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3022                 val |= 0x8;
3023         }
3024         if (modes & SHMEM_EEE_1G_ADV) {
3025                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3026                 val |= 0x4;
3027         }
3028
3029         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3030
3031         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3032         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3033
3034         return 0;
3035 }
3036
3037 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3038 {
3039         struct bnx2x *bp = params->bp;
3040
3041         if (bnx2x_eee_has_cap(params))
3042                 REG_WR(bp, params->shmem2_base +
3043                        offsetof(struct shmem2_region,
3044                                 eee_status[params->port]), eee_status);
3045 }
3046
3047 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3048                                   struct link_params *params,
3049                                   struct link_vars *vars)
3050 {
3051         struct bnx2x *bp = params->bp;
3052         u16 adv = 0, lp = 0;
3053         u32 lp_adv = 0;
3054         u8 neg = 0;
3055
3056         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3058
3059         if (lp & 0x2) {
3060                 lp_adv |= SHMEM_EEE_100M_ADV;
3061                 if (adv & 0x2) {
3062                         if (vars->line_speed == SPEED_100)
3063                                 neg = 1;
3064                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3065                 }
3066         }
3067         if (lp & 0x14) {
3068                 lp_adv |= SHMEM_EEE_1G_ADV;
3069                 if (adv & 0x14) {
3070                         if (vars->line_speed == SPEED_1000)
3071                                 neg = 1;
3072                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3073                 }
3074         }
3075         if (lp & 0x68) {
3076                 lp_adv |= SHMEM_EEE_10G_ADV;
3077                 if (adv & 0x68) {
3078                         if (vars->line_speed == SPEED_10000)
3079                                 neg = 1;
3080                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3081                 }
3082         }
3083
3084         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3085         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3086
3087         if (neg) {
3088                 DP(NETIF_MSG_LINK, "EEE is active\n");
3089                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3090         }
3091
3092 }
3093
3094 /******************************************************************/
3095 /*                      BSC access functions from E3              */
3096 /******************************************************************/
3097 static void bnx2x_bsc_module_sel(struct link_params *params)
3098 {
3099         int idx;
3100         u32 board_cfg, sfp_ctrl;
3101         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3102         struct bnx2x *bp = params->bp;
3103         u8 port = params->port;
3104         /* Read I2C output PINs */
3105         board_cfg = REG_RD(bp, params->shmem_base +
3106                            offsetof(struct shmem_region,
3107                                     dev_info.shared_hw_config.board));
3108         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3109         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3110                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3111
3112         /* Read I2C output value */
3113         sfp_ctrl = REG_RD(bp, params->shmem_base +
3114                           offsetof(struct shmem_region,
3115                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3116         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3117         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3118         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3119         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3120                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3121 }
3122
3123 static int bnx2x_bsc_read(struct link_params *params,
3124                           struct bnx2x_phy *phy,
3125                           u8 sl_devid,
3126                           u16 sl_addr,
3127                           u8 lc_addr,
3128                           u8 xfer_cnt,
3129                           u32 *data_array)
3130 {
3131         u32 val, i;
3132         int rc = 0;
3133         struct bnx2x *bp = params->bp;
3134
3135         if (xfer_cnt > 16) {
3136                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3137                                         xfer_cnt);
3138                 return -EINVAL;
3139         }
3140         bnx2x_bsc_module_sel(params);
3141
3142         xfer_cnt = 16 - lc_addr;
3143
3144         /* Enable the engine */
3145         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3146         val |= MCPR_IMC_COMMAND_ENABLE;
3147         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3148
3149         /* Program slave device ID */
3150         val = (sl_devid << 16) | sl_addr;
3151         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3152
3153         /* Start xfer with 0 byte to update the address pointer ???*/
3154         val = (MCPR_IMC_COMMAND_ENABLE) |
3155               (MCPR_IMC_COMMAND_WRITE_OP <<
3156                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3157                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3158         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3159
3160         /* Poll for completion */
3161         i = 0;
3162         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3163         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3164                 udelay(10);
3165                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166                 if (i++ > 1000) {
3167                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3168                                                                 i);
3169                         rc = -EFAULT;
3170                         break;
3171                 }
3172         }
3173         if (rc == -EFAULT)
3174                 return rc;
3175
3176         /* Start xfer with read op */
3177         val = (MCPR_IMC_COMMAND_ENABLE) |
3178                 (MCPR_IMC_COMMAND_READ_OP <<
3179                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3180                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3181                   (xfer_cnt);
3182         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3183
3184         /* Poll for completion */
3185         i = 0;
3186         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3187         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3188                 udelay(10);
3189                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3190                 if (i++ > 1000) {
3191                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3192                         rc = -EFAULT;
3193                         break;
3194                 }
3195         }
3196         if (rc == -EFAULT)
3197                 return rc;
3198
3199         for (i = (lc_addr >> 2); i < 4; i++) {
3200                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3201 #ifdef __BIG_ENDIAN
3202                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3203                                 ((data_array[i] & 0x0000ff00) << 8) |
3204                                 ((data_array[i] & 0x00ff0000) >> 8) |
3205                                 ((data_array[i] & 0xff000000) >> 24);
3206 #endif
3207         }
3208         return rc;
3209 }
3210
3211 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3212                                      u8 devad, u16 reg, u16 or_val)
3213 {
3214         u16 val;
3215         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3216         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3217 }
3218
3219 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3220                                       struct bnx2x_phy *phy,
3221                                       u8 devad, u16 reg, u16 and_val)
3222 {
3223         u16 val;
3224         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3225         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3226 }
3227
3228 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3229                    u8 devad, u16 reg, u16 *ret_val)
3230 {
3231         u8 phy_index;
3232         /* Probe for the phy according to the given phy_addr, and execute
3233          * the read request on it
3234          */
3235         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3236                 if (params->phy[phy_index].addr == phy_addr) {
3237                         return bnx2x_cl45_read(params->bp,
3238                                                &params->phy[phy_index], devad,
3239                                                reg, ret_val);
3240                 }
3241         }
3242         return -EINVAL;
3243 }
3244
3245 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3246                     u8 devad, u16 reg, u16 val)
3247 {
3248         u8 phy_index;
3249         /* Probe for the phy according to the given phy_addr, and execute
3250          * the write request on it
3251          */
3252         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3253                 if (params->phy[phy_index].addr == phy_addr) {
3254                         return bnx2x_cl45_write(params->bp,
3255                                                 &params->phy[phy_index], devad,
3256                                                 reg, val);
3257                 }
3258         }
3259         return -EINVAL;
3260 }
3261 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3262                                   struct link_params *params)
3263 {
3264         u8 lane = 0;
3265         struct bnx2x *bp = params->bp;
3266         u32 path_swap, path_swap_ovr;
3267         u8 path, port;
3268
3269         path = BP_PATH(bp);
3270         port = params->port;
3271
3272         if (bnx2x_is_4_port_mode(bp)) {
3273                 u32 port_swap, port_swap_ovr;
3274
3275                 /* Figure out path swap value */
3276                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3277                 if (path_swap_ovr & 0x1)
3278                         path_swap = (path_swap_ovr & 0x2);
3279                 else
3280                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3281
3282                 if (path_swap)
3283                         path = path ^ 1;
3284
3285                 /* Figure out port swap value */
3286                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3287                 if (port_swap_ovr & 0x1)
3288                         port_swap = (port_swap_ovr & 0x2);
3289                 else
3290                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3291
3292                 if (port_swap)
3293                         port = port ^ 1;
3294
3295                 lane = (port<<1) + path;
3296         } else { /* Two port mode - no port swap */
3297
3298                 /* Figure out path swap value */
3299                 path_swap_ovr =
3300                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3301                 if (path_swap_ovr & 0x1) {
3302                         path_swap = (path_swap_ovr & 0x2);
3303                 } else {
3304                         path_swap =
3305                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3306                 }
3307                 if (path_swap)
3308                         path = path ^ 1;
3309
3310                 lane = path << 1 ;
3311         }
3312         return lane;
3313 }
3314
3315 static void bnx2x_set_aer_mmd(struct link_params *params,
3316                               struct bnx2x_phy *phy)
3317 {
3318         u32 ser_lane;
3319         u16 offset, aer_val;
3320         struct bnx2x *bp = params->bp;
3321         ser_lane = ((params->lane_config &
3322                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3324
3325         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3326                 (phy->addr + ser_lane) : 0;
3327
3328         if (USES_WARPCORE(bp)) {
3329                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3330                 /* In Dual-lane mode, two lanes are joined together,
3331                  * so in order to configure them, the AER broadcast method is
3332                  * used here.
3333                  * 0x200 is the broadcast address for lanes 0,1
3334                  * 0x201 is the broadcast address for lanes 2,3
3335                  */
3336                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3337                         aer_val = (aer_val >> 1) | 0x200;
3338         } else if (CHIP_IS_E2(bp))
3339                 aer_val = 0x3800 + offset - 1;
3340         else
3341                 aer_val = 0x3800 + offset;
3342
3343         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3344                           MDIO_AER_BLOCK_AER_REG, aer_val);
3345
3346 }
3347
3348 /******************************************************************/
3349 /*                      Internal phy section                      */
3350 /******************************************************************/
3351
3352 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3353 {
3354         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3355
3356         /* Set Clause 22 */
3357         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3358         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3359         udelay(500);
3360         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3361         udelay(500);
3362          /* Set Clause 45 */
3363         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3364 }
3365
3366 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3367 {
3368         u32 val;
3369
3370         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3371
3372         val = SERDES_RESET_BITS << (port*16);
3373
3374         /* Reset and unreset the SerDes/XGXS */
3375         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3376         udelay(500);
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3378
3379         bnx2x_set_serdes_access(bp, port);
3380
3381         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3382                DEFAULT_PHY_DEV_ADDR);
3383 }
3384
3385 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3386                                      struct link_params *params,
3387                                      u32 action)
3388 {
3389         struct bnx2x *bp = params->bp;
3390         switch (action) {
3391         case PHY_INIT:
3392                 /* Set correct devad */
3393                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3395                        phy->def_md_devad);
3396                 break;
3397         }
3398 }
3399
3400 static void bnx2x_xgxs_deassert(struct link_params *params)
3401 {
3402         struct bnx2x *bp = params->bp;
3403         u8 port;
3404         u32 val;
3405         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3406         port = params->port;
3407
3408         val = XGXS_RESET_BITS << (port*16);
3409
3410         /* Reset and unreset the SerDes/XGXS */
3411         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3412         udelay(500);
3413         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3414         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3415                                  PHY_INIT);
3416 }
3417
3418 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3419                                      struct link_params *params, u16 *ieee_fc)
3420 {
3421         struct bnx2x *bp = params->bp;
3422         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3423         /* Resolve pause mode and advertisement Please refer to Table
3424          * 28B-3 of the 802.3ab-1999 spec
3425          */
3426
3427         switch (phy->req_flow_ctrl) {
3428         case BNX2X_FLOW_CTRL_AUTO:
3429                 switch (params->req_fc_auto_adv) {
3430                 case BNX2X_FLOW_CTRL_BOTH:
3431                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3432                         break;
3433                 case BNX2X_FLOW_CTRL_RX:
3434                 case BNX2X_FLOW_CTRL_TX:
3435                         *ieee_fc |=
3436                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3437                         break;
3438                 default:
3439                         break;
3440                 }
3441                 break;
3442         case BNX2X_FLOW_CTRL_TX:
3443                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3444                 break;
3445
3446         case BNX2X_FLOW_CTRL_RX:
3447         case BNX2X_FLOW_CTRL_BOTH:
3448                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3449                 break;
3450
3451         case BNX2X_FLOW_CTRL_NONE:
3452         default:
3453                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3454                 break;
3455         }
3456         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3457 }
3458
3459 static void set_phy_vars(struct link_params *params,
3460                          struct link_vars *vars)
3461 {
3462         struct bnx2x *bp = params->bp;
3463         u8 actual_phy_idx, phy_index, link_cfg_idx;
3464         u8 phy_config_swapped = params->multi_phy_config &
3465                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3466         for (phy_index = INT_PHY; phy_index < params->num_phys;
3467               phy_index++) {
3468                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3469                 actual_phy_idx = phy_index;
3470                 if (phy_config_swapped) {
3471                         if (phy_index == EXT_PHY1)
3472                                 actual_phy_idx = EXT_PHY2;
3473                         else if (phy_index == EXT_PHY2)
3474                                 actual_phy_idx = EXT_PHY1;
3475                 }
3476                 params->phy[actual_phy_idx].req_flow_ctrl =
3477                         params->req_flow_ctrl[link_cfg_idx];
3478
3479                 params->phy[actual_phy_idx].req_line_speed =
3480                         params->req_line_speed[link_cfg_idx];
3481
3482                 params->phy[actual_phy_idx].speed_cap_mask =
3483                         params->speed_cap_mask[link_cfg_idx];
3484
3485                 params->phy[actual_phy_idx].req_duplex =
3486                         params->req_duplex[link_cfg_idx];
3487
3488                 if (params->req_line_speed[link_cfg_idx] ==
3489                     SPEED_AUTO_NEG)
3490                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3491
3492                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3493                            " speed_cap_mask %x\n",
3494                            params->phy[actual_phy_idx].req_flow_ctrl,
3495                            params->phy[actual_phy_idx].req_line_speed,
3496                            params->phy[actual_phy_idx].speed_cap_mask);
3497         }
3498 }
3499
3500 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3501                                     struct bnx2x_phy *phy,
3502                                     struct link_vars *vars)
3503 {
3504         u16 val;
3505         struct bnx2x *bp = params->bp;
3506         /* Read modify write pause advertizing */
3507         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3508
3509         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3510
3511         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3512         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3513         if ((vars->ieee_fc &
3514             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3515             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3516                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3517         }
3518         if ((vars->ieee_fc &
3519             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3520             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3521                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3522         }
3523         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3524         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3525 }
3526
3527 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3528 {                                               /*  LD      LP   */
3529         switch (pause_result) {                 /* ASYM P ASYM P */
3530         case 0xb:                               /*   1  0   1  1 */
3531                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3532                 break;
3533
3534         case 0xe:                               /*   1  1   1  0 */
3535                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3536                 break;
3537
3538         case 0x5:                               /*   0  1   0  1 */
3539         case 0x7:                               /*   0  1   1  1 */
3540         case 0xd:                               /*   1  1   0  1 */
3541         case 0xf:                               /*   1  1   1  1 */
3542                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3543                 break;
3544
3545         default:
3546                 break;
3547         }
3548         if (pause_result & (1<<0))
3549                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3550         if (pause_result & (1<<1))
3551                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3552
3553 }
3554
3555 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3556                                         struct link_params *params,
3557                                         struct link_vars *vars)
3558 {
3559         u16 ld_pause;           /* local */
3560         u16 lp_pause;           /* link partner */
3561         u16 pause_result;
3562         struct bnx2x *bp = params->bp;
3563         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3564                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3565                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3566         } else if (CHIP_IS_E3(bp) &&
3567                 SINGLE_MEDIA_DIRECT(params)) {
3568                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3569                 u16 gp_status, gp_mask;
3570                 bnx2x_cl45_read(bp, phy,
3571                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3572                                 &gp_status);
3573                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3574                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3575                         lane;
3576                 if ((gp_status & gp_mask) == gp_mask) {
3577                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3578                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3579                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3580                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3581                 } else {
3582                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3583                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3584                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3585                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3586                         ld_pause = ((ld_pause &
3587                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3588                                     << 3);
3589                         lp_pause = ((lp_pause &
3590                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3591                                     << 3);
3592                 }
3593         } else {
3594                 bnx2x_cl45_read(bp, phy,
3595                                 MDIO_AN_DEVAD,
3596                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3597                 bnx2x_cl45_read(bp, phy,
3598                                 MDIO_AN_DEVAD,
3599                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3600         }
3601         pause_result = (ld_pause &
3602                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3603         pause_result |= (lp_pause &
3604                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3605         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3606         bnx2x_pause_resolve(vars, pause_result);
3607
3608 }
3609
3610 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3611                                    struct link_params *params,
3612                                    struct link_vars *vars)
3613 {
3614         u8 ret = 0;
3615         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3616         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3617                 /* Update the advertised flow-controled of LD/LP in AN */
3618                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3619                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3620                 /* But set the flow-control result as the requested one */
3621                 vars->flow_ctrl = phy->req_flow_ctrl;
3622         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3623                 vars->flow_ctrl = params->req_fc_auto_adv;
3624         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3625                 ret = 1;
3626                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3627         }
3628         return ret;
3629 }
3630 /******************************************************************/
3631 /*                      Warpcore section                          */
3632 /******************************************************************/
3633 /* The init_internal_warpcore should mirror the xgxs,
3634  * i.e. reset the lane (if needed), set aer for the
3635  * init configuration, and set/clear SGMII flag. Internal
3636  * phy init is done purely in phy_init stage.
3637  */
3638 #define WC_TX_DRIVER(post2, idriver, ipre) \
3639         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3640          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3641          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3642
3643 #define WC_TX_FIR(post, main, pre) \
3644         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3645          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3646          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3647
3648 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3649                                          struct link_params *params,
3650                                          struct link_vars *vars)
3651 {
3652         struct bnx2x *bp = params->bp;
3653         u16 i;
3654         static struct bnx2x_reg_set reg_set[] = {
3655                 /* Step 1 - Program the TX/RX alignment markers */
3656                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3662                 /* Step 2 - Configure the NP registers */
3663                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3672         };
3673         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3674
3675         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3676                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3677
3678         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3679                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3680                                  reg_set[i].val);
3681
3682         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3683         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3684         bnx2x_update_link_attr(params, vars->link_attr_sync);
3685 }
3686
3687 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3688                                                struct link_params *params)
3689 {
3690         struct bnx2x *bp = params->bp;
3691
3692         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3693         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3694                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3695         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3696                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3697 }
3698
3699 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3700                                          struct link_params *params)
3701 {
3702         /* Restart autoneg on the leading lane only */
3703         struct bnx2x *bp = params->bp;
3704         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3705         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3706                           MDIO_AER_BLOCK_AER_REG, lane);
3707         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3708                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3709
3710         /* Restore AER */
3711         bnx2x_set_aer_mmd(params, phy);
3712 }
3713
3714 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3715                                         struct link_params *params,
3716                                         struct link_vars *vars) {
3717         u16 lane, i, cl72_ctrl, an_adv = 0;
3718         u16 ucode_ver;
3719         struct bnx2x *bp = params->bp;
3720         static struct bnx2x_reg_set reg_set[] = {
3721                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3722                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3723                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3724                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3725                 /* Disable Autoneg: re-enable it after adv is done. */
3726                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3727                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3728                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3729         };
3730         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3731         /* Set to default registers that may be overriden by 10G force */
3732         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3733                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3734                                  reg_set[i].val);
3735
3736         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3737                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3738         cl72_ctrl &= 0x08ff;
3739         cl72_ctrl |= 0x3800;
3740         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3741                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3742
3743         /* Check adding advertisement for 1G KX */
3744         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3745              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3746             (vars->line_speed == SPEED_1000)) {
3747                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3748                 an_adv |= (1<<5);
3749
3750                 /* Enable CL37 1G Parallel Detect */
3751                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3752                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3753         }
3754         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3755              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3756             (vars->line_speed ==  SPEED_10000)) {
3757                 /* Check adding advertisement for 10G KR */
3758                 an_adv |= (1<<7);
3759                 /* Enable 10G Parallel Detect */
3760                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3761                                   MDIO_AER_BLOCK_AER_REG, 0);
3762
3763                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3764                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3765                 bnx2x_set_aer_mmd(params, phy);
3766                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3767         }
3768
3769         /* Set Transmit PMD settings */
3770         lane = bnx2x_get_warpcore_lane(phy, params);
3771         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3772                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3773                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3774         /* Configure the next lane if dual mode */
3775         if (phy->flags & FLAGS_WC_DUAL_MODE)
3776                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3777                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3778                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3779         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3780                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3781                          0x03f0);
3782         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3783                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3784                          0x03f0);
3785
3786         /* Advertised speeds */
3787         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3788                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3789
3790         /* Advertised and set FEC (Forward Error Correction) */
3791         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3792                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3793                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3794                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3795
3796         /* Enable CL37 BAM */
3797         if (REG_RD(bp, params->shmem_base +
3798                    offsetof(struct shmem_region, dev_info.
3799                             port_hw_config[params->port].default_cfg)) &
3800             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3801                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3802                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3803                                          1);
3804                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3805         }
3806
3807         /* Advertise pause */
3808         bnx2x_ext_phy_set_pause(params, phy, vars);
3809         /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3810          */
3811         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3812                         MDIO_WC_REG_UC_INFO_B1_VERSION, &ucode_ver);
3813         if (ucode_ver < 0xd108) {
3814                 DP(NETIF_MSG_LINK, "Enable AN KR work-around. WC ver:0x%x\n",
3815                                ucode_ver);
3816                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3817         }
3818         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3819                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3820
3821         /* Over 1G - AN local device user page 1 */
3822         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3823                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3824
3825         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3826              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3827             (phy->req_line_speed == SPEED_20000)) {
3828
3829                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3830                                   MDIO_AER_BLOCK_AER_REG, lane);
3831
3832                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3833                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3834                                          (1<<11));
3835
3836                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3838                 bnx2x_set_aer_mmd(params, phy);
3839
3840                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3841         }
3842
3843         /* Enable Autoneg: only on the main lane */
3844         bnx2x_warpcore_restart_AN_KR(phy, params);
3845 }
3846
3847 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3848                                       struct link_params *params,
3849                                       struct link_vars *vars)
3850 {
3851         struct bnx2x *bp = params->bp;
3852         u16 val16, i, lane;
3853         static struct bnx2x_reg_set reg_set[] = {
3854                 /* Disable Autoneg */
3855                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3856                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3857                         0x3f00},
3858                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3859                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3860                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3861                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3862                 /* Leave cl72 training enable, needed for KR */
3863                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3864         };
3865
3866         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3867                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3868                                  reg_set[i].val);
3869
3870         lane = bnx2x_get_warpcore_lane(phy, params);
3871         /* Global registers */
3872         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3873                           MDIO_AER_BLOCK_AER_REG, 0);
3874         /* Disable CL36 PCS Tx */
3875         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3876                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3877         val16 &= ~(0x0011 << lane);
3878         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3879                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3880
3881         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3882                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3883         val16 |= (0x0303 << (lane << 1));
3884         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3885                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3886         /* Restore AER */
3887         bnx2x_set_aer_mmd(params, phy);
3888         /* Set speed via PMA/PMD register */
3889         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3890                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3891
3892         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3893                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3894
3895         /* Enable encoded forced speed */
3896         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3897                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3898
3899         /* Turn TX scramble payload only the 64/66 scrambler */
3900         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3901                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3902
3903         /* Turn RX scramble payload only the 64/66 scrambler */
3904         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3905                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3906
3907         /* Set and clear loopback to cause a reset to 64/66 decoder */
3908         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3909                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3910         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3911                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3912
3913 }
3914
3915 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3916                                        struct link_params *params,
3917                                        u8 is_xfi)
3918 {
3919         struct bnx2x *bp = params->bp;
3920         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3921         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3922
3923         /* Hold rxSeqStart */
3924         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3925                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3926
3927         /* Hold tx_fifo_reset */
3928         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3929                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3930
3931         /* Disable CL73 AN */
3932         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3933
3934         /* Disable 100FX Enable and Auto-Detect */
3935         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3936                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3937
3938         /* Disable 100FX Idle detect */
3939         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3940                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3941
3942         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3943         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3944                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3945
3946         /* Turn off auto-detect & fiber mode */
3947         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3948                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3949                                   0xFFEE);
3950
3951         /* Set filter_force_link, disable_false_link and parallel_detect */
3952         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3953                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3954         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3955                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3956                          ((val | 0x0006) & 0xFFFE));
3957
3958         /* Set XFI / SFI */
3959         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3960                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3961
3962         misc1_val &= ~(0x1f);
3963
3964         if (is_xfi) {
3965                 misc1_val |= 0x5;
3966                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3967                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3968         } else {
3969                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3970                                      offsetof(struct shmem_region, dev_info.
3971                                               port_hw_config[params->port].
3972                                               sfi_tap_values));
3973
3974                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
3975
3976                 tx_drv_brdct = (cfg_tap_val &
3977                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
3978                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
3979
3980                 misc1_val |= 0x9;
3981
3982                 /* TAP values are controlled by nvram, if value there isn't 0 */
3983                 if (tx_equal)
3984                         tap_val = (u16)tx_equal;
3985                 else
3986                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
3987
3988                 if (tx_drv_brdct)
3989                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
3990                                                      0x06);
3991                 else
3992                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
3993         }
3994         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3995                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3996
3997         /* Set Transmit PMD settings */
3998         lane = bnx2x_get_warpcore_lane(phy, params);
3999         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4000                          MDIO_WC_REG_TX_FIR_TAP,
4001                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4002         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4003                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4004                          tx_driver_val);
4005
4006         /* Enable fiber mode, enable and invert sig_det */
4007         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4008                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4009
4010         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4011         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4012                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4013
4014         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4015
4016         /* 10G XFI Full Duplex */
4017         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4018                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4019
4020         /* Release tx_fifo_reset */
4021         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4022                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4023                                   0xFFFE);
4024         /* Release rxSeqStart */
4025         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4026                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4027 }
4028
4029 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4030                                              struct link_params *params)
4031 {
4032         u16 val;
4033         struct bnx2x *bp = params->bp;
4034         /* Set global registers, so set AER lane to 0 */
4035         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4036                           MDIO_AER_BLOCK_AER_REG, 0);
4037
4038         /* Disable sequencer */
4039         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4040                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4041
4042         bnx2x_set_aer_mmd(params, phy);
4043
4044         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4045                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4046         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4047                          MDIO_AN_REG_CTRL, 0);
4048         /* Turn off CL73 */
4049         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4050                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4051         val &= ~(1<<5);
4052         val |= (1<<6);
4053         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4054                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4055
4056         /* Set 20G KR2 force speed */
4057         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4058                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4059
4060         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4061                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4062
4063         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4064                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4065         val &= ~(3<<14);
4066         val |= (1<<15);
4067         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4068                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4069         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4070                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4071
4072         /* Enable sequencer (over lane 0) */
4073         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4074                           MDIO_AER_BLOCK_AER_REG, 0);
4075
4076         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4077                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4078
4079         bnx2x_set_aer_mmd(params, phy);
4080 }
4081
4082 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4083                                          struct bnx2x_phy *phy,
4084                                          u16 lane)
4085 {
4086         /* Rx0 anaRxControl1G */
4087         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4088                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4089
4090         /* Rx2 anaRxControl1G */
4091         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4092                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4093
4094         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4095                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4096
4097         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4098                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4099
4100         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4101                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4102
4103         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4104                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4105
4106         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4107                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4108
4109         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4110                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4111
4112         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4113                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4114
4115         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4117
4118         /* Serdes Digital Misc1 */
4119         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4120                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4121
4122         /* Serdes Digital4 Misc3 */
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4125
4126         /* Set Transmit PMD settings */
4127         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4128                          MDIO_WC_REG_TX_FIR_TAP,
4129                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4130                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4131         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4133                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4134 }
4135
4136 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4137                                            struct link_params *params,
4138                                            u8 fiber_mode,
4139                                            u8 always_autoneg)
4140 {
4141         struct bnx2x *bp = params->bp;
4142         u16 val16, digctrl_kx1, digctrl_kx2;
4143
4144         /* Clear XFI clock comp in non-10G single lane mode. */
4145         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4146                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4147
4148         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4149
4150         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4151                 /* SGMII Autoneg */
4152                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4153                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4154                                          0x1000);
4155                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4156         } else {
4157                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4158                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4159                 val16 &= 0xcebf;
4160                 switch (phy->req_line_speed) {
4161                 case SPEED_10:
4162                         break;
4163                 case SPEED_100:
4164                         val16 |= 0x2000;
4165                         break;
4166                 case SPEED_1000:
4167                         val16 |= 0x0040;
4168                         break;
4169                 default:
4170                         DP(NETIF_MSG_LINK,
4171                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4172                         return;
4173                 }
4174
4175                 if (phy->req_duplex == DUPLEX_FULL)
4176                         val16 |= 0x0100;
4177
4178                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4179                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4180
4181                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4182                                phy->req_line_speed);
4183                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4184                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4185                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4186         }
4187
4188         /* SGMII Slave mode and disable signal detect */
4189         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4190                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4191         if (fiber_mode)
4192                 digctrl_kx1 = 1;
4193         else
4194                 digctrl_kx1 &= 0xff4a;
4195
4196         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4197                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4198                         digctrl_kx1);
4199
4200         /* Turn off parallel detect */
4201         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4202                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4203         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4204                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4205                         (digctrl_kx2 & ~(1<<2)));
4206
4207         /* Re-enable parallel detect */
4208         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4209                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4210                         (digctrl_kx2 | (1<<2)));
4211
4212         /* Enable autodet */
4213         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4214                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4215                         (digctrl_kx1 | 0x10));
4216 }
4217
4218 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4219                                       struct bnx2x_phy *phy,
4220                                       u8 reset)
4221 {
4222         u16 val;
4223         /* Take lane out of reset after configuration is finished */
4224         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4225                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4226         if (reset)
4227                 val |= 0xC000;
4228         else
4229                 val &= 0x3FFF;
4230         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4231                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4232         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4233                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4234 }
4235 /* Clear SFI/XFI link settings registers */
4236 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4237                                       struct link_params *params,
4238                                       u16 lane)
4239 {
4240         struct bnx2x *bp = params->bp;
4241         u16 i;
4242         static struct bnx2x_reg_set wc_regs[] = {
4243                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4244                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4245                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4246                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4247                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4248                         0x0195},
4249                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4250                         0x0007},
4251                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4252                         0x0002},
4253                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4254                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4255                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4256                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4257         };
4258         /* Set XFI clock comp as default. */
4259         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4260                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4261
4262         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4263                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4264                                  wc_regs[i].val);
4265
4266         lane = bnx2x_get_warpcore_lane(phy, params);
4267         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4268                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4269
4270 }
4271
4272 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4273                                                 u32 chip_id,
4274                                                 u32 shmem_base, u8 port,
4275                                                 u8 *gpio_num, u8 *gpio_port)
4276 {
4277         u32 cfg_pin;
4278         *gpio_num = 0;
4279         *gpio_port = 0;
4280         if (CHIP_IS_E3(bp)) {
4281                 cfg_pin = (REG_RD(bp, shmem_base +
4282                                 offsetof(struct shmem_region,
4283                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4284                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4285                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4286
4287                 /* Should not happen. This function called upon interrupt
4288                  * triggered by GPIO ( since EPIO can only generate interrupts
4289                  * to MCP).
4290                  * So if this function was called and none of the GPIOs was set,
4291                  * it means the shit hit the fan.
4292                  */
4293                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4294                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4295                         DP(NETIF_MSG_LINK,
4296                            "No cfg pin %x for module detect indication\n",
4297                            cfg_pin);
4298                         return -EINVAL;
4299                 }
4300
4301                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4302                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4303         } else {
4304                 *gpio_num = MISC_REGISTERS_GPIO_3;
4305                 *gpio_port = port;
4306         }
4307
4308         return 0;
4309 }
4310
4311 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4312                                        struct link_params *params)
4313 {
4314         struct bnx2x *bp = params->bp;
4315         u8 gpio_num, gpio_port;
4316         u32 gpio_val;
4317         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4318                                       params->shmem_base, params->port,
4319                                       &gpio_num, &gpio_port) != 0)
4320                 return 0;
4321         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4322
4323         /* Call the handling function in case module is detected */
4324         if (gpio_val == 0)
4325                 return 1;
4326         else
4327                 return 0;
4328 }
4329 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4330                                      struct link_params *params)
4331 {
4332         u16 gp2_status_reg0, lane;
4333         struct bnx2x *bp = params->bp;
4334
4335         lane = bnx2x_get_warpcore_lane(phy, params);
4336
4337         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4338                                  &gp2_status_reg0);
4339
4340         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4341 }
4342
4343 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4344                                           struct link_params *params,
4345                                           struct link_vars *vars)
4346 {
4347         struct bnx2x *bp = params->bp;
4348         u32 serdes_net_if;
4349         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4350         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4351
4352         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4353
4354         if (!vars->turn_to_run_wc_rt)
4355                 return;
4356
4357         /* Return if there is no link partner */
4358         if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4359                 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4360                 return;
4361         }
4362
4363         if (vars->rx_tx_asic_rst) {
4364                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4365                                 offsetof(struct shmem_region, dev_info.
4366                                 port_hw_config[params->port].default_cfg)) &
4367                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4368
4369                 switch (serdes_net_if) {
4370                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4371                         /* Do we get link yet? */
4372                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4373                                         &gp_status1);
4374                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4375                                 /*10G KR*/
4376                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4377
4378                         DP(NETIF_MSG_LINK,
4379                                 "gp_status1 0x%x\n", gp_status1);
4380
4381                         if (lnkup_kr || lnkup) {
4382                                         vars->rx_tx_asic_rst = 0;
4383                                         DP(NETIF_MSG_LINK,
4384                                         "link up, rx_tx_asic_rst 0x%x\n",
4385                                         vars->rx_tx_asic_rst);
4386                         } else {
4387                                 /* Reset the lane to see if link comes up.*/
4388                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4389                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4390
4391                                 /* Restart Autoneg */
4392                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4393                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4394
4395                                 vars->rx_tx_asic_rst--;
4396                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4397                                 vars->rx_tx_asic_rst);
4398                         }
4399                         break;
4400
4401                 default:
4402                         break;
4403                 }
4404
4405         } /*params->rx_tx_asic_rst*/
4406
4407 }
4408 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4409                                       struct link_params *params)
4410 {
4411         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4412         struct bnx2x *bp = params->bp;
4413         bnx2x_warpcore_clear_regs(phy, params, lane);
4414         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4415              SPEED_10000) &&
4416             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4417                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4418                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4419         } else {
4420                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4421                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4422         }
4423 }
4424
4425 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4426                                          struct bnx2x_phy *phy,
4427                                          u8 tx_en)
4428 {
4429         struct bnx2x *bp = params->bp;
4430         u32 cfg_pin;
4431         u8 port = params->port;
4432
4433         cfg_pin = REG_RD(bp, params->shmem_base +
4434                          offsetof(struct shmem_region,
4435                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4436                 PORT_HW_CFG_E3_TX_LASER_MASK;
4437         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4438         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4439
4440         /* For 20G, the expected pin to be used is 3 pins after the current */
4441         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4442         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4443                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4444 }
4445
4446 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4447                                        struct link_params *params,
4448                                        struct link_vars *vars)
4449 {
4450         struct bnx2x *bp = params->bp;
4451         u32 serdes_net_if;
4452         u8 fiber_mode;
4453         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4454         serdes_net_if = (REG_RD(bp, params->shmem_base +
4455                          offsetof(struct shmem_region, dev_info.
4456                                   port_hw_config[params->port].default_cfg)) &
4457                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4458         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4459                            "serdes_net_if = 0x%x\n",
4460                        vars->line_speed, serdes_net_if);
4461         bnx2x_set_aer_mmd(params, phy);
4462         bnx2x_warpcore_reset_lane(bp, phy, 1);
4463         vars->phy_flags |= PHY_XGXS_FLAG;
4464         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4465             (phy->req_line_speed &&
4466              ((phy->req_line_speed == SPEED_100) ||
4467               (phy->req_line_speed == SPEED_10)))) {
4468                 vars->phy_flags |= PHY_SGMII_FLAG;
4469                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4470                 bnx2x_warpcore_clear_regs(phy, params, lane);
4471                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4472         } else {
4473                 switch (serdes_net_if) {
4474                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4475                         /* Enable KR Auto Neg */
4476                         if (params->loopback_mode != LOOPBACK_EXT)
4477                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4478                         else {
4479                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4480                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4481                         }
4482                         break;
4483
4484                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4485                         bnx2x_warpcore_clear_regs(phy, params, lane);
4486                         if (vars->line_speed == SPEED_10000) {
4487                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4488                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4489                         } else {
4490                                 if (SINGLE_MEDIA_DIRECT(params)) {
4491                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4492                                         fiber_mode = 1;
4493                                 } else {
4494                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4495                                         fiber_mode = 0;
4496                                 }
4497                                 bnx2x_warpcore_set_sgmii_speed(phy,
4498                                                                 params,
4499                                                                 fiber_mode,
4500                                                                 0);
4501                         }
4502
4503                         break;
4504
4505                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4506                         /* Issue Module detection if module is plugged, or
4507                          * enabled transmitter to avoid current leakage in case
4508                          * no module is connected
4509                          */
4510                         if (bnx2x_is_sfp_module_plugged(phy, params))
4511                                 bnx2x_sfp_module_detection(phy, params);
4512                         else
4513                                 bnx2x_sfp_e3_set_transmitter(params, phy, 1);
4514
4515                         bnx2x_warpcore_config_sfi(phy, params);
4516                         break;
4517
4518                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4519                         if (vars->line_speed != SPEED_20000) {
4520                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4521                                 return;
4522                         }
4523                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4524                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4525                         /* Issue Module detection */
4526
4527                         bnx2x_sfp_module_detection(phy, params);
4528                         break;
4529                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4530                         if (!params->loopback_mode) {
4531                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4532                         } else {
4533                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4534                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4535                         }
4536                         break;
4537                 default:
4538                         DP(NETIF_MSG_LINK,
4539                            "Unsupported Serdes Net Interface 0x%x\n",
4540                            serdes_net_if);
4541                         return;
4542                 }
4543         }
4544
4545         /* Take lane out of reset after configuration is finished */
4546         bnx2x_warpcore_reset_lane(bp, phy, 0);
4547         DP(NETIF_MSG_LINK, "Exit config init\n");
4548 }
4549
4550 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4551                                       struct link_params *params)
4552 {
4553         struct bnx2x *bp = params->bp;
4554         u16 val16, lane;
4555         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4556         bnx2x_set_mdio_emac_per_phy(bp, params);
4557         bnx2x_set_aer_mmd(params, phy);
4558         /* Global register */
4559         bnx2x_warpcore_reset_lane(bp, phy, 1);
4560
4561         /* Clear loopback settings (if any) */
4562         /* 10G & 20G */
4563         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4564                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4565
4566         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4567                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4568
4569         /* Update those 1-copy registers */
4570         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4571                           MDIO_AER_BLOCK_AER_REG, 0);
4572         /* Enable 1G MDIO (1-copy) */
4573         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4574                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4575                                   ~0x10);
4576
4577         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4578                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4579         lane = bnx2x_get_warpcore_lane(phy, params);
4580         /* Disable CL36 PCS Tx */
4581         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4582                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4583         val16 |= (0x11 << lane);
4584         if (phy->flags & FLAGS_WC_DUAL_MODE)
4585                 val16 |= (0x22 << lane);
4586         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4587                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4588
4589         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4590                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4591         val16 &= ~(0x0303 << (lane << 1));
4592         val16 |= (0x0101 << (lane << 1));
4593         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4594                 val16 &= ~(0x0c0c << (lane << 1));
4595                 val16 |= (0x0404 << (lane << 1));
4596         }
4597
4598         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4599                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4600         /* Restore AER */
4601         bnx2x_set_aer_mmd(params, phy);
4602
4603 }
4604
4605 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4606                                         struct link_params *params)
4607 {
4608         struct bnx2x *bp = params->bp;
4609         u16 val16;
4610         u32 lane;
4611         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4612                        params->loopback_mode, phy->req_line_speed);
4613
4614         if (phy->req_line_speed < SPEED_10000 ||
4615             phy->supported & SUPPORTED_20000baseKR2_Full) {
4616                 /* 10/100/1000/20G-KR2 */
4617
4618                 /* Update those 1-copy registers */
4619                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4620                                   MDIO_AER_BLOCK_AER_REG, 0);
4621                 /* Enable 1G MDIO (1-copy) */
4622                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4623                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4624                                          0x10);
4625                 /* Set 1G loopback based on lane (1-copy) */
4626                 lane = bnx2x_get_warpcore_lane(phy, params);
4627                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4628                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4629                 val16 |= (1<<lane);
4630                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4631                         val16 |= (2<<lane);
4632                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4633                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4634                                  val16);
4635
4636                 /* Switch back to 4-copy registers */
4637                 bnx2x_set_aer_mmd(params, phy);
4638         } else {
4639                 /* 10G / 20G-DXGXS */
4640                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4641                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4642                                          0x4000);
4643                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4644                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4645         }
4646 }
4647
4648
4649
4650 static void bnx2x_sync_link(struct link_params *params,
4651                              struct link_vars *vars)
4652 {
4653         struct bnx2x *bp = params->bp;
4654         u8 link_10g_plus;
4655         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4656                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4657         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4658         if (vars->link_up) {
4659                 DP(NETIF_MSG_LINK, "phy link up\n");
4660
4661                 vars->phy_link_up = 1;
4662                 vars->duplex = DUPLEX_FULL;
4663                 switch (vars->link_status &
4664                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4665                 case LINK_10THD:
4666                         vars->duplex = DUPLEX_HALF;
4667                         /* Fall thru */
4668                 case LINK_10TFD:
4669                         vars->line_speed = SPEED_10;
4670                         break;
4671
4672                 case LINK_100TXHD:
4673                         vars->duplex = DUPLEX_HALF;
4674                         /* Fall thru */
4675                 case LINK_100T4:
4676                 case LINK_100TXFD:
4677                         vars->line_speed = SPEED_100;
4678                         break;
4679
4680                 case LINK_1000THD:
4681                         vars->duplex = DUPLEX_HALF;
4682                         /* Fall thru */
4683                 case LINK_1000TFD:
4684                         vars->line_speed = SPEED_1000;
4685                         break;
4686
4687                 case LINK_2500THD:
4688                         vars->duplex = DUPLEX_HALF;
4689                         /* Fall thru */
4690                 case LINK_2500TFD:
4691                         vars->line_speed = SPEED_2500;
4692                         break;
4693
4694                 case LINK_10GTFD:
4695                         vars->line_speed = SPEED_10000;
4696                         break;
4697                 case LINK_20GTFD:
4698                         vars->line_speed = SPEED_20000;
4699                         break;
4700                 default:
4701                         break;
4702                 }
4703                 vars->flow_ctrl = 0;
4704                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4705                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4706
4707                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4708                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4709
4710                 if (!vars->flow_ctrl)
4711                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4712
4713                 if (vars->line_speed &&
4714                     ((vars->line_speed == SPEED_10) ||
4715                      (vars->line_speed == SPEED_100))) {
4716                         vars->phy_flags |= PHY_SGMII_FLAG;
4717                 } else {
4718                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4719                 }
4720                 if (vars->line_speed &&
4721                     USES_WARPCORE(bp) &&
4722                     (vars->line_speed == SPEED_1000))
4723                         vars->phy_flags |= PHY_SGMII_FLAG;
4724                 /* Anything 10 and over uses the bmac */
4725                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4726
4727                 if (link_10g_plus) {
4728                         if (USES_WARPCORE(bp))
4729                                 vars->mac_type = MAC_TYPE_XMAC;
4730                         else
4731                                 vars->mac_type = MAC_TYPE_BMAC;
4732                 } else {
4733                         if (USES_WARPCORE(bp))
4734                                 vars->mac_type = MAC_TYPE_UMAC;
4735                         else
4736                                 vars->mac_type = MAC_TYPE_EMAC;
4737                 }
4738         } else { /* Link down */
4739                 DP(NETIF_MSG_LINK, "phy link down\n");
4740
4741                 vars->phy_link_up = 0;
4742
4743                 vars->line_speed = 0;
4744                 vars->duplex = DUPLEX_FULL;
4745                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4746
4747                 /* Indicate no mac active */
4748                 vars->mac_type = MAC_TYPE_NONE;
4749                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4750                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4751                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4752                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4753         }
4754 }
4755
4756 void bnx2x_link_status_update(struct link_params *params,
4757                               struct link_vars *vars)
4758 {
4759         struct bnx2x *bp = params->bp;
4760         u8 port = params->port;
4761         u32 sync_offset, media_types;
4762         /* Update PHY configuration */
4763         set_phy_vars(params, vars);
4764
4765         vars->link_status = REG_RD(bp, params->shmem_base +
4766                                    offsetof(struct shmem_region,
4767                                             port_mb[port].link_status));
4768
4769         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4770         if (params->loopback_mode != LOOPBACK_NONE &&
4771             params->loopback_mode != LOOPBACK_EXT)
4772                 vars->link_status |= LINK_STATUS_LINK_UP;
4773
4774         if (bnx2x_eee_has_cap(params))
4775                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4776                                           offsetof(struct shmem2_region,
4777                                                    eee_status[params->port]));
4778
4779         vars->phy_flags = PHY_XGXS_FLAG;
4780         bnx2x_sync_link(params, vars);
4781         /* Sync media type */
4782         sync_offset = params->shmem_base +
4783                         offsetof(struct shmem_region,
4784                                  dev_info.port_hw_config[port].media_type);
4785         media_types = REG_RD(bp, sync_offset);
4786
4787         params->phy[INT_PHY].media_type =
4788                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4789                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4790         params->phy[EXT_PHY1].media_type =
4791                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4792                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4793         params->phy[EXT_PHY2].media_type =
4794                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4795                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4796         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4797
4798         /* Sync AEU offset */
4799         sync_offset = params->shmem_base +
4800                         offsetof(struct shmem_region,
4801                                  dev_info.port_hw_config[port].aeu_int_mask);
4802
4803         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4804
4805         /* Sync PFC status */
4806         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4807                 params->feature_config_flags |=
4808                                         FEATURE_CONFIG_PFC_ENABLED;
4809         else
4810                 params->feature_config_flags &=
4811                                         ~FEATURE_CONFIG_PFC_ENABLED;
4812
4813         if (SHMEM2_HAS(bp, link_attr_sync))
4814                 vars->link_attr_sync = SHMEM2_RD(bp,
4815                                                  link_attr_sync[params->port]);
4816
4817         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4818                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4819         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4820                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4821 }
4822
4823 static void bnx2x_set_master_ln(struct link_params *params,
4824                                 struct bnx2x_phy *phy)
4825 {
4826         struct bnx2x *bp = params->bp;
4827         u16 new_master_ln, ser_lane;
4828         ser_lane = ((params->lane_config &
4829                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4830                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4831
4832         /* Set the master_ln for AN */
4833         CL22_RD_OVER_CL45(bp, phy,
4834                           MDIO_REG_BANK_XGXS_BLOCK2,
4835                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4836                           &new_master_ln);
4837
4838         CL22_WR_OVER_CL45(bp, phy,
4839                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4840                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4841                           (new_master_ln | ser_lane));
4842 }
4843
4844 static int bnx2x_reset_unicore(struct link_params *params,
4845                                struct bnx2x_phy *phy,
4846                                u8 set_serdes)
4847 {
4848         struct bnx2x *bp = params->bp;
4849         u16 mii_control;
4850         u16 i;
4851         CL22_RD_OVER_CL45(bp, phy,
4852                           MDIO_REG_BANK_COMBO_IEEE0,
4853                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4854
4855         /* Reset the unicore */
4856         CL22_WR_OVER_CL45(bp, phy,
4857                           MDIO_REG_BANK_COMBO_IEEE0,
4858                           MDIO_COMBO_IEEE0_MII_CONTROL,
4859                           (mii_control |
4860                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4861         if (set_serdes)
4862                 bnx2x_set_serdes_access(bp, params->port);
4863
4864         /* Wait for the reset to self clear */
4865         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4866                 udelay(5);
4867
4868                 /* The reset erased the previous bank value */
4869                 CL22_RD_OVER_CL45(bp, phy,
4870                                   MDIO_REG_BANK_COMBO_IEEE0,
4871                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4872                                   &mii_control);
4873
4874                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4875                         udelay(5);
4876                         return 0;
4877                 }
4878         }
4879
4880         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4881                               " Port %d\n",
4882                          params->port);
4883         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4884         return -EINVAL;
4885
4886 }
4887
4888 static void bnx2x_set_swap_lanes(struct link_params *params,
4889                                  struct bnx2x_phy *phy)
4890 {
4891         struct bnx2x *bp = params->bp;
4892         /* Each two bits represents a lane number:
4893          * No swap is 0123 => 0x1b no need to enable the swap
4894          */
4895         u16 rx_lane_swap, tx_lane_swap;
4896
4897         rx_lane_swap = ((params->lane_config &
4898                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4899                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4900         tx_lane_swap = ((params->lane_config &
4901                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4902                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4903
4904         if (rx_lane_swap != 0x1b) {
4905                 CL22_WR_OVER_CL45(bp, phy,
4906                                   MDIO_REG_BANK_XGXS_BLOCK2,
4907                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4908                                   (rx_lane_swap |
4909                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4910                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4911         } else {
4912                 CL22_WR_OVER_CL45(bp, phy,
4913                                   MDIO_REG_BANK_XGXS_BLOCK2,
4914                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4915         }
4916
4917         if (tx_lane_swap != 0x1b) {
4918                 CL22_WR_OVER_CL45(bp, phy,
4919                                   MDIO_REG_BANK_XGXS_BLOCK2,
4920                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4921                                   (tx_lane_swap |
4922                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4923         } else {
4924                 CL22_WR_OVER_CL45(bp, phy,
4925                                   MDIO_REG_BANK_XGXS_BLOCK2,
4926                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4927         }
4928 }
4929
4930 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4931                                          struct link_params *params)
4932 {
4933         struct bnx2x *bp = params->bp;
4934         u16 control2;
4935         CL22_RD_OVER_CL45(bp, phy,
4936                           MDIO_REG_BANK_SERDES_DIGITAL,
4937                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4938                           &control2);
4939         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4940                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4941         else
4942                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4943         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4944                 phy->speed_cap_mask, control2);
4945         CL22_WR_OVER_CL45(bp, phy,
4946                           MDIO_REG_BANK_SERDES_DIGITAL,
4947                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4948                           control2);
4949
4950         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4951              (phy->speed_cap_mask &
4952                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4953                 DP(NETIF_MSG_LINK, "XGXS\n");
4954
4955                 CL22_WR_OVER_CL45(bp, phy,
4956                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4957                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4958                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4959
4960                 CL22_RD_OVER_CL45(bp, phy,
4961                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4962                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4963                                   &control2);
4964
4965
4966                 control2 |=
4967                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4968
4969                 CL22_WR_OVER_CL45(bp, phy,
4970                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4971                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4972                                   control2);
4973
4974                 /* Disable parallel detection of HiG */
4975                 CL22_WR_OVER_CL45(bp, phy,
4976                                   MDIO_REG_BANK_XGXS_BLOCK2,
4977                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4978                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4979                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4980         }
4981 }
4982
4983 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4984                               struct link_params *params,
4985                               struct link_vars *vars,
4986                               u8 enable_cl73)
4987 {
4988         struct bnx2x *bp = params->bp;
4989         u16 reg_val;
4990
4991         /* CL37 Autoneg */
4992         CL22_RD_OVER_CL45(bp, phy,
4993                           MDIO_REG_BANK_COMBO_IEEE0,
4994                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4995
4996         /* CL37 Autoneg Enabled */
4997         if (vars->line_speed == SPEED_AUTO_NEG)
4998                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4999         else /* CL37 Autoneg Disabled */
5000                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5001                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5002
5003         CL22_WR_OVER_CL45(bp, phy,
5004                           MDIO_REG_BANK_COMBO_IEEE0,
5005                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5006
5007         /* Enable/Disable Autodetection */
5008
5009         CL22_RD_OVER_CL45(bp, phy,
5010                           MDIO_REG_BANK_SERDES_DIGITAL,
5011                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5012         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5013                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5014         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5015         if (vars->line_speed == SPEED_AUTO_NEG)
5016                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5017         else
5018                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5019
5020         CL22_WR_OVER_CL45(bp, phy,
5021                           MDIO_REG_BANK_SERDES_DIGITAL,
5022                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5023
5024         /* Enable TetonII and BAM autoneg */
5025         CL22_RD_OVER_CL45(bp, phy,
5026                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5027                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5028                           &reg_val);
5029         if (vars->line_speed == SPEED_AUTO_NEG) {
5030                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5031                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5032                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5033         } else {
5034                 /* TetonII and BAM Autoneg Disabled */
5035                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5036                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5037         }
5038         CL22_WR_OVER_CL45(bp, phy,
5039                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5040                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5041                           reg_val);
5042
5043         if (enable_cl73) {
5044                 /* Enable Cl73 FSM status bits */
5045                 CL22_WR_OVER_CL45(bp, phy,
5046                                   MDIO_REG_BANK_CL73_USERB0,
5047                                   MDIO_CL73_USERB0_CL73_UCTRL,
5048                                   0xe);
5049
5050                 /* Enable BAM Station Manager*/
5051                 CL22_WR_OVER_CL45(bp, phy,
5052                         MDIO_REG_BANK_CL73_USERB0,
5053                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5054                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5055                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5056                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5057
5058                 /* Advertise CL73 link speeds */
5059                 CL22_RD_OVER_CL45(bp, phy,
5060                                   MDIO_REG_BANK_CL73_IEEEB1,
5061                                   MDIO_CL73_IEEEB1_AN_ADV2,
5062                                   &reg_val);
5063                 if (phy->speed_cap_mask &
5064                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5065                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5066                 if (phy->speed_cap_mask &
5067                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5068                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5069
5070                 CL22_WR_OVER_CL45(bp, phy,
5071                                   MDIO_REG_BANK_CL73_IEEEB1,
5072                                   MDIO_CL73_IEEEB1_AN_ADV2,
5073                                   reg_val);
5074
5075                 /* CL73 Autoneg Enabled */
5076                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5077
5078         } else /* CL73 Autoneg Disabled */
5079                 reg_val = 0;
5080
5081         CL22_WR_OVER_CL45(bp, phy,
5082                           MDIO_REG_BANK_CL73_IEEEB0,
5083                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5084 }
5085
5086 /* Program SerDes, forced speed */
5087 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5088                                  struct link_params *params,
5089                                  struct link_vars *vars)
5090 {
5091         struct bnx2x *bp = params->bp;
5092         u16 reg_val;
5093
5094         /* Program duplex, disable autoneg and sgmii*/
5095         CL22_RD_OVER_CL45(bp, phy,
5096                           MDIO_REG_BANK_COMBO_IEEE0,
5097                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5098         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5099                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5100                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5101         if (phy->req_duplex == DUPLEX_FULL)
5102                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5103         CL22_WR_OVER_CL45(bp, phy,
5104                           MDIO_REG_BANK_COMBO_IEEE0,
5105                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5106
5107         /* Program speed
5108          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5109          */
5110         CL22_RD_OVER_CL45(bp, phy,
5111                           MDIO_REG_BANK_SERDES_DIGITAL,
5112                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5113         /* Clearing the speed value before setting the right speed */
5114         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5115
5116         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5117                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5118
5119         if (!((vars->line_speed == SPEED_1000) ||
5120               (vars->line_speed == SPEED_100) ||
5121               (vars->line_speed == SPEED_10))) {
5122
5123                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5124                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5125                 if (vars->line_speed == SPEED_10000)
5126                         reg_val |=
5127                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5128         }
5129
5130         CL22_WR_OVER_CL45(bp, phy,
5131                           MDIO_REG_BANK_SERDES_DIGITAL,
5132                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5133
5134 }
5135
5136 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5137                                               struct link_params *params)
5138 {
5139         struct bnx2x *bp = params->bp;
5140         u16 val = 0;
5141
5142         /* Set extended capabilities */
5143         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5144                 val |= MDIO_OVER_1G_UP1_2_5G;
5145         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5146                 val |= MDIO_OVER_1G_UP1_10G;
5147         CL22_WR_OVER_CL45(bp, phy,
5148                           MDIO_REG_BANK_OVER_1G,
5149                           MDIO_OVER_1G_UP1, val);
5150
5151         CL22_WR_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_OVER_1G,
5153                           MDIO_OVER_1G_UP3, 0x400);
5154 }
5155
5156 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5157                                               struct link_params *params,
5158                                               u16 ieee_fc)
5159 {
5160         struct bnx2x *bp = params->bp;
5161         u16 val;
5162         /* For AN, we are always publishing full duplex */
5163
5164         CL22_WR_OVER_CL45(bp, phy,
5165                           MDIO_REG_BANK_COMBO_IEEE0,
5166                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5167         CL22_RD_OVER_CL45(bp, phy,
5168                           MDIO_REG_BANK_CL73_IEEEB1,
5169                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5170         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5171         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5172         CL22_WR_OVER_CL45(bp, phy,
5173                           MDIO_REG_BANK_CL73_IEEEB1,
5174                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5175 }
5176
5177 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5178                                   struct link_params *params,
5179                                   u8 enable_cl73)
5180 {
5181         struct bnx2x *bp = params->bp;
5182         u16 mii_control;
5183
5184         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5185         /* Enable and restart BAM/CL37 aneg */
5186
5187         if (enable_cl73) {
5188                 CL22_RD_OVER_CL45(bp, phy,
5189                                   MDIO_REG_BANK_CL73_IEEEB0,
5190                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5191                                   &mii_control);
5192
5193                 CL22_WR_OVER_CL45(bp, phy,
5194                                   MDIO_REG_BANK_CL73_IEEEB0,
5195                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5196                                   (mii_control |
5197                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5198                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5199         } else {
5200
5201                 CL22_RD_OVER_CL45(bp, phy,
5202                                   MDIO_REG_BANK_COMBO_IEEE0,
5203                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5204                                   &mii_control);
5205                 DP(NETIF_MSG_LINK,
5206                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5207                          mii_control);
5208                 CL22_WR_OVER_CL45(bp, phy,
5209                                   MDIO_REG_BANK_COMBO_IEEE0,
5210                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5211                                   (mii_control |
5212                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5213                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5214         }
5215 }
5216
5217 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5218                                            struct link_params *params,
5219                                            struct link_vars *vars)
5220 {
5221         struct bnx2x *bp = params->bp;
5222         u16 control1;
5223
5224         /* In SGMII mode, the unicore is always slave */
5225
5226         CL22_RD_OVER_CL45(bp, phy,
5227                           MDIO_REG_BANK_SERDES_DIGITAL,
5228                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5229                           &control1);
5230         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5231         /* Set sgmii mode (and not fiber) */
5232         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5233                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5234                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5235         CL22_WR_OVER_CL45(bp, phy,
5236                           MDIO_REG_BANK_SERDES_DIGITAL,
5237                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5238                           control1);
5239
5240         /* If forced speed */
5241         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5242                 /* Set speed, disable autoneg */
5243                 u16 mii_control;
5244
5245                 CL22_RD_OVER_CL45(bp, phy,
5246                                   MDIO_REG_BANK_COMBO_IEEE0,
5247                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5248                                   &mii_control);
5249                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5250                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5251                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5252
5253                 switch (vars->line_speed) {
5254                 case SPEED_100:
5255                         mii_control |=
5256                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5257                         break;
5258                 case SPEED_1000:
5259                         mii_control |=
5260                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5261                         break;
5262                 case SPEED_10:
5263                         /* There is nothing to set for 10M */
5264                         break;
5265                 default:
5266                         /* Invalid speed for SGMII */
5267                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5268                                   vars->line_speed);
5269                         break;
5270                 }
5271
5272                 /* Setting the full duplex */
5273                 if (phy->req_duplex == DUPLEX_FULL)
5274                         mii_control |=
5275                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5276                 CL22_WR_OVER_CL45(bp, phy,
5277                                   MDIO_REG_BANK_COMBO_IEEE0,
5278                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5279                                   mii_control);
5280
5281         } else { /* AN mode */
5282                 /* Enable and restart AN */
5283                 bnx2x_restart_autoneg(phy, params, 0);
5284         }
5285 }
5286
5287 /* Link management
5288  */
5289 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5290                                              struct link_params *params)
5291 {
5292         struct bnx2x *bp = params->bp;
5293         u16 pd_10g, status2_1000x;
5294         if (phy->req_line_speed != SPEED_AUTO_NEG)
5295                 return 0;
5296         CL22_RD_OVER_CL45(bp, phy,
5297                           MDIO_REG_BANK_SERDES_DIGITAL,
5298                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5299                           &status2_1000x);
5300         CL22_RD_OVER_CL45(bp, phy,
5301                           MDIO_REG_BANK_SERDES_DIGITAL,
5302                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5303                           &status2_1000x);
5304         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5305                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5306                          params->port);
5307                 return 1;
5308         }
5309
5310         CL22_RD_OVER_CL45(bp, phy,
5311                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5312                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5313                           &pd_10g);
5314
5315         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5316                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5317                          params->port);
5318                 return 1;
5319         }
5320         return 0;
5321 }
5322
5323 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5324                                 struct link_params *params,
5325                                 struct link_vars *vars,
5326                                 u32 gp_status)
5327 {
5328         u16 ld_pause;   /* local driver */
5329         u16 lp_pause;   /* link partner */
5330         u16 pause_result;
5331         struct bnx2x *bp = params->bp;
5332         if ((gp_status &
5333              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5334               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5335             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5336              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5337
5338                 CL22_RD_OVER_CL45(bp, phy,
5339                                   MDIO_REG_BANK_CL73_IEEEB1,
5340                                   MDIO_CL73_IEEEB1_AN_ADV1,
5341                                   &ld_pause);
5342                 CL22_RD_OVER_CL45(bp, phy,
5343                                   MDIO_REG_BANK_CL73_IEEEB1,
5344                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5345                                   &lp_pause);
5346                 pause_result = (ld_pause &
5347                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5348                 pause_result |= (lp_pause &
5349                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5350                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5351         } else {
5352                 CL22_RD_OVER_CL45(bp, phy,
5353                                   MDIO_REG_BANK_COMBO_IEEE0,
5354                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5355                                   &ld_pause);
5356                 CL22_RD_OVER_CL45(bp, phy,
5357                         MDIO_REG_BANK_COMBO_IEEE0,
5358                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5359                         &lp_pause);
5360                 pause_result = (ld_pause &
5361                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5362                 pause_result |= (lp_pause &
5363                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5364                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5365         }
5366         bnx2x_pause_resolve(vars, pause_result);
5367
5368 }
5369
5370 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5371                                     struct link_params *params,
5372                                     struct link_vars *vars,
5373                                     u32 gp_status)
5374 {
5375         struct bnx2x *bp = params->bp;
5376         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5377
5378         /* Resolve from gp_status in case of AN complete and not sgmii */
5379         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5380                 /* Update the advertised flow-controled of LD/LP in AN */
5381                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5382                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5383                 /* But set the flow-control result as the requested one */
5384                 vars->flow_ctrl = phy->req_flow_ctrl;
5385         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5386                 vars->flow_ctrl = params->req_fc_auto_adv;
5387         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5388                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5389                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5390                         vars->flow_ctrl = params->req_fc_auto_adv;
5391                         return;
5392                 }
5393                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5394         }
5395         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5396 }
5397
5398 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5399                                          struct link_params *params)
5400 {
5401         struct bnx2x *bp = params->bp;
5402         u16 rx_status, ustat_val, cl37_fsm_received;
5403         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5404         /* Step 1: Make sure signal is detected */
5405         CL22_RD_OVER_CL45(bp, phy,
5406                           MDIO_REG_BANK_RX0,
5407                           MDIO_RX0_RX_STATUS,
5408                           &rx_status);
5409         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5410             (MDIO_RX0_RX_STATUS_SIGDET)) {
5411                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5412                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5413                 CL22_WR_OVER_CL45(bp, phy,
5414                                   MDIO_REG_BANK_CL73_IEEEB0,
5415                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5416                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5417                 return;
5418         }
5419         /* Step 2: Check CL73 state machine */
5420         CL22_RD_OVER_CL45(bp, phy,
5421                           MDIO_REG_BANK_CL73_USERB0,
5422                           MDIO_CL73_USERB0_CL73_USTAT1,
5423                           &ustat_val);
5424         if ((ustat_val &
5425              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5426               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5427             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5428               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5429                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5430                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5431                 return;
5432         }
5433         /* Step 3: Check CL37 Message Pages received to indicate LP
5434          * supports only CL37
5435          */
5436         CL22_RD_OVER_CL45(bp, phy,
5437                           MDIO_REG_BANK_REMOTE_PHY,
5438                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5439                           &cl37_fsm_received);
5440         if ((cl37_fsm_received &
5441              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5442              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5443             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5444               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5445                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5446                              "misc_rx_status(0x8330) = 0x%x\n",
5447                          cl37_fsm_received);
5448                 return;
5449         }
5450         /* The combined cl37/cl73 fsm state information indicating that
5451          * we are connected to a device which does not support cl73, but
5452          * does support cl37 BAM. In this case we disable cl73 and
5453          * restart cl37 auto-neg
5454          */
5455
5456         /* Disable CL73 */
5457         CL22_WR_OVER_CL45(bp, phy,
5458                           MDIO_REG_BANK_CL73_IEEEB0,
5459                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5460                           0);
5461         /* Restart CL37 autoneg */
5462         bnx2x_restart_autoneg(phy, params, 0);
5463         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5464 }
5465
5466 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5467                                   struct link_params *params,
5468                                   struct link_vars *vars,
5469                                   u32 gp_status)
5470 {
5471         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5472                 vars->link_status |=
5473                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5474
5475         if (bnx2x_direct_parallel_detect_used(phy, params))
5476                 vars->link_status |=
5477                         LINK_STATUS_PARALLEL_DETECTION_USED;
5478 }
5479 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5480                                      struct link_params *params,
5481                                       struct link_vars *vars,
5482                                       u16 is_link_up,
5483                                       u16 speed_mask,
5484                                       u16 is_duplex)
5485 {
5486         struct bnx2x *bp = params->bp;
5487         if (phy->req_line_speed == SPEED_AUTO_NEG)
5488                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5489         if (is_link_up) {
5490                 DP(NETIF_MSG_LINK, "phy link up\n");
5491
5492                 vars->phy_link_up = 1;
5493                 vars->link_status |= LINK_STATUS_LINK_UP;
5494
5495                 switch (speed_mask) {
5496                 case GP_STATUS_10M:
5497                         vars->line_speed = SPEED_10;
5498                         if (is_duplex == DUPLEX_FULL)
5499                                 vars->link_status |= LINK_10TFD;
5500                         else
5501                                 vars->link_status |= LINK_10THD;
5502                         break;
5503
5504                 case GP_STATUS_100M:
5505                         vars->line_speed = SPEED_100;
5506                         if (is_duplex == DUPLEX_FULL)
5507                                 vars->link_status |= LINK_100TXFD;
5508                         else
5509                                 vars->link_status |= LINK_100TXHD;
5510                         break;
5511
5512                 case GP_STATUS_1G:
5513                 case GP_STATUS_1G_KX:
5514                         vars->line_speed = SPEED_1000;
5515                         if (is_duplex == DUPLEX_FULL)
5516                                 vars->link_status |= LINK_1000TFD;
5517                         else
5518                                 vars->link_status |= LINK_1000THD;
5519                         break;
5520
5521                 case GP_STATUS_2_5G:
5522                         vars->line_speed = SPEED_2500;
5523                         if (is_duplex == DUPLEX_FULL)
5524                                 vars->link_status |= LINK_2500TFD;
5525                         else
5526                                 vars->link_status |= LINK_2500THD;
5527                         break;
5528
5529                 case GP_STATUS_5G:
5530                 case GP_STATUS_6G:
5531                         DP(NETIF_MSG_LINK,
5532                                  "link speed unsupported  gp_status 0x%x\n",
5533                                   speed_mask);
5534                         return -EINVAL;
5535
5536                 case GP_STATUS_10G_KX4:
5537                 case GP_STATUS_10G_HIG:
5538                 case GP_STATUS_10G_CX4:
5539                 case GP_STATUS_10G_KR:
5540                 case GP_STATUS_10G_SFI:
5541                 case GP_STATUS_10G_XFI:
5542                         vars->line_speed = SPEED_10000;
5543                         vars->link_status |= LINK_10GTFD;
5544                         break;
5545                 case GP_STATUS_20G_DXGXS:
5546                 case GP_STATUS_20G_KR2:
5547                         vars->line_speed = SPEED_20000;
5548                         vars->link_status |= LINK_20GTFD;
5549                         break;
5550                 default:
5551                         DP(NETIF_MSG_LINK,
5552                                   "link speed unsupported gp_status 0x%x\n",
5553                                   speed_mask);
5554                         return -EINVAL;
5555                 }
5556         } else { /* link_down */
5557                 DP(NETIF_MSG_LINK, "phy link down\n");
5558
5559                 vars->phy_link_up = 0;
5560
5561                 vars->duplex = DUPLEX_FULL;
5562                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5563                 vars->mac_type = MAC_TYPE_NONE;
5564         }
5565         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5566                     vars->phy_link_up, vars->line_speed);
5567         return 0;
5568 }
5569
5570 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5571                                       struct link_params *params,
5572                                       struct link_vars *vars)
5573 {
5574         struct bnx2x *bp = params->bp;
5575
5576         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5577         int rc = 0;
5578
5579         /* Read gp_status */
5580         CL22_RD_OVER_CL45(bp, phy,
5581                           MDIO_REG_BANK_GP_STATUS,
5582                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5583                           &gp_status);
5584         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5585                 duplex = DUPLEX_FULL;
5586         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5587                 link_up = 1;
5588         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5589         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5590                        gp_status, link_up, speed_mask);
5591         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5592                                          duplex);
5593         if (rc == -EINVAL)
5594                 return rc;
5595
5596         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5597                 if (SINGLE_MEDIA_DIRECT(params)) {
5598                         vars->duplex = duplex;
5599                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5600                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5601                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5602                                                       gp_status);
5603                 }
5604         } else { /* Link_down */
5605                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5606                     SINGLE_MEDIA_DIRECT(params)) {
5607                         /* Check signal is detected */
5608                         bnx2x_check_fallback_to_cl37(phy, params);
5609                 }
5610         }
5611
5612         /* Read LP advertised speeds*/
5613         if (SINGLE_MEDIA_DIRECT(params) &&
5614             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5615                 u16 val;
5616
5617                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5618                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5619
5620                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5621                         vars->link_status |=
5622                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5623                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5624                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5625                         vars->link_status |=
5626                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5627
5628                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5629                                   MDIO_OVER_1G_LP_UP1, &val);
5630
5631                 if (val & MDIO_OVER_1G_UP1_2_5G)
5632                         vars->link_status |=
5633                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5634                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5635                         vars->link_status |=
5636                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5637         }
5638
5639         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5640                    vars->duplex, vars->flow_ctrl, vars->link_status);
5641         return rc;
5642 }
5643
5644 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5645                                      struct link_params *params,
5646                                      struct link_vars *vars)
5647 {
5648         struct bnx2x *bp = params->bp;
5649         u8 lane;
5650         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5651         int rc = 0;
5652         lane = bnx2x_get_warpcore_lane(phy, params);
5653         /* Read gp_status */
5654         if ((params->loopback_mode) &&
5655             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5656                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5657                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5658                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5659                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5660                 link_up &= 0x1;
5661         } else if ((phy->req_line_speed > SPEED_10000) &&
5662                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5663                 u16 temp_link_up;
5664                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5665                                 1, &temp_link_up);
5666                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5667                                 1, &link_up);
5668                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5669                                temp_link_up, link_up);
5670                 link_up &= (1<<2);
5671                 if (link_up)
5672                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5673         } else {
5674                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5675                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5676                                 &gp_status1);
5677                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5678                 /* Check for either KR, 1G, or AN up. */
5679                 link_up = ((gp_status1 >> 8) |
5680                            (gp_status1 >> 12) |
5681                            (gp_status1)) &
5682                         (1 << lane);
5683                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5684                         u16 an_link;
5685                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5686                                         MDIO_AN_REG_STATUS, &an_link);
5687                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5688                                         MDIO_AN_REG_STATUS, &an_link);
5689                         link_up |= (an_link & (1<<2));
5690                 }
5691                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5692                         u16 pd, gp_status4;
5693                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5694                                 /* Check Autoneg complete */
5695                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5696                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5697                                                 &gp_status4);
5698                                 if (gp_status4 & ((1<<12)<<lane))
5699                                         vars->link_status |=
5700                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5701
5702                                 /* Check parallel detect used */
5703                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5704                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5705                                                 &pd);
5706                                 if (pd & (1<<15))
5707                                         vars->link_status |=
5708                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5709                         }
5710                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5711                         vars->duplex = duplex;
5712                 }
5713         }
5714
5715         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5716             SINGLE_MEDIA_DIRECT(params)) {
5717                 u16 val;
5718
5719                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5720                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5721
5722                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5723                         vars->link_status |=
5724                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5725                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5726                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5727                         vars->link_status |=
5728                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5729
5730                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5731                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5732
5733                 if (val & MDIO_OVER_1G_UP1_2_5G)
5734                         vars->link_status |=
5735                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5736                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5737                         vars->link_status |=
5738                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5739
5740         }
5741
5742
5743         if (lane < 2) {
5744                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5745                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5746         } else {
5747                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5748                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5749         }
5750         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5751
5752         if ((lane & 1) == 0)
5753                 gp_speed <<= 8;
5754         gp_speed &= 0x3f00;
5755         link_up = !!link_up;
5756
5757         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5758                                          duplex);
5759
5760         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5761                    vars->duplex, vars->flow_ctrl, vars->link_status);
5762         return rc;
5763 }
5764 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5765 {
5766         struct bnx2x *bp = params->bp;
5767         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5768         u16 lp_up2;
5769         u16 tx_driver;
5770         u16 bank;
5771
5772         /* Read precomp */
5773         CL22_RD_OVER_CL45(bp, phy,
5774                           MDIO_REG_BANK_OVER_1G,
5775                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5776
5777         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5778         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5779                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5780                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5781
5782         if (lp_up2 == 0)
5783                 return;
5784
5785         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5786               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5787                 CL22_RD_OVER_CL45(bp, phy,
5788                                   bank,
5789                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5790
5791                 /* Replace tx_driver bits [15:12] */
5792                 if (lp_up2 !=
5793                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5794                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5795                         tx_driver |= lp_up2;
5796                         CL22_WR_OVER_CL45(bp, phy,
5797                                           bank,
5798                                           MDIO_TX0_TX_DRIVER, tx_driver);
5799                 }
5800         }
5801 }
5802
5803 static int bnx2x_emac_program(struct link_params *params,
5804                               struct link_vars *vars)
5805 {
5806         struct bnx2x *bp = params->bp;
5807         u8 port = params->port;
5808         u16 mode = 0;
5809
5810         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5811         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5812                        EMAC_REG_EMAC_MODE,
5813                        (EMAC_MODE_25G_MODE |
5814                         EMAC_MODE_PORT_MII_10M |
5815                         EMAC_MODE_HALF_DUPLEX));
5816         switch (vars->line_speed) {
5817         case SPEED_10:
5818                 mode |= EMAC_MODE_PORT_MII_10M;
5819                 break;
5820
5821         case SPEED_100:
5822                 mode |= EMAC_MODE_PORT_MII;
5823                 break;
5824
5825         case SPEED_1000:
5826                 mode |= EMAC_MODE_PORT_GMII;
5827                 break;
5828
5829         case SPEED_2500:
5830                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5831                 break;
5832
5833         default:
5834                 /* 10G not valid for EMAC */
5835                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5836                            vars->line_speed);
5837                 return -EINVAL;
5838         }
5839
5840         if (vars->duplex == DUPLEX_HALF)
5841                 mode |= EMAC_MODE_HALF_DUPLEX;
5842         bnx2x_bits_en(bp,
5843                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5844                       mode);
5845
5846         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5847         return 0;
5848 }
5849
5850 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5851                                   struct link_params *params)
5852 {
5853
5854         u16 bank, i = 0;
5855         struct bnx2x *bp = params->bp;
5856
5857         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5858               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5859                         CL22_WR_OVER_CL45(bp, phy,
5860                                           bank,
5861                                           MDIO_RX0_RX_EQ_BOOST,
5862                                           phy->rx_preemphasis[i]);
5863         }
5864
5865         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5866                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5867                         CL22_WR_OVER_CL45(bp, phy,
5868                                           bank,
5869                                           MDIO_TX0_TX_DRIVER,
5870                                           phy->tx_preemphasis[i]);
5871         }
5872 }
5873
5874 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5875                                    struct link_params *params,
5876                                    struct link_vars *vars)
5877 {
5878         struct bnx2x *bp = params->bp;
5879         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5880                           (params->loopback_mode == LOOPBACK_XGXS));
5881         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5882                 if (SINGLE_MEDIA_DIRECT(params) &&
5883                     (params->feature_config_flags &
5884                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5885                         bnx2x_set_preemphasis(phy, params);
5886
5887                 /* Forced speed requested? */
5888                 if (vars->line_speed != SPEED_AUTO_NEG ||
5889                     (SINGLE_MEDIA_DIRECT(params) &&
5890                      params->loopback_mode == LOOPBACK_EXT)) {
5891                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5892
5893                         /* Disable autoneg */
5894                         bnx2x_set_autoneg(phy, params, vars, 0);
5895
5896                         /* Program speed and duplex */
5897                         bnx2x_program_serdes(phy, params, vars);
5898
5899                 } else { /* AN_mode */
5900                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5901
5902                         /* AN enabled */
5903                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5904
5905                         /* Program duplex & pause advertisement (for aneg) */
5906                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5907                                                           vars->ieee_fc);
5908
5909                         /* Enable autoneg */
5910                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5911
5912                         /* Enable and restart AN */
5913                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5914                 }
5915
5916         } else { /* SGMII mode */
5917                 DP(NETIF_MSG_LINK, "SGMII\n");
5918
5919                 bnx2x_initialize_sgmii_process(phy, params, vars);
5920         }
5921 }
5922
5923 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5924                           struct link_params *params,
5925                           struct link_vars *vars)
5926 {
5927         int rc;
5928         vars->phy_flags |= PHY_XGXS_FLAG;
5929         if ((phy->req_line_speed &&
5930              ((phy->req_line_speed == SPEED_100) ||
5931               (phy->req_line_speed == SPEED_10))) ||
5932             (!phy->req_line_speed &&
5933              (phy->speed_cap_mask >=
5934               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5935              (phy->speed_cap_mask <
5936               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5937             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5938                 vars->phy_flags |= PHY_SGMII_FLAG;
5939         else
5940                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5941
5942         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5943         bnx2x_set_aer_mmd(params, phy);
5944         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5945                 bnx2x_set_master_ln(params, phy);
5946
5947         rc = bnx2x_reset_unicore(params, phy, 0);
5948         /* Reset the SerDes and wait for reset bit return low */
5949         if (rc)
5950                 return rc;
5951
5952         bnx2x_set_aer_mmd(params, phy);
5953         /* Setting the masterLn_def again after the reset */
5954         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5955                 bnx2x_set_master_ln(params, phy);
5956                 bnx2x_set_swap_lanes(params, phy);
5957         }
5958
5959         return rc;
5960 }
5961
5962 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5963                                      struct bnx2x_phy *phy,
5964                                      struct link_params *params)
5965 {
5966         u16 cnt, ctrl;
5967         /* Wait for soft reset to get cleared up to 1 sec */
5968         for (cnt = 0; cnt < 1000; cnt++) {
5969                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5970                         bnx2x_cl22_read(bp, phy,
5971                                 MDIO_PMA_REG_CTRL, &ctrl);
5972                 else
5973                         bnx2x_cl45_read(bp, phy,
5974                                 MDIO_PMA_DEVAD,
5975                                 MDIO_PMA_REG_CTRL, &ctrl);
5976                 if (!(ctrl & (1<<15)))
5977                         break;
5978                 usleep_range(1000, 2000);
5979         }
5980
5981         if (cnt == 1000)
5982                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5983                                       " Port %d\n",
5984                          params->port);
5985         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5986         return cnt;
5987 }
5988
5989 static void bnx2x_link_int_enable(struct link_params *params)
5990 {
5991         u8 port = params->port;
5992         u32 mask;
5993         struct bnx2x *bp = params->bp;
5994
5995         /* Setting the status to report on link up for either XGXS or SerDes */
5996         if (CHIP_IS_E3(bp)) {
5997                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5998                 if (!(SINGLE_MEDIA_DIRECT(params)))
5999                         mask |= NIG_MASK_MI_INT;
6000         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6001                 mask = (NIG_MASK_XGXS0_LINK10G |
6002                         NIG_MASK_XGXS0_LINK_STATUS);
6003                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6004                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6005                         params->phy[INT_PHY].type !=
6006                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6007                         mask |= NIG_MASK_MI_INT;
6008                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6009                 }
6010
6011         } else { /* SerDes */
6012                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6013                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6014                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6015                         params->phy[INT_PHY].type !=
6016                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6017                         mask |= NIG_MASK_MI_INT;
6018                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6019                 }
6020         }
6021         bnx2x_bits_en(bp,
6022                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6023                       mask);
6024
6025         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6026                  (params->switch_cfg == SWITCH_CFG_10G),
6027                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6028         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6029                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6030                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6031                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6032         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6033            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6034            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6035 }
6036
6037 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6038                                      u8 exp_mi_int)
6039 {
6040         u32 latch_status = 0;
6041
6042         /* Disable the MI INT ( external phy int ) by writing 1 to the
6043          * status register. Link down indication is high-active-signal,
6044          * so in this case we need to write the status to clear the XOR
6045          */
6046         /* Read Latched signals */
6047         latch_status = REG_RD(bp,
6048                                     NIG_REG_LATCH_STATUS_0 + port*8);
6049         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6050         /* Handle only those with latched-signal=up.*/
6051         if (exp_mi_int)
6052                 bnx2x_bits_en(bp,
6053                               NIG_REG_STATUS_INTERRUPT_PORT0
6054                               + port*4,
6055                               NIG_STATUS_EMAC0_MI_INT);
6056         else
6057                 bnx2x_bits_dis(bp,
6058                                NIG_REG_STATUS_INTERRUPT_PORT0
6059                                + port*4,
6060                                NIG_STATUS_EMAC0_MI_INT);
6061
6062         if (latch_status & 1) {
6063
6064                 /* For all latched-signal=up : Re-Arm Latch signals */
6065                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6066                        (latch_status & 0xfffe) | (latch_status & 1));
6067         }
6068         /* For all latched-signal=up,Write original_signal to status */
6069 }
6070
6071 static void bnx2x_link_int_ack(struct link_params *params,
6072                                struct link_vars *vars, u8 is_10g_plus)
6073 {
6074         struct bnx2x *bp = params->bp;
6075         u8 port = params->port;
6076         u32 mask;
6077         /* First reset all status we assume only one line will be
6078          * change at a time
6079          */
6080         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6081                        (NIG_STATUS_XGXS0_LINK10G |
6082                         NIG_STATUS_XGXS0_LINK_STATUS |
6083                         NIG_STATUS_SERDES0_LINK_STATUS));
6084         if (vars->phy_link_up) {
6085                 if (USES_WARPCORE(bp))
6086                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6087                 else {
6088                         if (is_10g_plus)
6089                                 mask = NIG_STATUS_XGXS0_LINK10G;
6090                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6091                                 /* Disable the link interrupt by writing 1 to
6092                                  * the relevant lane in the status register
6093                                  */
6094                                 u32 ser_lane =
6095                                         ((params->lane_config &
6096                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6097                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6098                                 mask = ((1 << ser_lane) <<
6099                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6100                         } else
6101                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6102                 }
6103                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6104                                mask);
6105                 bnx2x_bits_en(bp,
6106                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6107                               mask);
6108         }
6109 }
6110
6111 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6112 {
6113         u8 *str_ptr = str;
6114         u32 mask = 0xf0000000;
6115         u8 shift = 8*4;
6116         u8 digit;
6117         u8 remove_leading_zeros = 1;
6118         if (*len < 10) {
6119                 /* Need more than 10chars for this format */
6120                 *str_ptr = '\0';
6121                 (*len)--;
6122                 return -EINVAL;
6123         }
6124         while (shift > 0) {
6125
6126                 shift -= 4;
6127                 digit = ((num & mask) >> shift);
6128                 if (digit == 0 && remove_leading_zeros) {
6129                         mask = mask >> 4;
6130                         continue;
6131                 } else if (digit < 0xa)
6132                         *str_ptr = digit + '0';
6133                 else
6134                         *str_ptr = digit - 0xa + 'a';
6135                 remove_leading_zeros = 0;
6136                 str_ptr++;
6137                 (*len)--;
6138                 mask = mask >> 4;
6139                 if (shift == 4*4) {
6140                         *str_ptr = '.';
6141                         str_ptr++;
6142                         (*len)--;
6143                         remove_leading_zeros = 1;
6144                 }
6145         }
6146         return 0;
6147 }
6148
6149
6150 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6151 {
6152         str[0] = '\0';
6153         (*len)--;
6154         return 0;
6155 }
6156
6157 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6158                                  u16 len)
6159 {
6160         struct bnx2x *bp;
6161         u32 spirom_ver = 0;
6162         int status = 0;
6163         u8 *ver_p = version;
6164         u16 remain_len = len;
6165         if (version == NULL || params == NULL)
6166                 return -EINVAL;
6167         bp = params->bp;
6168
6169         /* Extract first external phy*/
6170         version[0] = '\0';
6171         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6172
6173         if (params->phy[EXT_PHY1].format_fw_ver) {
6174                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6175                                                               ver_p,
6176                                                               &remain_len);
6177                 ver_p += (len - remain_len);
6178         }
6179         if ((params->num_phys == MAX_PHYS) &&
6180             (params->phy[EXT_PHY2].ver_addr != 0)) {
6181                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6182                 if (params->phy[EXT_PHY2].format_fw_ver) {
6183                         *ver_p = '/';
6184                         ver_p++;
6185                         remain_len--;
6186                         status |= params->phy[EXT_PHY2].format_fw_ver(
6187                                 spirom_ver,
6188                                 ver_p,
6189                                 &remain_len);
6190                         ver_p = version + (len - remain_len);
6191                 }
6192         }
6193         *ver_p = '\0';
6194         return status;
6195 }
6196
6197 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6198                                     struct link_params *params)
6199 {
6200         u8 port = params->port;
6201         struct bnx2x *bp = params->bp;
6202
6203         if (phy->req_line_speed != SPEED_1000) {
6204                 u32 md_devad = 0;
6205
6206                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6207
6208                 if (!CHIP_IS_E3(bp)) {
6209                         /* Change the uni_phy_addr in the nig */
6210                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6211                                                port*0x18));
6212
6213                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6214                                0x5);
6215                 }
6216
6217                 bnx2x_cl45_write(bp, phy,
6218                                  5,
6219                                  (MDIO_REG_BANK_AER_BLOCK +
6220                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6221                                  0x2800);
6222
6223                 bnx2x_cl45_write(bp, phy,
6224                                  5,
6225                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6226                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6227                                  0x6041);
6228                 msleep(200);
6229                 /* Set aer mmd back */
6230                 bnx2x_set_aer_mmd(params, phy);
6231
6232                 if (!CHIP_IS_E3(bp)) {
6233                         /* And md_devad */
6234                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6235                                md_devad);
6236                 }
6237         } else {
6238                 u16 mii_ctrl;
6239                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6240                 bnx2x_cl45_read(bp, phy, 5,
6241                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6242                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6243                                 &mii_ctrl);
6244                 bnx2x_cl45_write(bp, phy, 5,
6245                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6246                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6247                                  mii_ctrl |
6248                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6249         }
6250 }
6251
6252 int bnx2x_set_led(struct link_params *params,
6253                   struct link_vars *vars, u8 mode, u32 speed)
6254 {
6255         u8 port = params->port;
6256         u16 hw_led_mode = params->hw_led_mode;
6257         int rc = 0;
6258         u8 phy_idx;
6259         u32 tmp;
6260         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6261         struct bnx2x *bp = params->bp;
6262         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6263         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6264                  speed, hw_led_mode);
6265         /* In case */
6266         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6267                 if (params->phy[phy_idx].set_link_led) {
6268                         params->phy[phy_idx].set_link_led(
6269                                 &params->phy[phy_idx], params, mode);
6270                 }
6271         }
6272
6273         switch (mode) {
6274         case LED_MODE_FRONT_PANEL_OFF:
6275         case LED_MODE_OFF:
6276                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6277                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6278                        SHARED_HW_CFG_LED_MAC1);
6279
6280                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6281                 if (params->phy[EXT_PHY1].type ==
6282                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6283                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6284                                 EMAC_LED_100MB_OVERRIDE |
6285                                 EMAC_LED_10MB_OVERRIDE);
6286                 else
6287                         tmp |= EMAC_LED_OVERRIDE;
6288
6289                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6290                 break;
6291
6292         case LED_MODE_OPER:
6293                 /* For all other phys, OPER mode is same as ON, so in case
6294                  * link is down, do nothing
6295                  */
6296                 if (!vars->link_up)
6297                         break;
6298         case LED_MODE_ON:
6299                 if (((params->phy[EXT_PHY1].type ==
6300                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6301                          (params->phy[EXT_PHY1].type ==
6302                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6303                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6304                         /* This is a work-around for E2+8727 Configurations */
6305                         if (mode == LED_MODE_ON ||
6306                                 speed == SPEED_10000){
6307                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6308                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6309
6310                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6311                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6312                                         (tmp | EMAC_LED_OVERRIDE));
6313                                 /* Return here without enabling traffic
6314                                  * LED blink and setting rate in ON mode.
6315                                  * In oper mode, enabling LED blink
6316                                  * and setting rate is needed.
6317                                  */
6318                                 if (mode == LED_MODE_ON)
6319                                         return rc;
6320                         }
6321                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6322                         /* This is a work-around for HW issue found when link
6323                          * is up in CL73
6324                          */
6325                         if ((!CHIP_IS_E3(bp)) ||
6326                             (CHIP_IS_E3(bp) &&
6327                              mode == LED_MODE_ON))
6328                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6329
6330                         if (CHIP_IS_E1x(bp) ||
6331                             CHIP_IS_E2(bp) ||
6332                             (mode == LED_MODE_ON))
6333                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6334                         else
6335                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6336                                        hw_led_mode);
6337                 } else if ((params->phy[EXT_PHY1].type ==
6338                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6339                            (mode == LED_MODE_ON)) {
6340                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6341                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6342                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6343                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6344                         /* Break here; otherwise, it'll disable the
6345                          * intended override.
6346                          */
6347                         break;
6348                 } else
6349                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6350                                hw_led_mode);
6351
6352                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6353                 /* Set blinking rate to ~15.9Hz */
6354                 if (CHIP_IS_E3(bp))
6355                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6356                                LED_BLINK_RATE_VAL_E3);
6357                 else
6358                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6359                                LED_BLINK_RATE_VAL_E1X_E2);
6360                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6361                        port*4, 1);
6362                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6363                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6364                         (tmp & (~EMAC_LED_OVERRIDE)));
6365
6366                 if (CHIP_IS_E1(bp) &&
6367                     ((speed == SPEED_2500) ||
6368                      (speed == SPEED_1000) ||
6369                      (speed == SPEED_100) ||
6370                      (speed == SPEED_10))) {
6371                         /* For speeds less than 10G LED scheme is different */
6372                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6373                                + port*4, 1);
6374                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6375                                port*4, 0);
6376                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6377                                port*4, 1);
6378                 }
6379                 break;
6380
6381         default:
6382                 rc = -EINVAL;
6383                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6384                          mode);
6385                 break;
6386         }
6387         return rc;
6388
6389 }
6390
6391 /* This function comes to reflect the actual link state read DIRECTLY from the
6392  * HW
6393  */
6394 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6395                     u8 is_serdes)
6396 {
6397         struct bnx2x *bp = params->bp;
6398         u16 gp_status = 0, phy_index = 0;
6399         u8 ext_phy_link_up = 0, serdes_phy_type;
6400         struct link_vars temp_vars;
6401         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6402
6403         if (CHIP_IS_E3(bp)) {
6404                 u16 link_up;
6405                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6406                     > SPEED_10000) {
6407                         /* Check 20G link */
6408                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6409                                         1, &link_up);
6410                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6411                                         1, &link_up);
6412                         link_up &= (1<<2);
6413                 } else {
6414                         /* Check 10G link and below*/
6415                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6416                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6417                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6418                                         &gp_status);
6419                         gp_status = ((gp_status >> 8) & 0xf) |
6420                                 ((gp_status >> 12) & 0xf);
6421                         link_up = gp_status & (1 << lane);
6422                 }
6423                 if (!link_up)
6424                         return -ESRCH;
6425         } else {
6426                 CL22_RD_OVER_CL45(bp, int_phy,
6427                           MDIO_REG_BANK_GP_STATUS,
6428                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6429                           &gp_status);
6430         /* Link is up only if both local phy and external phy are up */
6431         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6432                 return -ESRCH;
6433         }
6434         /* In XGXS loopback mode, do not check external PHY */
6435         if (params->loopback_mode == LOOPBACK_XGXS)
6436                 return 0;
6437
6438         switch (params->num_phys) {
6439         case 1:
6440                 /* No external PHY */
6441                 return 0;
6442         case 2:
6443                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6444                         &params->phy[EXT_PHY1],
6445                         params, &temp_vars);
6446                 break;
6447         case 3: /* Dual Media */
6448                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6449                       phy_index++) {
6450                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6451                                             ETH_PHY_SFPP_10G_FIBER) ||
6452                                            (params->phy[phy_index].media_type ==
6453                                             ETH_PHY_SFP_1G_FIBER) ||
6454                                            (params->phy[phy_index].media_type ==
6455                                             ETH_PHY_XFP_FIBER) ||
6456                                            (params->phy[phy_index].media_type ==
6457                                             ETH_PHY_DA_TWINAX));
6458
6459                         if (is_serdes != serdes_phy_type)
6460                                 continue;
6461                         if (params->phy[phy_index].read_status) {
6462                                 ext_phy_link_up |=
6463                                         params->phy[phy_index].read_status(
6464                                                 &params->phy[phy_index],
6465                                                 params, &temp_vars);
6466                         }
6467                 }
6468                 break;
6469         }
6470         if (ext_phy_link_up)
6471                 return 0;
6472         return -ESRCH;
6473 }
6474
6475 static int bnx2x_link_initialize(struct link_params *params,
6476                                  struct link_vars *vars)
6477 {
6478         int rc = 0;
6479         u8 phy_index, non_ext_phy;
6480         struct bnx2x *bp = params->bp;
6481         /* In case of external phy existence, the line speed would be the
6482          * line speed linked up by the external phy. In case it is direct
6483          * only, then the line_speed during initialization will be
6484          * equal to the req_line_speed
6485          */
6486         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6487
6488         /* Initialize the internal phy in case this is a direct board
6489          * (no external phys), or this board has external phy which requires
6490          * to first.
6491          */
6492         if (!USES_WARPCORE(bp))
6493                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6494         /* init ext phy and enable link state int */
6495         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6496                        (params->loopback_mode == LOOPBACK_XGXS));
6497
6498         if (non_ext_phy ||
6499             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6500             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6501                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6502                 if (vars->line_speed == SPEED_AUTO_NEG &&
6503                     (CHIP_IS_E1x(bp) ||
6504                      CHIP_IS_E2(bp))) {
6505                         bnx2x_set_parallel_detection(phy, params);
6506                         if (params->phy[INT_PHY].config_init)
6507                                 params->phy[INT_PHY].config_init(phy,
6508                                                                  params,
6509                                                                  vars);
6510                 }
6511         }
6512
6513         /* Init external phy*/
6514         if (non_ext_phy) {
6515                 if (params->phy[INT_PHY].supported &
6516                     SUPPORTED_FIBRE)
6517                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6518         } else {
6519                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6520                       phy_index++) {
6521                         /* No need to initialize second phy in case of first
6522                          * phy only selection. In case of second phy, we do
6523                          * need to initialize the first phy, since they are
6524                          * connected.
6525                          */
6526                         if (params->phy[phy_index].supported &
6527                             SUPPORTED_FIBRE)
6528                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6529
6530                         if (phy_index == EXT_PHY2 &&
6531                             (bnx2x_phy_selection(params) ==
6532                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6533                                 DP(NETIF_MSG_LINK,
6534                                    "Not initializing second phy\n");
6535                                 continue;
6536                         }
6537                         params->phy[phy_index].config_init(
6538                                 &params->phy[phy_index],
6539                                 params, vars);
6540                 }
6541         }
6542         /* Reset the interrupt indication after phy was initialized */
6543         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6544                        params->port*4,
6545                        (NIG_STATUS_XGXS0_LINK10G |
6546                         NIG_STATUS_XGXS0_LINK_STATUS |
6547                         NIG_STATUS_SERDES0_LINK_STATUS |
6548                         NIG_MASK_MI_INT));
6549         return rc;
6550 }
6551
6552 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6553                                  struct link_params *params)
6554 {
6555         /* Reset the SerDes/XGXS */
6556         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6557                (0x1ff << (params->port*16)));
6558 }
6559
6560 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6561                                         struct link_params *params)
6562 {
6563         struct bnx2x *bp = params->bp;
6564         u8 gpio_port;
6565         /* HW reset */
6566         if (CHIP_IS_E2(bp))
6567                 gpio_port = BP_PATH(bp);
6568         else
6569                 gpio_port = params->port;
6570         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6571                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6572                        gpio_port);
6573         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6574                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6575                        gpio_port);
6576         DP(NETIF_MSG_LINK, "reset external PHY\n");
6577 }
6578
6579 static int bnx2x_update_link_down(struct link_params *params,
6580                                   struct link_vars *vars)
6581 {
6582         struct bnx2x *bp = params->bp;
6583         u8 port = params->port;
6584
6585         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6586         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6587         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6588         /* Indicate no mac active */
6589         vars->mac_type = MAC_TYPE_NONE;
6590
6591         /* Update shared memory */
6592         vars->link_status &= ~LINK_UPDATE_MASK;
6593         vars->line_speed = 0;
6594         bnx2x_update_mng(params, vars->link_status);
6595
6596         /* Activate nig drain */
6597         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6598
6599         /* Disable emac */
6600         if (!CHIP_IS_E3(bp))
6601                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6602
6603         usleep_range(10000, 20000);
6604         /* Reset BigMac/Xmac */
6605         if (CHIP_IS_E1x(bp) ||
6606             CHIP_IS_E2(bp))
6607                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6608
6609         if (CHIP_IS_E3(bp)) {
6610                 /* Prevent LPI Generation by chip */
6611                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6612                        0);
6613                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6614                        0);
6615                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6616                                       SHMEM_EEE_ACTIVE_BIT);
6617
6618                 bnx2x_update_mng_eee(params, vars->eee_status);
6619                 bnx2x_set_xmac_rxtx(params, 0);
6620                 bnx2x_set_umac_rxtx(params, 0);
6621         }
6622
6623         return 0;
6624 }
6625
6626 static int bnx2x_update_link_up(struct link_params *params,
6627                                 struct link_vars *vars,
6628                                 u8 link_10g)
6629 {
6630         struct bnx2x *bp = params->bp;
6631         u8 phy_idx, port = params->port;
6632         int rc = 0;
6633
6634         vars->link_status |= (LINK_STATUS_LINK_UP |
6635                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6636         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6637
6638         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6639                 vars->link_status |=
6640                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6641
6642         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6643                 vars->link_status |=
6644                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6645         if (USES_WARPCORE(bp)) {
6646                 if (link_10g) {
6647                         if (bnx2x_xmac_enable(params, vars, 0) ==
6648                             -ESRCH) {
6649                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6650                                 vars->link_up = 0;
6651                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6652                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6653                         }
6654                 } else
6655                         bnx2x_umac_enable(params, vars, 0);
6656                 bnx2x_set_led(params, vars,
6657                               LED_MODE_OPER, vars->line_speed);
6658
6659                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6660                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6661                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6662                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6663                                (params->port << 2), 1);
6664                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6665                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6666                                (params->port << 2), 0xfc20);
6667                 }
6668         }
6669         if ((CHIP_IS_E1x(bp) ||
6670              CHIP_IS_E2(bp))) {
6671                 if (link_10g) {
6672                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6673                             -ESRCH) {
6674                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6675                                 vars->link_up = 0;
6676                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6677                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6678                         }
6679
6680                         bnx2x_set_led(params, vars,
6681                                       LED_MODE_OPER, SPEED_10000);
6682                 } else {
6683                         rc = bnx2x_emac_program(params, vars);
6684                         bnx2x_emac_enable(params, vars, 0);
6685
6686                         /* AN complete? */
6687                         if ((vars->link_status &
6688                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6689                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6690                             SINGLE_MEDIA_DIRECT(params))
6691                                 bnx2x_set_gmii_tx_driver(params);
6692                 }
6693         }
6694
6695         /* PBF - link up */
6696         if (CHIP_IS_E1x(bp))
6697                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6698                                        vars->line_speed);
6699
6700         /* Disable drain */
6701         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6702
6703         /* Update shared memory */
6704         bnx2x_update_mng(params, vars->link_status);
6705         bnx2x_update_mng_eee(params, vars->eee_status);
6706         /* Check remote fault */
6707         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6708                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6709                         bnx2x_check_half_open_conn(params, vars, 0);
6710                         break;
6711                 }
6712         }
6713         msleep(20);
6714         return rc;
6715 }
6716 /* The bnx2x_link_update function should be called upon link
6717  * interrupt.
6718  * Link is considered up as follows:
6719  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6720  *   to be up
6721  * - SINGLE_MEDIA - The link between the 577xx and the external
6722  *   phy (XGXS) need to up as well as the external link of the
6723  *   phy (PHY_EXT1)
6724  * - DUAL_MEDIA - The link between the 577xx and the first
6725  *   external phy needs to be up, and at least one of the 2
6726  *   external phy link must be up.
6727  */
6728 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6729 {
6730         struct bnx2x *bp = params->bp;
6731         struct link_vars phy_vars[MAX_PHYS];
6732         u8 port = params->port;
6733         u8 link_10g_plus, phy_index;
6734         u8 ext_phy_link_up = 0, cur_link_up;
6735         int rc = 0;
6736         u8 is_mi_int = 0;
6737         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6738         u8 active_external_phy = INT_PHY;
6739         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6740         vars->link_status &= ~LINK_UPDATE_MASK;
6741         for (phy_index = INT_PHY; phy_index < params->num_phys;
6742               phy_index++) {
6743                 phy_vars[phy_index].flow_ctrl = 0;
6744                 phy_vars[phy_index].link_status = 0;
6745                 phy_vars[phy_index].line_speed = 0;
6746                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6747                 phy_vars[phy_index].phy_link_up = 0;
6748                 phy_vars[phy_index].link_up = 0;
6749                 phy_vars[phy_index].fault_detected = 0;
6750                 /* different consideration, since vars holds inner state */
6751                 phy_vars[phy_index].eee_status = vars->eee_status;
6752         }
6753
6754         if (USES_WARPCORE(bp))
6755                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6756
6757         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6758                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6759                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6760
6761         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6762                                 port*0x18) > 0);
6763         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6764                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6765                  is_mi_int,
6766                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6767
6768         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6769           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6770           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6771
6772         /* Disable emac */
6773         if (!CHIP_IS_E3(bp))
6774                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6775
6776         /* Step 1:
6777          * Check external link change only for external phys, and apply
6778          * priority selection between them in case the link on both phys
6779          * is up. Note that instead of the common vars, a temporary
6780          * vars argument is used since each phy may have different link/
6781          * speed/duplex result
6782          */
6783         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6784               phy_index++) {
6785                 struct bnx2x_phy *phy = &params->phy[phy_index];
6786                 if (!phy->read_status)
6787                         continue;
6788                 /* Read link status and params of this ext phy */
6789                 cur_link_up = phy->read_status(phy, params,
6790                                                &phy_vars[phy_index]);
6791                 if (cur_link_up) {
6792                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6793                                    phy_index);
6794                 } else {
6795                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6796                                    phy_index);
6797                         continue;
6798                 }
6799
6800                 if (!ext_phy_link_up) {
6801                         ext_phy_link_up = 1;
6802                         active_external_phy = phy_index;
6803                 } else {
6804                         switch (bnx2x_phy_selection(params)) {
6805                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6806                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6807                         /* In this option, the first PHY makes sure to pass the
6808                          * traffic through itself only.
6809                          * Its not clear how to reset the link on the second phy
6810                          */
6811                                 active_external_phy = EXT_PHY1;
6812                                 break;
6813                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6814                         /* In this option, the first PHY makes sure to pass the
6815                          * traffic through the second PHY.
6816                          */
6817                                 active_external_phy = EXT_PHY2;
6818                                 break;
6819                         default:
6820                         /* Link indication on both PHYs with the following cases
6821                          * is invalid:
6822                          * - FIRST_PHY means that second phy wasn't initialized,
6823                          * hence its link is expected to be down
6824                          * - SECOND_PHY means that first phy should not be able
6825                          * to link up by itself (using configuration)
6826                          * - DEFAULT should be overriden during initialiazation
6827                          */
6828                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6829                                            "mpc=0x%x. DISABLING LINK !!!\n",
6830                                            params->multi_phy_config);
6831                                 ext_phy_link_up = 0;
6832                                 break;
6833                         }
6834                 }
6835         }
6836         prev_line_speed = vars->line_speed;
6837         /* Step 2:
6838          * Read the status of the internal phy. In case of
6839          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6840          * otherwise this is the link between the 577xx and the first
6841          * external phy
6842          */
6843         if (params->phy[INT_PHY].read_status)
6844                 params->phy[INT_PHY].read_status(
6845                         &params->phy[INT_PHY],
6846                         params, vars);
6847         /* The INT_PHY flow control reside in the vars. This include the
6848          * case where the speed or flow control are not set to AUTO.
6849          * Otherwise, the active external phy flow control result is set
6850          * to the vars. The ext_phy_line_speed is needed to check if the
6851          * speed is different between the internal phy and external phy.
6852          * This case may be result of intermediate link speed change.
6853          */
6854         if (active_external_phy > INT_PHY) {
6855                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6856                 /* Link speed is taken from the XGXS. AN and FC result from
6857                  * the external phy.
6858                  */
6859                 vars->link_status |= phy_vars[active_external_phy].link_status;
6860
6861                 /* if active_external_phy is first PHY and link is up - disable
6862                  * disable TX on second external PHY
6863                  */
6864                 if (active_external_phy == EXT_PHY1) {
6865                         if (params->phy[EXT_PHY2].phy_specific_func) {
6866                                 DP(NETIF_MSG_LINK,
6867                                    "Disabling TX on EXT_PHY2\n");
6868                                 params->phy[EXT_PHY2].phy_specific_func(
6869                                         &params->phy[EXT_PHY2],
6870                                         params, DISABLE_TX);
6871                         }
6872                 }
6873
6874                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6875                 vars->duplex = phy_vars[active_external_phy].duplex;
6876                 if (params->phy[active_external_phy].supported &
6877                     SUPPORTED_FIBRE)
6878                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6879                 else
6880                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6881
6882                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6883
6884                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6885                            active_external_phy);
6886         }
6887
6888         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6889               phy_index++) {
6890                 if (params->phy[phy_index].flags &
6891                     FLAGS_REARM_LATCH_SIGNAL) {
6892                         bnx2x_rearm_latch_signal(bp, port,
6893                                                  phy_index ==
6894                                                  active_external_phy);
6895                         break;
6896                 }
6897         }
6898         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6899                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6900                    vars->link_status, ext_phy_line_speed);
6901         /* Upon link speed change set the NIG into drain mode. Comes to
6902          * deals with possible FIFO glitch due to clk change when speed
6903          * is decreased without link down indicator
6904          */
6905
6906         if (vars->phy_link_up) {
6907                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6908                     (ext_phy_line_speed != vars->line_speed)) {
6909                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6910                                    " different than the external"
6911                                    " link speed %d\n", vars->line_speed,
6912                                    ext_phy_line_speed);
6913                         vars->phy_link_up = 0;
6914                 } else if (prev_line_speed != vars->line_speed) {
6915                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6916                                0);
6917                         usleep_range(1000, 2000);
6918                 }
6919         }
6920
6921         /* Anything 10 and over uses the bmac */
6922         link_10g_plus = (vars->line_speed >= SPEED_10000);
6923
6924         bnx2x_link_int_ack(params, vars, link_10g_plus);
6925
6926         /* In case external phy link is up, and internal link is down
6927          * (not initialized yet probably after link initialization, it
6928          * needs to be initialized.
6929          * Note that after link down-up as result of cable plug, the xgxs
6930          * link would probably become up again without the need
6931          * initialize it
6932          */
6933         if (!(SINGLE_MEDIA_DIRECT(params))) {
6934                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6935                            " init_preceding = %d\n", ext_phy_link_up,
6936                            vars->phy_link_up,
6937                            params->phy[EXT_PHY1].flags &
6938                            FLAGS_INIT_XGXS_FIRST);
6939                 if (!(params->phy[EXT_PHY1].flags &
6940                       FLAGS_INIT_XGXS_FIRST)
6941                     && ext_phy_link_up && !vars->phy_link_up) {
6942                         vars->line_speed = ext_phy_line_speed;
6943                         if (vars->line_speed < SPEED_1000)
6944                                 vars->phy_flags |= PHY_SGMII_FLAG;
6945                         else
6946                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6947
6948                         if (params->phy[INT_PHY].config_init)
6949                                 params->phy[INT_PHY].config_init(
6950                                         &params->phy[INT_PHY], params,
6951                                                 vars);
6952                 }
6953         }
6954         /* Link is up only if both local phy and external phy (in case of
6955          * non-direct board) are up and no fault detected on active PHY.
6956          */
6957         vars->link_up = (vars->phy_link_up &&
6958                          (ext_phy_link_up ||
6959                           SINGLE_MEDIA_DIRECT(params)) &&
6960                          (phy_vars[active_external_phy].fault_detected == 0));
6961
6962         /* Update the PFC configuration in case it was changed */
6963         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6964                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6965         else
6966                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6967
6968         if (vars->link_up)
6969                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6970         else
6971                 rc = bnx2x_update_link_down(params, vars);
6972
6973         /* Update MCP link status was changed */
6974         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
6975                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
6976
6977         return rc;
6978 }
6979
6980 /*****************************************************************************/
6981 /*                          External Phy section                             */
6982 /*****************************************************************************/
6983 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6984 {
6985         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6986                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6987         usleep_range(1000, 2000);
6988         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6989                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6990 }
6991
6992 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6993                                       u32 spirom_ver, u32 ver_addr)
6994 {
6995         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6996                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6997
6998         if (ver_addr)
6999                 REG_WR(bp, ver_addr, spirom_ver);
7000 }
7001
7002 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7003                                       struct bnx2x_phy *phy,
7004                                       u8 port)
7005 {
7006         u16 fw_ver1, fw_ver2;
7007
7008         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7009                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7010         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7011                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7012         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7013                                   phy->ver_addr);
7014 }
7015
7016 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7017                                        struct bnx2x_phy *phy,
7018                                        struct link_vars *vars)
7019 {
7020         u16 val;
7021         bnx2x_cl45_read(bp, phy,
7022                         MDIO_AN_DEVAD,
7023                         MDIO_AN_REG_STATUS, &val);
7024         bnx2x_cl45_read(bp, phy,
7025                         MDIO_AN_DEVAD,
7026                         MDIO_AN_REG_STATUS, &val);
7027         if (val & (1<<5))
7028                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7029         if ((val & (1<<0)) == 0)
7030                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7031 }
7032
7033 /******************************************************************/
7034 /*              common BCM8073/BCM8727 PHY SECTION                */
7035 /******************************************************************/
7036 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7037                                   struct link_params *params,
7038                                   struct link_vars *vars)
7039 {
7040         struct bnx2x *bp = params->bp;
7041         if (phy->req_line_speed == SPEED_10 ||
7042             phy->req_line_speed == SPEED_100) {
7043                 vars->flow_ctrl = phy->req_flow_ctrl;
7044                 return;
7045         }
7046
7047         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7048             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7049                 u16 pause_result;
7050                 u16 ld_pause;           /* local */
7051                 u16 lp_pause;           /* link partner */
7052                 bnx2x_cl45_read(bp, phy,
7053                                 MDIO_AN_DEVAD,
7054                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7055
7056                 bnx2x_cl45_read(bp, phy,
7057                                 MDIO_AN_DEVAD,
7058                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7059                 pause_result = (ld_pause &
7060                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7061                 pause_result |= (lp_pause &
7062                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7063
7064                 bnx2x_pause_resolve(vars, pause_result);
7065                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7066                            pause_result);
7067         }
7068 }
7069 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7070                                              struct bnx2x_phy *phy,
7071                                              u8 port)
7072 {
7073         u32 count = 0;
7074         u16 fw_ver1, fw_msgout;
7075         int rc = 0;
7076
7077         /* Boot port from external ROM  */
7078         /* EDC grst */
7079         bnx2x_cl45_write(bp, phy,
7080                          MDIO_PMA_DEVAD,
7081                          MDIO_PMA_REG_GEN_CTRL,
7082                          0x0001);
7083
7084         /* Ucode reboot and rst */
7085         bnx2x_cl45_write(bp, phy,
7086                          MDIO_PMA_DEVAD,
7087                          MDIO_PMA_REG_GEN_CTRL,
7088                          0x008c);
7089
7090         bnx2x_cl45_write(bp, phy,
7091                          MDIO_PMA_DEVAD,
7092                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7093
7094         /* Reset internal microprocessor */
7095         bnx2x_cl45_write(bp, phy,
7096                          MDIO_PMA_DEVAD,
7097                          MDIO_PMA_REG_GEN_CTRL,
7098                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7099
7100         /* Release srst bit */
7101         bnx2x_cl45_write(bp, phy,
7102                          MDIO_PMA_DEVAD,
7103                          MDIO_PMA_REG_GEN_CTRL,
7104                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7105
7106         /* Delay 100ms per the PHY specifications */
7107         msleep(100);
7108
7109         /* 8073 sometimes taking longer to download */
7110         do {
7111                 count++;
7112                 if (count > 300) {
7113                         DP(NETIF_MSG_LINK,
7114                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7115                                  "Download failed. fw version = 0x%x\n",
7116                                  port, fw_ver1);
7117                         rc = -EINVAL;
7118                         break;
7119                 }
7120
7121                 bnx2x_cl45_read(bp, phy,
7122                                 MDIO_PMA_DEVAD,
7123                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7124                 bnx2x_cl45_read(bp, phy,
7125                                 MDIO_PMA_DEVAD,
7126                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7127
7128                 usleep_range(1000, 2000);
7129         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7130                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7131                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7132
7133         /* Clear ser_boot_ctl bit */
7134         bnx2x_cl45_write(bp, phy,
7135                          MDIO_PMA_DEVAD,
7136                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7137         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7138
7139         DP(NETIF_MSG_LINK,
7140                  "bnx2x_8073_8727_external_rom_boot port %x:"
7141                  "Download complete. fw version = 0x%x\n",
7142                  port, fw_ver1);
7143
7144         return rc;
7145 }
7146
7147 /******************************************************************/
7148 /*                      BCM8073 PHY SECTION                       */
7149 /******************************************************************/
7150 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7151 {
7152         /* This is only required for 8073A1, version 102 only */
7153         u16 val;
7154
7155         /* Read 8073 HW revision*/
7156         bnx2x_cl45_read(bp, phy,
7157                         MDIO_PMA_DEVAD,
7158                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7159
7160         if (val != 1) {
7161                 /* No need to workaround in 8073 A1 */
7162                 return 0;
7163         }
7164
7165         bnx2x_cl45_read(bp, phy,
7166                         MDIO_PMA_DEVAD,
7167                         MDIO_PMA_REG_ROM_VER2, &val);
7168
7169         /* SNR should be applied only for version 0x102 */
7170         if (val != 0x102)
7171                 return 0;
7172
7173         return 1;
7174 }
7175
7176 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7177 {
7178         u16 val, cnt, cnt1 ;
7179
7180         bnx2x_cl45_read(bp, phy,
7181                         MDIO_PMA_DEVAD,
7182                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7183
7184         if (val > 0) {
7185                 /* No need to workaround in 8073 A1 */
7186                 return 0;
7187         }
7188         /* XAUI workaround in 8073 A0: */
7189
7190         /* After loading the boot ROM and restarting Autoneg, poll
7191          * Dev1, Reg $C820:
7192          */
7193
7194         for (cnt = 0; cnt < 1000; cnt++) {
7195                 bnx2x_cl45_read(bp, phy,
7196                                 MDIO_PMA_DEVAD,
7197                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7198                                 &val);
7199                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7200                    * system initialization (XAUI work-around not required, as
7201                    * these bits indicate 2.5G or 1G link up).
7202                    */
7203                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7204                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7205                         return 0;
7206                 } else if (!(val & (1<<15))) {
7207                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7208                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7209                          * MSB (bit15) goes to 1 (indicating that the XAUI
7210                          * workaround has completed), then continue on with
7211                          * system initialization.
7212                          */
7213                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7214                                 bnx2x_cl45_read(bp, phy,
7215                                         MDIO_PMA_DEVAD,
7216                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7217                                 if (val & (1<<15)) {
7218                                         DP(NETIF_MSG_LINK,
7219                                           "XAUI workaround has completed\n");
7220                                         return 0;
7221                                  }
7222                                  usleep_range(3000, 6000);
7223                         }
7224                         break;
7225                 }
7226                 usleep_range(3000, 6000);
7227         }
7228         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7229         return -EINVAL;
7230 }
7231
7232 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7233 {
7234         /* Force KR or KX */
7235         bnx2x_cl45_write(bp, phy,
7236                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7237         bnx2x_cl45_write(bp, phy,
7238                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7239         bnx2x_cl45_write(bp, phy,
7240                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7241         bnx2x_cl45_write(bp, phy,
7242                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7243 }
7244
7245 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7246                                       struct bnx2x_phy *phy,
7247                                       struct link_vars *vars)
7248 {
7249         u16 cl37_val;
7250         struct bnx2x *bp = params->bp;
7251         bnx2x_cl45_read(bp, phy,
7252                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7253
7254         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7255         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7256         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7257         if ((vars->ieee_fc &
7258             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7259             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7260                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7261         }
7262         if ((vars->ieee_fc &
7263             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7264             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7265                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7266         }
7267         if ((vars->ieee_fc &
7268             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7269             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7270                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7271         }
7272         DP(NETIF_MSG_LINK,
7273                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7274
7275         bnx2x_cl45_write(bp, phy,
7276                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7277         msleep(500);
7278 }
7279
7280 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7281                                      struct link_params *params,
7282                                      u32 action)
7283 {
7284         struct bnx2x *bp = params->bp;
7285         switch (action) {
7286         case PHY_INIT:
7287                 /* Enable LASI */
7288                 bnx2x_cl45_write(bp, phy,
7289                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7290                 bnx2x_cl45_write(bp, phy,
7291                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7292                 break;
7293         }
7294 }
7295
7296 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7297                                   struct link_params *params,
7298                                   struct link_vars *vars)
7299 {
7300         struct bnx2x *bp = params->bp;
7301         u16 val = 0, tmp1;
7302         u8 gpio_port;
7303         DP(NETIF_MSG_LINK, "Init 8073\n");
7304
7305         if (CHIP_IS_E2(bp))
7306                 gpio_port = BP_PATH(bp);
7307         else
7308                 gpio_port = params->port;
7309         /* Restore normal power mode*/
7310         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7311                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7312
7313         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7314                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7315
7316         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7317         bnx2x_8073_set_pause_cl37(params, phy, vars);
7318
7319         bnx2x_cl45_read(bp, phy,
7320                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7321
7322         bnx2x_cl45_read(bp, phy,
7323                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7324
7325         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7326
7327         /* Swap polarity if required - Must be done only in non-1G mode */
7328         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7329                 /* Configure the 8073 to swap _P and _N of the KR lines */
7330                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7331                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7332                 bnx2x_cl45_read(bp, phy,
7333                                 MDIO_PMA_DEVAD,
7334                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7335                 bnx2x_cl45_write(bp, phy,
7336                                  MDIO_PMA_DEVAD,
7337                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7338                                  (val | (3<<9)));
7339         }
7340
7341
7342         /* Enable CL37 BAM */
7343         if (REG_RD(bp, params->shmem_base +
7344                          offsetof(struct shmem_region, dev_info.
7345                                   port_hw_config[params->port].default_cfg)) &
7346             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7347
7348                 bnx2x_cl45_read(bp, phy,
7349                                 MDIO_AN_DEVAD,
7350                                 MDIO_AN_REG_8073_BAM, &val);
7351                 bnx2x_cl45_write(bp, phy,
7352                                  MDIO_AN_DEVAD,
7353                                  MDIO_AN_REG_8073_BAM, val | 1);
7354                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7355         }
7356         if (params->loopback_mode == LOOPBACK_EXT) {
7357                 bnx2x_807x_force_10G(bp, phy);
7358                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7359                 return 0;
7360         } else {
7361                 bnx2x_cl45_write(bp, phy,
7362                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7363         }
7364         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7365                 if (phy->req_line_speed == SPEED_10000) {
7366                         val = (1<<7);
7367                 } else if (phy->req_line_speed ==  SPEED_2500) {
7368                         val = (1<<5);
7369                         /* Note that 2.5G works only when used with 1G
7370                          * advertisement
7371                          */
7372                 } else
7373                         val = (1<<5);
7374         } else {
7375                 val = 0;
7376                 if (phy->speed_cap_mask &
7377                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7378                         val |= (1<<7);
7379
7380                 /* Note that 2.5G works only when used with 1G advertisement */
7381                 if (phy->speed_cap_mask &
7382                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7383                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7384                         val |= (1<<5);
7385                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7386         }
7387
7388         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7389         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7390
7391         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7392              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7393             (phy->req_line_speed == SPEED_2500)) {
7394                 u16 phy_ver;
7395                 /* Allow 2.5G for A1 and above */
7396                 bnx2x_cl45_read(bp, phy,
7397                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7398                                 &phy_ver);
7399                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7400                 if (phy_ver > 0)
7401                         tmp1 |= 1;
7402                 else
7403                         tmp1 &= 0xfffe;
7404         } else {
7405                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7406                 tmp1 &= 0xfffe;
7407         }
7408
7409         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7410         /* Add support for CL37 (passive mode) II */
7411
7412         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7413         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7414                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7415                                   0x20 : 0x40)));
7416
7417         /* Add support for CL37 (passive mode) III */
7418         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7419
7420         /* The SNR will improve about 2db by changing BW and FEE main
7421          * tap. Rest commands are executed after link is up
7422          * Change FFE main cursor to 5 in EDC register
7423          */
7424         if (bnx2x_8073_is_snr_needed(bp, phy))
7425                 bnx2x_cl45_write(bp, phy,
7426                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7427                                  0xFB0C);
7428
7429         /* Enable FEC (Forware Error Correction) Request in the AN */
7430         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7431         tmp1 |= (1<<15);
7432         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7433
7434         bnx2x_ext_phy_set_pause(params, phy, vars);
7435
7436         /* Restart autoneg */
7437         msleep(500);
7438         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7439         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7440                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7441         return 0;
7442 }
7443
7444 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7445                                  struct link_params *params,
7446                                  struct link_vars *vars)
7447 {
7448         struct bnx2x *bp = params->bp;
7449         u8 link_up = 0;
7450         u16 val1, val2;
7451         u16 link_status = 0;
7452         u16 an1000_status = 0;
7453
7454         bnx2x_cl45_read(bp, phy,
7455                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7456
7457         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7458
7459         /* Clear the interrupt LASI status register */
7460         bnx2x_cl45_read(bp, phy,
7461                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7462         bnx2x_cl45_read(bp, phy,
7463                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7464         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7465         /* Clear MSG-OUT */
7466         bnx2x_cl45_read(bp, phy,
7467                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7468
7469         /* Check the LASI */
7470         bnx2x_cl45_read(bp, phy,
7471                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7472
7473         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7474
7475         /* Check the link status */
7476         bnx2x_cl45_read(bp, phy,
7477                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7478         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7479
7480         bnx2x_cl45_read(bp, phy,
7481                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7482         bnx2x_cl45_read(bp, phy,
7483                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7484         link_up = ((val1 & 4) == 4);
7485         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7486
7487         if (link_up &&
7488              ((phy->req_line_speed != SPEED_10000))) {
7489                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7490                         return 0;
7491         }
7492         bnx2x_cl45_read(bp, phy,
7493                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7494         bnx2x_cl45_read(bp, phy,
7495                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7496
7497         /* Check the link status on 1.1.2 */
7498         bnx2x_cl45_read(bp, phy,
7499                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7500         bnx2x_cl45_read(bp, phy,
7501                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7502         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7503                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7504
7505         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7506         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7507                 /* The SNR will improve about 2dbby changing the BW and FEE main
7508                  * tap. The 1st write to change FFE main tap is set before
7509                  * restart AN. Change PLL Bandwidth in EDC register
7510                  */
7511                 bnx2x_cl45_write(bp, phy,
7512                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7513                                  0x26BC);
7514
7515                 /* Change CDR Bandwidth in EDC register */
7516                 bnx2x_cl45_write(bp, phy,
7517                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7518                                  0x0333);
7519         }
7520         bnx2x_cl45_read(bp, phy,
7521                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7522                         &link_status);
7523
7524         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7525         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7526                 link_up = 1;
7527                 vars->line_speed = SPEED_10000;
7528                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7529                            params->port);
7530         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7531                 link_up = 1;
7532                 vars->line_speed = SPEED_2500;
7533                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7534                            params->port);
7535         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7536                 link_up = 1;
7537                 vars->line_speed = SPEED_1000;
7538                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7539                            params->port);
7540         } else {
7541                 link_up = 0;
7542                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7543                            params->port);
7544         }
7545
7546         if (link_up) {
7547                 /* Swap polarity if required */
7548                 if (params->lane_config &
7549                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7550                         /* Configure the 8073 to swap P and N of the KR lines */
7551                         bnx2x_cl45_read(bp, phy,
7552                                         MDIO_XS_DEVAD,
7553                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7554                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7555                          * when it`s in 10G mode.
7556                          */
7557                         if (vars->line_speed == SPEED_1000) {
7558                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7559                                               "the 8073\n");
7560                                 val1 |= (1<<3);
7561                         } else
7562                                 val1 &= ~(1<<3);
7563
7564                         bnx2x_cl45_write(bp, phy,
7565                                          MDIO_XS_DEVAD,
7566                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7567                                          val1);
7568                 }
7569                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7570                 bnx2x_8073_resolve_fc(phy, params, vars);
7571                 vars->duplex = DUPLEX_FULL;
7572         }
7573
7574         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7575                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7576                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7577
7578                 if (val1 & (1<<5))
7579                         vars->link_status |=
7580                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7581                 if (val1 & (1<<7))
7582                         vars->link_status |=
7583                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7584         }
7585
7586         return link_up;
7587 }
7588
7589 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7590                                   struct link_params *params)
7591 {
7592         struct bnx2x *bp = params->bp;
7593         u8 gpio_port;
7594         if (CHIP_IS_E2(bp))
7595                 gpio_port = BP_PATH(bp);
7596         else
7597                 gpio_port = params->port;
7598         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7599            gpio_port);
7600         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7601                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7602                        gpio_port);
7603 }
7604
7605 /******************************************************************/
7606 /*                      BCM8705 PHY SECTION                       */
7607 /******************************************************************/
7608 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7609                                   struct link_params *params,
7610                                   struct link_vars *vars)
7611 {
7612         struct bnx2x *bp = params->bp;
7613         DP(NETIF_MSG_LINK, "init 8705\n");
7614         /* Restore normal power mode*/
7615         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7616                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7617         /* HW reset */
7618         bnx2x_ext_phy_hw_reset(bp, params->port);
7619         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7620         bnx2x_wait_reset_complete(bp, phy, params);
7621
7622         bnx2x_cl45_write(bp, phy,
7623                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7624         bnx2x_cl45_write(bp, phy,
7625                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7626         bnx2x_cl45_write(bp, phy,
7627                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7628         bnx2x_cl45_write(bp, phy,
7629                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7630         /* BCM8705 doesn't have microcode, hence the 0 */
7631         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7632         return 0;
7633 }
7634
7635 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7636                                  struct link_params *params,
7637                                  struct link_vars *vars)
7638 {
7639         u8 link_up = 0;
7640         u16 val1, rx_sd;
7641         struct bnx2x *bp = params->bp;
7642         DP(NETIF_MSG_LINK, "read status 8705\n");
7643         bnx2x_cl45_read(bp, phy,
7644                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7645         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7646
7647         bnx2x_cl45_read(bp, phy,
7648                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7649         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7650
7651         bnx2x_cl45_read(bp, phy,
7652                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7653
7654         bnx2x_cl45_read(bp, phy,
7655                       MDIO_PMA_DEVAD, 0xc809, &val1);
7656         bnx2x_cl45_read(bp, phy,
7657                       MDIO_PMA_DEVAD, 0xc809, &val1);
7658
7659         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7660         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7661         if (link_up) {
7662                 vars->line_speed = SPEED_10000;
7663                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7664         }
7665         return link_up;
7666 }
7667
7668 /******************************************************************/
7669 /*                      SFP+ module Section                       */
7670 /******************************************************************/
7671 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7672                                            struct bnx2x_phy *phy,
7673                                            u8 pmd_dis)
7674 {
7675         struct bnx2x *bp = params->bp;
7676         /* Disable transmitter only for bootcodes which can enable it afterwards
7677          * (for D3 link)
7678          */
7679         if (pmd_dis) {
7680                 if (params->feature_config_flags &
7681                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7682                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7683                 else {
7684                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7685                         return;
7686                 }
7687         } else
7688                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7689         bnx2x_cl45_write(bp, phy,
7690                          MDIO_PMA_DEVAD,
7691                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7692 }
7693
7694 static u8 bnx2x_get_gpio_port(struct link_params *params)
7695 {
7696         u8 gpio_port;
7697         u32 swap_val, swap_override;
7698         struct bnx2x *bp = params->bp;
7699         if (CHIP_IS_E2(bp))
7700                 gpio_port = BP_PATH(bp);
7701         else
7702                 gpio_port = params->port;
7703         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7704         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7705         return gpio_port ^ (swap_val && swap_override);
7706 }
7707
7708 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7709                                            struct bnx2x_phy *phy,
7710                                            u8 tx_en)
7711 {
7712         u16 val;
7713         u8 port = params->port;
7714         struct bnx2x *bp = params->bp;
7715         u32 tx_en_mode;
7716
7717         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7718         tx_en_mode = REG_RD(bp, params->shmem_base +
7719                             offsetof(struct shmem_region,
7720                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7721                 PORT_HW_CFG_TX_LASER_MASK;
7722         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7723                            "mode = %x\n", tx_en, port, tx_en_mode);
7724         switch (tx_en_mode) {
7725         case PORT_HW_CFG_TX_LASER_MDIO:
7726
7727                 bnx2x_cl45_read(bp, phy,
7728                                 MDIO_PMA_DEVAD,
7729                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7730                                 &val);
7731
7732                 if (tx_en)
7733                         val &= ~(1<<15);
7734                 else
7735                         val |= (1<<15);
7736
7737                 bnx2x_cl45_write(bp, phy,
7738                                  MDIO_PMA_DEVAD,
7739                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7740                                  val);
7741         break;
7742         case PORT_HW_CFG_TX_LASER_GPIO0:
7743         case PORT_HW_CFG_TX_LASER_GPIO1:
7744         case PORT_HW_CFG_TX_LASER_GPIO2:
7745         case PORT_HW_CFG_TX_LASER_GPIO3:
7746         {
7747                 u16 gpio_pin;
7748                 u8 gpio_port, gpio_mode;
7749                 if (tx_en)
7750                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7751                 else
7752                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7753
7754                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7755                 gpio_port = bnx2x_get_gpio_port(params);
7756                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7757                 break;
7758         }
7759         default:
7760                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7761                 break;
7762         }
7763 }
7764
7765 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7766                                       struct bnx2x_phy *phy,
7767                                       u8 tx_en)
7768 {
7769         struct bnx2x *bp = params->bp;
7770         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7771         if (CHIP_IS_E3(bp))
7772                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7773         else
7774                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7775 }
7776
7777 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7778                                              struct link_params *params,
7779                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7780                                              u8 *o_buf, u8 is_init)
7781 {
7782         struct bnx2x *bp = params->bp;
7783         u16 val = 0;
7784         u16 i;
7785         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7786                 DP(NETIF_MSG_LINK,
7787                    "Reading from eeprom is limited to 0xf\n");
7788                 return -EINVAL;
7789         }
7790         /* Set the read command byte count */
7791         bnx2x_cl45_write(bp, phy,
7792                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7793                          (byte_cnt | (dev_addr << 8)));
7794
7795         /* Set the read command address */
7796         bnx2x_cl45_write(bp, phy,
7797                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7798                          addr);
7799
7800         /* Activate read command */
7801         bnx2x_cl45_write(bp, phy,
7802                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7803                          0x2c0f);
7804
7805         /* Wait up to 500us for command complete status */
7806         for (i = 0; i < 100; i++) {
7807                 bnx2x_cl45_read(bp, phy,
7808                                 MDIO_PMA_DEVAD,
7809                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7810                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7811                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7812                         break;
7813                 udelay(5);
7814         }
7815
7816         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7817                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7818                 DP(NETIF_MSG_LINK,
7819                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7820                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7821                 return -EINVAL;
7822         }
7823
7824         /* Read the buffer */
7825         for (i = 0; i < byte_cnt; i++) {
7826                 bnx2x_cl45_read(bp, phy,
7827                                 MDIO_PMA_DEVAD,
7828                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7829                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7830         }
7831
7832         for (i = 0; i < 100; i++) {
7833                 bnx2x_cl45_read(bp, phy,
7834                                 MDIO_PMA_DEVAD,
7835                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7836                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7837                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7838                         return 0;
7839                 usleep_range(1000, 2000);
7840         }
7841         return -EINVAL;
7842 }
7843
7844 static void bnx2x_warpcore_power_module(struct link_params *params,
7845                                         u8 power)
7846 {
7847         u32 pin_cfg;
7848         struct bnx2x *bp = params->bp;
7849
7850         pin_cfg = (REG_RD(bp, params->shmem_base +
7851                           offsetof(struct shmem_region,
7852                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7853                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7854                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7855
7856         if (pin_cfg == PIN_CFG_NA)
7857                 return;
7858         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7859                        power, pin_cfg);
7860         /* Low ==> corresponding SFP+ module is powered
7861          * high ==> the SFP+ module is powered down
7862          */
7863         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7864 }
7865 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7866                                                  struct link_params *params,
7867                                                  u8 dev_addr,
7868                                                  u16 addr, u8 byte_cnt,
7869                                                  u8 *o_buf, u8 is_init)
7870 {
7871         int rc = 0;
7872         u8 i, j = 0, cnt = 0;
7873         u32 data_array[4];
7874         u16 addr32;
7875         struct bnx2x *bp = params->bp;
7876
7877         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7878                 DP(NETIF_MSG_LINK,
7879                    "Reading from eeprom is limited to 16 bytes\n");
7880                 return -EINVAL;
7881         }
7882
7883         /* 4 byte aligned address */
7884         addr32 = addr & (~0x3);
7885         do {
7886                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7887                         bnx2x_warpcore_power_module(params, 0);
7888                         /* Note that 100us are not enough here */
7889                         usleep_range(1000, 2000);
7890                         bnx2x_warpcore_power_module(params, 1);
7891                 }
7892                 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7893                                     data_array);
7894         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7895
7896         if (rc == 0) {
7897                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7898                         o_buf[j] = *((u8 *)data_array + i);
7899                         j++;
7900                 }
7901         }
7902
7903         return rc;
7904 }
7905
7906 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7907                                              struct link_params *params,
7908                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7909                                              u8 *o_buf, u8 is_init)
7910 {
7911         struct bnx2x *bp = params->bp;
7912         u16 val, i;
7913
7914         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7915                 DP(NETIF_MSG_LINK,
7916                    "Reading from eeprom is limited to 0xf\n");
7917                 return -EINVAL;
7918         }
7919
7920         /* Set 2-wire transfer rate of SFP+ module EEPROM
7921          * to 100Khz since some DACs(direct attached cables) do
7922          * not work at 400Khz.
7923          */
7924         bnx2x_cl45_write(bp, phy,
7925                          MDIO_PMA_DEVAD,
7926                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7927                          ((dev_addr << 8) | 1));
7928
7929         /* Need to read from 1.8000 to clear it */
7930         bnx2x_cl45_read(bp, phy,
7931                         MDIO_PMA_DEVAD,
7932                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7933                         &val);
7934
7935         /* Set the read command byte count */
7936         bnx2x_cl45_write(bp, phy,
7937                          MDIO_PMA_DEVAD,
7938                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7939                          ((byte_cnt < 2) ? 2 : byte_cnt));
7940
7941         /* Set the read command address */
7942         bnx2x_cl45_write(bp, phy,
7943                          MDIO_PMA_DEVAD,
7944                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7945                          addr);
7946         /* Set the destination address */
7947         bnx2x_cl45_write(bp, phy,
7948                          MDIO_PMA_DEVAD,
7949                          0x8004,
7950                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7951
7952         /* Activate read command */
7953         bnx2x_cl45_write(bp, phy,
7954                          MDIO_PMA_DEVAD,
7955                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7956                          0x8002);
7957         /* Wait appropriate time for two-wire command to finish before
7958          * polling the status register
7959          */
7960         usleep_range(1000, 2000);
7961
7962         /* Wait up to 500us for command complete status */
7963         for (i = 0; i < 100; i++) {
7964                 bnx2x_cl45_read(bp, phy,
7965                                 MDIO_PMA_DEVAD,
7966                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7967                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7968                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7969                         break;
7970                 udelay(5);
7971         }
7972
7973         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7974                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7975                 DP(NETIF_MSG_LINK,
7976                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7977                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7978                 return -EFAULT;
7979         }
7980
7981         /* Read the buffer */
7982         for (i = 0; i < byte_cnt; i++) {
7983                 bnx2x_cl45_read(bp, phy,
7984                                 MDIO_PMA_DEVAD,
7985                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7986                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7987         }
7988
7989         for (i = 0; i < 100; i++) {
7990                 bnx2x_cl45_read(bp, phy,
7991                                 MDIO_PMA_DEVAD,
7992                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7993                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7994                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7995                         return 0;
7996                 usleep_range(1000, 2000);
7997         }
7998
7999         return -EINVAL;
8000 }
8001 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8002                                  struct link_params *params, u8 dev_addr,
8003                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8004 {
8005         int rc = 0;
8006         struct bnx2x *bp = params->bp;
8007         u8 xfer_size;
8008         u8 *user_data = o_buf;
8009         read_sfp_module_eeprom_func_p read_func;
8010
8011         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8012                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8013                 return -EINVAL;
8014         }
8015
8016         switch (phy->type) {
8017         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8018                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8019                 break;
8020         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8021         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8022                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8023                 break;
8024         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8025                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8026                 break;
8027         default:
8028                 return -EOPNOTSUPP;
8029         }
8030
8031         while (!rc && (byte_cnt > 0)) {
8032                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8033                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8034                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8035                                user_data, 0);
8036                 byte_cnt -= xfer_size;
8037                 user_data += xfer_size;
8038                 addr += xfer_size;
8039         }
8040         return rc;
8041 }
8042
8043 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8044                               struct link_params *params,
8045                               u16 *edc_mode)
8046 {
8047         struct bnx2x *bp = params->bp;
8048         u32 sync_offset = 0, phy_idx, media_types;
8049         u8 gport, val[2], check_limiting_mode = 0;
8050         *edc_mode = EDC_MODE_LIMITING;
8051         phy->media_type = ETH_PHY_UNSPECIFIED;
8052         /* First check for copper cable */
8053         if (bnx2x_read_sfp_module_eeprom(phy,
8054                                          params,
8055                                          I2C_DEV_ADDR_A0,
8056                                          SFP_EEPROM_CON_TYPE_ADDR,
8057                                          2,
8058                                          (u8 *)val) != 0) {
8059                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8060                 return -EINVAL;
8061         }
8062
8063         switch (val[0]) {
8064         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8065         {
8066                 u8 copper_module_type;
8067                 phy->media_type = ETH_PHY_DA_TWINAX;
8068                 /* Check if its active cable (includes SFP+ module)
8069                  * of passive cable
8070                  */
8071                 if (bnx2x_read_sfp_module_eeprom(phy,
8072                                                params,
8073                                                I2C_DEV_ADDR_A0,
8074                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8075                                                1,
8076                                                &copper_module_type) != 0) {
8077                         DP(NETIF_MSG_LINK,
8078                                 "Failed to read copper-cable-type"
8079                                 " from SFP+ EEPROM\n");
8080                         return -EINVAL;
8081                 }
8082
8083                 if (copper_module_type &
8084                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8085                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8086                         check_limiting_mode = 1;
8087                 } else if (copper_module_type &
8088                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8089                                 DP(NETIF_MSG_LINK,
8090                                    "Passive Copper cable detected\n");
8091                                 *edc_mode =
8092                                       EDC_MODE_PASSIVE_DAC;
8093                 } else {
8094                         DP(NETIF_MSG_LINK,
8095                            "Unknown copper-cable-type 0x%x !!!\n",
8096                            copper_module_type);
8097                         return -EINVAL;
8098                 }
8099                 break;
8100         }
8101         case SFP_EEPROM_CON_TYPE_VAL_LC:
8102         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8103                 check_limiting_mode = 1;
8104                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8105                                SFP_EEPROM_COMP_CODE_LR_MASK |
8106                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8107                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8108                         gport = params->port;
8109                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8110                         if (phy->req_line_speed != SPEED_1000) {
8111                                 phy->req_line_speed = SPEED_1000;
8112                                 if (!CHIP_IS_E1x(bp)) {
8113                                         gport = BP_PATH(bp) +
8114                                         (params->port << 1);
8115                                 }
8116                                 netdev_err(bp->dev,
8117                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8118                                            gport);
8119                         }
8120                 } else {
8121                         int idx, cfg_idx = 0;
8122                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8123                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8124                                 if (params->phy[idx].type == phy->type) {
8125                                         cfg_idx = LINK_CONFIG_IDX(idx);
8126                                         break;
8127                                 }
8128                         }
8129                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8130                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8131                 }
8132                 break;
8133         default:
8134                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8135                          val[0]);
8136                 return -EINVAL;
8137         }
8138         sync_offset = params->shmem_base +
8139                 offsetof(struct shmem_region,
8140                          dev_info.port_hw_config[params->port].media_type);
8141         media_types = REG_RD(bp, sync_offset);
8142         /* Update media type for non-PMF sync */
8143         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8144                 if (&(params->phy[phy_idx]) == phy) {
8145                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8146                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8147                         media_types |= ((phy->media_type &
8148                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8149                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8150                         break;
8151                 }
8152         }
8153         REG_WR(bp, sync_offset, media_types);
8154         if (check_limiting_mode) {
8155                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8156                 if (bnx2x_read_sfp_module_eeprom(phy,
8157                                                  params,
8158                                                  I2C_DEV_ADDR_A0,
8159                                                  SFP_EEPROM_OPTIONS_ADDR,
8160                                                  SFP_EEPROM_OPTIONS_SIZE,
8161                                                  options) != 0) {
8162                         DP(NETIF_MSG_LINK,
8163                            "Failed to read Option field from module EEPROM\n");
8164                         return -EINVAL;
8165                 }
8166                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8167                         *edc_mode = EDC_MODE_LINEAR;
8168                 else
8169                         *edc_mode = EDC_MODE_LIMITING;
8170         }
8171         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8172         return 0;
8173 }
8174 /* This function read the relevant field from the module (SFP+), and verify it
8175  * is compliant with this board
8176  */
8177 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8178                                    struct link_params *params)
8179 {
8180         struct bnx2x *bp = params->bp;
8181         u32 val, cmd;
8182         u32 fw_resp, fw_cmd_param;
8183         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8184         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8185         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8186         val = REG_RD(bp, params->shmem_base +
8187                          offsetof(struct shmem_region, dev_info.
8188                                   port_feature_config[params->port].config));
8189         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8190             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8191                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8192                 return 0;
8193         }
8194
8195         if (params->feature_config_flags &
8196             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8197                 /* Use specific phy request */
8198                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8199         } else if (params->feature_config_flags &
8200                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8201                 /* Use first phy request only in case of non-dual media*/
8202                 if (DUAL_MEDIA(params)) {
8203                         DP(NETIF_MSG_LINK,
8204                            "FW does not support OPT MDL verification\n");
8205                         return -EINVAL;
8206                 }
8207                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8208         } else {
8209                 /* No support in OPT MDL detection */
8210                 DP(NETIF_MSG_LINK,
8211                    "FW does not support OPT MDL verification\n");
8212                 return -EINVAL;
8213         }
8214
8215         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8216         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8217         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8218                 DP(NETIF_MSG_LINK, "Approved module\n");
8219                 return 0;
8220         }
8221
8222         /* Format the warning message */
8223         if (bnx2x_read_sfp_module_eeprom(phy,
8224                                          params,
8225                                          I2C_DEV_ADDR_A0,
8226                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8227                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8228                                          (u8 *)vendor_name))
8229                 vendor_name[0] = '\0';
8230         else
8231                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8232         if (bnx2x_read_sfp_module_eeprom(phy,
8233                                          params,
8234                                          I2C_DEV_ADDR_A0,
8235                                          SFP_EEPROM_PART_NO_ADDR,
8236                                          SFP_EEPROM_PART_NO_SIZE,
8237                                          (u8 *)vendor_pn))
8238                 vendor_pn[0] = '\0';
8239         else
8240                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8241
8242         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8243                               " Port %d from %s part number %s\n",
8244                          params->port, vendor_name, vendor_pn);
8245         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8246             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8247                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8248         return -EINVAL;
8249 }
8250
8251 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8252                                                  struct link_params *params)
8253
8254 {
8255         u8 val;
8256         int rc;
8257         struct bnx2x *bp = params->bp;
8258         u16 timeout;
8259         /* Initialization time after hot-plug may take up to 300ms for
8260          * some phys type ( e.g. JDSU )
8261          */
8262
8263         for (timeout = 0; timeout < 60; timeout++) {
8264                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8265                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8266                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8267                                 1);
8268                 else
8269                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8270                                                           I2C_DEV_ADDR_A0,
8271                                                           1, 1, &val);
8272                 if (rc == 0) {
8273                         DP(NETIF_MSG_LINK,
8274                            "SFP+ module initialization took %d ms\n",
8275                            timeout * 5);
8276                         return 0;
8277                 }
8278                 usleep_range(5000, 10000);
8279         }
8280         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8281                                           1, 1, &val);
8282         return rc;
8283 }
8284
8285 static void bnx2x_8727_power_module(struct bnx2x *bp,
8286                                     struct bnx2x_phy *phy,
8287                                     u8 is_power_up) {
8288         /* Make sure GPIOs are not using for LED mode */
8289         u16 val;
8290         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8291          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8292          * output
8293          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8294          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8295          * where the 1st bit is the over-current(only input), and 2nd bit is
8296          * for power( only output )
8297          *
8298          * In case of NOC feature is disabled and power is up, set GPIO control
8299          *  as input to enable listening of over-current indication
8300          */
8301         if (phy->flags & FLAGS_NOC)
8302                 return;
8303         if (is_power_up)
8304                 val = (1<<4);
8305         else
8306                 /* Set GPIO control to OUTPUT, and set the power bit
8307                  * to according to the is_power_up
8308                  */
8309                 val = (1<<1);
8310
8311         bnx2x_cl45_write(bp, phy,
8312                          MDIO_PMA_DEVAD,
8313                          MDIO_PMA_REG_8727_GPIO_CTRL,
8314                          val);
8315 }
8316
8317 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8318                                         struct bnx2x_phy *phy,
8319                                         u16 edc_mode)
8320 {
8321         u16 cur_limiting_mode;
8322
8323         bnx2x_cl45_read(bp, phy,
8324                         MDIO_PMA_DEVAD,
8325                         MDIO_PMA_REG_ROM_VER2,
8326                         &cur_limiting_mode);
8327         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8328                  cur_limiting_mode);
8329
8330         if (edc_mode == EDC_MODE_LIMITING) {
8331                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8332                 bnx2x_cl45_write(bp, phy,
8333                                  MDIO_PMA_DEVAD,
8334                                  MDIO_PMA_REG_ROM_VER2,
8335                                  EDC_MODE_LIMITING);
8336         } else { /* LRM mode ( default )*/
8337
8338                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8339
8340                 /* Changing to LRM mode takes quite few seconds. So do it only
8341                  * if current mode is limiting (default is LRM)
8342                  */
8343                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8344                         return 0;
8345
8346                 bnx2x_cl45_write(bp, phy,
8347                                  MDIO_PMA_DEVAD,
8348                                  MDIO_PMA_REG_LRM_MODE,
8349                                  0);
8350                 bnx2x_cl45_write(bp, phy,
8351                                  MDIO_PMA_DEVAD,
8352                                  MDIO_PMA_REG_ROM_VER2,
8353                                  0x128);
8354                 bnx2x_cl45_write(bp, phy,
8355                                  MDIO_PMA_DEVAD,
8356                                  MDIO_PMA_REG_MISC_CTRL0,
8357                                  0x4008);
8358                 bnx2x_cl45_write(bp, phy,
8359                                  MDIO_PMA_DEVAD,
8360                                  MDIO_PMA_REG_LRM_MODE,
8361                                  0xaaaa);
8362         }
8363         return 0;
8364 }
8365
8366 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8367                                         struct bnx2x_phy *phy,
8368                                         u16 edc_mode)
8369 {
8370         u16 phy_identifier;
8371         u16 rom_ver2_val;
8372         bnx2x_cl45_read(bp, phy,
8373                         MDIO_PMA_DEVAD,
8374                         MDIO_PMA_REG_PHY_IDENTIFIER,
8375                         &phy_identifier);
8376
8377         bnx2x_cl45_write(bp, phy,
8378                          MDIO_PMA_DEVAD,
8379                          MDIO_PMA_REG_PHY_IDENTIFIER,
8380                          (phy_identifier & ~(1<<9)));
8381
8382         bnx2x_cl45_read(bp, phy,
8383                         MDIO_PMA_DEVAD,
8384                         MDIO_PMA_REG_ROM_VER2,
8385                         &rom_ver2_val);
8386         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8387         bnx2x_cl45_write(bp, phy,
8388                          MDIO_PMA_DEVAD,
8389                          MDIO_PMA_REG_ROM_VER2,
8390                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8391
8392         bnx2x_cl45_write(bp, phy,
8393                          MDIO_PMA_DEVAD,
8394                          MDIO_PMA_REG_PHY_IDENTIFIER,
8395                          (phy_identifier | (1<<9)));
8396
8397         return 0;
8398 }
8399
8400 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8401                                      struct link_params *params,
8402                                      u32 action)
8403 {
8404         struct bnx2x *bp = params->bp;
8405         u16 val;
8406         switch (action) {
8407         case DISABLE_TX:
8408                 bnx2x_sfp_set_transmitter(params, phy, 0);
8409                 break;
8410         case ENABLE_TX:
8411                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8412                         bnx2x_sfp_set_transmitter(params, phy, 1);
8413                 break;
8414         case PHY_INIT:
8415                 bnx2x_cl45_write(bp, phy,
8416                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8417                                  (1<<2) | (1<<5));
8418                 bnx2x_cl45_write(bp, phy,
8419                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8420                                  0);
8421                 bnx2x_cl45_write(bp, phy,
8422                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8423                 /* Make MOD_ABS give interrupt on change */
8424                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8425                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8426                                 &val);
8427                 val |= (1<<12);
8428                 if (phy->flags & FLAGS_NOC)
8429                         val |= (3<<5);
8430                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8431                  * status which reflect SFP+ module over-current
8432                  */
8433                 if (!(phy->flags & FLAGS_NOC))
8434                         val &= 0xff8f; /* Reset bits 4-6 */
8435                 bnx2x_cl45_write(bp, phy,
8436                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8437                                  val);
8438                 break;
8439         default:
8440                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8441                    action);
8442                 return;
8443         }
8444 }
8445
8446 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8447                                            u8 gpio_mode)
8448 {
8449         struct bnx2x *bp = params->bp;
8450
8451         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8452                             offsetof(struct shmem_region,
8453                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8454                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8455         switch (fault_led_gpio) {
8456         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8457                 return;
8458         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8459         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8460         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8461         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8462         {
8463                 u8 gpio_port = bnx2x_get_gpio_port(params);
8464                 u16 gpio_pin = fault_led_gpio -
8465                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8466                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8467                                    "pin %x port %x mode %x\n",
8468                                gpio_pin, gpio_port, gpio_mode);
8469                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8470         }
8471         break;
8472         default:
8473                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8474                                fault_led_gpio);
8475         }
8476 }
8477
8478 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8479                                           u8 gpio_mode)
8480 {
8481         u32 pin_cfg;
8482         u8 port = params->port;
8483         struct bnx2x *bp = params->bp;
8484         pin_cfg = (REG_RD(bp, params->shmem_base +
8485                          offsetof(struct shmem_region,
8486                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8487                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8488                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8489         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8490                        gpio_mode, pin_cfg);
8491         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8492 }
8493
8494 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8495                                            u8 gpio_mode)
8496 {
8497         struct bnx2x *bp = params->bp;
8498         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8499         if (CHIP_IS_E3(bp)) {
8500                 /* Low ==> if SFP+ module is supported otherwise
8501                  * High ==> if SFP+ module is not on the approved vendor list
8502                  */
8503                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8504         } else
8505                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8506 }
8507
8508 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8509                                     struct link_params *params)
8510 {
8511         struct bnx2x *bp = params->bp;
8512         bnx2x_warpcore_power_module(params, 0);
8513         /* Put Warpcore in low power mode */
8514         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8515
8516         /* Put LCPLL in low power mode */
8517         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8518         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8519         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8520 }
8521
8522 static void bnx2x_power_sfp_module(struct link_params *params,
8523                                    struct bnx2x_phy *phy,
8524                                    u8 power)
8525 {
8526         struct bnx2x *bp = params->bp;
8527         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8528
8529         switch (phy->type) {
8530         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8531         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8532                 bnx2x_8727_power_module(params->bp, phy, power);
8533                 break;
8534         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8535                 bnx2x_warpcore_power_module(params, power);
8536                 break;
8537         default:
8538                 break;
8539         }
8540 }
8541 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8542                                              struct bnx2x_phy *phy,
8543                                              u16 edc_mode)
8544 {
8545         u16 val = 0;
8546         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8547         struct bnx2x *bp = params->bp;
8548
8549         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8550         /* This is a global register which controls all lanes */
8551         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8552                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8553         val &= ~(0xf << (lane << 2));
8554
8555         switch (edc_mode) {
8556         case EDC_MODE_LINEAR:
8557         case EDC_MODE_LIMITING:
8558                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8559                 break;
8560         case EDC_MODE_PASSIVE_DAC:
8561                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8562                 break;
8563         default:
8564                 break;
8565         }
8566
8567         val |= (mode << (lane << 2));
8568         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8569                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8570         /* A must read */
8571         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8572                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8573
8574         /* Restart microcode to re-read the new mode */
8575         bnx2x_warpcore_reset_lane(bp, phy, 1);
8576         bnx2x_warpcore_reset_lane(bp, phy, 0);
8577
8578 }
8579
8580 static void bnx2x_set_limiting_mode(struct link_params *params,
8581                                     struct bnx2x_phy *phy,
8582                                     u16 edc_mode)
8583 {
8584         switch (phy->type) {
8585         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8586                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8587                 break;
8588         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8589         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8590                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8591                 break;
8592         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8593                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8594                 break;
8595         }
8596 }
8597
8598 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8599                                struct link_params *params)
8600 {
8601         struct bnx2x *bp = params->bp;
8602         u16 edc_mode;
8603         int rc = 0;
8604
8605         u32 val = REG_RD(bp, params->shmem_base +
8606                              offsetof(struct shmem_region, dev_info.
8607                                      port_feature_config[params->port].config));
8608         /* Enabled transmitter by default */
8609         bnx2x_sfp_set_transmitter(params, phy, 1);
8610         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8611                  params->port);
8612         /* Power up module */
8613         bnx2x_power_sfp_module(params, phy, 1);
8614         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8615                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8616                 return -EINVAL;
8617         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8618                 /* Check SFP+ module compatibility */
8619                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8620                 rc = -EINVAL;
8621                 /* Turn on fault module-detected led */
8622                 bnx2x_set_sfp_module_fault_led(params,
8623                                                MISC_REGISTERS_GPIO_HIGH);
8624
8625                 /* Check if need to power down the SFP+ module */
8626                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8627                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8628                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8629                         bnx2x_power_sfp_module(params, phy, 0);
8630                         return rc;
8631                 }
8632         } else {
8633                 /* Turn off fault module-detected led */
8634                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8635         }
8636
8637         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8638          * is done automatically
8639          */
8640         bnx2x_set_limiting_mode(params, phy, edc_mode);
8641
8642         /* Disable transmit for this module if the module is not approved, and
8643          * laser needs to be disabled.
8644          */
8645         if ((rc) &&
8646             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8647              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8648                 bnx2x_sfp_set_transmitter(params, phy, 0);
8649
8650         return rc;
8651 }
8652
8653 void bnx2x_handle_module_detect_int(struct link_params *params)
8654 {
8655         struct bnx2x *bp = params->bp;
8656         struct bnx2x_phy *phy;
8657         u32 gpio_val;
8658         u8 gpio_num, gpio_port;
8659         if (CHIP_IS_E3(bp)) {
8660                 phy = &params->phy[INT_PHY];
8661                 /* Always enable TX laser,will be disabled in case of fault */
8662                 bnx2x_sfp_set_transmitter(params, phy, 1);
8663         } else {
8664                 phy = &params->phy[EXT_PHY1];
8665         }
8666         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8667                                       params->port, &gpio_num, &gpio_port) ==
8668             -EINVAL) {
8669                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8670                 return;
8671         }
8672
8673         /* Set valid module led off */
8674         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8675
8676         /* Get current gpio val reflecting module plugged in / out*/
8677         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8678
8679         /* Call the handling function in case module is detected */
8680         if (gpio_val == 0) {
8681                 bnx2x_set_mdio_emac_per_phy(bp, params);
8682                 bnx2x_set_aer_mmd(params, phy);
8683
8684                 bnx2x_power_sfp_module(params, phy, 1);
8685                 bnx2x_set_gpio_int(bp, gpio_num,
8686                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8687                                    gpio_port);
8688                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8689                         bnx2x_sfp_module_detection(phy, params);
8690                         if (CHIP_IS_E3(bp)) {
8691                                 u16 rx_tx_in_reset;
8692                                 /* In case WC is out of reset, reconfigure the
8693                                  * link speed while taking into account 1G
8694                                  * module limitation.
8695                                  */
8696                                 bnx2x_cl45_read(bp, phy,
8697                                                 MDIO_WC_DEVAD,
8698                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8699                                                 &rx_tx_in_reset);
8700                                 if ((!rx_tx_in_reset) &&
8701                                     (params->link_flags &
8702                                      PHY_INITIALIZED)) {
8703                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8704                                         bnx2x_warpcore_config_sfi(phy, params);
8705                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8706                                 }
8707                         }
8708                 } else {
8709                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8710                 }
8711         } else {
8712                 bnx2x_set_gpio_int(bp, gpio_num,
8713                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8714                                    gpio_port);
8715                 /* Module was plugged out.
8716                  * Disable transmit for this module
8717                  */
8718                 phy->media_type = ETH_PHY_NOT_PRESENT;
8719         }
8720 }
8721
8722 /******************************************************************/
8723 /*              Used by 8706 and 8727                             */
8724 /******************************************************************/
8725 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8726                                  struct bnx2x_phy *phy,
8727                                  u16 alarm_status_offset,
8728                                  u16 alarm_ctrl_offset)
8729 {
8730         u16 alarm_status, val;
8731         bnx2x_cl45_read(bp, phy,
8732                         MDIO_PMA_DEVAD, alarm_status_offset,
8733                         &alarm_status);
8734         bnx2x_cl45_read(bp, phy,
8735                         MDIO_PMA_DEVAD, alarm_status_offset,
8736                         &alarm_status);
8737         /* Mask or enable the fault event. */
8738         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8739         if (alarm_status & (1<<0))
8740                 val &= ~(1<<0);
8741         else
8742                 val |= (1<<0);
8743         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8744 }
8745 /******************************************************************/
8746 /*              common BCM8706/BCM8726 PHY SECTION                */
8747 /******************************************************************/
8748 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8749                                       struct link_params *params,
8750                                       struct link_vars *vars)
8751 {
8752         u8 link_up = 0;
8753         u16 val1, val2, rx_sd, pcs_status;
8754         struct bnx2x *bp = params->bp;
8755         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8756         /* Clear RX Alarm*/
8757         bnx2x_cl45_read(bp, phy,
8758                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8759
8760         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8761                              MDIO_PMA_LASI_TXCTRL);
8762
8763         /* Clear LASI indication*/
8764         bnx2x_cl45_read(bp, phy,
8765                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8766         bnx2x_cl45_read(bp, phy,
8767                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8768         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8769
8770         bnx2x_cl45_read(bp, phy,
8771                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8772         bnx2x_cl45_read(bp, phy,
8773                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8774         bnx2x_cl45_read(bp, phy,
8775                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8776         bnx2x_cl45_read(bp, phy,
8777                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8778
8779         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8780                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8781         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8782          * are set, or if the autoneg bit 1 is set
8783          */
8784         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8785         if (link_up) {
8786                 if (val2 & (1<<1))
8787                         vars->line_speed = SPEED_1000;
8788                 else
8789                         vars->line_speed = SPEED_10000;
8790                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8791                 vars->duplex = DUPLEX_FULL;
8792         }
8793
8794         /* Capture 10G link fault. Read twice to clear stale value. */
8795         if (vars->line_speed == SPEED_10000) {
8796                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8797                             MDIO_PMA_LASI_TXSTAT, &val1);
8798                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8799                             MDIO_PMA_LASI_TXSTAT, &val1);
8800                 if (val1 & (1<<0))
8801                         vars->fault_detected = 1;
8802         }
8803
8804         return link_up;
8805 }
8806
8807 /******************************************************************/
8808 /*                      BCM8706 PHY SECTION                       */
8809 /******************************************************************/
8810 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8811                                  struct link_params *params,
8812                                  struct link_vars *vars)
8813 {
8814         u32 tx_en_mode;
8815         u16 cnt, val, tmp1;
8816         struct bnx2x *bp = params->bp;
8817
8818         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8819                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8820         /* HW reset */
8821         bnx2x_ext_phy_hw_reset(bp, params->port);
8822         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8823         bnx2x_wait_reset_complete(bp, phy, params);
8824
8825         /* Wait until fw is loaded */
8826         for (cnt = 0; cnt < 100; cnt++) {
8827                 bnx2x_cl45_read(bp, phy,
8828                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8829                 if (val)
8830                         break;
8831                 usleep_range(10000, 20000);
8832         }
8833         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8834         if ((params->feature_config_flags &
8835              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8836                 u8 i;
8837                 u16 reg;
8838                 for (i = 0; i < 4; i++) {
8839                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8840                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8841                                    MDIO_XS_8706_REG_BANK_RX0);
8842                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8843                         /* Clear first 3 bits of the control */
8844                         val &= ~0x7;
8845                         /* Set control bits according to configuration */
8846                         val |= (phy->rx_preemphasis[i] & 0x7);
8847                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8848                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8849                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8850                 }
8851         }
8852         /* Force speed */
8853         if (phy->req_line_speed == SPEED_10000) {
8854                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8855
8856                 bnx2x_cl45_write(bp, phy,
8857                                  MDIO_PMA_DEVAD,
8858                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8859                 bnx2x_cl45_write(bp, phy,
8860                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8861                                  0);
8862                 /* Arm LASI for link and Tx fault. */
8863                 bnx2x_cl45_write(bp, phy,
8864                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8865         } else {
8866                 /* Force 1Gbps using autoneg with 1G advertisement */
8867
8868                 /* Allow CL37 through CL73 */
8869                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8870                 bnx2x_cl45_write(bp, phy,
8871                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8872
8873                 /* Enable Full-Duplex advertisement on CL37 */
8874                 bnx2x_cl45_write(bp, phy,
8875                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8876                 /* Enable CL37 AN */
8877                 bnx2x_cl45_write(bp, phy,
8878                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8879                 /* 1G support */
8880                 bnx2x_cl45_write(bp, phy,
8881                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8882
8883                 /* Enable clause 73 AN */
8884                 bnx2x_cl45_write(bp, phy,
8885                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8886                 bnx2x_cl45_write(bp, phy,
8887                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8888                                  0x0400);
8889                 bnx2x_cl45_write(bp, phy,
8890                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8891                                  0x0004);
8892         }
8893         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8894
8895         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8896          * power mode, if TX Laser is disabled
8897          */
8898
8899         tx_en_mode = REG_RD(bp, params->shmem_base +
8900                             offsetof(struct shmem_region,
8901                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8902                         & PORT_HW_CFG_TX_LASER_MASK;
8903
8904         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8905                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8906                 bnx2x_cl45_read(bp, phy,
8907                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8908                 tmp1 |= 0x1;
8909                 bnx2x_cl45_write(bp, phy,
8910                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8911         }
8912
8913         return 0;
8914 }
8915
8916 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8917                                   struct link_params *params,
8918                                   struct link_vars *vars)
8919 {
8920         return bnx2x_8706_8726_read_status(phy, params, vars);
8921 }
8922
8923 /******************************************************************/
8924 /*                      BCM8726 PHY SECTION                       */
8925 /******************************************************************/
8926 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8927                                        struct link_params *params)
8928 {
8929         struct bnx2x *bp = params->bp;
8930         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8931         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8932 }
8933
8934 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8935                                          struct link_params *params)
8936 {
8937         struct bnx2x *bp = params->bp;
8938         /* Need to wait 100ms after reset */
8939         msleep(100);
8940
8941         /* Micro controller re-boot */
8942         bnx2x_cl45_write(bp, phy,
8943                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8944
8945         /* Set soft reset */
8946         bnx2x_cl45_write(bp, phy,
8947                          MDIO_PMA_DEVAD,
8948                          MDIO_PMA_REG_GEN_CTRL,
8949                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8950
8951         bnx2x_cl45_write(bp, phy,
8952                          MDIO_PMA_DEVAD,
8953                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8954
8955         bnx2x_cl45_write(bp, phy,
8956                          MDIO_PMA_DEVAD,
8957                          MDIO_PMA_REG_GEN_CTRL,
8958                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8959
8960         /* Wait for 150ms for microcode load */
8961         msleep(150);
8962
8963         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8964         bnx2x_cl45_write(bp, phy,
8965                          MDIO_PMA_DEVAD,
8966                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8967
8968         msleep(200);
8969         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8970 }
8971
8972 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8973                                  struct link_params *params,
8974                                  struct link_vars *vars)
8975 {
8976         struct bnx2x *bp = params->bp;
8977         u16 val1;
8978         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8979         if (link_up) {
8980                 bnx2x_cl45_read(bp, phy,
8981                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8982                                 &val1);
8983                 if (val1 & (1<<15)) {
8984                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8985                         link_up = 0;
8986                         vars->line_speed = 0;
8987                 }
8988         }
8989         return link_up;
8990 }
8991
8992
8993 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8994                                   struct link_params *params,
8995                                   struct link_vars *vars)
8996 {
8997         struct bnx2x *bp = params->bp;
8998         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8999
9000         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9001         bnx2x_wait_reset_complete(bp, phy, params);
9002
9003         bnx2x_8726_external_rom_boot(phy, params);
9004
9005         /* Need to call module detected on initialization since the module
9006          * detection triggered by actual module insertion might occur before
9007          * driver is loaded, and when driver is loaded, it reset all
9008          * registers, including the transmitter
9009          */
9010         bnx2x_sfp_module_detection(phy, params);
9011
9012         if (phy->req_line_speed == SPEED_1000) {
9013                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9014                 bnx2x_cl45_write(bp, phy,
9015                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9016                 bnx2x_cl45_write(bp, phy,
9017                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9018                 bnx2x_cl45_write(bp, phy,
9019                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9020                 bnx2x_cl45_write(bp, phy,
9021                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9022                                  0x400);
9023         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9024                    (phy->speed_cap_mask &
9025                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9026                    ((phy->speed_cap_mask &
9027                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9028                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9029                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9030                 /* Set Flow control */
9031                 bnx2x_ext_phy_set_pause(params, phy, vars);
9032                 bnx2x_cl45_write(bp, phy,
9033                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9034                 bnx2x_cl45_write(bp, phy,
9035                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9036                 bnx2x_cl45_write(bp, phy,
9037                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9038                 bnx2x_cl45_write(bp, phy,
9039                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9040                 bnx2x_cl45_write(bp, phy,
9041                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9042                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9043                  * change
9044                  */
9045                 bnx2x_cl45_write(bp, phy,
9046                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9047                 bnx2x_cl45_write(bp, phy,
9048                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9049                                  0x400);
9050
9051         } else { /* Default 10G. Set only LASI control */
9052                 bnx2x_cl45_write(bp, phy,
9053                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9054         }
9055
9056         /* Set TX PreEmphasis if needed */
9057         if ((params->feature_config_flags &
9058              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9059                 DP(NETIF_MSG_LINK,
9060                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9061                          phy->tx_preemphasis[0],
9062                          phy->tx_preemphasis[1]);
9063                 bnx2x_cl45_write(bp, phy,
9064                                  MDIO_PMA_DEVAD,
9065                                  MDIO_PMA_REG_8726_TX_CTRL1,
9066                                  phy->tx_preemphasis[0]);
9067
9068                 bnx2x_cl45_write(bp, phy,
9069                                  MDIO_PMA_DEVAD,
9070                                  MDIO_PMA_REG_8726_TX_CTRL2,
9071                                  phy->tx_preemphasis[1]);
9072         }
9073
9074         return 0;
9075
9076 }
9077
9078 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9079                                   struct link_params *params)
9080 {
9081         struct bnx2x *bp = params->bp;
9082         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9083         /* Set serial boot control for external load */
9084         bnx2x_cl45_write(bp, phy,
9085                          MDIO_PMA_DEVAD,
9086                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9087 }
9088
9089 /******************************************************************/
9090 /*                      BCM8727 PHY SECTION                       */
9091 /******************************************************************/
9092
9093 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9094                                     struct link_params *params, u8 mode)
9095 {
9096         struct bnx2x *bp = params->bp;
9097         u16 led_mode_bitmask = 0;
9098         u16 gpio_pins_bitmask = 0;
9099         u16 val;
9100         /* Only NOC flavor requires to set the LED specifically */
9101         if (!(phy->flags & FLAGS_NOC))
9102                 return;
9103         switch (mode) {
9104         case LED_MODE_FRONT_PANEL_OFF:
9105         case LED_MODE_OFF:
9106                 led_mode_bitmask = 0;
9107                 gpio_pins_bitmask = 0x03;
9108                 break;
9109         case LED_MODE_ON:
9110                 led_mode_bitmask = 0;
9111                 gpio_pins_bitmask = 0x02;
9112                 break;
9113         case LED_MODE_OPER:
9114                 led_mode_bitmask = 0x60;
9115                 gpio_pins_bitmask = 0x11;
9116                 break;
9117         }
9118         bnx2x_cl45_read(bp, phy,
9119                         MDIO_PMA_DEVAD,
9120                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9121                         &val);
9122         val &= 0xff8f;
9123         val |= led_mode_bitmask;
9124         bnx2x_cl45_write(bp, phy,
9125                          MDIO_PMA_DEVAD,
9126                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9127                          val);
9128         bnx2x_cl45_read(bp, phy,
9129                         MDIO_PMA_DEVAD,
9130                         MDIO_PMA_REG_8727_GPIO_CTRL,
9131                         &val);
9132         val &= 0xffe0;
9133         val |= gpio_pins_bitmask;
9134         bnx2x_cl45_write(bp, phy,
9135                          MDIO_PMA_DEVAD,
9136                          MDIO_PMA_REG_8727_GPIO_CTRL,
9137                          val);
9138 }
9139 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9140                                 struct link_params *params) {
9141         u32 swap_val, swap_override;
9142         u8 port;
9143         /* The PHY reset is controlled by GPIO 1. Fake the port number
9144          * to cancel the swap done in set_gpio()
9145          */
9146         struct bnx2x *bp = params->bp;
9147         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9148         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9149         port = (swap_val && swap_override) ^ 1;
9150         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9151                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9152 }
9153
9154 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9155                                     struct link_params *params)
9156 {
9157         struct bnx2x *bp = params->bp;
9158         u16 tmp1, val;
9159         /* Set option 1G speed */
9160         if ((phy->req_line_speed == SPEED_1000) ||
9161             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9162                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9163                 bnx2x_cl45_write(bp, phy,
9164                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9165                 bnx2x_cl45_write(bp, phy,
9166                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9167                 bnx2x_cl45_read(bp, phy,
9168                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9169                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9170                 /* Power down the XAUI until link is up in case of dual-media
9171                  * and 1G
9172                  */
9173                 if (DUAL_MEDIA(params)) {
9174                         bnx2x_cl45_read(bp, phy,
9175                                         MDIO_PMA_DEVAD,
9176                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9177                         val |= (3<<10);
9178                         bnx2x_cl45_write(bp, phy,
9179                                          MDIO_PMA_DEVAD,
9180                                          MDIO_PMA_REG_8727_PCS_GP, val);
9181                 }
9182         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9183                    ((phy->speed_cap_mask &
9184                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9185                    ((phy->speed_cap_mask &
9186                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9187                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9188
9189                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9190                 bnx2x_cl45_write(bp, phy,
9191                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9192                 bnx2x_cl45_write(bp, phy,
9193                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9194         } else {
9195                 /* Since the 8727 has only single reset pin, need to set the 10G
9196                  * registers although it is default
9197                  */
9198                 bnx2x_cl45_write(bp, phy,
9199                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9200                                  0x0020);
9201                 bnx2x_cl45_write(bp, phy,
9202                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9203                 bnx2x_cl45_write(bp, phy,
9204                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9205                 bnx2x_cl45_write(bp, phy,
9206                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9207                                  0x0008);
9208         }
9209 }
9210
9211 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9212                                   struct link_params *params,
9213                                   struct link_vars *vars)
9214 {
9215         u32 tx_en_mode;
9216         u16 tmp1, mod_abs, tmp2;
9217         struct bnx2x *bp = params->bp;
9218         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9219
9220         bnx2x_wait_reset_complete(bp, phy, params);
9221
9222         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9223
9224         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9225         /* Initially configure MOD_ABS to interrupt when module is
9226          * presence( bit 8)
9227          */
9228         bnx2x_cl45_read(bp, phy,
9229                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9230         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9231          * When the EDC is off it locks onto a reference clock and avoids
9232          * becoming 'lost'
9233          */
9234         mod_abs &= ~(1<<8);
9235         if (!(phy->flags & FLAGS_NOC))
9236                 mod_abs &= ~(1<<9);
9237         bnx2x_cl45_write(bp, phy,
9238                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9239
9240         /* Enable/Disable PHY transmitter output */
9241         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9242
9243         bnx2x_8727_power_module(bp, phy, 1);
9244
9245         bnx2x_cl45_read(bp, phy,
9246                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9247
9248         bnx2x_cl45_read(bp, phy,
9249                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9250
9251         bnx2x_8727_config_speed(phy, params);
9252
9253
9254         /* Set TX PreEmphasis if needed */
9255         if ((params->feature_config_flags &
9256              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9257                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9258                            phy->tx_preemphasis[0],
9259                            phy->tx_preemphasis[1]);
9260                 bnx2x_cl45_write(bp, phy,
9261                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9262                                  phy->tx_preemphasis[0]);
9263
9264                 bnx2x_cl45_write(bp, phy,
9265                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9266                                  phy->tx_preemphasis[1]);
9267         }
9268
9269         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9270          * power mode, if TX Laser is disabled
9271          */
9272         tx_en_mode = REG_RD(bp, params->shmem_base +
9273                             offsetof(struct shmem_region,
9274                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9275                         & PORT_HW_CFG_TX_LASER_MASK;
9276
9277         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9278
9279                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9280                 bnx2x_cl45_read(bp, phy,
9281                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9282                 tmp2 |= 0x1000;
9283                 tmp2 &= 0xFFEF;
9284                 bnx2x_cl45_write(bp, phy,
9285                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9286                 bnx2x_cl45_read(bp, phy,
9287                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9288                                 &tmp2);
9289                 bnx2x_cl45_write(bp, phy,
9290                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9291                                  (tmp2 & 0x7fff));
9292         }
9293
9294         return 0;
9295 }
9296
9297 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9298                                       struct link_params *params)
9299 {
9300         struct bnx2x *bp = params->bp;
9301         u16 mod_abs, rx_alarm_status;
9302         u32 val = REG_RD(bp, params->shmem_base +
9303                              offsetof(struct shmem_region, dev_info.
9304                                       port_feature_config[params->port].
9305                                       config));
9306         bnx2x_cl45_read(bp, phy,
9307                         MDIO_PMA_DEVAD,
9308                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9309         if (mod_abs & (1<<8)) {
9310
9311                 /* Module is absent */
9312                 DP(NETIF_MSG_LINK,
9313                    "MOD_ABS indication show module is absent\n");
9314                 phy->media_type = ETH_PHY_NOT_PRESENT;
9315                 /* 1. Set mod_abs to detect next module
9316                  *    presence event
9317                  * 2. Set EDC off by setting OPTXLOS signal input to low
9318                  *    (bit 9).
9319                  *    When the EDC is off it locks onto a reference clock and
9320                  *    avoids becoming 'lost'.
9321                  */
9322                 mod_abs &= ~(1<<8);
9323                 if (!(phy->flags & FLAGS_NOC))
9324                         mod_abs &= ~(1<<9);
9325                 bnx2x_cl45_write(bp, phy,
9326                                  MDIO_PMA_DEVAD,
9327                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9328
9329                 /* Clear RX alarm since it stays up as long as
9330                  * the mod_abs wasn't changed
9331                  */
9332                 bnx2x_cl45_read(bp, phy,
9333                                 MDIO_PMA_DEVAD,
9334                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9335
9336         } else {
9337                 /* Module is present */
9338                 DP(NETIF_MSG_LINK,
9339                    "MOD_ABS indication show module is present\n");
9340                 /* First disable transmitter, and if the module is ok, the
9341                  * module_detection will enable it
9342                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9343                  * 2. Restore the default polarity of the OPRXLOS signal and
9344                  * this signal will then correctly indicate the presence or
9345                  * absence of the Rx signal. (bit 9)
9346                  */
9347                 mod_abs |= (1<<8);
9348                 if (!(phy->flags & FLAGS_NOC))
9349                         mod_abs |= (1<<9);
9350                 bnx2x_cl45_write(bp, phy,
9351                                  MDIO_PMA_DEVAD,
9352                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9353
9354                 /* Clear RX alarm since it stays up as long as the mod_abs
9355                  * wasn't changed. This is need to be done before calling the
9356                  * module detection, otherwise it will clear* the link update
9357                  * alarm
9358                  */
9359                 bnx2x_cl45_read(bp, phy,
9360                                 MDIO_PMA_DEVAD,
9361                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9362
9363
9364                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9365                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9366                         bnx2x_sfp_set_transmitter(params, phy, 0);
9367
9368                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9369                         bnx2x_sfp_module_detection(phy, params);
9370                 else
9371                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9372
9373                 /* Reconfigure link speed based on module type limitations */
9374                 bnx2x_8727_config_speed(phy, params);
9375         }
9376
9377         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9378                    rx_alarm_status);
9379         /* No need to check link status in case of module plugged in/out */
9380 }
9381
9382 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9383                                  struct link_params *params,
9384                                  struct link_vars *vars)
9385
9386 {
9387         struct bnx2x *bp = params->bp;
9388         u8 link_up = 0, oc_port = params->port;
9389         u16 link_status = 0;
9390         u16 rx_alarm_status, lasi_ctrl, val1;
9391
9392         /* If PHY is not initialized, do not check link status */
9393         bnx2x_cl45_read(bp, phy,
9394                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9395                         &lasi_ctrl);
9396         if (!lasi_ctrl)
9397                 return 0;
9398
9399         /* Check the LASI on Rx */
9400         bnx2x_cl45_read(bp, phy,
9401                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9402                         &rx_alarm_status);
9403         vars->line_speed = 0;
9404         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9405
9406         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9407                              MDIO_PMA_LASI_TXCTRL);
9408
9409         bnx2x_cl45_read(bp, phy,
9410                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9411
9412         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9413
9414         /* Clear MSG-OUT */
9415         bnx2x_cl45_read(bp, phy,
9416                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9417
9418         /* If a module is present and there is need to check
9419          * for over current
9420          */
9421         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9422                 /* Check over-current using 8727 GPIO0 input*/
9423                 bnx2x_cl45_read(bp, phy,
9424                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9425                                 &val1);
9426
9427                 if ((val1 & (1<<8)) == 0) {
9428                         if (!CHIP_IS_E1x(bp))
9429                                 oc_port = BP_PATH(bp) + (params->port << 1);
9430                         DP(NETIF_MSG_LINK,
9431                            "8727 Power fault has been detected on port %d\n",
9432                            oc_port);
9433                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9434                                             "been detected and the power to "
9435                                             "that SFP+ module has been removed "
9436                                             "to prevent failure of the card. "
9437                                             "Please remove the SFP+ module and "
9438                                             "restart the system to clear this "
9439                                             "error.\n",
9440                          oc_port);
9441                         /* Disable all RX_ALARMs except for mod_abs */
9442                         bnx2x_cl45_write(bp, phy,
9443                                          MDIO_PMA_DEVAD,
9444                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9445
9446                         bnx2x_cl45_read(bp, phy,
9447                                         MDIO_PMA_DEVAD,
9448                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9449                         /* Wait for module_absent_event */
9450                         val1 |= (1<<8);
9451                         bnx2x_cl45_write(bp, phy,
9452                                          MDIO_PMA_DEVAD,
9453                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9454                         /* Clear RX alarm */
9455                         bnx2x_cl45_read(bp, phy,
9456                                 MDIO_PMA_DEVAD,
9457                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9458                         bnx2x_8727_power_module(params->bp, phy, 0);
9459                         return 0;
9460                 }
9461         } /* Over current check */
9462
9463         /* When module absent bit is set, check module */
9464         if (rx_alarm_status & (1<<5)) {
9465                 bnx2x_8727_handle_mod_abs(phy, params);
9466                 /* Enable all mod_abs and link detection bits */
9467                 bnx2x_cl45_write(bp, phy,
9468                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9469                                  ((1<<5) | (1<<2)));
9470         }
9471
9472         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9473                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9474                 bnx2x_sfp_set_transmitter(params, phy, 1);
9475         } else {
9476                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9477                 return 0;
9478         }
9479
9480         bnx2x_cl45_read(bp, phy,
9481                         MDIO_PMA_DEVAD,
9482                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9483
9484         /* Bits 0..2 --> speed detected,
9485          * Bits 13..15--> link is down
9486          */
9487         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9488                 link_up = 1;
9489                 vars->line_speed = SPEED_10000;
9490                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9491                            params->port);
9492         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9493                 link_up = 1;
9494                 vars->line_speed = SPEED_1000;
9495                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9496                            params->port);
9497         } else {
9498                 link_up = 0;
9499                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9500                            params->port);
9501         }
9502
9503         /* Capture 10G link fault. */
9504         if (vars->line_speed == SPEED_10000) {
9505                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9506                             MDIO_PMA_LASI_TXSTAT, &val1);
9507
9508                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9509                             MDIO_PMA_LASI_TXSTAT, &val1);
9510
9511                 if (val1 & (1<<0)) {
9512                         vars->fault_detected = 1;
9513                 }
9514         }
9515
9516         if (link_up) {
9517                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9518                 vars->duplex = DUPLEX_FULL;
9519                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9520         }
9521
9522         if ((DUAL_MEDIA(params)) &&
9523             (phy->req_line_speed == SPEED_1000)) {
9524                 bnx2x_cl45_read(bp, phy,
9525                                 MDIO_PMA_DEVAD,
9526                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9527                 /* In case of dual-media board and 1G, power up the XAUI side,
9528                  * otherwise power it down. For 10G it is done automatically
9529                  */
9530                 if (link_up)
9531                         val1 &= ~(3<<10);
9532                 else
9533                         val1 |= (3<<10);
9534                 bnx2x_cl45_write(bp, phy,
9535                                  MDIO_PMA_DEVAD,
9536                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9537         }
9538         return link_up;
9539 }
9540
9541 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9542                                   struct link_params *params)
9543 {
9544         struct bnx2x *bp = params->bp;
9545
9546         /* Enable/Disable PHY transmitter output */
9547         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9548
9549         /* Disable Transmitter */
9550         bnx2x_sfp_set_transmitter(params, phy, 0);
9551         /* Clear LASI */
9552         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9553
9554 }
9555
9556 /******************************************************************/
9557 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9558 /******************************************************************/
9559 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9560                                             struct bnx2x *bp,
9561                                             u8 port)
9562 {
9563         u16 val, fw_ver2, cnt, i;
9564         static struct bnx2x_reg_set reg_set[] = {
9565                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9566                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9567                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9568                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9569                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9570         };
9571         u16 fw_ver1;
9572
9573         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9574             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9575                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9576                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9577                                 phy->ver_addr);
9578         } else {
9579                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9580                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9581                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9582                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9583                                          reg_set[i].reg, reg_set[i].val);
9584
9585                 for (cnt = 0; cnt < 100; cnt++) {
9586                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9587                         if (val & 1)
9588                                 break;
9589                         udelay(5);
9590                 }
9591                 if (cnt == 100) {
9592                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9593                                         "phy fw version(1)\n");
9594                         bnx2x_save_spirom_version(bp, port, 0,
9595                                                   phy->ver_addr);
9596                         return;
9597                 }
9598
9599
9600                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9601                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9602                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9603                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9604                 for (cnt = 0; cnt < 100; cnt++) {
9605                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9606                         if (val & 1)
9607                                 break;
9608                         udelay(5);
9609                 }
9610                 if (cnt == 100) {
9611                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9612                                         "version(2)\n");
9613                         bnx2x_save_spirom_version(bp, port, 0,
9614                                                   phy->ver_addr);
9615                         return;
9616                 }
9617
9618                 /* lower 16 bits of the register SPI_FW_STATUS */
9619                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9620                 /* upper 16 bits of register SPI_FW_STATUS */
9621                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9622
9623                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9624                                           phy->ver_addr);
9625         }
9626
9627 }
9628 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9629                                 struct bnx2x_phy *phy)
9630 {
9631         u16 val, offset, i;
9632         static struct bnx2x_reg_set reg_set[] = {
9633                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9634                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9635                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9636                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9637                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9638                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9639                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9640         };
9641         /* PHYC_CTL_LED_CTL */
9642         bnx2x_cl45_read(bp, phy,
9643                         MDIO_PMA_DEVAD,
9644                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9645         val &= 0xFE00;
9646         val |= 0x0092;
9647
9648         bnx2x_cl45_write(bp, phy,
9649                          MDIO_PMA_DEVAD,
9650                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9651
9652         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9653                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9654                                  reg_set[i].val);
9655
9656         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9657             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9658                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9659         else
9660                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9661
9662         /* stretch_en for LED3*/
9663         bnx2x_cl45_read_or_write(bp, phy,
9664                                  MDIO_PMA_DEVAD, offset,
9665                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9666 }
9667
9668 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9669                                       struct link_params *params,
9670                                       u32 action)
9671 {
9672         struct bnx2x *bp = params->bp;
9673         switch (action) {
9674         case PHY_INIT:
9675                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9676                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9677                         /* Save spirom version */
9678                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9679                 }
9680                 /* This phy uses the NIG latch mechanism since link indication
9681                  * arrives through its LED4 and not via its LASI signal, so we
9682                  * get steady signal instead of clear on read
9683                  */
9684                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9685                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9686
9687                 bnx2x_848xx_set_led(bp, phy);
9688                 break;
9689         }
9690 }
9691
9692 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9693                                        struct link_params *params,
9694                                        struct link_vars *vars)
9695 {
9696         struct bnx2x *bp = params->bp;
9697         u16 autoneg_val, an_1000_val, an_10_100_val;
9698
9699         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9700         bnx2x_cl45_write(bp, phy,
9701                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9702
9703         /* set 1000 speed advertisement */
9704         bnx2x_cl45_read(bp, phy,
9705                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9706                         &an_1000_val);
9707
9708         bnx2x_ext_phy_set_pause(params, phy, vars);
9709         bnx2x_cl45_read(bp, phy,
9710                         MDIO_AN_DEVAD,
9711                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9712                         &an_10_100_val);
9713         bnx2x_cl45_read(bp, phy,
9714                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9715                         &autoneg_val);
9716         /* Disable forced speed */
9717         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9718         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9719
9720         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9721              (phy->speed_cap_mask &
9722              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9723             (phy->req_line_speed == SPEED_1000)) {
9724                 an_1000_val |= (1<<8);
9725                 autoneg_val |= (1<<9 | 1<<12);
9726                 if (phy->req_duplex == DUPLEX_FULL)
9727                         an_1000_val |= (1<<9);
9728                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9729         } else
9730                 an_1000_val &= ~((1<<8) | (1<<9));
9731
9732         bnx2x_cl45_write(bp, phy,
9733                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9734                          an_1000_val);
9735
9736         /* set 100 speed advertisement */
9737         if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9738              (phy->speed_cap_mask &
9739               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9740                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))) {
9741                 an_10_100_val |= (1<<7);
9742                 /* Enable autoneg and restart autoneg for legacy speeds */
9743                 autoneg_val |= (1<<9 | 1<<12);
9744
9745                 if (phy->req_duplex == DUPLEX_FULL)
9746                         an_10_100_val |= (1<<8);
9747                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9748         }
9749         /* set 10 speed advertisement */
9750         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9751              (phy->speed_cap_mask &
9752               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9753                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9754              (phy->supported &
9755               (SUPPORTED_10baseT_Half |
9756                SUPPORTED_10baseT_Full)))) {
9757                 an_10_100_val |= (1<<5);
9758                 autoneg_val |= (1<<9 | 1<<12);
9759                 if (phy->req_duplex == DUPLEX_FULL)
9760                         an_10_100_val |= (1<<6);
9761                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9762         }
9763
9764         /* Only 10/100 are allowed to work in FORCE mode */
9765         if ((phy->req_line_speed == SPEED_100) &&
9766             (phy->supported &
9767              (SUPPORTED_100baseT_Half |
9768               SUPPORTED_100baseT_Full))) {
9769                 autoneg_val |= (1<<13);
9770                 /* Enabled AUTO-MDIX when autoneg is disabled */
9771                 bnx2x_cl45_write(bp, phy,
9772                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9773                                  (1<<15 | 1<<9 | 7<<0));
9774                 /* The PHY needs this set even for forced link. */
9775                 an_10_100_val |= (1<<8) | (1<<7);
9776                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9777         }
9778         if ((phy->req_line_speed == SPEED_10) &&
9779             (phy->supported &
9780              (SUPPORTED_10baseT_Half |
9781               SUPPORTED_10baseT_Full))) {
9782                 /* Enabled AUTO-MDIX when autoneg is disabled */
9783                 bnx2x_cl45_write(bp, phy,
9784                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9785                                  (1<<15 | 1<<9 | 7<<0));
9786                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9787         }
9788
9789         bnx2x_cl45_write(bp, phy,
9790                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9791                          an_10_100_val);
9792
9793         if (phy->req_duplex == DUPLEX_FULL)
9794                 autoneg_val |= (1<<8);
9795
9796         /* Always write this if this is not 84833/4.
9797          * For 84833/4, write it only when it's a forced speed.
9798          */
9799         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9800              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9801             ((autoneg_val & (1<<12)) == 0))
9802                 bnx2x_cl45_write(bp, phy,
9803                          MDIO_AN_DEVAD,
9804                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9805
9806         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9807             (phy->speed_cap_mask &
9808              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9809                 (phy->req_line_speed == SPEED_10000)) {
9810                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9811                         /* Restart autoneg for 10G*/
9812
9813                         bnx2x_cl45_read_or_write(
9814                                 bp, phy,
9815                                 MDIO_AN_DEVAD,
9816                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9817                                 0x1000);
9818                         bnx2x_cl45_write(bp, phy,
9819                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9820                                          0x3200);
9821         } else
9822                 bnx2x_cl45_write(bp, phy,
9823                                  MDIO_AN_DEVAD,
9824                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9825                                  1);
9826
9827         return 0;
9828 }
9829
9830 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9831                                   struct link_params *params,
9832                                   struct link_vars *vars)
9833 {
9834         struct bnx2x *bp = params->bp;
9835         /* Restore normal power mode*/
9836         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9837                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9838
9839         /* HW reset */
9840         bnx2x_ext_phy_hw_reset(bp, params->port);
9841         bnx2x_wait_reset_complete(bp, phy, params);
9842
9843         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9844         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9845 }
9846
9847 #define PHY84833_CMDHDLR_WAIT 300
9848 #define PHY84833_CMDHDLR_MAX_ARGS 5
9849 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9850                                 struct link_params *params, u16 fw_cmd,
9851                                 u16 cmd_args[], int argc)
9852 {
9853         int idx;
9854         u16 val;
9855         struct bnx2x *bp = params->bp;
9856         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9857         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9858                         MDIO_84833_CMD_HDLR_STATUS,
9859                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9860         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9861                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9862                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9863                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9864                         break;
9865                 usleep_range(1000, 2000);
9866         }
9867         if (idx >= PHY84833_CMDHDLR_WAIT) {
9868                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9869                 return -EINVAL;
9870         }
9871
9872         /* Prepare argument(s) and issue command */
9873         for (idx = 0; idx < argc; idx++) {
9874                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9875                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9876                                 cmd_args[idx]);
9877         }
9878         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9879                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9880         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9881                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9882                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9883                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9884                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9885                         break;
9886                 usleep_range(1000, 2000);
9887         }
9888         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9889                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9890                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9891                 return -EINVAL;
9892         }
9893         /* Gather returning data */
9894         for (idx = 0; idx < argc; idx++) {
9895                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9896                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9897                                 &cmd_args[idx]);
9898         }
9899         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9900                         MDIO_84833_CMD_HDLR_STATUS,
9901                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9902         return 0;
9903 }
9904
9905 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9906                                    struct link_params *params,
9907                                    struct link_vars *vars)
9908 {
9909         u32 pair_swap;
9910         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9911         int status;
9912         struct bnx2x *bp = params->bp;
9913
9914         /* Check for configuration. */
9915         pair_swap = REG_RD(bp, params->shmem_base +
9916                            offsetof(struct shmem_region,
9917                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9918                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9919
9920         if (pair_swap == 0)
9921                 return 0;
9922
9923         /* Only the second argument is used for this command */
9924         data[1] = (u16)pair_swap;
9925
9926         status = bnx2x_84833_cmd_hdlr(phy, params,
9927                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9928         if (status == 0)
9929                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9930
9931         return status;
9932 }
9933
9934 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9935                                       u32 shmem_base_path[],
9936                                       u32 chip_id)
9937 {
9938         u32 reset_pin[2];
9939         u32 idx;
9940         u8 reset_gpios;
9941         if (CHIP_IS_E3(bp)) {
9942                 /* Assume that these will be GPIOs, not EPIOs. */
9943                 for (idx = 0; idx < 2; idx++) {
9944                         /* Map config param to register bit. */
9945                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9946                                 offsetof(struct shmem_region,
9947                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9948                         reset_pin[idx] = (reset_pin[idx] &
9949                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9950                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9951                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9952                         reset_pin[idx] = (1 << reset_pin[idx]);
9953                 }
9954                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9955         } else {
9956                 /* E2, look from diff place of shmem. */
9957                 for (idx = 0; idx < 2; idx++) {
9958                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9959                                 offsetof(struct shmem_region,
9960                                 dev_info.port_hw_config[0].default_cfg));
9961                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9962                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9963                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9964                         reset_pin[idx] = (1 << reset_pin[idx]);
9965                 }
9966                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9967         }
9968
9969         return reset_gpios;
9970 }
9971
9972 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9973                                 struct link_params *params)
9974 {
9975         struct bnx2x *bp = params->bp;
9976         u8 reset_gpios;
9977         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9978                                 offsetof(struct shmem2_region,
9979                                 other_shmem_base_addr));
9980
9981         u32 shmem_base_path[2];
9982
9983         /* Work around for 84833 LED failure inside RESET status */
9984         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9985                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9986                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
9987         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
9988                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
9989                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
9990
9991         shmem_base_path[0] = params->shmem_base;
9992         shmem_base_path[1] = other_shmem_base_addr;
9993
9994         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9995                                                   params->chip_id);
9996
9997         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9998         udelay(10);
9999         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10000                 reset_gpios);
10001
10002         return 0;
10003 }
10004
10005 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10006                                    struct link_params *params,
10007                                    struct link_vars *vars)
10008 {
10009         int rc;
10010         struct bnx2x *bp = params->bp;
10011         u16 cmd_args = 0;
10012
10013         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10014
10015         /* Prevent Phy from working in EEE and advertising it */
10016         rc = bnx2x_84833_cmd_hdlr(phy, params,
10017                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10018         if (rc) {
10019                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10020                 return rc;
10021         }
10022
10023         return bnx2x_eee_disable(phy, params, vars);
10024 }
10025
10026 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10027                                    struct link_params *params,
10028                                    struct link_vars *vars)
10029 {
10030         int rc;
10031         struct bnx2x *bp = params->bp;
10032         u16 cmd_args = 1;
10033
10034         rc = bnx2x_84833_cmd_hdlr(phy, params,
10035                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10036         if (rc) {
10037                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10038                 return rc;
10039         }
10040
10041         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10042 }
10043
10044 #define PHY84833_CONSTANT_LATENCY 1193
10045 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10046                                    struct link_params *params,
10047                                    struct link_vars *vars)
10048 {
10049         struct bnx2x *bp = params->bp;
10050         u8 port, initialize = 1;
10051         u16 val;
10052         u32 actual_phy_selection;
10053         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10054         int rc = 0;
10055
10056         usleep_range(1000, 2000);
10057
10058         if (!(CHIP_IS_E1x(bp)))
10059                 port = BP_PATH(bp);
10060         else
10061                 port = params->port;
10062
10063         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10064                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10065                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10066                                port);
10067         } else {
10068                 /* MDIO reset */
10069                 bnx2x_cl45_write(bp, phy,
10070                                 MDIO_PMA_DEVAD,
10071                                 MDIO_PMA_REG_CTRL, 0x8000);
10072         }
10073
10074         bnx2x_wait_reset_complete(bp, phy, params);
10075
10076         /* Wait for GPHY to come out of reset */
10077         msleep(50);
10078         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10079             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10080                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10081                  * behavior.
10082                  */
10083                 u16 temp;
10084                 temp = vars->line_speed;
10085                 vars->line_speed = SPEED_10000;
10086                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10087                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10088                 vars->line_speed = temp;
10089         }
10090
10091         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10092                         MDIO_CTL_REG_84823_MEDIA, &val);
10093         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10094                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10095                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10096                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10097                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10098
10099         if (CHIP_IS_E3(bp)) {
10100                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10101                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10102         } else {
10103                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10104                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10105         }
10106
10107         actual_phy_selection = bnx2x_phy_selection(params);
10108
10109         switch (actual_phy_selection) {
10110         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10111                 /* Do nothing. Essentially this is like the priority copper */
10112                 break;
10113         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10114                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10115                 break;
10116         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10117                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10118                 break;
10119         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10120                 /* Do nothing here. The first PHY won't be initialized at all */
10121                 break;
10122         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10123                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10124                 initialize = 0;
10125                 break;
10126         }
10127         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10128                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10129
10130         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10131                          MDIO_CTL_REG_84823_MEDIA, val);
10132         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10133                    params->multi_phy_config, val);
10134
10135         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10136             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10137                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10138
10139                 /* Keep AutogrEEEn disabled. */
10140                 cmd_args[0] = 0x0;
10141                 cmd_args[1] = 0x0;
10142                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10143                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10144                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10145                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10146                         PHY84833_CMDHDLR_MAX_ARGS);
10147                 if (rc)
10148                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10149         }
10150         if (initialize)
10151                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10152         else
10153                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10154         /* 84833 PHY has a better feature and doesn't need to support this. */
10155         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10156                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10157                         offsetof(struct shmem_region,
10158                         dev_info.port_hw_config[params->port].default_cfg)) &
10159                         PORT_HW_CFG_ENABLE_CMS_MASK;
10160
10161                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10162                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10163                 if (cms_enable)
10164                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10165                 else
10166                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10167                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10168                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10169         }
10170
10171         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10172                         MDIO_84833_TOP_CFG_FW_REV, &val);
10173
10174         /* Configure EEE support */
10175         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10176             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10177             bnx2x_eee_has_cap(params)) {
10178                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10179                 if (rc) {
10180                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10181                         bnx2x_8483x_disable_eee(phy, params, vars);
10182                         return rc;
10183                 }
10184
10185                 if ((phy->req_duplex == DUPLEX_FULL) &&
10186                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10187                     (bnx2x_eee_calc_timer(params) ||
10188                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10189                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10190                 else
10191                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10192                 if (rc) {
10193                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10194                         return rc;
10195                 }
10196         } else {
10197                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10198         }
10199
10200         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10201             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10202                 /* Bring PHY out of super isolate mode as the final step. */
10203                 bnx2x_cl45_read_and_write(bp, phy,
10204                                           MDIO_CTL_DEVAD,
10205                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10206                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10207         }
10208         return rc;
10209 }
10210
10211 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10212                                   struct link_params *params,
10213                                   struct link_vars *vars)
10214 {
10215         struct bnx2x *bp = params->bp;
10216         u16 val, val1, val2;
10217         u8 link_up = 0;
10218
10219
10220         /* Check 10G-BaseT link status */
10221         /* Check PMD signal ok */
10222         bnx2x_cl45_read(bp, phy,
10223                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10224         bnx2x_cl45_read(bp, phy,
10225                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10226                         &val2);
10227         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10228
10229         /* Check link 10G */
10230         if (val2 & (1<<11)) {
10231                 vars->line_speed = SPEED_10000;
10232                 vars->duplex = DUPLEX_FULL;
10233                 link_up = 1;
10234                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10235         } else { /* Check Legacy speed link */
10236                 u16 legacy_status, legacy_speed;
10237
10238                 /* Enable expansion register 0x42 (Operation mode status) */
10239                 bnx2x_cl45_write(bp, phy,
10240                                  MDIO_AN_DEVAD,
10241                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10242
10243                 /* Get legacy speed operation status */
10244                 bnx2x_cl45_read(bp, phy,
10245                                 MDIO_AN_DEVAD,
10246                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10247                                 &legacy_status);
10248
10249                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10250                    legacy_status);
10251                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10252                 legacy_speed = (legacy_status & (3<<9));
10253                 if (legacy_speed == (0<<9))
10254                         vars->line_speed = SPEED_10;
10255                 else if (legacy_speed == (1<<9))
10256                         vars->line_speed = SPEED_100;
10257                 else if (legacy_speed == (2<<9))
10258                         vars->line_speed = SPEED_1000;
10259                 else { /* Should not happen: Treat as link down */
10260                         vars->line_speed = 0;
10261                         link_up = 0;
10262                 }
10263
10264                 if (link_up) {
10265                         if (legacy_status & (1<<8))
10266                                 vars->duplex = DUPLEX_FULL;
10267                         else
10268                                 vars->duplex = DUPLEX_HALF;
10269
10270                         DP(NETIF_MSG_LINK,
10271                            "Link is up in %dMbps, is_duplex_full= %d\n",
10272                            vars->line_speed,
10273                            (vars->duplex == DUPLEX_FULL));
10274                         /* Check legacy speed AN resolution */
10275                         bnx2x_cl45_read(bp, phy,
10276                                         MDIO_AN_DEVAD,
10277                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10278                                         &val);
10279                         if (val & (1<<5))
10280                                 vars->link_status |=
10281                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10282                         bnx2x_cl45_read(bp, phy,
10283                                         MDIO_AN_DEVAD,
10284                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10285                                         &val);
10286                         if ((val & (1<<0)) == 0)
10287                                 vars->link_status |=
10288                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10289                 }
10290         }
10291         if (link_up) {
10292                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10293                            vars->line_speed);
10294                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10295
10296                 /* Read LP advertised speeds */
10297                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10298                                 MDIO_AN_REG_CL37_FC_LP, &val);
10299                 if (val & (1<<5))
10300                         vars->link_status |=
10301                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10302                 if (val & (1<<6))
10303                         vars->link_status |=
10304                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10305                 if (val & (1<<7))
10306                         vars->link_status |=
10307                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10308                 if (val & (1<<8))
10309                         vars->link_status |=
10310                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10311                 if (val & (1<<9))
10312                         vars->link_status |=
10313                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10314
10315                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10316                                 MDIO_AN_REG_1000T_STATUS, &val);
10317
10318                 if (val & (1<<10))
10319                         vars->link_status |=
10320                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10321                 if (val & (1<<11))
10322                         vars->link_status |=
10323                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10324
10325                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10326                                 MDIO_AN_REG_MASTER_STATUS, &val);
10327
10328                 if (val & (1<<11))
10329                         vars->link_status |=
10330                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10331
10332                 /* Determine if EEE was negotiated */
10333                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10334                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10335                         bnx2x_eee_an_resolve(phy, params, vars);
10336         }
10337
10338         return link_up;
10339 }
10340
10341 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10342 {
10343         int status = 0;
10344         u32 spirom_ver;
10345         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10346         status = bnx2x_format_ver(spirom_ver, str, len);
10347         return status;
10348 }
10349
10350 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10351                                 struct link_params *params)
10352 {
10353         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10354                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10355         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10356                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10357 }
10358
10359 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10360                                         struct link_params *params)
10361 {
10362         bnx2x_cl45_write(params->bp, phy,
10363                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10364         bnx2x_cl45_write(params->bp, phy,
10365                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10366 }
10367
10368 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10369                                    struct link_params *params)
10370 {
10371         struct bnx2x *bp = params->bp;
10372         u8 port;
10373         u16 val16;
10374
10375         if (!(CHIP_IS_E1x(bp)))
10376                 port = BP_PATH(bp);
10377         else
10378                 port = params->port;
10379
10380         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10381                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10382                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10383                                port);
10384         } else {
10385                 bnx2x_cl45_read(bp, phy,
10386                                 MDIO_CTL_DEVAD,
10387                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10388                 val16 |= MDIO_84833_SUPER_ISOLATE;
10389                 bnx2x_cl45_write(bp, phy,
10390                                  MDIO_CTL_DEVAD,
10391                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10392         }
10393 }
10394
10395 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10396                                      struct link_params *params, u8 mode)
10397 {
10398         struct bnx2x *bp = params->bp;
10399         u16 val;
10400         u8 port;
10401
10402         if (!(CHIP_IS_E1x(bp)))
10403                 port = BP_PATH(bp);
10404         else
10405                 port = params->port;
10406
10407         switch (mode) {
10408         case LED_MODE_OFF:
10409
10410                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10411
10412                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10413                     SHARED_HW_CFG_LED_EXTPHY1) {
10414
10415                         /* Set LED masks */
10416                         bnx2x_cl45_write(bp, phy,
10417                                         MDIO_PMA_DEVAD,
10418                                         MDIO_PMA_REG_8481_LED1_MASK,
10419                                         0x0);
10420
10421                         bnx2x_cl45_write(bp, phy,
10422                                         MDIO_PMA_DEVAD,
10423                                         MDIO_PMA_REG_8481_LED2_MASK,
10424                                         0x0);
10425
10426                         bnx2x_cl45_write(bp, phy,
10427                                         MDIO_PMA_DEVAD,
10428                                         MDIO_PMA_REG_8481_LED3_MASK,
10429                                         0x0);
10430
10431                         bnx2x_cl45_write(bp, phy,
10432                                         MDIO_PMA_DEVAD,
10433                                         MDIO_PMA_REG_8481_LED5_MASK,
10434                                         0x0);
10435
10436                 } else {
10437                         bnx2x_cl45_write(bp, phy,
10438                                          MDIO_PMA_DEVAD,
10439                                          MDIO_PMA_REG_8481_LED1_MASK,
10440                                          0x0);
10441                 }
10442                 break;
10443         case LED_MODE_FRONT_PANEL_OFF:
10444
10445                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10446                    port);
10447
10448                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10449                     SHARED_HW_CFG_LED_EXTPHY1) {
10450
10451                         /* Set LED masks */
10452                         bnx2x_cl45_write(bp, phy,
10453                                          MDIO_PMA_DEVAD,
10454                                          MDIO_PMA_REG_8481_LED1_MASK,
10455                                          0x0);
10456
10457                         bnx2x_cl45_write(bp, phy,
10458                                          MDIO_PMA_DEVAD,
10459                                          MDIO_PMA_REG_8481_LED2_MASK,
10460                                          0x0);
10461
10462                         bnx2x_cl45_write(bp, phy,
10463                                          MDIO_PMA_DEVAD,
10464                                          MDIO_PMA_REG_8481_LED3_MASK,
10465                                          0x0);
10466
10467                         bnx2x_cl45_write(bp, phy,
10468                                          MDIO_PMA_DEVAD,
10469                                          MDIO_PMA_REG_8481_LED5_MASK,
10470                                          0x20);
10471
10472                 } else {
10473                         bnx2x_cl45_write(bp, phy,
10474                                          MDIO_PMA_DEVAD,
10475                                          MDIO_PMA_REG_8481_LED1_MASK,
10476                                          0x0);
10477                         if (phy->type ==
10478                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10479                                 /* Disable MI_INT interrupt before setting LED4
10480                                  * source to constant off.
10481                                  */
10482                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10483                                            params->port*4) &
10484                                     NIG_MASK_MI_INT) {
10485                                         params->link_flags |=
10486                                         LINK_FLAGS_INT_DISABLED;
10487
10488                                         bnx2x_bits_dis(
10489                                                 bp,
10490                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10491                                                 params->port*4,
10492                                                 NIG_MASK_MI_INT);
10493                                 }
10494                                 bnx2x_cl45_write(bp, phy,
10495                                                  MDIO_PMA_DEVAD,
10496                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10497                                                  0x0);
10498                         }
10499                 }
10500                 break;
10501         case LED_MODE_ON:
10502
10503                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10504
10505                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10506                     SHARED_HW_CFG_LED_EXTPHY1) {
10507                         /* Set control reg */
10508                         bnx2x_cl45_read(bp, phy,
10509                                         MDIO_PMA_DEVAD,
10510                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10511                                         &val);
10512                         val &= 0x8000;
10513                         val |= 0x2492;
10514
10515                         bnx2x_cl45_write(bp, phy,
10516                                          MDIO_PMA_DEVAD,
10517                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10518                                          val);
10519
10520                         /* Set LED masks */
10521                         bnx2x_cl45_write(bp, phy,
10522                                          MDIO_PMA_DEVAD,
10523                                          MDIO_PMA_REG_8481_LED1_MASK,
10524                                          0x0);
10525
10526                         bnx2x_cl45_write(bp, phy,
10527                                          MDIO_PMA_DEVAD,
10528                                          MDIO_PMA_REG_8481_LED2_MASK,
10529                                          0x20);
10530
10531                         bnx2x_cl45_write(bp, phy,
10532                                          MDIO_PMA_DEVAD,
10533                                          MDIO_PMA_REG_8481_LED3_MASK,
10534                                          0x20);
10535
10536                         bnx2x_cl45_write(bp, phy,
10537                                          MDIO_PMA_DEVAD,
10538                                          MDIO_PMA_REG_8481_LED5_MASK,
10539                                          0x0);
10540                 } else {
10541                         bnx2x_cl45_write(bp, phy,
10542                                          MDIO_PMA_DEVAD,
10543                                          MDIO_PMA_REG_8481_LED1_MASK,
10544                                          0x20);
10545                         if (phy->type ==
10546                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10547                                 /* Disable MI_INT interrupt before setting LED4
10548                                  * source to constant on.
10549                                  */
10550                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10551                                            params->port*4) &
10552                                     NIG_MASK_MI_INT) {
10553                                         params->link_flags |=
10554                                         LINK_FLAGS_INT_DISABLED;
10555
10556                                         bnx2x_bits_dis(
10557                                                 bp,
10558                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10559                                                 params->port*4,
10560                                                 NIG_MASK_MI_INT);
10561                                 }
10562                                 bnx2x_cl45_write(bp, phy,
10563                                                  MDIO_PMA_DEVAD,
10564                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10565                                                  0x20);
10566                         }
10567                 }
10568                 break;
10569
10570         case LED_MODE_OPER:
10571
10572                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10573
10574                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10575                     SHARED_HW_CFG_LED_EXTPHY1) {
10576
10577                         /* Set control reg */
10578                         bnx2x_cl45_read(bp, phy,
10579                                         MDIO_PMA_DEVAD,
10580                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10581                                         &val);
10582
10583                         if (!((val &
10584                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10585                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10586                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10587                                 bnx2x_cl45_write(bp, phy,
10588                                                  MDIO_PMA_DEVAD,
10589                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10590                                                  0xa492);
10591                         }
10592
10593                         /* Set LED masks */
10594                         bnx2x_cl45_write(bp, phy,
10595                                          MDIO_PMA_DEVAD,
10596                                          MDIO_PMA_REG_8481_LED1_MASK,
10597                                          0x10);
10598
10599                         bnx2x_cl45_write(bp, phy,
10600                                          MDIO_PMA_DEVAD,
10601                                          MDIO_PMA_REG_8481_LED2_MASK,
10602                                          0x80);
10603
10604                         bnx2x_cl45_write(bp, phy,
10605                                          MDIO_PMA_DEVAD,
10606                                          MDIO_PMA_REG_8481_LED3_MASK,
10607                                          0x98);
10608
10609                         bnx2x_cl45_write(bp, phy,
10610                                          MDIO_PMA_DEVAD,
10611                                          MDIO_PMA_REG_8481_LED5_MASK,
10612                                          0x40);
10613
10614                 } else {
10615                         bnx2x_cl45_write(bp, phy,
10616                                          MDIO_PMA_DEVAD,
10617                                          MDIO_PMA_REG_8481_LED1_MASK,
10618                                          0x80);
10619
10620                         /* Tell LED3 to blink on source */
10621                         bnx2x_cl45_read(bp, phy,
10622                                         MDIO_PMA_DEVAD,
10623                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10624                                         &val);
10625                         val &= ~(7<<6);
10626                         val |= (1<<6); /* A83B[8:6]= 1 */
10627                         bnx2x_cl45_write(bp, phy,
10628                                          MDIO_PMA_DEVAD,
10629                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10630                                          val);
10631                         if (phy->type ==
10632                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10633                                 /* Restore LED4 source to external link,
10634                                  * and re-enable interrupts.
10635                                  */
10636                                 bnx2x_cl45_write(bp, phy,
10637                                                  MDIO_PMA_DEVAD,
10638                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10639                                                  0x40);
10640                                 if (params->link_flags &
10641                                     LINK_FLAGS_INT_DISABLED) {
10642                                         bnx2x_link_int_enable(params);
10643                                         params->link_flags &=
10644                                                 ~LINK_FLAGS_INT_DISABLED;
10645                                 }
10646                         }
10647                 }
10648                 break;
10649         }
10650
10651         /* This is a workaround for E3+84833 until autoneg
10652          * restart is fixed in f/w
10653          */
10654         if (CHIP_IS_E3(bp)) {
10655                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10656                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10657         }
10658 }
10659
10660 /******************************************************************/
10661 /*                      54618SE PHY SECTION                       */
10662 /******************************************************************/
10663 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10664                                         struct link_params *params,
10665                                         u32 action)
10666 {
10667         struct bnx2x *bp = params->bp;
10668         u16 temp;
10669         switch (action) {
10670         case PHY_INIT:
10671                 /* Configure LED4: set to INTR (0x6). */
10672                 /* Accessing shadow register 0xe. */
10673                 bnx2x_cl22_write(bp, phy,
10674                                  MDIO_REG_GPHY_SHADOW,
10675                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10676                 bnx2x_cl22_read(bp, phy,
10677                                 MDIO_REG_GPHY_SHADOW,
10678                                 &temp);
10679                 temp &= ~(0xf << 4);
10680                 temp |= (0x6 << 4);
10681                 bnx2x_cl22_write(bp, phy,
10682                                  MDIO_REG_GPHY_SHADOW,
10683                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10684                 /* Configure INTR based on link status change. */
10685                 bnx2x_cl22_write(bp, phy,
10686                                  MDIO_REG_INTR_MASK,
10687                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10688                 break;
10689         }
10690 }
10691
10692 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10693                                                struct link_params *params,
10694                                                struct link_vars *vars)
10695 {
10696         struct bnx2x *bp = params->bp;
10697         u8 port;
10698         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10699         u32 cfg_pin;
10700
10701         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10702         usleep_range(1000, 2000);
10703
10704         /* This works with E3 only, no need to check the chip
10705          * before determining the port.
10706          */
10707         port = params->port;
10708
10709         cfg_pin = (REG_RD(bp, params->shmem_base +
10710                         offsetof(struct shmem_region,
10711                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10712                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10713                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10714
10715         /* Drive pin high to bring the GPHY out of reset. */
10716         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10717
10718         /* wait for GPHY to reset */
10719         msleep(50);
10720
10721         /* reset phy */
10722         bnx2x_cl22_write(bp, phy,
10723                          MDIO_PMA_REG_CTRL, 0x8000);
10724         bnx2x_wait_reset_complete(bp, phy, params);
10725
10726         /* Wait for GPHY to reset */
10727         msleep(50);
10728
10729
10730         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10731         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10732         bnx2x_cl22_write(bp, phy,
10733                         MDIO_REG_GPHY_SHADOW,
10734                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10735         bnx2x_cl22_read(bp, phy,
10736                         MDIO_REG_GPHY_SHADOW,
10737                         &temp);
10738         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10739         bnx2x_cl22_write(bp, phy,
10740                         MDIO_REG_GPHY_SHADOW,
10741                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10742
10743         /* Set up fc */
10744         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10745         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10746         fc_val = 0;
10747         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10748                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10749                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10750
10751         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10752                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10753                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10754
10755         /* Read all advertisement */
10756         bnx2x_cl22_read(bp, phy,
10757                         0x09,
10758                         &an_1000_val);
10759
10760         bnx2x_cl22_read(bp, phy,
10761                         0x04,
10762                         &an_10_100_val);
10763
10764         bnx2x_cl22_read(bp, phy,
10765                         MDIO_PMA_REG_CTRL,
10766                         &autoneg_val);
10767
10768         /* Disable forced speed */
10769         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10770         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10771                            (1<<11));
10772
10773         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10774                         (phy->speed_cap_mask &
10775                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10776                         (phy->req_line_speed == SPEED_1000)) {
10777                 an_1000_val |= (1<<8);
10778                 autoneg_val |= (1<<9 | 1<<12);
10779                 if (phy->req_duplex == DUPLEX_FULL)
10780                         an_1000_val |= (1<<9);
10781                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10782         } else
10783                 an_1000_val &= ~((1<<8) | (1<<9));
10784
10785         bnx2x_cl22_write(bp, phy,
10786                         0x09,
10787                         an_1000_val);
10788         bnx2x_cl22_read(bp, phy,
10789                         0x09,
10790                         &an_1000_val);
10791
10792         /* Set 100 speed advertisement */
10793         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10794                         (phy->speed_cap_mask &
10795                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10796                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10797                 an_10_100_val |= (1<<7);
10798                 /* Enable autoneg and restart autoneg for legacy speeds */
10799                 autoneg_val |= (1<<9 | 1<<12);
10800
10801                 if (phy->req_duplex == DUPLEX_FULL)
10802                         an_10_100_val |= (1<<8);
10803                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10804         }
10805
10806         /* Set 10 speed advertisement */
10807         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10808                         (phy->speed_cap_mask &
10809                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10810                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10811                 an_10_100_val |= (1<<5);
10812                 autoneg_val |= (1<<9 | 1<<12);
10813                 if (phy->req_duplex == DUPLEX_FULL)
10814                         an_10_100_val |= (1<<6);
10815                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10816         }
10817
10818         /* Only 10/100 are allowed to work in FORCE mode */
10819         if (phy->req_line_speed == SPEED_100) {
10820                 autoneg_val |= (1<<13);
10821                 /* Enabled AUTO-MDIX when autoneg is disabled */
10822                 bnx2x_cl22_write(bp, phy,
10823                                 0x18,
10824                                 (1<<15 | 1<<9 | 7<<0));
10825                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10826         }
10827         if (phy->req_line_speed == SPEED_10) {
10828                 /* Enabled AUTO-MDIX when autoneg is disabled */
10829                 bnx2x_cl22_write(bp, phy,
10830                                 0x18,
10831                                 (1<<15 | 1<<9 | 7<<0));
10832                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10833         }
10834
10835         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10836                 int rc;
10837
10838                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10839                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10840                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10841                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10842                 temp &= 0xfffe;
10843                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10844
10845                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10846                 if (rc) {
10847                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10848                         bnx2x_eee_disable(phy, params, vars);
10849                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10850                            (phy->req_duplex == DUPLEX_FULL) &&
10851                            (bnx2x_eee_calc_timer(params) ||
10852                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10853                         /* Need to advertise EEE only when requested,
10854                          * and either no LPI assertion was requested,
10855                          * or it was requested and a valid timer was set.
10856                          * Also notice full duplex is required for EEE.
10857                          */
10858                         bnx2x_eee_advertise(phy, params, vars,
10859                                             SHMEM_EEE_1G_ADV);
10860                 } else {
10861                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10862                         bnx2x_eee_disable(phy, params, vars);
10863                 }
10864         } else {
10865                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10866                                     SHMEM_EEE_SUPPORTED_SHIFT;
10867
10868                 if (phy->flags & FLAGS_EEE) {
10869                         /* Handle legacy auto-grEEEn */
10870                         if (params->feature_config_flags &
10871                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10872                                 temp = 6;
10873                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10874                         } else {
10875                                 temp = 0;
10876                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10877                         }
10878                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10879                                          MDIO_AN_REG_EEE_ADV, temp);
10880                 }
10881         }
10882
10883         bnx2x_cl22_write(bp, phy,
10884                         0x04,
10885                         an_10_100_val | fc_val);
10886
10887         if (phy->req_duplex == DUPLEX_FULL)
10888                 autoneg_val |= (1<<8);
10889
10890         bnx2x_cl22_write(bp, phy,
10891                         MDIO_PMA_REG_CTRL, autoneg_val);
10892
10893         return 0;
10894 }
10895
10896
10897 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10898                                        struct link_params *params, u8 mode)
10899 {
10900         struct bnx2x *bp = params->bp;
10901         u16 temp;
10902
10903         bnx2x_cl22_write(bp, phy,
10904                 MDIO_REG_GPHY_SHADOW,
10905                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10906         bnx2x_cl22_read(bp, phy,
10907                 MDIO_REG_GPHY_SHADOW,
10908                 &temp);
10909         temp &= 0xff00;
10910
10911         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10912         switch (mode) {
10913         case LED_MODE_FRONT_PANEL_OFF:
10914         case LED_MODE_OFF:
10915                 temp |= 0x00ee;
10916                 break;
10917         case LED_MODE_OPER:
10918                 temp |= 0x0001;
10919                 break;
10920         case LED_MODE_ON:
10921                 temp |= 0x00ff;
10922                 break;
10923         default:
10924                 break;
10925         }
10926         bnx2x_cl22_write(bp, phy,
10927                 MDIO_REG_GPHY_SHADOW,
10928                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10929         return;
10930 }
10931
10932
10933 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10934                                      struct link_params *params)
10935 {
10936         struct bnx2x *bp = params->bp;
10937         u32 cfg_pin;
10938         u8 port;
10939
10940         /* In case of no EPIO routed to reset the GPHY, put it
10941          * in low power mode.
10942          */
10943         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10944         /* This works with E3 only, no need to check the chip
10945          * before determining the port.
10946          */
10947         port = params->port;
10948         cfg_pin = (REG_RD(bp, params->shmem_base +
10949                         offsetof(struct shmem_region,
10950                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10951                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10952                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10953
10954         /* Drive pin low to put GPHY in reset. */
10955         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10956 }
10957
10958 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10959                                     struct link_params *params,
10960                                     struct link_vars *vars)
10961 {
10962         struct bnx2x *bp = params->bp;
10963         u16 val;
10964         u8 link_up = 0;
10965         u16 legacy_status, legacy_speed;
10966
10967         /* Get speed operation status */
10968         bnx2x_cl22_read(bp, phy,
10969                         MDIO_REG_GPHY_AUX_STATUS,
10970                         &legacy_status);
10971         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10972
10973         /* Read status to clear the PHY interrupt. */
10974         bnx2x_cl22_read(bp, phy,
10975                         MDIO_REG_INTR_STATUS,
10976                         &val);
10977
10978         link_up = ((legacy_status & (1<<2)) == (1<<2));
10979
10980         if (link_up) {
10981                 legacy_speed = (legacy_status & (7<<8));
10982                 if (legacy_speed == (7<<8)) {
10983                         vars->line_speed = SPEED_1000;
10984                         vars->duplex = DUPLEX_FULL;
10985                 } else if (legacy_speed == (6<<8)) {
10986                         vars->line_speed = SPEED_1000;
10987                         vars->duplex = DUPLEX_HALF;
10988                 } else if (legacy_speed == (5<<8)) {
10989                         vars->line_speed = SPEED_100;
10990                         vars->duplex = DUPLEX_FULL;
10991                 }
10992                 /* Omitting 100Base-T4 for now */
10993                 else if (legacy_speed == (3<<8)) {
10994                         vars->line_speed = SPEED_100;
10995                         vars->duplex = DUPLEX_HALF;
10996                 } else if (legacy_speed == (2<<8)) {
10997                         vars->line_speed = SPEED_10;
10998                         vars->duplex = DUPLEX_FULL;
10999                 } else if (legacy_speed == (1<<8)) {
11000                         vars->line_speed = SPEED_10;
11001                         vars->duplex = DUPLEX_HALF;
11002                 } else /* Should not happen */
11003                         vars->line_speed = 0;
11004
11005                 DP(NETIF_MSG_LINK,
11006                    "Link is up in %dMbps, is_duplex_full= %d\n",
11007                    vars->line_speed,
11008                    (vars->duplex == DUPLEX_FULL));
11009
11010                 /* Check legacy speed AN resolution */
11011                 bnx2x_cl22_read(bp, phy,
11012                                 0x01,
11013                                 &val);
11014                 if (val & (1<<5))
11015                         vars->link_status |=
11016                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11017                 bnx2x_cl22_read(bp, phy,
11018                                 0x06,
11019                                 &val);
11020                 if ((val & (1<<0)) == 0)
11021                         vars->link_status |=
11022                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11023
11024                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11025                            vars->line_speed);
11026
11027                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11028
11029                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11030                         /* Report LP advertised speeds */
11031                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11032
11033                         if (val & (1<<5))
11034                                 vars->link_status |=
11035                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11036                         if (val & (1<<6))
11037                                 vars->link_status |=
11038                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11039                         if (val & (1<<7))
11040                                 vars->link_status |=
11041                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11042                         if (val & (1<<8))
11043                                 vars->link_status |=
11044                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11045                         if (val & (1<<9))
11046                                 vars->link_status |=
11047                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11048
11049                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11050                         if (val & (1<<10))
11051                                 vars->link_status |=
11052                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11053                         if (val & (1<<11))
11054                                 vars->link_status |=
11055                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11056
11057                         if ((phy->flags & FLAGS_EEE) &&
11058                             bnx2x_eee_has_cap(params))
11059                                 bnx2x_eee_an_resolve(phy, params, vars);
11060                 }
11061         }
11062         return link_up;
11063 }
11064
11065 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11066                                           struct link_params *params)
11067 {
11068         struct bnx2x *bp = params->bp;
11069         u16 val;
11070         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11071
11072         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11073
11074         /* Enable master/slave manual mmode and set to master */
11075         /* mii write 9 [bits set 11 12] */
11076         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11077
11078         /* forced 1G and disable autoneg */
11079         /* set val [mii read 0] */
11080         /* set val [expr $val & [bits clear 6 12 13]] */
11081         /* set val [expr $val | [bits set 6 8]] */
11082         /* mii write 0 $val */
11083         bnx2x_cl22_read(bp, phy, 0x00, &val);
11084         val &= ~((1<<6) | (1<<12) | (1<<13));
11085         val |= (1<<6) | (1<<8);
11086         bnx2x_cl22_write(bp, phy, 0x00, val);
11087
11088         /* Set external loopback and Tx using 6dB coding */
11089         /* mii write 0x18 7 */
11090         /* set val [mii read 0x18] */
11091         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11092         bnx2x_cl22_write(bp, phy, 0x18, 7);
11093         bnx2x_cl22_read(bp, phy, 0x18, &val);
11094         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11095
11096         /* This register opens the gate for the UMAC despite its name */
11097         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11098
11099         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11100          * length used by the MAC receive logic to check frames.
11101          */
11102         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11103 }
11104
11105 /******************************************************************/
11106 /*                      SFX7101 PHY SECTION                       */
11107 /******************************************************************/
11108 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11109                                        struct link_params *params)
11110 {
11111         struct bnx2x *bp = params->bp;
11112         /* SFX7101_XGXS_TEST1 */
11113         bnx2x_cl45_write(bp, phy,
11114                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11115 }
11116
11117 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11118                                   struct link_params *params,
11119                                   struct link_vars *vars)
11120 {
11121         u16 fw_ver1, fw_ver2, val;
11122         struct bnx2x *bp = params->bp;
11123         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11124
11125         /* Restore normal power mode*/
11126         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11127                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11128         /* HW reset */
11129         bnx2x_ext_phy_hw_reset(bp, params->port);
11130         bnx2x_wait_reset_complete(bp, phy, params);
11131
11132         bnx2x_cl45_write(bp, phy,
11133                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11134         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11135         bnx2x_cl45_write(bp, phy,
11136                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11137
11138         bnx2x_ext_phy_set_pause(params, phy, vars);
11139         /* Restart autoneg */
11140         bnx2x_cl45_read(bp, phy,
11141                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11142         val |= 0x200;
11143         bnx2x_cl45_write(bp, phy,
11144                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11145
11146         /* Save spirom version */
11147         bnx2x_cl45_read(bp, phy,
11148                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11149
11150         bnx2x_cl45_read(bp, phy,
11151                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11152         bnx2x_save_spirom_version(bp, params->port,
11153                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11154         return 0;
11155 }
11156
11157 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11158                                  struct link_params *params,
11159                                  struct link_vars *vars)
11160 {
11161         struct bnx2x *bp = params->bp;
11162         u8 link_up;
11163         u16 val1, val2;
11164         bnx2x_cl45_read(bp, phy,
11165                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11166         bnx2x_cl45_read(bp, phy,
11167                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11168         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11169                    val2, val1);
11170         bnx2x_cl45_read(bp, phy,
11171                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11172         bnx2x_cl45_read(bp, phy,
11173                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11174         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11175                    val2, val1);
11176         link_up = ((val1 & 4) == 4);
11177         /* If link is up print the AN outcome of the SFX7101 PHY */
11178         if (link_up) {
11179                 bnx2x_cl45_read(bp, phy,
11180                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11181                                 &val2);
11182                 vars->line_speed = SPEED_10000;
11183                 vars->duplex = DUPLEX_FULL;
11184                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11185                            val2, (val2 & (1<<14)));
11186                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11187                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11188
11189                 /* Read LP advertised speeds */
11190                 if (val2 & (1<<11))
11191                         vars->link_status |=
11192                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11193         }
11194         return link_up;
11195 }
11196
11197 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11198 {
11199         if (*len < 5)
11200                 return -EINVAL;
11201         str[0] = (spirom_ver & 0xFF);
11202         str[1] = (spirom_ver & 0xFF00) >> 8;
11203         str[2] = (spirom_ver & 0xFF0000) >> 16;
11204         str[3] = (spirom_ver & 0xFF000000) >> 24;
11205         str[4] = '\0';
11206         *len -= 5;
11207         return 0;
11208 }
11209
11210 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11211 {
11212         u16 val, cnt;
11213
11214         bnx2x_cl45_read(bp, phy,
11215                         MDIO_PMA_DEVAD,
11216                         MDIO_PMA_REG_7101_RESET, &val);
11217
11218         for (cnt = 0; cnt < 10; cnt++) {
11219                 msleep(50);
11220                 /* Writes a self-clearing reset */
11221                 bnx2x_cl45_write(bp, phy,
11222                                  MDIO_PMA_DEVAD,
11223                                  MDIO_PMA_REG_7101_RESET,
11224                                  (val | (1<<15)));
11225                 /* Wait for clear */
11226                 bnx2x_cl45_read(bp, phy,
11227                                 MDIO_PMA_DEVAD,
11228                                 MDIO_PMA_REG_7101_RESET, &val);
11229
11230                 if ((val & (1<<15)) == 0)
11231                         break;
11232         }
11233 }
11234
11235 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11236                                 struct link_params *params) {
11237         /* Low power mode is controlled by GPIO 2 */
11238         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11239                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11240         /* The PHY reset is controlled by GPIO 1 */
11241         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11242                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11243 }
11244
11245 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11246                                     struct link_params *params, u8 mode)
11247 {
11248         u16 val = 0;
11249         struct bnx2x *bp = params->bp;
11250         switch (mode) {
11251         case LED_MODE_FRONT_PANEL_OFF:
11252         case LED_MODE_OFF:
11253                 val = 2;
11254                 break;
11255         case LED_MODE_ON:
11256                 val = 1;
11257                 break;
11258         case LED_MODE_OPER:
11259                 val = 0;
11260                 break;
11261         }
11262         bnx2x_cl45_write(bp, phy,
11263                          MDIO_PMA_DEVAD,
11264                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11265                          val);
11266 }
11267
11268 /******************************************************************/
11269 /*                      STATIC PHY DECLARATION                    */
11270 /******************************************************************/
11271
11272 static const struct bnx2x_phy phy_null = {
11273         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11274         .addr           = 0,
11275         .def_md_devad   = 0,
11276         .flags          = FLAGS_INIT_XGXS_FIRST,
11277         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11278         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11279         .mdio_ctrl      = 0,
11280         .supported      = 0,
11281         .media_type     = ETH_PHY_NOT_PRESENT,
11282         .ver_addr       = 0,
11283         .req_flow_ctrl  = 0,
11284         .req_line_speed = 0,
11285         .speed_cap_mask = 0,
11286         .req_duplex     = 0,
11287         .rsrv           = 0,
11288         .config_init    = (config_init_t)NULL,
11289         .read_status    = (read_status_t)NULL,
11290         .link_reset     = (link_reset_t)NULL,
11291         .config_loopback = (config_loopback_t)NULL,
11292         .format_fw_ver  = (format_fw_ver_t)NULL,
11293         .hw_reset       = (hw_reset_t)NULL,
11294         .set_link_led   = (set_link_led_t)NULL,
11295         .phy_specific_func = (phy_specific_func_t)NULL
11296 };
11297
11298 static const struct bnx2x_phy phy_serdes = {
11299         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11300         .addr           = 0xff,
11301         .def_md_devad   = 0,
11302         .flags          = 0,
11303         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11304         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11305         .mdio_ctrl      = 0,
11306         .supported      = (SUPPORTED_10baseT_Half |
11307                            SUPPORTED_10baseT_Full |
11308                            SUPPORTED_100baseT_Half |
11309                            SUPPORTED_100baseT_Full |
11310                            SUPPORTED_1000baseT_Full |
11311                            SUPPORTED_2500baseX_Full |
11312                            SUPPORTED_TP |
11313                            SUPPORTED_Autoneg |
11314                            SUPPORTED_Pause |
11315                            SUPPORTED_Asym_Pause),
11316         .media_type     = ETH_PHY_BASE_T,
11317         .ver_addr       = 0,
11318         .req_flow_ctrl  = 0,
11319         .req_line_speed = 0,
11320         .speed_cap_mask = 0,
11321         .req_duplex     = 0,
11322         .rsrv           = 0,
11323         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11324         .read_status    = (read_status_t)bnx2x_link_settings_status,
11325         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11326         .config_loopback = (config_loopback_t)NULL,
11327         .format_fw_ver  = (format_fw_ver_t)NULL,
11328         .hw_reset       = (hw_reset_t)NULL,
11329         .set_link_led   = (set_link_led_t)NULL,
11330         .phy_specific_func = (phy_specific_func_t)NULL
11331 };
11332
11333 static const struct bnx2x_phy phy_xgxs = {
11334         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11335         .addr           = 0xff,
11336         .def_md_devad   = 0,
11337         .flags          = 0,
11338         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11339         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11340         .mdio_ctrl      = 0,
11341         .supported      = (SUPPORTED_10baseT_Half |
11342                            SUPPORTED_10baseT_Full |
11343                            SUPPORTED_100baseT_Half |
11344                            SUPPORTED_100baseT_Full |
11345                            SUPPORTED_1000baseT_Full |
11346                            SUPPORTED_2500baseX_Full |
11347                            SUPPORTED_10000baseT_Full |
11348                            SUPPORTED_FIBRE |
11349                            SUPPORTED_Autoneg |
11350                            SUPPORTED_Pause |
11351                            SUPPORTED_Asym_Pause),
11352         .media_type     = ETH_PHY_CX4,
11353         .ver_addr       = 0,
11354         .req_flow_ctrl  = 0,
11355         .req_line_speed = 0,
11356         .speed_cap_mask = 0,
11357         .req_duplex     = 0,
11358         .rsrv           = 0,
11359         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11360         .read_status    = (read_status_t)bnx2x_link_settings_status,
11361         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11362         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11363         .format_fw_ver  = (format_fw_ver_t)NULL,
11364         .hw_reset       = (hw_reset_t)NULL,
11365         .set_link_led   = (set_link_led_t)NULL,
11366         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11367 };
11368 static const struct bnx2x_phy phy_warpcore = {
11369         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11370         .addr           = 0xff,
11371         .def_md_devad   = 0,
11372         .flags          = FLAGS_TX_ERROR_CHECK,
11373         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11374         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11375         .mdio_ctrl      = 0,
11376         .supported      = (SUPPORTED_10baseT_Half |
11377                            SUPPORTED_10baseT_Full |
11378                            SUPPORTED_100baseT_Half |
11379                            SUPPORTED_100baseT_Full |
11380                            SUPPORTED_1000baseT_Full |
11381                            SUPPORTED_10000baseT_Full |
11382                            SUPPORTED_20000baseKR2_Full |
11383                            SUPPORTED_20000baseMLD2_Full |
11384                            SUPPORTED_FIBRE |
11385                            SUPPORTED_Autoneg |
11386                            SUPPORTED_Pause |
11387                            SUPPORTED_Asym_Pause),
11388         .media_type     = ETH_PHY_UNSPECIFIED,
11389         .ver_addr       = 0,
11390         .req_flow_ctrl  = 0,
11391         .req_line_speed = 0,
11392         .speed_cap_mask = 0,
11393         /* req_duplex = */0,
11394         /* rsrv = */0,
11395         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11396         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11397         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11398         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11399         .format_fw_ver  = (format_fw_ver_t)NULL,
11400         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11401         .set_link_led   = (set_link_led_t)NULL,
11402         .phy_specific_func = (phy_specific_func_t)NULL
11403 };
11404
11405
11406 static const struct bnx2x_phy phy_7101 = {
11407         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11408         .addr           = 0xff,
11409         .def_md_devad   = 0,
11410         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11411         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11412         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11413         .mdio_ctrl      = 0,
11414         .supported      = (SUPPORTED_10000baseT_Full |
11415                            SUPPORTED_TP |
11416                            SUPPORTED_Autoneg |
11417                            SUPPORTED_Pause |
11418                            SUPPORTED_Asym_Pause),
11419         .media_type     = ETH_PHY_BASE_T,
11420         .ver_addr       = 0,
11421         .req_flow_ctrl  = 0,
11422         .req_line_speed = 0,
11423         .speed_cap_mask = 0,
11424         .req_duplex     = 0,
11425         .rsrv           = 0,
11426         .config_init    = (config_init_t)bnx2x_7101_config_init,
11427         .read_status    = (read_status_t)bnx2x_7101_read_status,
11428         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11429         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11430         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11431         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11432         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11433         .phy_specific_func = (phy_specific_func_t)NULL
11434 };
11435 static const struct bnx2x_phy phy_8073 = {
11436         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11437         .addr           = 0xff,
11438         .def_md_devad   = 0,
11439         .flags          = 0,
11440         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11441         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11442         .mdio_ctrl      = 0,
11443         .supported      = (SUPPORTED_10000baseT_Full |
11444                            SUPPORTED_2500baseX_Full |
11445                            SUPPORTED_1000baseT_Full |
11446                            SUPPORTED_FIBRE |
11447                            SUPPORTED_Autoneg |
11448                            SUPPORTED_Pause |
11449                            SUPPORTED_Asym_Pause),
11450         .media_type     = ETH_PHY_KR,
11451         .ver_addr       = 0,
11452         .req_flow_ctrl  = 0,
11453         .req_line_speed = 0,
11454         .speed_cap_mask = 0,
11455         .req_duplex     = 0,
11456         .rsrv           = 0,
11457         .config_init    = (config_init_t)bnx2x_8073_config_init,
11458         .read_status    = (read_status_t)bnx2x_8073_read_status,
11459         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11460         .config_loopback = (config_loopback_t)NULL,
11461         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11462         .hw_reset       = (hw_reset_t)NULL,
11463         .set_link_led   = (set_link_led_t)NULL,
11464         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11465 };
11466 static const struct bnx2x_phy phy_8705 = {
11467         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11468         .addr           = 0xff,
11469         .def_md_devad   = 0,
11470         .flags          = FLAGS_INIT_XGXS_FIRST,
11471         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11472         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11473         .mdio_ctrl      = 0,
11474         .supported      = (SUPPORTED_10000baseT_Full |
11475                            SUPPORTED_FIBRE |
11476                            SUPPORTED_Pause |
11477                            SUPPORTED_Asym_Pause),
11478         .media_type     = ETH_PHY_XFP_FIBER,
11479         .ver_addr       = 0,
11480         .req_flow_ctrl  = 0,
11481         .req_line_speed = 0,
11482         .speed_cap_mask = 0,
11483         .req_duplex     = 0,
11484         .rsrv           = 0,
11485         .config_init    = (config_init_t)bnx2x_8705_config_init,
11486         .read_status    = (read_status_t)bnx2x_8705_read_status,
11487         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11488         .config_loopback = (config_loopback_t)NULL,
11489         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11490         .hw_reset       = (hw_reset_t)NULL,
11491         .set_link_led   = (set_link_led_t)NULL,
11492         .phy_specific_func = (phy_specific_func_t)NULL
11493 };
11494 static const struct bnx2x_phy phy_8706 = {
11495         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11496         .addr           = 0xff,
11497         .def_md_devad   = 0,
11498         .flags          = FLAGS_INIT_XGXS_FIRST,
11499         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11500         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11501         .mdio_ctrl      = 0,
11502         .supported      = (SUPPORTED_10000baseT_Full |
11503                            SUPPORTED_1000baseT_Full |
11504                            SUPPORTED_FIBRE |
11505                            SUPPORTED_Pause |
11506                            SUPPORTED_Asym_Pause),
11507         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11508         .ver_addr       = 0,
11509         .req_flow_ctrl  = 0,
11510         .req_line_speed = 0,
11511         .speed_cap_mask = 0,
11512         .req_duplex     = 0,
11513         .rsrv           = 0,
11514         .config_init    = (config_init_t)bnx2x_8706_config_init,
11515         .read_status    = (read_status_t)bnx2x_8706_read_status,
11516         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11517         .config_loopback = (config_loopback_t)NULL,
11518         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11519         .hw_reset       = (hw_reset_t)NULL,
11520         .set_link_led   = (set_link_led_t)NULL,
11521         .phy_specific_func = (phy_specific_func_t)NULL
11522 };
11523
11524 static const struct bnx2x_phy phy_8726 = {
11525         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11526         .addr           = 0xff,
11527         .def_md_devad   = 0,
11528         .flags          = (FLAGS_INIT_XGXS_FIRST |
11529                            FLAGS_TX_ERROR_CHECK),
11530         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11531         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11532         .mdio_ctrl      = 0,
11533         .supported      = (SUPPORTED_10000baseT_Full |
11534                            SUPPORTED_1000baseT_Full |
11535                            SUPPORTED_Autoneg |
11536                            SUPPORTED_FIBRE |
11537                            SUPPORTED_Pause |
11538                            SUPPORTED_Asym_Pause),
11539         .media_type     = ETH_PHY_NOT_PRESENT,
11540         .ver_addr       = 0,
11541         .req_flow_ctrl  = 0,
11542         .req_line_speed = 0,
11543         .speed_cap_mask = 0,
11544         .req_duplex     = 0,
11545         .rsrv           = 0,
11546         .config_init    = (config_init_t)bnx2x_8726_config_init,
11547         .read_status    = (read_status_t)bnx2x_8726_read_status,
11548         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11549         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11550         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11551         .hw_reset       = (hw_reset_t)NULL,
11552         .set_link_led   = (set_link_led_t)NULL,
11553         .phy_specific_func = (phy_specific_func_t)NULL
11554 };
11555
11556 static const struct bnx2x_phy phy_8727 = {
11557         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11558         .addr           = 0xff,
11559         .def_md_devad   = 0,
11560         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11561                            FLAGS_TX_ERROR_CHECK),
11562         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11563         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11564         .mdio_ctrl      = 0,
11565         .supported      = (SUPPORTED_10000baseT_Full |
11566                            SUPPORTED_1000baseT_Full |
11567                            SUPPORTED_FIBRE |
11568                            SUPPORTED_Pause |
11569                            SUPPORTED_Asym_Pause),
11570         .media_type     = ETH_PHY_NOT_PRESENT,
11571         .ver_addr       = 0,
11572         .req_flow_ctrl  = 0,
11573         .req_line_speed = 0,
11574         .speed_cap_mask = 0,
11575         .req_duplex     = 0,
11576         .rsrv           = 0,
11577         .config_init    = (config_init_t)bnx2x_8727_config_init,
11578         .read_status    = (read_status_t)bnx2x_8727_read_status,
11579         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11580         .config_loopback = (config_loopback_t)NULL,
11581         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11582         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11583         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11584         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11585 };
11586 static const struct bnx2x_phy phy_8481 = {
11587         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11588         .addr           = 0xff,
11589         .def_md_devad   = 0,
11590         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11591                           FLAGS_REARM_LATCH_SIGNAL,
11592         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11593         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11594         .mdio_ctrl      = 0,
11595         .supported      = (SUPPORTED_10baseT_Half |
11596                            SUPPORTED_10baseT_Full |
11597                            SUPPORTED_100baseT_Half |
11598                            SUPPORTED_100baseT_Full |
11599                            SUPPORTED_1000baseT_Full |
11600                            SUPPORTED_10000baseT_Full |
11601                            SUPPORTED_TP |
11602                            SUPPORTED_Autoneg |
11603                            SUPPORTED_Pause |
11604                            SUPPORTED_Asym_Pause),
11605         .media_type     = ETH_PHY_BASE_T,
11606         .ver_addr       = 0,
11607         .req_flow_ctrl  = 0,
11608         .req_line_speed = 0,
11609         .speed_cap_mask = 0,
11610         .req_duplex     = 0,
11611         .rsrv           = 0,
11612         .config_init    = (config_init_t)bnx2x_8481_config_init,
11613         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11614         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11615         .config_loopback = (config_loopback_t)NULL,
11616         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11617         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11618         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11619         .phy_specific_func = (phy_specific_func_t)NULL
11620 };
11621
11622 static const struct bnx2x_phy phy_84823 = {
11623         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11624         .addr           = 0xff,
11625         .def_md_devad   = 0,
11626         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11627                            FLAGS_REARM_LATCH_SIGNAL |
11628                            FLAGS_TX_ERROR_CHECK),
11629         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11630         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11631         .mdio_ctrl      = 0,
11632         .supported      = (SUPPORTED_10baseT_Half |
11633                            SUPPORTED_10baseT_Full |
11634                            SUPPORTED_100baseT_Half |
11635                            SUPPORTED_100baseT_Full |
11636                            SUPPORTED_1000baseT_Full |
11637                            SUPPORTED_10000baseT_Full |
11638                            SUPPORTED_TP |
11639                            SUPPORTED_Autoneg |
11640                            SUPPORTED_Pause |
11641                            SUPPORTED_Asym_Pause),
11642         .media_type     = ETH_PHY_BASE_T,
11643         .ver_addr       = 0,
11644         .req_flow_ctrl  = 0,
11645         .req_line_speed = 0,
11646         .speed_cap_mask = 0,
11647         .req_duplex     = 0,
11648         .rsrv           = 0,
11649         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11650         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11651         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11652         .config_loopback = (config_loopback_t)NULL,
11653         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11654         .hw_reset       = (hw_reset_t)NULL,
11655         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11656         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11657 };
11658
11659 static const struct bnx2x_phy phy_84833 = {
11660         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11661         .addr           = 0xff,
11662         .def_md_devad   = 0,
11663         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11664                            FLAGS_REARM_LATCH_SIGNAL |
11665                            FLAGS_TX_ERROR_CHECK),
11666         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11667         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11668         .mdio_ctrl      = 0,
11669         .supported      = (SUPPORTED_100baseT_Half |
11670                            SUPPORTED_100baseT_Full |
11671                            SUPPORTED_1000baseT_Full |
11672                            SUPPORTED_10000baseT_Full |
11673                            SUPPORTED_TP |
11674                            SUPPORTED_Autoneg |
11675                            SUPPORTED_Pause |
11676                            SUPPORTED_Asym_Pause),
11677         .media_type     = ETH_PHY_BASE_T,
11678         .ver_addr       = 0,
11679         .req_flow_ctrl  = 0,
11680         .req_line_speed = 0,
11681         .speed_cap_mask = 0,
11682         .req_duplex     = 0,
11683         .rsrv           = 0,
11684         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11685         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11686         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11687         .config_loopback = (config_loopback_t)NULL,
11688         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11689         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11690         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11691         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11692 };
11693
11694 static const struct bnx2x_phy phy_84834 = {
11695         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11696         .addr           = 0xff,
11697         .def_md_devad   = 0,
11698         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11699                             FLAGS_REARM_LATCH_SIGNAL,
11700         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11701         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11702         .mdio_ctrl      = 0,
11703         .supported      = (SUPPORTED_100baseT_Half |
11704                            SUPPORTED_100baseT_Full |
11705                            SUPPORTED_1000baseT_Full |
11706                            SUPPORTED_10000baseT_Full |
11707                            SUPPORTED_TP |
11708                            SUPPORTED_Autoneg |
11709                            SUPPORTED_Pause |
11710                            SUPPORTED_Asym_Pause),
11711         .media_type     = ETH_PHY_BASE_T,
11712         .ver_addr       = 0,
11713         .req_flow_ctrl  = 0,
11714         .req_line_speed = 0,
11715         .speed_cap_mask = 0,
11716         .req_duplex     = 0,
11717         .rsrv           = 0,
11718         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11719         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11720         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11721         .config_loopback = (config_loopback_t)NULL,
11722         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11723         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11724         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11725         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11726 };
11727
11728 static const struct bnx2x_phy phy_54618se = {
11729         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11730         .addr           = 0xff,
11731         .def_md_devad   = 0,
11732         .flags          = FLAGS_INIT_XGXS_FIRST,
11733         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11734         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11735         .mdio_ctrl      = 0,
11736         .supported      = (SUPPORTED_10baseT_Half |
11737                            SUPPORTED_10baseT_Full |
11738                            SUPPORTED_100baseT_Half |
11739                            SUPPORTED_100baseT_Full |
11740                            SUPPORTED_1000baseT_Full |
11741                            SUPPORTED_TP |
11742                            SUPPORTED_Autoneg |
11743                            SUPPORTED_Pause |
11744                            SUPPORTED_Asym_Pause),
11745         .media_type     = ETH_PHY_BASE_T,
11746         .ver_addr       = 0,
11747         .req_flow_ctrl  = 0,
11748         .req_line_speed = 0,
11749         .speed_cap_mask = 0,
11750         /* req_duplex = */0,
11751         /* rsrv = */0,
11752         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11753         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11754         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11755         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11756         .format_fw_ver  = (format_fw_ver_t)NULL,
11757         .hw_reset       = (hw_reset_t)NULL,
11758         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11759         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11760 };
11761 /*****************************************************************/
11762 /*                                                               */
11763 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11764 /*                                                               */
11765 /*****************************************************************/
11766
11767 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11768                                      struct bnx2x_phy *phy, u8 port,
11769                                      u8 phy_index)
11770 {
11771         /* Get the 4 lanes xgxs config rx and tx */
11772         u32 rx = 0, tx = 0, i;
11773         for (i = 0; i < 2; i++) {
11774                 /* INT_PHY and EXT_PHY1 share the same value location in
11775                  * the shmem. When num_phys is greater than 1, than this value
11776                  * applies only to EXT_PHY1
11777                  */
11778                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11779                         rx = REG_RD(bp, shmem_base +
11780                                     offsetof(struct shmem_region,
11781                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11782
11783                         tx = REG_RD(bp, shmem_base +
11784                                     offsetof(struct shmem_region,
11785                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11786                 } else {
11787                         rx = REG_RD(bp, shmem_base +
11788                                     offsetof(struct shmem_region,
11789                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11790
11791                         tx = REG_RD(bp, shmem_base +
11792                                     offsetof(struct shmem_region,
11793                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11794                 }
11795
11796                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11797                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11798
11799                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11800                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11801         }
11802 }
11803
11804 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11805                                     u8 phy_index, u8 port)
11806 {
11807         u32 ext_phy_config = 0;
11808         switch (phy_index) {
11809         case EXT_PHY1:
11810                 ext_phy_config = REG_RD(bp, shmem_base +
11811                                               offsetof(struct shmem_region,
11812                         dev_info.port_hw_config[port].external_phy_config));
11813                 break;
11814         case EXT_PHY2:
11815                 ext_phy_config = REG_RD(bp, shmem_base +
11816                                               offsetof(struct shmem_region,
11817                         dev_info.port_hw_config[port].external_phy_config2));
11818                 break;
11819         default:
11820                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11821                 return -EINVAL;
11822         }
11823
11824         return ext_phy_config;
11825 }
11826 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11827                                   struct bnx2x_phy *phy)
11828 {
11829         u32 phy_addr;
11830         u32 chip_id;
11831         u32 switch_cfg = (REG_RD(bp, shmem_base +
11832                                        offsetof(struct shmem_region,
11833                         dev_info.port_feature_config[port].link_config)) &
11834                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11835         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11836                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11837
11838         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11839         if (USES_WARPCORE(bp)) {
11840                 u32 serdes_net_if;
11841                 phy_addr = REG_RD(bp,
11842                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11843                 *phy = phy_warpcore;
11844                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11845                         phy->flags |= FLAGS_4_PORT_MODE;
11846                 else
11847                         phy->flags &= ~FLAGS_4_PORT_MODE;
11848                         /* Check Dual mode */
11849                 serdes_net_if = (REG_RD(bp, shmem_base +
11850                                         offsetof(struct shmem_region, dev_info.
11851                                         port_hw_config[port].default_cfg)) &
11852                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11853                 /* Set the appropriate supported and flags indications per
11854                  * interface type of the chip
11855                  */
11856                 switch (serdes_net_if) {
11857                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11858                         phy->supported &= (SUPPORTED_10baseT_Half |
11859                                            SUPPORTED_10baseT_Full |
11860                                            SUPPORTED_100baseT_Half |
11861                                            SUPPORTED_100baseT_Full |
11862                                            SUPPORTED_1000baseT_Full |
11863                                            SUPPORTED_FIBRE |
11864                                            SUPPORTED_Autoneg |
11865                                            SUPPORTED_Pause |
11866                                            SUPPORTED_Asym_Pause);
11867                         phy->media_type = ETH_PHY_BASE_T;
11868                         break;
11869                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11870                         phy->supported &= (SUPPORTED_1000baseT_Full |
11871                                            SUPPORTED_10000baseT_Full |
11872                                            SUPPORTED_FIBRE |
11873                                            SUPPORTED_Pause |
11874                                            SUPPORTED_Asym_Pause);
11875                         phy->media_type = ETH_PHY_XFP_FIBER;
11876                         break;
11877                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11878                         phy->supported &= (SUPPORTED_1000baseT_Full |
11879                                            SUPPORTED_10000baseT_Full |
11880                                            SUPPORTED_FIBRE |
11881                                            SUPPORTED_Pause |
11882                                            SUPPORTED_Asym_Pause);
11883                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11884                         break;
11885                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11886                         phy->media_type = ETH_PHY_KR;
11887                         phy->supported &= (SUPPORTED_1000baseT_Full |
11888                                            SUPPORTED_10000baseT_Full |
11889                                            SUPPORTED_FIBRE |
11890                                            SUPPORTED_Autoneg |
11891                                            SUPPORTED_Pause |
11892                                            SUPPORTED_Asym_Pause);
11893                         break;
11894                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11895                         phy->media_type = ETH_PHY_KR;
11896                         phy->flags |= FLAGS_WC_DUAL_MODE;
11897                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11898                                            SUPPORTED_FIBRE |
11899                                            SUPPORTED_Pause |
11900                                            SUPPORTED_Asym_Pause);
11901                         break;
11902                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11903                         phy->media_type = ETH_PHY_KR;
11904                         phy->flags |= FLAGS_WC_DUAL_MODE;
11905                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11906                                            SUPPORTED_10000baseT_Full |
11907                                            SUPPORTED_1000baseT_Full |
11908                                            SUPPORTED_Autoneg |
11909                                            SUPPORTED_FIBRE |
11910                                            SUPPORTED_Pause |
11911                                            SUPPORTED_Asym_Pause);
11912                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11913                         break;
11914                 default:
11915                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11916                                        serdes_net_if);
11917                         break;
11918                 }
11919
11920                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11921                  * was not set as expected. For B0, ECO will be enabled so there
11922                  * won't be an issue there
11923                  */
11924                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11925                         phy->flags |= FLAGS_MDC_MDIO_WA;
11926                 else
11927                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11928         } else {
11929                 switch (switch_cfg) {
11930                 case SWITCH_CFG_1G:
11931                         phy_addr = REG_RD(bp,
11932                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11933                                           port * 0x10);
11934                         *phy = phy_serdes;
11935                         break;
11936                 case SWITCH_CFG_10G:
11937                         phy_addr = REG_RD(bp,
11938                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11939                                           port * 0x18);
11940                         *phy = phy_xgxs;
11941                         break;
11942                 default:
11943                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11944                         return -EINVAL;
11945                 }
11946         }
11947         phy->addr = (u8)phy_addr;
11948         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11949                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11950                                             port);
11951         if (CHIP_IS_E2(bp))
11952                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11953         else
11954                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11955
11956         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11957                    port, phy->addr, phy->mdio_ctrl);
11958
11959         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11960         return 0;
11961 }
11962
11963 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11964                                   u8 phy_index,
11965                                   u32 shmem_base,
11966                                   u32 shmem2_base,
11967                                   u8 port,
11968                                   struct bnx2x_phy *phy)
11969 {
11970         u32 ext_phy_config, phy_type, config2;
11971         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11972         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11973                                                   phy_index, port);
11974         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11975         /* Select the phy type */
11976         switch (phy_type) {
11977         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11978                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11979                 *phy = phy_8073;
11980                 break;
11981         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11982                 *phy = phy_8705;
11983                 break;
11984         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11985                 *phy = phy_8706;
11986                 break;
11987         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11988                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11989                 *phy = phy_8726;
11990                 break;
11991         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11992                 /* BCM8727_NOC => BCM8727 no over current */
11993                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11994                 *phy = phy_8727;
11995                 phy->flags |= FLAGS_NOC;
11996                 break;
11997         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11998         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11999                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12000                 *phy = phy_8727;
12001                 break;
12002         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12003                 *phy = phy_8481;
12004                 break;
12005         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12006                 *phy = phy_84823;
12007                 break;
12008         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12009                 *phy = phy_84833;
12010                 break;
12011         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12012                 *phy = phy_84834;
12013                 break;
12014         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12015         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12016                 *phy = phy_54618se;
12017                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12018                         phy->flags |= FLAGS_EEE;
12019                 break;
12020         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12021                 *phy = phy_7101;
12022                 break;
12023         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12024                 *phy = phy_null;
12025                 return -EINVAL;
12026         default:
12027                 *phy = phy_null;
12028                 /* In case external PHY wasn't found */
12029                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12030                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12031                         return -EINVAL;
12032                 return 0;
12033         }
12034
12035         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12036         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12037
12038         /* The shmem address of the phy version is located on different
12039          * structures. In case this structure is too old, do not set
12040          * the address
12041          */
12042         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12043                                         dev_info.shared_hw_config.config2));
12044         if (phy_index == EXT_PHY1) {
12045                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12046                                 port_mb[port].ext_phy_fw_version);
12047
12048                 /* Check specific mdc mdio settings */
12049                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12050                         mdc_mdio_access = config2 &
12051                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12052         } else {
12053                 u32 size = REG_RD(bp, shmem2_base);
12054
12055                 if (size >
12056                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12057                         phy->ver_addr = shmem2_base +
12058                             offsetof(struct shmem2_region,
12059                                      ext_phy_fw_version2[port]);
12060                 }
12061                 /* Check specific mdc mdio settings */
12062                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12063                         mdc_mdio_access = (config2 &
12064                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12065                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12066                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12067         }
12068         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12069
12070         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12071              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12072             (phy->ver_addr)) {
12073                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12074                  * version lower than or equal to 1.39
12075                  */
12076                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12077                 if (((raw_ver & 0x7F) <= 39) &&
12078                     (((raw_ver & 0xF80) >> 7) <= 1))
12079                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12080                                             SUPPORTED_100baseT_Full);
12081         }
12082
12083         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12084                    phy_type, port, phy_index);
12085         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12086                    phy->addr, phy->mdio_ctrl);
12087         return 0;
12088 }
12089
12090 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12091                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12092 {
12093         int status = 0;
12094         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12095         if (phy_index == INT_PHY)
12096                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12097         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12098                                         port, phy);
12099         return status;
12100 }
12101
12102 static void bnx2x_phy_def_cfg(struct link_params *params,
12103                               struct bnx2x_phy *phy,
12104                               u8 phy_index)
12105 {
12106         struct bnx2x *bp = params->bp;
12107         u32 link_config;
12108         /* Populate the default phy configuration for MF mode */
12109         if (phy_index == EXT_PHY2) {
12110                 link_config = REG_RD(bp, params->shmem_base +
12111                                      offsetof(struct shmem_region, dev_info.
12112                         port_feature_config[params->port].link_config2));
12113                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12114                                              offsetof(struct shmem_region,
12115                                                       dev_info.
12116                         port_hw_config[params->port].speed_capability_mask2));
12117         } else {
12118                 link_config = REG_RD(bp, params->shmem_base +
12119                                      offsetof(struct shmem_region, dev_info.
12120                                 port_feature_config[params->port].link_config));
12121                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12122                                              offsetof(struct shmem_region,
12123                                                       dev_info.
12124                         port_hw_config[params->port].speed_capability_mask));
12125         }
12126         DP(NETIF_MSG_LINK,
12127            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12128            phy_index, link_config, phy->speed_cap_mask);
12129
12130         phy->req_duplex = DUPLEX_FULL;
12131         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12132         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12133                 phy->req_duplex = DUPLEX_HALF;
12134         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12135                 phy->req_line_speed = SPEED_10;
12136                 break;
12137         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12138                 phy->req_duplex = DUPLEX_HALF;
12139         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12140                 phy->req_line_speed = SPEED_100;
12141                 break;
12142         case PORT_FEATURE_LINK_SPEED_1G:
12143                 phy->req_line_speed = SPEED_1000;
12144                 break;
12145         case PORT_FEATURE_LINK_SPEED_2_5G:
12146                 phy->req_line_speed = SPEED_2500;
12147                 break;
12148         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12149                 phy->req_line_speed = SPEED_10000;
12150                 break;
12151         default:
12152                 phy->req_line_speed = SPEED_AUTO_NEG;
12153                 break;
12154         }
12155
12156         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12157         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12158                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12159                 break;
12160         case PORT_FEATURE_FLOW_CONTROL_TX:
12161                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12162                 break;
12163         case PORT_FEATURE_FLOW_CONTROL_RX:
12164                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12165                 break;
12166         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12167                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12168                 break;
12169         default:
12170                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12171                 break;
12172         }
12173 }
12174
12175 u32 bnx2x_phy_selection(struct link_params *params)
12176 {
12177         u32 phy_config_swapped, prio_cfg;
12178         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12179
12180         phy_config_swapped = params->multi_phy_config &
12181                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12182
12183         prio_cfg = params->multi_phy_config &
12184                         PORT_HW_CFG_PHY_SELECTION_MASK;
12185
12186         if (phy_config_swapped) {
12187                 switch (prio_cfg) {
12188                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12189                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12190                      break;
12191                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12192                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12193                      break;
12194                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12195                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12196                      break;
12197                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12198                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12199                      break;
12200                 }
12201         } else
12202                 return_cfg = prio_cfg;
12203
12204         return return_cfg;
12205 }
12206
12207 int bnx2x_phy_probe(struct link_params *params)
12208 {
12209         u8 phy_index, actual_phy_idx;
12210         u32 phy_config_swapped, sync_offset, media_types;
12211         struct bnx2x *bp = params->bp;
12212         struct bnx2x_phy *phy;
12213         params->num_phys = 0;
12214         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12215         phy_config_swapped = params->multi_phy_config &
12216                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12217
12218         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12219               phy_index++) {
12220                 actual_phy_idx = phy_index;
12221                 if (phy_config_swapped) {
12222                         if (phy_index == EXT_PHY1)
12223                                 actual_phy_idx = EXT_PHY2;
12224                         else if (phy_index == EXT_PHY2)
12225                                 actual_phy_idx = EXT_PHY1;
12226                 }
12227                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12228                                " actual_phy_idx %x\n", phy_config_swapped,
12229                            phy_index, actual_phy_idx);
12230                 phy = &params->phy[actual_phy_idx];
12231                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12232                                        params->shmem2_base, params->port,
12233                                        phy) != 0) {
12234                         params->num_phys = 0;
12235                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12236                                    phy_index);
12237                         for (phy_index = INT_PHY;
12238                               phy_index < MAX_PHYS;
12239                               phy_index++)
12240                                 *phy = phy_null;
12241                         return -EINVAL;
12242                 }
12243                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12244                         break;
12245
12246                 if (params->feature_config_flags &
12247                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12248                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12249
12250                 if (!(params->feature_config_flags &
12251                       FEATURE_CONFIG_MT_SUPPORT))
12252                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12253
12254                 sync_offset = params->shmem_base +
12255                         offsetof(struct shmem_region,
12256                         dev_info.port_hw_config[params->port].media_type);
12257                 media_types = REG_RD(bp, sync_offset);
12258
12259                 /* Update media type for non-PMF sync only for the first time
12260                  * In case the media type changes afterwards, it will be updated
12261                  * using the update_status function
12262                  */
12263                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12264                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12265                                      actual_phy_idx))) == 0) {
12266                         media_types |= ((phy->media_type &
12267                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12268                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12269                                  actual_phy_idx));
12270                 }
12271                 REG_WR(bp, sync_offset, media_types);
12272
12273                 bnx2x_phy_def_cfg(params, phy, phy_index);
12274                 params->num_phys++;
12275         }
12276
12277         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12278         return 0;
12279 }
12280
12281 static void bnx2x_init_bmac_loopback(struct link_params *params,
12282                                      struct link_vars *vars)
12283 {
12284         struct bnx2x *bp = params->bp;
12285                 vars->link_up = 1;
12286                 vars->line_speed = SPEED_10000;
12287                 vars->duplex = DUPLEX_FULL;
12288                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12289                 vars->mac_type = MAC_TYPE_BMAC;
12290
12291                 vars->phy_flags = PHY_XGXS_FLAG;
12292
12293                 bnx2x_xgxs_deassert(params);
12294
12295                 /* Set bmac loopback */
12296                 bnx2x_bmac_enable(params, vars, 1, 1);
12297
12298                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12299 }
12300
12301 static void bnx2x_init_emac_loopback(struct link_params *params,
12302                                      struct link_vars *vars)
12303 {
12304         struct bnx2x *bp = params->bp;
12305                 vars->link_up = 1;
12306                 vars->line_speed = SPEED_1000;
12307                 vars->duplex = DUPLEX_FULL;
12308                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12309                 vars->mac_type = MAC_TYPE_EMAC;
12310
12311                 vars->phy_flags = PHY_XGXS_FLAG;
12312
12313                 bnx2x_xgxs_deassert(params);
12314                 /* Set bmac loopback */
12315                 bnx2x_emac_enable(params, vars, 1);
12316                 bnx2x_emac_program(params, vars);
12317                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12318 }
12319
12320 static void bnx2x_init_xmac_loopback(struct link_params *params,
12321                                      struct link_vars *vars)
12322 {
12323         struct bnx2x *bp = params->bp;
12324         vars->link_up = 1;
12325         if (!params->req_line_speed[0])
12326                 vars->line_speed = SPEED_10000;
12327         else
12328                 vars->line_speed = params->req_line_speed[0];
12329         vars->duplex = DUPLEX_FULL;
12330         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12331         vars->mac_type = MAC_TYPE_XMAC;
12332         vars->phy_flags = PHY_XGXS_FLAG;
12333         /* Set WC to loopback mode since link is required to provide clock
12334          * to the XMAC in 20G mode
12335          */
12336         bnx2x_set_aer_mmd(params, &params->phy[0]);
12337         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12338         params->phy[INT_PHY].config_loopback(
12339                         &params->phy[INT_PHY],
12340                         params);
12341
12342         bnx2x_xmac_enable(params, vars, 1);
12343         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12344 }
12345
12346 static void bnx2x_init_umac_loopback(struct link_params *params,
12347                                      struct link_vars *vars)
12348 {
12349         struct bnx2x *bp = params->bp;
12350         vars->link_up = 1;
12351         vars->line_speed = SPEED_1000;
12352         vars->duplex = DUPLEX_FULL;
12353         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12354         vars->mac_type = MAC_TYPE_UMAC;
12355         vars->phy_flags = PHY_XGXS_FLAG;
12356         bnx2x_umac_enable(params, vars, 1);
12357
12358         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12359 }
12360
12361 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12362                                      struct link_vars *vars)
12363 {
12364         struct bnx2x *bp = params->bp;
12365         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12366         vars->link_up = 1;
12367         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12368         vars->duplex = DUPLEX_FULL;
12369         if (params->req_line_speed[0] == SPEED_1000)
12370                 vars->line_speed = SPEED_1000;
12371         else if ((params->req_line_speed[0] == SPEED_20000) ||
12372                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12373                 vars->line_speed = SPEED_20000;
12374         else
12375                 vars->line_speed = SPEED_10000;
12376
12377         if (!USES_WARPCORE(bp))
12378                 bnx2x_xgxs_deassert(params);
12379         bnx2x_link_initialize(params, vars);
12380
12381         if (params->req_line_speed[0] == SPEED_1000) {
12382                 if (USES_WARPCORE(bp))
12383                         bnx2x_umac_enable(params, vars, 0);
12384                 else {
12385                         bnx2x_emac_program(params, vars);
12386                         bnx2x_emac_enable(params, vars, 0);
12387                 }
12388         } else {
12389                 if (USES_WARPCORE(bp))
12390                         bnx2x_xmac_enable(params, vars, 0);
12391                 else
12392                         bnx2x_bmac_enable(params, vars, 0, 1);
12393         }
12394
12395         if (params->loopback_mode == LOOPBACK_XGXS) {
12396                 /* Set 10G XGXS loopback */
12397                 int_phy->config_loopback(int_phy, params);
12398         } else {
12399                 /* Set external phy loopback */
12400                 u8 phy_index;
12401                 for (phy_index = EXT_PHY1;
12402                       phy_index < params->num_phys; phy_index++)
12403                         if (params->phy[phy_index].config_loopback)
12404                                 params->phy[phy_index].config_loopback(
12405                                         &params->phy[phy_index],
12406                                         params);
12407         }
12408         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12409
12410         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12411 }
12412
12413 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12414 {
12415         struct bnx2x *bp = params->bp;
12416         u8 val = en * 0x1F;
12417
12418         /* Open / close the gate between the NIG and the BRB */
12419         if (!CHIP_IS_E1x(bp))
12420                 val |= en * 0x20;
12421         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12422
12423         if (!CHIP_IS_E1(bp)) {
12424                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12425                        en*0x3);
12426         }
12427
12428         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12429                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12430 }
12431 static int bnx2x_avoid_link_flap(struct link_params *params,
12432                                             struct link_vars *vars)
12433 {
12434         u32 phy_idx;
12435         u32 dont_clear_stat, lfa_sts;
12436         struct bnx2x *bp = params->bp;
12437
12438         /* Sync the link parameters */
12439         bnx2x_link_status_update(params, vars);
12440
12441         /*
12442          * The module verification was already done by previous link owner,
12443          * so this call is meant only to get warning message
12444          */
12445
12446         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12447                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12448                 if (phy->phy_specific_func) {
12449                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12450                         phy->phy_specific_func(phy, params, PHY_INIT);
12451                 }
12452                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12453                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12454                     (phy->media_type == ETH_PHY_DA_TWINAX))
12455                         bnx2x_verify_sfp_module(phy, params);
12456         }
12457         lfa_sts = REG_RD(bp, params->lfa_base +
12458                          offsetof(struct shmem_lfa,
12459                                   lfa_sts));
12460
12461         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12462
12463         /* Re-enable the NIG/MAC */
12464         if (CHIP_IS_E3(bp)) {
12465                 if (!dont_clear_stat) {
12466                         REG_WR(bp, GRCBASE_MISC +
12467                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12468                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12469                                 params->port));
12470                         REG_WR(bp, GRCBASE_MISC +
12471                                MISC_REGISTERS_RESET_REG_2_SET,
12472                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12473                                 params->port));
12474                 }
12475                 if (vars->line_speed < SPEED_10000)
12476                         bnx2x_umac_enable(params, vars, 0);
12477                 else
12478                         bnx2x_xmac_enable(params, vars, 0);
12479         } else {
12480                 if (vars->line_speed < SPEED_10000)
12481                         bnx2x_emac_enable(params, vars, 0);
12482                 else
12483                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12484         }
12485
12486         /* Increment LFA count */
12487         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12488                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12489                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12490                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12491         /* Clear link flap reason */
12492         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12493
12494         REG_WR(bp, params->lfa_base +
12495                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12496
12497         /* Disable NIG DRAIN */
12498         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12499
12500         /* Enable interrupts */
12501         bnx2x_link_int_enable(params);
12502         return 0;
12503 }
12504
12505 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12506                                          struct link_vars *vars,
12507                                          int lfa_status)
12508 {
12509         u32 lfa_sts, cfg_idx, tmp_val;
12510         struct bnx2x *bp = params->bp;
12511
12512         bnx2x_link_reset(params, vars, 1);
12513
12514         if (!params->lfa_base)
12515                 return;
12516         /* Store the new link parameters */
12517         REG_WR(bp, params->lfa_base +
12518                offsetof(struct shmem_lfa, req_duplex),
12519                params->req_duplex[0] | (params->req_duplex[1] << 16));
12520
12521         REG_WR(bp, params->lfa_base +
12522                offsetof(struct shmem_lfa, req_flow_ctrl),
12523                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12524
12525         REG_WR(bp, params->lfa_base +
12526                offsetof(struct shmem_lfa, req_line_speed),
12527                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12528
12529         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12530                 REG_WR(bp, params->lfa_base +
12531                        offsetof(struct shmem_lfa,
12532                                 speed_cap_mask[cfg_idx]),
12533                        params->speed_cap_mask[cfg_idx]);
12534         }
12535
12536         tmp_val = REG_RD(bp, params->lfa_base +
12537                          offsetof(struct shmem_lfa, additional_config));
12538         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12539         tmp_val |= params->req_fc_auto_adv;
12540
12541         REG_WR(bp, params->lfa_base +
12542                offsetof(struct shmem_lfa, additional_config), tmp_val);
12543
12544         lfa_sts = REG_RD(bp, params->lfa_base +
12545                          offsetof(struct shmem_lfa, lfa_sts));
12546
12547         /* Clear the "Don't Clear Statistics" bit, and set reason */
12548         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12549
12550         /* Set link flap reason */
12551         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12552         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12553                     LFA_LINK_FLAP_REASON_OFFSET);
12554
12555         /* Increment link flap counter */
12556         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12557                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12558                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12559                     << LINK_FLAP_COUNT_OFFSET));
12560         REG_WR(bp, params->lfa_base +
12561                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12562         /* Proceed with regular link initialization */
12563 }
12564
12565 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12566 {
12567         int lfa_status;
12568         struct bnx2x *bp = params->bp;
12569         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12570         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12571                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12572         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12573                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12574         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12575         vars->link_status = 0;
12576         vars->phy_link_up = 0;
12577         vars->link_up = 0;
12578         vars->line_speed = 0;
12579         vars->duplex = DUPLEX_FULL;
12580         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12581         vars->mac_type = MAC_TYPE_NONE;
12582         vars->phy_flags = 0;
12583         vars->check_kr2_recovery_cnt = 0;
12584         params->link_flags = PHY_INITIALIZED;
12585         /* Driver opens NIG-BRB filters */
12586         bnx2x_set_rx_filter(params, 1);
12587         /* Check if link flap can be avoided */
12588         lfa_status = bnx2x_check_lfa(params);
12589
12590         if (lfa_status == 0) {
12591                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12592                 return bnx2x_avoid_link_flap(params, vars);
12593         }
12594
12595         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12596                        lfa_status);
12597         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12598
12599         /* Disable attentions */
12600         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12601                        (NIG_MASK_XGXS0_LINK_STATUS |
12602                         NIG_MASK_XGXS0_LINK10G |
12603                         NIG_MASK_SERDES0_LINK_STATUS |
12604                         NIG_MASK_MI_INT));
12605
12606         bnx2x_emac_init(params, vars);
12607
12608         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12609                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12610
12611         if (params->num_phys == 0) {
12612                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12613                 return -EINVAL;
12614         }
12615         set_phy_vars(params, vars);
12616
12617         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12618         switch (params->loopback_mode) {
12619         case LOOPBACK_BMAC:
12620                 bnx2x_init_bmac_loopback(params, vars);
12621                 break;
12622         case LOOPBACK_EMAC:
12623                 bnx2x_init_emac_loopback(params, vars);
12624                 break;
12625         case LOOPBACK_XMAC:
12626                 bnx2x_init_xmac_loopback(params, vars);
12627                 break;
12628         case LOOPBACK_UMAC:
12629                 bnx2x_init_umac_loopback(params, vars);
12630                 break;
12631         case LOOPBACK_XGXS:
12632         case LOOPBACK_EXT_PHY:
12633                 bnx2x_init_xgxs_loopback(params, vars);
12634                 break;
12635         default:
12636                 if (!CHIP_IS_E3(bp)) {
12637                         if (params->switch_cfg == SWITCH_CFG_10G)
12638                                 bnx2x_xgxs_deassert(params);
12639                         else
12640                                 bnx2x_serdes_deassert(bp, params->port);
12641                 }
12642                 bnx2x_link_initialize(params, vars);
12643                 msleep(30);
12644                 bnx2x_link_int_enable(params);
12645                 break;
12646         }
12647         bnx2x_update_mng(params, vars->link_status);
12648
12649         bnx2x_update_mng_eee(params, vars->eee_status);
12650         return 0;
12651 }
12652
12653 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12654                      u8 reset_ext_phy)
12655 {
12656         struct bnx2x *bp = params->bp;
12657         u8 phy_index, port = params->port, clear_latch_ind = 0;
12658         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12659         /* Disable attentions */
12660         vars->link_status = 0;
12661         bnx2x_update_mng(params, vars->link_status);
12662         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12663                               SHMEM_EEE_ACTIVE_BIT);
12664         bnx2x_update_mng_eee(params, vars->eee_status);
12665         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12666                        (NIG_MASK_XGXS0_LINK_STATUS |
12667                         NIG_MASK_XGXS0_LINK10G |
12668                         NIG_MASK_SERDES0_LINK_STATUS |
12669                         NIG_MASK_MI_INT));
12670
12671         /* Activate nig drain */
12672         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12673
12674         /* Disable nig egress interface */
12675         if (!CHIP_IS_E3(bp)) {
12676                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12677                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12678         }
12679
12680                 if (!CHIP_IS_E3(bp)) {
12681                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12682                 } else {
12683                         bnx2x_set_xmac_rxtx(params, 0);
12684                         bnx2x_set_umac_rxtx(params, 0);
12685                 }
12686         /* Disable emac */
12687         if (!CHIP_IS_E3(bp))
12688                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12689
12690         usleep_range(10000, 20000);
12691         /* The PHY reset is controlled by GPIO 1
12692          * Hold it as vars low
12693          */
12694          /* Clear link led */
12695         bnx2x_set_mdio_emac_per_phy(bp, params);
12696         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12697
12698         if (reset_ext_phy) {
12699                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12700                       phy_index++) {
12701                         if (params->phy[phy_index].link_reset) {
12702                                 bnx2x_set_aer_mmd(params,
12703                                                   &params->phy[phy_index]);
12704                                 params->phy[phy_index].link_reset(
12705                                         &params->phy[phy_index],
12706                                         params);
12707                         }
12708                         if (params->phy[phy_index].flags &
12709                             FLAGS_REARM_LATCH_SIGNAL)
12710                                 clear_latch_ind = 1;
12711                 }
12712         }
12713
12714         if (clear_latch_ind) {
12715                 /* Clear latching indication */
12716                 bnx2x_rearm_latch_signal(bp, port, 0);
12717                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12718                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12719         }
12720         if (params->phy[INT_PHY].link_reset)
12721                 params->phy[INT_PHY].link_reset(
12722                         &params->phy[INT_PHY], params);
12723
12724         /* Disable nig ingress interface */
12725         if (!CHIP_IS_E3(bp)) {
12726                 /* Reset BigMac */
12727                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12728                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12729                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12730                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12731         } else {
12732                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12733                 bnx2x_set_xumac_nig(params, 0, 0);
12734                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12735                     MISC_REGISTERS_RESET_REG_2_XMAC)
12736                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12737                                XMAC_CTRL_REG_SOFT_RESET);
12738         }
12739         vars->link_up = 0;
12740         vars->phy_flags = 0;
12741         return 0;
12742 }
12743 int bnx2x_lfa_reset(struct link_params *params,
12744                                struct link_vars *vars)
12745 {
12746         struct bnx2x *bp = params->bp;
12747         vars->link_up = 0;
12748         vars->phy_flags = 0;
12749         params->link_flags &= ~PHY_INITIALIZED;
12750         if (!params->lfa_base)
12751                 return bnx2x_link_reset(params, vars, 1);
12752         /*
12753          * Activate NIG drain so that during this time the device won't send
12754          * anything while it is unable to response.
12755          */
12756         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12757
12758         /*
12759          * Close gracefully the gate from BMAC to NIG such that no half packets
12760          * are passed.
12761          */
12762         if (!CHIP_IS_E3(bp))
12763                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12764
12765         if (CHIP_IS_E3(bp)) {
12766                 bnx2x_set_xmac_rxtx(params, 0);
12767                 bnx2x_set_umac_rxtx(params, 0);
12768         }
12769         /* Wait 10ms for the pipe to clean up*/
12770         usleep_range(10000, 20000);
12771
12772         /* Clean the NIG-BRB using the network filters in a way that will
12773          * not cut a packet in the middle.
12774          */
12775         bnx2x_set_rx_filter(params, 0);
12776
12777         /*
12778          * Re-open the gate between the BMAC and the NIG, after verifying the
12779          * gate to the BRB is closed, otherwise packets may arrive to the
12780          * firmware before driver had initialized it. The target is to achieve
12781          * minimum management protocol down time.
12782          */
12783         if (!CHIP_IS_E3(bp))
12784                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12785
12786         if (CHIP_IS_E3(bp)) {
12787                 bnx2x_set_xmac_rxtx(params, 1);
12788                 bnx2x_set_umac_rxtx(params, 1);
12789         }
12790         /* Disable NIG drain */
12791         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12792         return 0;
12793 }
12794
12795 /****************************************************************************/
12796 /*                              Common function                             */
12797 /****************************************************************************/
12798 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12799                                       u32 shmem_base_path[],
12800                                       u32 shmem2_base_path[], u8 phy_index,
12801                                       u32 chip_id)
12802 {
12803         struct bnx2x_phy phy[PORT_MAX];
12804         struct bnx2x_phy *phy_blk[PORT_MAX];
12805         u16 val;
12806         s8 port = 0;
12807         s8 port_of_path = 0;
12808         u32 swap_val, swap_override;
12809         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12810         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12811         port ^= (swap_val && swap_override);
12812         bnx2x_ext_phy_hw_reset(bp, port);
12813         /* PART1 - Reset both phys */
12814         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12815                 u32 shmem_base, shmem2_base;
12816                 /* In E2, same phy is using for port0 of the two paths */
12817                 if (CHIP_IS_E1x(bp)) {
12818                         shmem_base = shmem_base_path[0];
12819                         shmem2_base = shmem2_base_path[0];
12820                         port_of_path = port;
12821                 } else {
12822                         shmem_base = shmem_base_path[port];
12823                         shmem2_base = shmem2_base_path[port];
12824                         port_of_path = 0;
12825                 }
12826
12827                 /* Extract the ext phy address for the port */
12828                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12829                                        port_of_path, &phy[port]) !=
12830                     0) {
12831                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12832                         return -EINVAL;
12833                 }
12834                 /* Disable attentions */
12835                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12836                                port_of_path*4,
12837                                (NIG_MASK_XGXS0_LINK_STATUS |
12838                                 NIG_MASK_XGXS0_LINK10G |
12839                                 NIG_MASK_SERDES0_LINK_STATUS |
12840                                 NIG_MASK_MI_INT));
12841
12842                 /* Need to take the phy out of low power mode in order
12843                  * to write to access its registers
12844                  */
12845                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12846                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12847                                port);
12848
12849                 /* Reset the phy */
12850                 bnx2x_cl45_write(bp, &phy[port],
12851                                  MDIO_PMA_DEVAD,
12852                                  MDIO_PMA_REG_CTRL,
12853                                  1<<15);
12854         }
12855
12856         /* Add delay of 150ms after reset */
12857         msleep(150);
12858
12859         if (phy[PORT_0].addr & 0x1) {
12860                 phy_blk[PORT_0] = &(phy[PORT_1]);
12861                 phy_blk[PORT_1] = &(phy[PORT_0]);
12862         } else {
12863                 phy_blk[PORT_0] = &(phy[PORT_0]);
12864                 phy_blk[PORT_1] = &(phy[PORT_1]);
12865         }
12866
12867         /* PART2 - Download firmware to both phys */
12868         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12869                 if (CHIP_IS_E1x(bp))
12870                         port_of_path = port;
12871                 else
12872                         port_of_path = 0;
12873
12874                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12875                            phy_blk[port]->addr);
12876                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12877                                                       port_of_path))
12878                         return -EINVAL;
12879
12880                 /* Only set bit 10 = 1 (Tx power down) */
12881                 bnx2x_cl45_read(bp, phy_blk[port],
12882                                 MDIO_PMA_DEVAD,
12883                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12884
12885                 /* Phase1 of TX_POWER_DOWN reset */
12886                 bnx2x_cl45_write(bp, phy_blk[port],
12887                                  MDIO_PMA_DEVAD,
12888                                  MDIO_PMA_REG_TX_POWER_DOWN,
12889                                  (val | 1<<10));
12890         }
12891
12892         /* Toggle Transmitter: Power down and then up with 600ms delay
12893          * between
12894          */
12895         msleep(600);
12896
12897         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12898         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12899                 /* Phase2 of POWER_DOWN_RESET */
12900                 /* Release bit 10 (Release Tx power down) */
12901                 bnx2x_cl45_read(bp, phy_blk[port],
12902                                 MDIO_PMA_DEVAD,
12903                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12904
12905                 bnx2x_cl45_write(bp, phy_blk[port],
12906                                 MDIO_PMA_DEVAD,
12907                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12908                 usleep_range(15000, 30000);
12909
12910                 /* Read modify write the SPI-ROM version select register */
12911                 bnx2x_cl45_read(bp, phy_blk[port],
12912                                 MDIO_PMA_DEVAD,
12913                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12914                 bnx2x_cl45_write(bp, phy_blk[port],
12915                                  MDIO_PMA_DEVAD,
12916                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12917
12918                 /* set GPIO2 back to LOW */
12919                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12920                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12921         }
12922         return 0;
12923 }
12924 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12925                                       u32 shmem_base_path[],
12926                                       u32 shmem2_base_path[], u8 phy_index,
12927                                       u32 chip_id)
12928 {
12929         u32 val;
12930         s8 port;
12931         struct bnx2x_phy phy;
12932         /* Use port1 because of the static port-swap */
12933         /* Enable the module detection interrupt */
12934         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12935         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12936                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12937         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12938
12939         bnx2x_ext_phy_hw_reset(bp, 0);
12940         usleep_range(5000, 10000);
12941         for (port = 0; port < PORT_MAX; port++) {
12942                 u32 shmem_base, shmem2_base;
12943
12944                 /* In E2, same phy is using for port0 of the two paths */
12945                 if (CHIP_IS_E1x(bp)) {
12946                         shmem_base = shmem_base_path[0];
12947                         shmem2_base = shmem2_base_path[0];
12948                 } else {
12949                         shmem_base = shmem_base_path[port];
12950                         shmem2_base = shmem2_base_path[port];
12951                 }
12952                 /* Extract the ext phy address for the port */
12953                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12954                                        port, &phy) !=
12955                     0) {
12956                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12957                         return -EINVAL;
12958                 }
12959
12960                 /* Reset phy*/
12961                 bnx2x_cl45_write(bp, &phy,
12962                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
12963
12964
12965                 /* Set fault module detected LED on */
12966                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
12967                                MISC_REGISTERS_GPIO_HIGH,
12968                                port);
12969         }
12970
12971         return 0;
12972 }
12973 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
12974                                          u8 *io_gpio, u8 *io_port)
12975 {
12976
12977         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
12978                                           offsetof(struct shmem_region,
12979                                 dev_info.port_hw_config[PORT_0].default_cfg));
12980         switch (phy_gpio_reset) {
12981         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
12982                 *io_gpio = 0;
12983                 *io_port = 0;
12984                 break;
12985         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
12986                 *io_gpio = 1;
12987                 *io_port = 0;
12988                 break;
12989         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
12990                 *io_gpio = 2;
12991                 *io_port = 0;
12992                 break;
12993         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
12994                 *io_gpio = 3;
12995                 *io_port = 0;
12996                 break;
12997         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
12998                 *io_gpio = 0;
12999                 *io_port = 1;
13000                 break;
13001         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13002                 *io_gpio = 1;
13003                 *io_port = 1;
13004                 break;
13005         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13006                 *io_gpio = 2;
13007                 *io_port = 1;
13008                 break;
13009         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13010                 *io_gpio = 3;
13011                 *io_port = 1;
13012                 break;
13013         default:
13014                 /* Don't override the io_gpio and io_port */
13015                 break;
13016         }
13017 }
13018
13019 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13020                                       u32 shmem_base_path[],
13021                                       u32 shmem2_base_path[], u8 phy_index,
13022                                       u32 chip_id)
13023 {
13024         s8 port, reset_gpio;
13025         u32 swap_val, swap_override;
13026         struct bnx2x_phy phy[PORT_MAX];
13027         struct bnx2x_phy *phy_blk[PORT_MAX];
13028         s8 port_of_path;
13029         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13030         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13031
13032         reset_gpio = MISC_REGISTERS_GPIO_1;
13033         port = 1;
13034
13035         /* Retrieve the reset gpio/port which control the reset.
13036          * Default is GPIO1, PORT1
13037          */
13038         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13039                                      (u8 *)&reset_gpio, (u8 *)&port);
13040
13041         /* Calculate the port based on port swap */
13042         port ^= (swap_val && swap_override);
13043
13044         /* Initiate PHY reset*/
13045         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13046                        port);
13047         usleep_range(1000, 2000);
13048         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13049                        port);
13050
13051         usleep_range(5000, 10000);
13052
13053         /* PART1 - Reset both phys */
13054         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13055                 u32 shmem_base, shmem2_base;
13056
13057                 /* In E2, same phy is using for port0 of the two paths */
13058                 if (CHIP_IS_E1x(bp)) {
13059                         shmem_base = shmem_base_path[0];
13060                         shmem2_base = shmem2_base_path[0];
13061                         port_of_path = port;
13062                 } else {
13063                         shmem_base = shmem_base_path[port];
13064                         shmem2_base = shmem2_base_path[port];
13065                         port_of_path = 0;
13066                 }
13067
13068                 /* Extract the ext phy address for the port */
13069                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13070                                        port_of_path, &phy[port]) !=
13071                                        0) {
13072                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13073                         return -EINVAL;
13074                 }
13075                 /* disable attentions */
13076                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13077                                port_of_path*4,
13078                                (NIG_MASK_XGXS0_LINK_STATUS |
13079                                 NIG_MASK_XGXS0_LINK10G |
13080                                 NIG_MASK_SERDES0_LINK_STATUS |
13081                                 NIG_MASK_MI_INT));
13082
13083
13084                 /* Reset the phy */
13085                 bnx2x_cl45_write(bp, &phy[port],
13086                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13087         }
13088
13089         /* Add delay of 150ms after reset */
13090         msleep(150);
13091         if (phy[PORT_0].addr & 0x1) {
13092                 phy_blk[PORT_0] = &(phy[PORT_1]);
13093                 phy_blk[PORT_1] = &(phy[PORT_0]);
13094         } else {
13095                 phy_blk[PORT_0] = &(phy[PORT_0]);
13096                 phy_blk[PORT_1] = &(phy[PORT_1]);
13097         }
13098         /* PART2 - Download firmware to both phys */
13099         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13100                 if (CHIP_IS_E1x(bp))
13101                         port_of_path = port;
13102                 else
13103                         port_of_path = 0;
13104                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13105                            phy_blk[port]->addr);
13106                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13107                                                       port_of_path))
13108                         return -EINVAL;
13109                 /* Disable PHY transmitter output */
13110                 bnx2x_cl45_write(bp, phy_blk[port],
13111                                  MDIO_PMA_DEVAD,
13112                                  MDIO_PMA_REG_TX_DISABLE, 1);
13113
13114         }
13115         return 0;
13116 }
13117
13118 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13119                                                 u32 shmem_base_path[],
13120                                                 u32 shmem2_base_path[],
13121                                                 u8 phy_index,
13122                                                 u32 chip_id)
13123 {
13124         u8 reset_gpios;
13125         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13126         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13127         udelay(10);
13128         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13129         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13130                 reset_gpios);
13131         return 0;
13132 }
13133
13134 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13135                                      u32 shmem2_base_path[], u8 phy_index,
13136                                      u32 ext_phy_type, u32 chip_id)
13137 {
13138         int rc = 0;
13139
13140         switch (ext_phy_type) {
13141         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13142                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13143                                                 shmem2_base_path,
13144                                                 phy_index, chip_id);
13145                 break;
13146         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13147         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13148         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13149                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13150                                                 shmem2_base_path,
13151                                                 phy_index, chip_id);
13152                 break;
13153
13154         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13155                 /* GPIO1 affects both ports, so there's need to pull
13156                  * it for single port alone
13157                  */
13158                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13159                                                 shmem2_base_path,
13160                                                 phy_index, chip_id);
13161                 break;
13162         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13163         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13164                 /* GPIO3's are linked, and so both need to be toggled
13165                  * to obtain required 2us pulse.
13166                  */
13167                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13168                                                 shmem2_base_path,
13169                                                 phy_index, chip_id);
13170                 break;
13171         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13172                 rc = -EINVAL;
13173                 break;
13174         default:
13175                 DP(NETIF_MSG_LINK,
13176                            "ext_phy 0x%x common init not required\n",
13177                            ext_phy_type);
13178                 break;
13179         }
13180
13181         if (rc)
13182                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13183                                       " Port %d\n",
13184                          0);
13185         return rc;
13186 }
13187
13188 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13189                           u32 shmem2_base_path[], u32 chip_id)
13190 {
13191         int rc = 0;
13192         u32 phy_ver, val;
13193         u8 phy_index = 0;
13194         u32 ext_phy_type, ext_phy_config;
13195
13196         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13197         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13198         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13199         if (CHIP_IS_E3(bp)) {
13200                 /* Enable EPIO */
13201                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13202                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13203         }
13204         /* Check if common init was already done */
13205         phy_ver = REG_RD(bp, shmem_base_path[0] +
13206                          offsetof(struct shmem_region,
13207                                   port_mb[PORT_0].ext_phy_fw_version));
13208         if (phy_ver) {
13209                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13210                                phy_ver);
13211                 return 0;
13212         }
13213
13214         /* Read the ext_phy_type for arbitrary port(0) */
13215         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13216               phy_index++) {
13217                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13218                                                           shmem_base_path[0],
13219                                                           phy_index, 0);
13220                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13221                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13222                                                 shmem2_base_path,
13223                                                 phy_index, ext_phy_type,
13224                                                 chip_id);
13225         }
13226         return rc;
13227 }
13228
13229 static void bnx2x_check_over_curr(struct link_params *params,
13230                                   struct link_vars *vars)
13231 {
13232         struct bnx2x *bp = params->bp;
13233         u32 cfg_pin;
13234         u8 port = params->port;
13235         u32 pin_val;
13236
13237         cfg_pin = (REG_RD(bp, params->shmem_base +
13238                           offsetof(struct shmem_region,
13239                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13240                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13241                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13242
13243         /* Ignore check if no external input PIN available */
13244         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13245                 return;
13246
13247         if (!pin_val) {
13248                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13249                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13250                                             " been detected and the power to "
13251                                             "that SFP+ module has been removed"
13252                                             " to prevent failure of the card."
13253                                             " Please remove the SFP+ module and"
13254                                             " restart the system to clear this"
13255                                             " error.\n",
13256                          params->port);
13257                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13258                         bnx2x_warpcore_power_module(params, 0);
13259                 }
13260         } else
13261                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13262 }
13263
13264 /* Returns 0 if no change occured since last check; 1 otherwise. */
13265 static u8 bnx2x_analyze_link_error(struct link_params *params,
13266                                     struct link_vars *vars, u32 status,
13267                                     u32 phy_flag, u32 link_flag, u8 notify)
13268 {
13269         struct bnx2x *bp = params->bp;
13270         /* Compare new value with previous value */
13271         u8 led_mode;
13272         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13273
13274         if ((status ^ old_status) == 0)
13275                 return 0;
13276
13277         /* If values differ */
13278         switch (phy_flag) {
13279         case PHY_HALF_OPEN_CONN_FLAG:
13280                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13281                 break;
13282         case PHY_SFP_TX_FAULT_FLAG:
13283                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13284                 break;
13285         default:
13286                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13287         }
13288         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13289            old_status, status);
13290
13291         /* a. Update shmem->link_status accordingly
13292          * b. Update link_vars->link_up
13293          */
13294         if (status) {
13295                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13296                 vars->link_status |= link_flag;
13297                 vars->link_up = 0;
13298                 vars->phy_flags |= phy_flag;
13299
13300                 /* activate nig drain */
13301                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13302                 /* Set LED mode to off since the PHY doesn't know about these
13303                  * errors
13304                  */
13305                 led_mode = LED_MODE_OFF;
13306         } else {
13307                 vars->link_status |= LINK_STATUS_LINK_UP;
13308                 vars->link_status &= ~link_flag;
13309                 vars->link_up = 1;
13310                 vars->phy_flags &= ~phy_flag;
13311                 led_mode = LED_MODE_OPER;
13312
13313                 /* Clear nig drain */
13314                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13315         }
13316         bnx2x_sync_link(params, vars);
13317         /* Update the LED according to the link state */
13318         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13319
13320         /* Update link status in the shared memory */
13321         bnx2x_update_mng(params, vars->link_status);
13322
13323         /* C. Trigger General Attention */
13324         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13325         if (notify)
13326                 bnx2x_notify_link_changed(bp);
13327
13328         return 1;
13329 }
13330
13331 /******************************************************************************
13332 * Description:
13333 *       This function checks for half opened connection change indication.
13334 *       When such change occurs, it calls the bnx2x_analyze_link_error
13335 *       to check if Remote Fault is set or cleared. Reception of remote fault
13336 *       status message in the MAC indicates that the peer's MAC has detected
13337 *       a fault, for example, due to break in the TX side of fiber.
13338 *
13339 ******************************************************************************/
13340 int bnx2x_check_half_open_conn(struct link_params *params,
13341                                 struct link_vars *vars,
13342                                 u8 notify)
13343 {
13344         struct bnx2x *bp = params->bp;
13345         u32 lss_status = 0;
13346         u32 mac_base;
13347         /* In case link status is physically up @ 10G do */
13348         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13349             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13350                 return 0;
13351
13352         if (CHIP_IS_E3(bp) &&
13353             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13354               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13355                 /* Check E3 XMAC */
13356                 /* Note that link speed cannot be queried here, since it may be
13357                  * zero while link is down. In case UMAC is active, LSS will
13358                  * simply not be set
13359                  */
13360                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13361
13362                 /* Clear stick bits (Requires rising edge) */
13363                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13364                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13365                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13366                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13367                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13368                         lss_status = 1;
13369
13370                 bnx2x_analyze_link_error(params, vars, lss_status,
13371                                          PHY_HALF_OPEN_CONN_FLAG,
13372                                          LINK_STATUS_NONE, notify);
13373         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13374                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13375                 /* Check E1X / E2 BMAC */
13376                 u32 lss_status_reg;
13377                 u32 wb_data[2];
13378                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13379                         NIG_REG_INGRESS_BMAC0_MEM;
13380                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13381                 if (CHIP_IS_E2(bp))
13382                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13383                 else
13384                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13385
13386                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13387                 lss_status = (wb_data[0] > 0);
13388
13389                 bnx2x_analyze_link_error(params, vars, lss_status,
13390                                          PHY_HALF_OPEN_CONN_FLAG,
13391                                          LINK_STATUS_NONE, notify);
13392         }
13393         return 0;
13394 }
13395 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13396                                          struct link_params *params,
13397                                          struct link_vars *vars)
13398 {
13399         struct bnx2x *bp = params->bp;
13400         u32 cfg_pin, value = 0;
13401         u8 led_change, port = params->port;
13402
13403         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13404         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13405                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13406                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13407                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13408
13409         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13410                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13411                 return;
13412         }
13413
13414         led_change = bnx2x_analyze_link_error(params, vars, value,
13415                                               PHY_SFP_TX_FAULT_FLAG,
13416                                               LINK_STATUS_SFP_TX_FAULT, 1);
13417
13418         if (led_change) {
13419                 /* Change TX_Fault led, set link status for further syncs */
13420                 u8 led_mode;
13421
13422                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13423                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13424                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13425                 } else {
13426                         led_mode = MISC_REGISTERS_GPIO_LOW;
13427                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13428                 }
13429
13430                 /* If module is unapproved, led should be on regardless */
13431                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13432                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13433                            led_mode);
13434                         bnx2x_set_e3_module_fault_led(params, led_mode);
13435                 }
13436         }
13437 }
13438 static void bnx2x_disable_kr2(struct link_params *params,
13439                               struct link_vars *vars,
13440                               struct bnx2x_phy *phy)
13441 {
13442         struct bnx2x *bp = params->bp;
13443         int i;
13444         static struct bnx2x_reg_set reg_set[] = {
13445                 /* Step 1 - Program the TX/RX alignment markers */
13446                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
13447                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
13448                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
13449                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
13450                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
13451                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
13452                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
13453                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
13454                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
13455                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
13456                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
13457                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
13458                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
13459                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
13460                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
13461         };
13462         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
13463
13464         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
13465                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
13466                                  reg_set[i].val);
13467         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
13468         bnx2x_update_link_attr(params, vars->link_attr_sync);
13469
13470         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
13471         /* Restart AN on leading lane */
13472         bnx2x_warpcore_restart_AN_KR(phy, params);
13473 }
13474
13475 static void bnx2x_kr2_recovery(struct link_params *params,
13476                                struct link_vars *vars,
13477                                struct bnx2x_phy *phy)
13478 {
13479         struct bnx2x *bp = params->bp;
13480         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13481         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13482         bnx2x_warpcore_restart_AN_KR(phy, params);
13483 }
13484
13485 static void bnx2x_check_kr2_wa(struct link_params *params,
13486                                struct link_vars *vars,
13487                                struct bnx2x_phy *phy)
13488 {
13489         struct bnx2x *bp = params->bp;
13490         u16 base_page, next_page, not_kr2_device, lane;
13491         int sigdet;
13492
13493         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13494          * Since some switches tend to reinit the AN process and clear the
13495          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13496          * and recovered many times
13497          */
13498         if (vars->check_kr2_recovery_cnt > 0) {
13499                 vars->check_kr2_recovery_cnt--;
13500                 return;
13501         }
13502
13503         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13504         if (!sigdet) {
13505                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13506                         bnx2x_kr2_recovery(params, vars, phy);
13507                         DP(NETIF_MSG_LINK, "No sigdet\n");
13508                 }
13509                 return;
13510         }
13511
13512         lane = bnx2x_get_warpcore_lane(phy, params);
13513         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13514                           MDIO_AER_BLOCK_AER_REG, lane);
13515         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13516                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13517         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13518                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13519         bnx2x_set_aer_mmd(params, phy);
13520
13521         /* CL73 has not begun yet */
13522         if (base_page == 0) {
13523                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13524                         bnx2x_kr2_recovery(params, vars, phy);
13525                         DP(NETIF_MSG_LINK, "No BP\n");
13526                 }
13527                 return;
13528         }
13529
13530         /* In case NP bit is not set in the BasePage, or it is set,
13531          * but only KX is advertised, declare this link partner as non-KR2
13532          * device.
13533          */
13534         not_kr2_device = (((base_page & 0x8000) == 0) ||
13535                           (((base_page & 0x8000) &&
13536                             ((next_page & 0xe0) == 0x2))));
13537
13538         /* In case KR2 is already disabled, check if we need to re-enable it */
13539         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13540                 if (!not_kr2_device) {
13541                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13542                            next_page);
13543                         bnx2x_kr2_recovery(params, vars, phy);
13544                 }
13545                 return;
13546         }
13547         /* KR2 is enabled, but not KR2 device */
13548         if (not_kr2_device) {
13549                 /* Disable KR2 on both lanes */
13550                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13551                 bnx2x_disable_kr2(params, vars, phy);
13552                 return;
13553         }
13554 }
13555
13556 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13557 {
13558         u16 phy_idx;
13559         struct bnx2x *bp = params->bp;
13560         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13561                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13562                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13563                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13564                             0)
13565                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13566                         break;
13567                 }
13568         }
13569
13570         if (CHIP_IS_E3(bp)) {
13571                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13572                 bnx2x_set_aer_mmd(params, phy);
13573                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13574                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13575                         bnx2x_check_kr2_wa(params, vars, phy);
13576                 bnx2x_check_over_curr(params, vars);
13577                 if (vars->rx_tx_asic_rst)
13578                         bnx2x_warpcore_config_runtime(phy, params, vars);
13579
13580                 if ((REG_RD(bp, params->shmem_base +
13581                             offsetof(struct shmem_region, dev_info.
13582                                 port_hw_config[params->port].default_cfg))
13583                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13584                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13585                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13586                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13587                         } else if (vars->link_status &
13588                                 LINK_STATUS_SFP_TX_FAULT) {
13589                                 /* Clean trail, interrupt corrects the leds */
13590                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13591                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13592                                 /* Update link status in the shared memory */
13593                                 bnx2x_update_mng(params, vars->link_status);
13594                         }
13595                 }
13596         }
13597 }
13598
13599 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13600                              u32 shmem_base,
13601                              u32 shmem2_base,
13602                              u8 port)
13603 {
13604         u8 phy_index, fan_failure_det_req = 0;
13605         struct bnx2x_phy phy;
13606         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13607               phy_index++) {
13608                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13609                                        port, &phy)
13610                     != 0) {
13611                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13612                         return 0;
13613                 }
13614                 fan_failure_det_req |= (phy.flags &
13615                                         FLAGS_FAN_FAILURE_DET_REQ);
13616         }
13617         return fan_failure_det_req;
13618 }
13619
13620 void bnx2x_hw_reset_phy(struct link_params *params)
13621 {
13622         u8 phy_index;
13623         struct bnx2x *bp = params->bp;
13624         bnx2x_update_mng(params, 0);
13625         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13626                        (NIG_MASK_XGXS0_LINK_STATUS |
13627                         NIG_MASK_XGXS0_LINK10G |
13628                         NIG_MASK_SERDES0_LINK_STATUS |
13629                         NIG_MASK_MI_INT));
13630
13631         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13632               phy_index++) {
13633                 if (params->phy[phy_index].hw_reset) {
13634                         params->phy[phy_index].hw_reset(
13635                                 &params->phy[phy_index],
13636                                 params);
13637                         params->phy[phy_index] = phy_null;
13638                 }
13639         }
13640 }
13641
13642 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13643                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13644                             u8 port)
13645 {
13646         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13647         u32 val;
13648         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13649         if (CHIP_IS_E3(bp)) {
13650                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13651                                               shmem_base,
13652                                               port,
13653                                               &gpio_num,
13654                                               &gpio_port) != 0)
13655                         return;
13656         } else {
13657                 struct bnx2x_phy phy;
13658                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13659                       phy_index++) {
13660                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13661                                                shmem2_base, port, &phy)
13662                             != 0) {
13663                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13664                                 return;
13665                         }
13666                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13667                                 gpio_num = MISC_REGISTERS_GPIO_3;
13668                                 gpio_port = port;
13669                                 break;
13670                         }
13671                 }
13672         }
13673
13674         if (gpio_num == 0xff)
13675                 return;
13676
13677         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13678         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13679
13680         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13681         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13682         gpio_port ^= (swap_val && swap_override);
13683
13684         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13685                 (gpio_num + (gpio_port << 2));
13686
13687         sync_offset = shmem_base +
13688                 offsetof(struct shmem_region,
13689                          dev_info.port_hw_config[port].aeu_int_mask);
13690         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13691
13692         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13693                        gpio_num, gpio_port, vars->aeu_int_mask);
13694
13695         if (port == 0)
13696                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13697         else
13698                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13699
13700         /* Open appropriate AEU for interrupts */
13701         aeu_mask = REG_RD(bp, offset);
13702         aeu_mask |= vars->aeu_int_mask;
13703         REG_WR(bp, offset, aeu_mask);
13704
13705         /* Enable the GPIO to trigger interrupt */
13706         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13707         val |= 1 << (gpio_num + (gpio_port << 2));
13708         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13709 }