Pileus Git - ~andy/linux/blob - drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 /*
  20  * The MMCIF driver is now processing MMC requests asynchronously, according
  21  * to the Linux MMC API requirement.
  22  *
  23  * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
  24  * data, and optional stop. To achieve asynchronous processing each of these
  25  * stages is split into two halves: a top and a bottom half. The top half
  26  * initialises the hardware, installs a timeout handler to handle completion
  27  * timeouts, and returns. In case of the command stage this immediately returns
  28  * control to the caller, leaving all further processing to run asynchronously.
  29  * All further request processing is performed by the bottom halves.
  30  *
  31  * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
  32  * thread, a DMA completion callback, if DMA is used, a timeout work, and
  33  * request- and stage-specific handler methods.
  34  *
  35  * Each bottom half run begins with either a hardware interrupt, a DMA callback
  36  * invocation, or a timeout work run. In case of an error or a successful
  37  * processing completion, the MMC core is informed and the request processing is
  38  * finished. In case processing has to continue, i.e., if data has to be read
  39  * from or written to the card, or if a stop command has to be sent, the next
  40  * top half is called, which performs the necessary hardware handling and
  41  * reschedules the timeout work. This returns the driver state machine into the
  42  * bottom half waiting state.
  43  */
  44
  45 #include <linux/bitops.h>
  46 #include <linux/clk.h>
  47 #include <linux/completion.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/dmaengine.h>
  51 #include <linux/mmc/card.h>
  52 #include <linux/mmc/core.h>
  53 #include <linux/mmc/host.h>
  54 #include <linux/mmc/mmc.h>
  55 #include <linux/mmc/sdio.h>
  56 #include <linux/mmc/sh_mmcif.h>
  57 #include <linux/pagemap.h>
  58 #include <linux/platform_device.h>
  59 #include <linux/pm_qos.h>
  60 #include <linux/pm_runtime.h>
  61 #include <linux/spinlock.h>
  62 #include <linux/module.h>
  63
  64 #define DRIVER_NAME     "sh_mmcif"
  65 #define DRIVER_VERSION  "2010-04-28"
  66
  67 /* CE_CMD_SET */
  68 #define CMD_MASK                0x3f000000
  69 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  70 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  71 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  72 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  73 #define CMD_SET_CCSEN           (1 << 20)
  74 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  75 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  76 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  77 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  78 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  79 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  80 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  81 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  82 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  83 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  84 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  85 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  86 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  87 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  88 #define CMD_SET_CCSH            (1 << 5)
  89 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  90 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  91 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  92
  93 /* CE_CMD_CTRL */
  94 #define CMD_CTRL_BREAK          (1 << 0)
  95
  96 /* CE_BLOCK_SET */
  97 #define BLOCK_SIZE_MASK         0x0000ffff
  98
  99 /* CE_INT */
 100 #define INT_CCSDE               (1 << 29)
 101 #define INT_CMD12DRE            (1 << 26)
 102 #define INT_CMD12RBE            (1 << 25)
 103 #define INT_CMD12CRE            (1 << 24)
 104 #define INT_DTRANE              (1 << 23)
 105 #define INT_BUFRE               (1 << 22)
 106 #define INT_BUFWEN              (1 << 21)
 107 #define INT_BUFREN              (1 << 20)
 108 #define INT_CCSRCV              (1 << 19)
 109 #define INT_RBSYE               (1 << 17)
 110 #define INT_CRSPE               (1 << 16)
 111 #define INT_CMDVIO              (1 << 15)
 112 #define INT_BUFVIO              (1 << 14)
 113 #define INT_WDATERR             (1 << 11)
 114 #define INT_RDATERR             (1 << 10)
 115 #define INT_RIDXERR             (1 << 9)
 116 #define INT_RSPERR              (1 << 8)
 117 #define INT_CCSTO               (1 << 5)
 118 #define INT_CRCSTO              (1 << 4)
 119 #define INT_WDATTO              (1 << 3)
 120 #define INT_RDATTO              (1 << 2)
 121 #define INT_RBSYTO              (1 << 1)
 122 #define INT_RSPTO               (1 << 0)
 123 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
 124                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
 125                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
 126                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
 127
 128 /* CE_INT_MASK */
 129 #define MASK_ALL                0x00000000
 130 #define MASK_MCCSDE             (1 << 29)
 131 #define MASK_MCMD12DRE          (1 << 26)
 132 #define MASK_MCMD12RBE          (1 << 25)
 133 #define MASK_MCMD12CRE          (1 << 24)
 134 #define MASK_MDTRANE            (1 << 23)
 135 #define MASK_MBUFRE             (1 << 22)
 136 #define MASK_MBUFWEN            (1 << 21)
 137 #define MASK_MBUFREN            (1 << 20)
 138 #define MASK_MCCSRCV            (1 << 19)
 139 #define MASK_MRBSYE             (1 << 17)
 140 #define MASK_MCRSPE             (1 << 16)
 141 #define MASK_MCMDVIO            (1 << 15)
 142 #define MASK_MBUFVIO            (1 << 14)
 143 #define MASK_MWDATERR           (1 << 11)
 144 #define MASK_MRDATERR           (1 << 10)
 145 #define MASK_MRIDXERR           (1 << 9)
 146 #define MASK_MRSPERR            (1 << 8)
 147 #define MASK_MCCSTO             (1 << 5)
 148 #define MASK_MCRCSTO            (1 << 4)
 149 #define MASK_MWDATTO            (1 << 3)
 150 #define MASK_MRDATTO            (1 << 2)
 151 #define MASK_MRBSYTO            (1 << 1)
 152 #define MASK_MRSPTO             (1 << 0)
 153
 154 #define MASK_START_CMD          (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
 155                                  MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
 156                                  MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
 157                                  MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
 158
 159 /* CE_HOST_STS1 */
 160 #define STS1_CMDSEQ             (1 << 31)
 161
 162 /* CE_HOST_STS2 */
 163 #define STS2_CRCSTE             (1 << 31)
 164 #define STS2_CRC16E             (1 << 30)
 165 #define STS2_AC12CRCE           (1 << 29)
 166 #define STS2_RSPCRC7E           (1 << 28)
 167 #define STS2_CRCSTEBE           (1 << 27)
 168 #define STS2_RDATEBE            (1 << 26)
 169 #define STS2_AC12REBE           (1 << 25)
 170 #define STS2_RSPEBE             (1 << 24)
 171 #define STS2_AC12IDXE           (1 << 23)
 172 #define STS2_RSPIDXE            (1 << 22)
 173 #define STS2_CCSTO              (1 << 15)
 174 #define STS2_RDATTO             (1 << 14)
 175 #define STS2_DATBSYTO           (1 << 13)
 176 #define STS2_CRCSTTO            (1 << 12)
 177 #define STS2_AC12BSYTO          (1 << 11)
 178 #define STS2_RSPBSYTO           (1 << 10)
 179 #define STS2_AC12RSPTO          (1 << 9)
 180 #define STS2_RSPTO              (1 << 8)
 181 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 182                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 183 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 184                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 185                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 186                                  STS2_AC12RSPTO | STS2_RSPTO)
 187
 188 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 189 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 190 #define CLKDEV_INIT             400000   /* 400 KHz */
 191
 192 enum mmcif_state {
 193         STATE_IDLE,
 194         STATE_REQUEST,
 195         STATE_IOS,
 196 };
 197
 198 enum mmcif_wait_for {
 199         MMCIF_WAIT_FOR_REQUEST,
 200         MMCIF_WAIT_FOR_CMD,
 201         MMCIF_WAIT_FOR_MREAD,
 202         MMCIF_WAIT_FOR_MWRITE,
 203         MMCIF_WAIT_FOR_READ,
 204         MMCIF_WAIT_FOR_WRITE,
 205         MMCIF_WAIT_FOR_READ_END,
 206         MMCIF_WAIT_FOR_WRITE_END,
 207         MMCIF_WAIT_FOR_STOP,
 208 };
 209
 210 struct sh_mmcif_host {
 211         struct mmc_host *mmc;
 212         struct mmc_request *mrq;
 213         struct platform_device *pd;
 214         struct clk *hclk;
 215         unsigned int clk;
 216         int bus_width;
 217         bool sd_error;
 218         bool dying;
 219         long timeout;
 220         void __iomem *addr;
 221         u32 *pio_ptr;
 222         spinlock_t lock;                /* protect sh_mmcif_host::state */
 223         enum mmcif_state state;
 224         enum mmcif_wait_for wait_for;
 225         struct delayed_work timeout_work;
 226         size_t blocksize;
 227         int sg_idx;
 228         int sg_blkidx;
 229         bool power;
 230         bool card_present;
 231
 232         /* DMA support */
 233         struct dma_chan         *chan_rx;
 234         struct dma_chan         *chan_tx;
 235         struct completion       dma_complete;
 236         bool                    dma_active;
 237 };
 238
 239 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 240                                         unsigned int reg, u32 val)
 241 {
 242         writel(val | readl(host->addr + reg), host->addr + reg);
 243 }
 244
 245 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 246                                         unsigned int reg, u32 val)
 247 {
 248         writel(~val & readl(host->addr + reg), host->addr + reg);
 249 }
 250
 251 static void mmcif_dma_complete(void *arg)
 252 {
 253         struct sh_mmcif_host *host = arg;
 254         struct mmc_data *data = host->mrq->data;
 255
 256         dev_dbg(&host->pd->dev, "Command completed\n");
 257
 258         if (WARN(!data, "%s: NULL data in DMA completion!\n",
 259                  dev_name(&host->pd->dev)))
 260                 return;
 261
 262         if (data->flags & MMC_DATA_READ)
 263                 dma_unmap_sg(host->chan_rx->device->dev,
 264                              data->sg, data->sg_len,
 265                              DMA_FROM_DEVICE);
 266         else
 267                 dma_unmap_sg(host->chan_tx->device->dev,
 268                              data->sg, data->sg_len,
 269                              DMA_TO_DEVICE);
 270
 271         complete(&host->dma_complete);
 272 }
 273
 274 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 275 {
 276         struct mmc_data *data = host->mrq->data;
 277         struct scatterlist *sg = data->sg;
 278         struct dma_async_tx_descriptor *desc = NULL;
 279         struct dma_chan *chan = host->chan_rx;
 280         dma_cookie_t cookie = -EINVAL;
 281         int ret;
 282
 283         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 284                          DMA_FROM_DEVICE);
 285         if (ret > 0) {
 286                 host->dma_active = true;
 287                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 288                         DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 289         }
 290
 291         if (desc) {
 292                 desc->callback = mmcif_dma_complete;
 293                 desc->callback_param = host;
 294                 cookie = dmaengine_submit(desc);
 295                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 296                 dma_async_issue_pending(chan);
 297         }
 298         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 299                 __func__, data->sg_len, ret, cookie);
 300
 301         if (!desc) {
 302                 /* DMA failed, fall back to PIO */
 303                 if (ret >= 0)
 304                         ret = -EIO;
 305                 host->chan_rx = NULL;
 306                 host->dma_active = false;
 307                 dma_release_channel(chan);
 308                 /* Free the Tx channel too */
 309                 chan = host->chan_tx;
 310                 if (chan) {
 311                         host->chan_tx = NULL;
 312                         dma_release_channel(chan);
 313                 }
 314                 dev_warn(&host->pd->dev,
 315                          "DMA failed: %d, falling back to PIO\n", ret);
 316                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 317         }
 318
 319         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 320                 desc, cookie, data->sg_len);
 321 }
 322
 323 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 324 {
 325         struct mmc_data *data = host->mrq->data;
 326         struct scatterlist *sg = data->sg;
 327         struct dma_async_tx_descriptor *desc = NULL;
 328         struct dma_chan *chan = host->chan_tx;
 329         dma_cookie_t cookie = -EINVAL;
 330         int ret;
 331
 332         ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
 333                          DMA_TO_DEVICE);
 334         if (ret > 0) {
 335                 host->dma_active = true;
 336                 desc = dmaengine_prep_slave_sg(chan, sg, ret,
 337                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 338         }
 339
 340         if (desc) {
 341                 desc->callback = mmcif_dma_complete;
 342                 desc->callback_param = host;
 343                 cookie = dmaengine_submit(desc);
 344                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 345                 dma_async_issue_pending(chan);
 346         }
 347         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 348                 __func__, data->sg_len, ret, cookie);
 349
 350         if (!desc) {
 351                 /* DMA failed, fall back to PIO */
 352                 if (ret >= 0)
 353                         ret = -EIO;
 354                 host->chan_tx = NULL;
 355                 host->dma_active = false;
 356                 dma_release_channel(chan);
 357                 /* Free the Rx channel too */
 358                 chan = host->chan_rx;
 359                 if (chan) {
 360                         host->chan_rx = NULL;
 361                         dma_release_channel(chan);
 362                 }
 363                 dev_warn(&host->pd->dev,
 364                          "DMA failed: %d, falling back to PIO\n", ret);
 365                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 366         }
 367
 368         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 369                 desc, cookie);
 370 }
 371
 372 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 373                                  struct sh_mmcif_plat_data *pdata)
 374 {
 375         struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
 376         struct dma_slave_config cfg;
 377         dma_cap_mask_t mask;
 378         int ret;
 379
 380         host->dma_active = false;
 381
 382         if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0)
 383                 return;
 384
 385         /* We can only either use DMA for both Tx and Rx or not use it at all */
 386         dma_cap_zero(mask);
 387         dma_cap_set(DMA_SLAVE, mask);
 388
 389         host->chan_tx = dma_request_channel(mask, shdma_chan_filter,
 390                                             (void *)pdata->slave_id_tx);
 391         dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 392                 host->chan_tx);
 393
 394         if (!host->chan_tx)
 395                 return;
 396
 397         cfg.slave_id = pdata->slave_id_tx;
 398         cfg.direction = DMA_MEM_TO_DEV;
 399         cfg.dst_addr = res->start + MMCIF_CE_DATA;
 400         cfg.src_addr = 0;
 401         ret = dmaengine_slave_config(host->chan_tx, &cfg);
 402         if (ret < 0)
 403                 goto ecfgtx;
 404
 405         host->chan_rx = dma_request_channel(mask, shdma_chan_filter,
 406                                             (void *)pdata->slave_id_rx);
 407         dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 408                 host->chan_rx);
 409
 410         if (!host->chan_rx)
 411                 goto erqrx;
 412
 413         cfg.slave_id = pdata->slave_id_rx;
 414         cfg.direction = DMA_DEV_TO_MEM;
 415         cfg.dst_addr = 0;
 416         cfg.src_addr = res->start + MMCIF_CE_DATA;
 417         ret = dmaengine_slave_config(host->chan_rx, &cfg);
 418         if (ret < 0)
 419                 goto ecfgrx;
 420
 421         init_completion(&host->dma_complete);
 422
 423         return;
 424
 425 ecfgrx:
 426         dma_release_channel(host->chan_rx);
 427         host->chan_rx = NULL;
 428 erqrx:
 429 ecfgtx:
 430         dma_release_channel(host->chan_tx);
 431         host->chan_tx = NULL;
 432 }
 433
 434 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 435 {
 436         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 437         /* Descriptors are freed automatically */
 438         if (host->chan_tx) {
 439                 struct dma_chan *chan = host->chan_tx;
 440                 host->chan_tx = NULL;
 441                 dma_release_channel(chan);
 442         }
 443         if (host->chan_rx) {
 444                 struct dma_chan *chan = host->chan_rx;
 445                 host->chan_rx = NULL;
 446                 dma_release_channel(chan);
 447         }
 448
 449         host->dma_active = false;
 450 }
 451
 452 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 453 {
 454         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 455
 456         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 457         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 458
 459         if (!clk)
 460                 return;
 461         if (p->sup_pclk && clk == host->clk)
 462                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 463         else
 464                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 465                                 ((fls(DIV_ROUND_UP(host->clk,
 466                                                    clk) - 1) - 1) << 16));
 467
 468         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 469 }
 470
 471 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 472 {
 473         u32 tmp;
 474
 475         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 476
 477         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 478         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 479         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 480                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 481         /* byte swap on */
 482         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 483 }
 484
 485 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 486 {
 487         u32 state1, state2;
 488         int ret, timeout;
 489
 490         host->sd_error = false;
 491
 492         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 493         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 494         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 495         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 496
 497         if (state1 & STS1_CMDSEQ) {
 498                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 499                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 500                 for (timeout = 10000000; timeout; timeout--) {
 501                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 502                               & STS1_CMDSEQ))
 503                                 break;
 504                         mdelay(1);
 505                 }
 506                 if (!timeout) {
 507                         dev_err(&host->pd->dev,
 508                                 "Forced end of command sequence timeout err\n");
 509                         return -EIO;
 510                 }
 511                 sh_mmcif_sync_reset(host);
 512                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 513                 return -EIO;
 514         }
 515
 516         if (state2 & STS2_CRC_ERR) {
 517                 dev_dbg(&host->pd->dev, ": CRC error\n");
 518                 ret = -EIO;
 519         } else if (state2 & STS2_TIMEOUT_ERR) {
 520                 dev_dbg(&host->pd->dev, ": Timeout\n");
 521                 ret = -ETIMEDOUT;
 522         } else {
 523                 dev_dbg(&host->pd->dev, ": End/Index error\n");
 524                 ret = -EIO;
 525         }
 526         return ret;
 527 }
 528
 529 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
 530 {
 531         struct mmc_data *data = host->mrq->data;
 532
 533         host->sg_blkidx += host->blocksize;
 534
 535         /* data->sg->length must be a multiple of host->blocksize? */
 536         BUG_ON(host->sg_blkidx > data->sg->length);
 537
 538         if (host->sg_blkidx == data->sg->length) {
 539                 host->sg_blkidx = 0;
 540                 if (++host->sg_idx < data->sg_len)
 541                         host->pio_ptr = sg_virt(++data->sg);
 542         } else {
 543                 host->pio_ptr = p;
 544         }
 545
 546         if (host->sg_idx == data->sg_len)
 547                 return false;
 548
 549         return true;
 550 }
 551
 552 static void sh_mmcif_single_read(struct sh_mmcif_host *host,
 553                                  struct mmc_request *mrq)
 554 {
 555         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 556                            BLOCK_SIZE_MASK) + 3;
 557
 558         host->wait_for = MMCIF_WAIT_FOR_READ;
 559         schedule_delayed_work(&host->timeout_work, host->timeout);
 560
 561         /* buf read enable */
 562         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 563 }
 564
 565 static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
 566 {
 567         struct mmc_data *data = host->mrq->data;
 568         u32 *p = sg_virt(data->sg);
 569         int i;
 570
 571         if (host->sd_error) {
 572                 data->error = sh_mmcif_error_manage(host);
 573                 return false;
 574         }
 575
 576         for (i = 0; i < host->blocksize / 4; i++)
 577                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 578
 579         /* buffer read end */
 580         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 581         host->wait_for = MMCIF_WAIT_FOR_READ_END;
 582
 583         return true;
 584 }
 585
 586 static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
 587                                 struct mmc_request *mrq)
 588 {
 589         struct mmc_data *data = mrq->data;
 590
 591         if (!data->sg_len || !data->sg->length)
 592                 return;
 593
 594         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 595                 BLOCK_SIZE_MASK;
 596
 597         host->wait_for = MMCIF_WAIT_FOR_MREAD;
 598         host->sg_idx = 0;
 599         host->sg_blkidx = 0;
 600         host->pio_ptr = sg_virt(data->sg);
 601         schedule_delayed_work(&host->timeout_work, host->timeout);
 602         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 603 }
 604
 605 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
 606 {
 607         struct mmc_data *data = host->mrq->data;
 608         u32 *p = host->pio_ptr;
 609         int i;
 610
 611         if (host->sd_error) {
 612                 data->error = sh_mmcif_error_manage(host);
 613                 return false;
 614         }
 615
 616         BUG_ON(!data->sg->length);
 617
 618         for (i = 0; i < host->blocksize / 4; i++)
 619                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 620
 621         if (!sh_mmcif_next_block(host, p))
 622                 return false;
 623
 624         schedule_delayed_work(&host->timeout_work, host->timeout);
 625         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 626
 627         return true;
 628 }
 629
 630 static void sh_mmcif_single_write(struct sh_mmcif_host *host,
 631                                         struct mmc_request *mrq)
 632 {
 633         host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 634                            BLOCK_SIZE_MASK) + 3;
 635
 636         host->wait_for = MMCIF_WAIT_FOR_WRITE;
 637         schedule_delayed_work(&host->timeout_work, host->timeout);
 638
 639         /* buf write enable */
 640         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 641 }
 642
 643 static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
 644 {
 645         struct mmc_data *data = host->mrq->data;
 646         u32 *p = sg_virt(data->sg);
 647         int i;
 648
 649         if (host->sd_error) {
 650                 data->error = sh_mmcif_error_manage(host);
 651                 return false;
 652         }
 653
 654         for (i = 0; i < host->blocksize / 4; i++)
 655                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 656
 657         /* buffer write end */
 658         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 659         host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
 660
 661         return true;
 662 }
 663
 664 static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
 665                                 struct mmc_request *mrq)
 666 {
 667         struct mmc_data *data = mrq->data;
 668
 669         if (!data->sg_len || !data->sg->length)
 670                 return;
 671
 672         host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
 673                 BLOCK_SIZE_MASK;
 674
 675         host->wait_for = MMCIF_WAIT_FOR_MWRITE;
 676         host->sg_idx = 0;
 677         host->sg_blkidx = 0;
 678         host->pio_ptr = sg_virt(data->sg);
 679         schedule_delayed_work(&host->timeout_work, host->timeout);
 680         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 681 }
 682
 683 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
 684 {
 685         struct mmc_data *data = host->mrq->data;
 686         u32 *p = host->pio_ptr;
 687         int i;
 688
 689         if (host->sd_error) {
 690                 data->error = sh_mmcif_error_manage(host);
 691                 return false;
 692         }
 693
 694         BUG_ON(!data->sg->length);
 695
 696         for (i = 0; i < host->blocksize / 4; i++)
 697                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 698
 699         if (!sh_mmcif_next_block(host, p))
 700                 return false;
 701
 702         schedule_delayed_work(&host->timeout_work, host->timeout);
 703         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 704
 705         return true;
 706 }
 707
 708 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 709                                                 struct mmc_command *cmd)
 710 {
 711         if (cmd->flags & MMC_RSP_136) {
 712                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 713                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 714                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 715                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 716         } else
 717                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 718 }
 719
 720 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 721                                                 struct mmc_command *cmd)
 722 {
 723         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 724 }
 725
 726 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 727                             struct mmc_request *mrq)
 728 {
 729         struct mmc_data *data = mrq->data;
 730         struct mmc_command *cmd = mrq->cmd;
 731         u32 opc = cmd->opcode;
 732         u32 tmp = 0;
 733
 734         /* Response Type check */
 735         switch (mmc_resp_type(cmd)) {
 736         case MMC_RSP_NONE:
 737                 tmp |= CMD_SET_RTYP_NO;
 738                 break;
 739         case MMC_RSP_R1:
 740         case MMC_RSP_R1B:
 741         case MMC_RSP_R3:
 742                 tmp |= CMD_SET_RTYP_6B;
 743                 break;
 744         case MMC_RSP_R2:
 745                 tmp |= CMD_SET_RTYP_17B;
 746                 break;
 747         default:
 748                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 749                 break;
 750         }
 751         switch (opc) {
 752         /* RBSY */
 753         case MMC_SWITCH:
 754         case MMC_STOP_TRANSMISSION:
 755         case MMC_SET_WRITE_PROT:
 756         case MMC_CLR_WRITE_PROT:
 757         case MMC_ERASE:
 758                 tmp |= CMD_SET_RBSY;
 759                 break;
 760         }
 761         /* WDAT / DATW */
 762         if (data) {
 763                 tmp |= CMD_SET_WDAT;
 764                 switch (host->bus_width) {
 765                 case MMC_BUS_WIDTH_1:
 766                         tmp |= CMD_SET_DATW_1;
 767                         break;
 768                 case MMC_BUS_WIDTH_4:
 769                         tmp |= CMD_SET_DATW_4;
 770                         break;
 771                 case MMC_BUS_WIDTH_8:
 772                         tmp |= CMD_SET_DATW_8;
 773                         break;
 774                 default:
 775                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 776                         break;
 777                 }
 778         }
 779         /* DWEN */
 780         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 781                 tmp |= CMD_SET_DWEN;
 782         /* CMLTE/CMD12EN */
 783         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 784                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 785                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 786                                 data->blocks << 16);
 787         }
 788         /* RIDXC[1:0] check bits */
 789         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 790             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 791                 tmp |= CMD_SET_RIDXC_BITS;
 792         /* RCRC7C[1:0] check bits */
 793         if (opc == MMC_SEND_OP_COND)
 794                 tmp |= CMD_SET_CRC7C_BITS;
 795         /* RCRC7C[1:0] internal CRC7 */
 796         if (opc == MMC_ALL_SEND_CID ||
 797                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 798                 tmp |= CMD_SET_CRC7C_INTERNAL;
 799
 800         return (opc << 24) | tmp;
 801 }
 802
 803 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 804                                struct mmc_request *mrq, u32 opc)
 805 {
 806         switch (opc) {
 807         case MMC_READ_MULTIPLE_BLOCK:
 808                 sh_mmcif_multi_read(host, mrq);
 809                 return 0;
 810         case MMC_WRITE_MULTIPLE_BLOCK:
 811                 sh_mmcif_multi_write(host, mrq);
 812                 return 0;
 813         case MMC_WRITE_BLOCK:
 814                 sh_mmcif_single_write(host, mrq);
 815                 return 0;
 816         case MMC_READ_SINGLE_BLOCK:
 817         case MMC_SEND_EXT_CSD:
 818                 sh_mmcif_single_read(host, mrq);
 819                 return 0;
 820         default:
 821                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 822                 return -EINVAL;
 823         }
 824 }
 825
 826 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 827                                struct mmc_request *mrq)
 828 {
 829         struct mmc_command *cmd = mrq->cmd;
 830         u32 opc = cmd->opcode;
 831         u32 mask;
 832
 833         switch (opc) {
 834         /* response busy check */
 835         case MMC_SWITCH:
 836         case MMC_STOP_TRANSMISSION:
 837         case MMC_SET_WRITE_PROT:
 838         case MMC_CLR_WRITE_PROT:
 839         case MMC_ERASE:
 840                 mask = MASK_START_CMD | MASK_MRBSYE;
 841                 break;
 842         default:
 843                 mask = MASK_START_CMD | MASK_MCRSPE;
 844                 break;
 845         }
 846
 847         if (mrq->data) {
 848                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 849                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 850                                 mrq->data->blksz);
 851         }
 852         opc = sh_mmcif_set_cmd(host, mrq);
 853
 854         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 855         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 856         /* set arg */
 857         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 858         /* set cmd */
 859         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 860
 861         host->wait_for = MMCIF_WAIT_FOR_CMD;
 862         schedule_delayed_work(&host->timeout_work, host->timeout);
 863 }
 864
 865 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 866                               struct mmc_request *mrq)
 867 {
 868         switch (mrq->cmd->opcode) {
 869         case MMC_READ_MULTIPLE_BLOCK:
 870                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 871                 break;
 872         case MMC_WRITE_MULTIPLE_BLOCK:
 873                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 874                 break;
 875         default:
 876                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 877                 mrq->stop->error = sh_mmcif_error_manage(host);
 878                 return;
 879         }
 880
 881         host->wait_for = MMCIF_WAIT_FOR_STOP;
 882         schedule_delayed_work(&host->timeout_work, host->timeout);
 883 }
 884
 885 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 886 {
 887         struct sh_mmcif_host *host = mmc_priv(mmc);
 888         unsigned long flags;
 889
 890         spin_lock_irqsave(&host->lock, flags);
 891         if (host->state != STATE_IDLE) {
 892                 spin_unlock_irqrestore(&host->lock, flags);
 893                 mrq->cmd->error = -EAGAIN;
 894                 mmc_request_done(mmc, mrq);
 895                 return;
 896         }
 897
 898         host->state = STATE_REQUEST;
 899         spin_unlock_irqrestore(&host->lock, flags);
 900
 901         switch (mrq->cmd->opcode) {
 902         /* MMCIF does not support SD/SDIO command */
 903         case SD_IO_SEND_OP_COND:
 904         case MMC_APP_CMD:
 905                 host->state = STATE_IDLE;
 906                 mrq->cmd->error = -ETIMEDOUT;
 907                 mmc_request_done(mmc, mrq);
 908                 return;
 909         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 910                 if (!mrq->data) {
 911                         /* send_if_cond cmd (not support) */
 912                         host->state = STATE_IDLE;
 913                         mrq->cmd->error = -ETIMEDOUT;
 914                         mmc_request_done(mmc, mrq);
 915                         return;
 916                 }
 917                 break;
 918         default:
 919                 break;
 920         }
 921
 922         host->mrq = mrq;
 923
 924         sh_mmcif_start_cmd(host, mrq);
 925 }
 926
 927 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 928 {
 929         struct sh_mmcif_host *host = mmc_priv(mmc);
 930         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 931         unsigned long flags;
 932
 933         spin_lock_irqsave(&host->lock, flags);
 934         if (host->state != STATE_IDLE) {
 935                 spin_unlock_irqrestore(&host->lock, flags);
 936                 return;
 937         }
 938
 939         host->state = STATE_IOS;
 940         spin_unlock_irqrestore(&host->lock, flags);
 941
 942         if (ios->power_mode == MMC_POWER_UP) {
 943                 if (!host->card_present) {
 944                         /* See if we also get DMA */
 945                         sh_mmcif_request_dma(host, host->pd->dev.platform_data);
 946                         host->card_present = true;
 947                 }
 948         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 949                 /* clock stop */
 950                 sh_mmcif_clock_control(host, 0);
 951                 if (ios->power_mode == MMC_POWER_OFF) {
 952                         if (host->card_present) {
 953                                 sh_mmcif_release_dma(host);
 954                                 host->card_present = false;
 955                         }
 956                 }
 957                 if (host->power) {
 958                         pm_runtime_put(&host->pd->dev);
 959                         host->power = false;
 960                         if (p->down_pwr && ios->power_mode == MMC_POWER_OFF)
 961                                 p->down_pwr(host->pd);
 962                 }
 963                 host->state = STATE_IDLE;
 964                 return;
 965         }
 966
 967         if (ios->clock) {
 968                 if (!host->power) {
 969                         if (p->set_pwr)
 970                                 p->set_pwr(host->pd, ios->power_mode);
 971                         pm_runtime_get_sync(&host->pd->dev);
 972                         host->power = true;
 973                         sh_mmcif_sync_reset(host);
 974                 }
 975                 sh_mmcif_clock_control(host, ios->clock);
 976         }
 977
 978         host->bus_width = ios->bus_width;
 979         host->state = STATE_IDLE;
 980 }
 981
 982 static int sh_mmcif_get_cd(struct mmc_host *mmc)
 983 {
 984         struct sh_mmcif_host *host = mmc_priv(mmc);
 985         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 986
 987         if (!p->get_cd)
 988                 return -ENOSYS;
 989         else
 990                 return p->get_cd(host->pd);
 991 }
 992
 993 static struct mmc_host_ops sh_mmcif_ops = {
 994         .request        = sh_mmcif_request,
 995         .set_ios        = sh_mmcif_set_ios,
 996         .get_cd         = sh_mmcif_get_cd,
 997 };
 998
 999 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1000 {
1001         struct mmc_command *cmd = host->mrq->cmd;
1002         struct mmc_data *data = host->mrq->data;
1003         long time;
1004
1005         if (host->sd_error) {
1006                 switch (cmd->opcode) {
1007                 case MMC_ALL_SEND_CID:
1008                 case MMC_SELECT_CARD:
1009                 case MMC_APP_CMD:
1010                         cmd->error = -ETIMEDOUT;
1011                         host->sd_error = false;
1012                         break;
1013                 default:
1014                         cmd->error = sh_mmcif_error_manage(host);
1015                         dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n",
1016                                 cmd->opcode, cmd->error);
1017                         break;
1018                 }
1019                 return false;
1020         }
1021         if (!(cmd->flags & MMC_RSP_PRESENT)) {
1022                 cmd->error = 0;
1023                 return false;
1024         }
1025
1026         sh_mmcif_get_response(host, cmd);
1027
1028         if (!data)
1029                 return false;
1030
1031         if (data->flags & MMC_DATA_READ) {
1032                 if (host->chan_rx)
1033                         sh_mmcif_start_dma_rx(host);
1034         } else {
1035                 if (host->chan_tx)
1036                         sh_mmcif_start_dma_tx(host);
1037         }
1038
1039         if (!host->dma_active) {
1040                 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
1041                 if (!data->error)
1042                         return true;
1043                 return false;
1044         }
1045
1046         /* Running in the IRQ thread, can sleep */
1047         time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1048                                                          host->timeout);
1049         if (host->sd_error) {
1050                 dev_err(host->mmc->parent,
1051                         "Error IRQ while waiting for DMA completion!\n");
1052                 /* Woken up by an error IRQ: abort DMA */
1053                 if (data->flags & MMC_DATA_READ)
1054                         dmaengine_terminate_all(host->chan_rx);
1055                 else
1056                         dmaengine_terminate_all(host->chan_tx);
1057                 data->error = sh_mmcif_error_manage(host);
1058         } else if (!time) {
1059                 data->error = -ETIMEDOUT;
1060         } else if (time < 0) {
1061                 data->error = time;
1062         }
1063         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1064                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1065         host->dma_active = false;
1066
1067         if (data->error)
1068                 data->bytes_xfered = 0;
1069
1070         return false;
1071 }
1072
1073 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1074 {
1075         struct sh_mmcif_host *host = dev_id;
1076         struct mmc_request *mrq = host->mrq;
1077         struct mmc_data *data = mrq->data;
1078
1079         cancel_delayed_work_sync(&host->timeout_work);
1080
1081         /*
1082          * All handlers return true, if processing continues, and false, if the
1083          * request has to be completed - successfully or not
1084          */
1085         switch (host->wait_for) {
1086         case MMCIF_WAIT_FOR_REQUEST:
1087                 /* We're too late, the timeout has already kicked in */
1088                 return IRQ_HANDLED;
1089         case MMCIF_WAIT_FOR_CMD:
1090                 if (sh_mmcif_end_cmd(host))
1091                         /* Wait for data */
1092                         return IRQ_HANDLED;
1093                 break;
1094         case MMCIF_WAIT_FOR_MREAD:
1095                 if (sh_mmcif_mread_block(host))
1096                         /* Wait for more data */
1097                         return IRQ_HANDLED;
1098                 break;
1099         case MMCIF_WAIT_FOR_READ:
1100                 if (sh_mmcif_read_block(host))
1101                         /* Wait for data end */
1102                         return IRQ_HANDLED;
1103                 break;
1104         case MMCIF_WAIT_FOR_MWRITE:
1105                 if (sh_mmcif_mwrite_block(host))
1106                         /* Wait data to write */
1107                         return IRQ_HANDLED;
1108                 break;
1109         case MMCIF_WAIT_FOR_WRITE:
1110                 if (sh_mmcif_write_block(host))
1111                         /* Wait for data end */
1112                         return IRQ_HANDLED;
1113                 break;
1114         case MMCIF_WAIT_FOR_STOP:
1115                 if (host->sd_error) {
1116                         mrq->stop->error = sh_mmcif_error_manage(host);
1117                         break;
1118                 }
1119                 sh_mmcif_get_cmd12response(host, mrq->stop);
1120                 mrq->stop->error = 0;
1121                 break;
1122         case MMCIF_WAIT_FOR_READ_END:
1123         case MMCIF_WAIT_FOR_WRITE_END:
1124                 if (host->sd_error)
1125                         data->error = sh_mmcif_error_manage(host);
1126                 break;
1127         default:
1128                 BUG();
1129         }
1130
1131         if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
1132                 if (!mrq->cmd->error && data && !data->error)
1133                         data->bytes_xfered =
1134                                 data->blocks * data->blksz;
1135
1136                 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1137                         sh_mmcif_stop_cmd(host, mrq);
1138                         if (!mrq->stop->error)
1139                                 return IRQ_HANDLED;
1140                 }
1141         }
1142
1143         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1144         host->state = STATE_IDLE;
1145         host->mrq = NULL;
1146         mmc_request_done(host->mmc, mrq);
1147
1148         return IRQ_HANDLED;
1149 }
1150
1151 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1152 {
1153         struct sh_mmcif_host *host = dev_id;
1154         u32 state;
1155         int err = 0;
1156
1157         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1158
1159         if (state & INT_ERR_STS) {
1160                 /* error interrupts - process first */
1161                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1162                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1163                 err = 1;
1164         } else if (state & INT_RBSYE) {
1165                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1166                                 ~(INT_RBSYE | INT_CRSPE));
1167                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
1168         } else if (state & INT_CRSPE) {
1169                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
1170                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
1171         } else if (state & INT_BUFREN) {
1172                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
1173                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
1174         } else if (state & INT_BUFWEN) {
1175                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
1176                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
1177         } else if (state & INT_CMD12DRE) {
1178                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1179                         ~(INT_CMD12DRE | INT_CMD12RBE |
1180                           INT_CMD12CRE | INT_BUFRE));
1181                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
1182         } else if (state & INT_BUFRE) {
1183                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
1184                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
1185         } else if (state & INT_DTRANE) {
1186                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
1187                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
1188         } else if (state & INT_CMD12RBE) {
1189                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
1190                                 ~(INT_CMD12RBE | INT_CMD12CRE));
1191                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
1192         } else {
1193                 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
1194                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
1195                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
1196                 err = 1;
1197         }
1198         if (err) {
1199                 host->sd_error = true;
1200                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
1201         }
1202         if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
1203                 if (!host->dma_active)
1204                         return IRQ_WAKE_THREAD;
1205                 else if (host->sd_error)
1206                         mmcif_dma_complete(host);
1207         } else {
1208                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
1209         }
1210
1211         return IRQ_HANDLED;
1212 }
1213
1214 static void mmcif_timeout_work(struct work_struct *work)
1215 {
1216         struct delayed_work *d = container_of(work, struct delayed_work, work);
1217         struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1218         struct mmc_request *mrq = host->mrq;
1219
1220         if (host->dying)
1221                 /* Don't run after mmc_remove_host() */
1222                 return;
1223
1224         /*
1225          * Handle races with cancel_delayed_work(), unless
1226          * cancel_delayed_work_sync() is used
1227          */
1228         switch (host->wait_for) {
1229         case MMCIF_WAIT_FOR_CMD:
1230                 mrq->cmd->error = sh_mmcif_error_manage(host);
1231                 break;
1232         case MMCIF_WAIT_FOR_STOP:
1233                 mrq->stop->error = sh_mmcif_error_manage(host);
1234                 break;
1235         case MMCIF_WAIT_FOR_MREAD:
1236         case MMCIF_WAIT_FOR_MWRITE:
1237         case MMCIF_WAIT_FOR_READ:
1238         case MMCIF_WAIT_FOR_WRITE:
1239         case MMCIF_WAIT_FOR_READ_END:
1240         case MMCIF_WAIT_FOR_WRITE_END:
1241                 mrq->data->error = sh_mmcif_error_manage(host);
1242                 break;
1243         default:
1244                 BUG();
1245         }
1246
1247         host->state = STATE_IDLE;
1248         host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1249         host->mrq = NULL;
1250         mmc_request_done(host->mmc, mrq);
1251 }
1252
1253 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
1254 {
1255         int ret = 0, irq[2];
1256         struct mmc_host *mmc;
1257         struct sh_mmcif_host *host;
1258         struct sh_mmcif_plat_data *pd;
1259         struct resource *res;
1260         void __iomem *reg;
1261         char clk_name[8];
1262
1263         irq[0] = platform_get_irq(pdev, 0);
1264         irq[1] = platform_get_irq(pdev, 1);
1265         if (irq[0] < 0 || irq[1] < 0) {
1266                 dev_err(&pdev->dev, "Get irq error\n");
1267                 return -ENXIO;
1268         }
1269         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1270         if (!res) {
1271                 dev_err(&pdev->dev, "platform_get_resource error.\n");
1272                 return -ENXIO;
1273         }
1274         reg = ioremap(res->start, resource_size(res));
1275         if (!reg) {
1276                 dev_err(&pdev->dev, "ioremap error.\n");
1277                 return -ENOMEM;
1278         }
1279         pd = pdev->dev.platform_data;
1280         if (!pd) {
1281                 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
1282                 ret = -ENXIO;
1283                 goto clean_up;
1284         }
1285         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
1286         if (!mmc) {
1287                 ret = -ENOMEM;
1288                 goto clean_up;
1289         }
1290         host            = mmc_priv(mmc);
1291         host->mmc       = mmc;
1292         host->addr      = reg;
1293         host->timeout   = 1000;
1294
1295         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
1296         host->hclk = clk_get(&pdev->dev, clk_name);
1297         if (IS_ERR(host->hclk)) {
1298                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
1299                 ret = PTR_ERR(host->hclk);
1300                 goto clean_up1;
1301         }
1302         clk_enable(host->hclk);
1303         host->clk = clk_get_rate(host->hclk);
1304         host->pd = pdev;
1305
1306         spin_lock_init(&host->lock);
1307
1308         mmc->ops = &sh_mmcif_ops;
1309         mmc->f_max = host->clk / 2;
1310         mmc->f_min = host->clk / 512;
1311         if (pd->ocr)
1312                 mmc->ocr_avail = pd->ocr;
1313         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1314         if (pd->caps)
1315                 mmc->caps |= pd->caps;
1316         mmc->max_segs = 32;
1317         mmc->max_blk_size = 512;
1318         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1319         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1320         mmc->max_seg_size = mmc->max_req_size;
1321
1322         sh_mmcif_sync_reset(host);
1323         platform_set_drvdata(pdev, host);
1324
1325         pm_runtime_enable(&pdev->dev);
1326         host->power = false;
1327
1328         ret = pm_runtime_resume(&pdev->dev);
1329         if (ret < 0)
1330                 goto clean_up2;
1331
1332         INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work);
1333
1334         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1335
1336         ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host);
1337         if (ret) {
1338                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1339                 goto clean_up3;
1340         }
1341         ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host);
1342         if (ret) {
1343                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1344                 goto clean_up4;
1345         }
1346
1347         ret = mmc_add_host(mmc);
1348         if (ret < 0)
1349                 goto clean_up5;
1350
1351         dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
1352
1353         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1354         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1355                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1356         return ret;
1357
1358 clean_up5:
1359         free_irq(irq[1], host);
1360 clean_up4:
1361         free_irq(irq[0], host);
1362 clean_up3:
1363         pm_runtime_suspend(&pdev->dev);
1364 clean_up2:
1365         pm_runtime_disable(&pdev->dev);
1366         clk_disable(host->hclk);
1367 clean_up1:
1368         mmc_free_host(mmc);
1369 clean_up:
1370         if (reg)
1371                 iounmap(reg);
1372         return ret;
1373 }
1374
1375 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1376 {
1377         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1378         int irq[2];
1379
1380         host->dying = true;
1381         pm_runtime_get_sync(&pdev->dev);
1382
1383         dev_pm_qos_hide_latency_limit(&pdev->dev);
1384
1385         mmc_remove_host(host->mmc);
1386         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1387
1388         /*
1389          * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1390          * mmc_remove_host() call above. But swapping order doesn't help either
1391          * (a query on the linux-mmc mailing list didn't bring any replies).
1392          */
1393         cancel_delayed_work_sync(&host->timeout_work);
1394
1395         if (host->addr)
1396                 iounmap(host->addr);
1397
1398         irq[0] = platform_get_irq(pdev, 0);
1399         irq[1] = platform_get_irq(pdev, 1);
1400
1401         free_irq(irq[0], host);
1402         free_irq(irq[1], host);
1403
1404         platform_set_drvdata(pdev, NULL);
1405
1406         clk_disable(host->hclk);
1407         mmc_free_host(host->mmc);
1408         pm_runtime_put_sync(&pdev->dev);
1409         pm_runtime_disable(&pdev->dev);
1410
1411         return 0;
1412 }
1413
1414 #ifdef CONFIG_PM
1415 static int sh_mmcif_suspend(struct device *dev)
1416 {
1417         struct platform_device *pdev = to_platform_device(dev);
1418         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1419         int ret = mmc_suspend_host(host->mmc);
1420
1421         if (!ret) {
1422                 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1423                 clk_disable(host->hclk);
1424         }
1425
1426         return ret;
1427 }
1428
1429 static int sh_mmcif_resume(struct device *dev)
1430 {
1431         struct platform_device *pdev = to_platform_device(dev);
1432         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1433
1434         clk_enable(host->hclk);
1435
1436         return mmc_resume_host(host->mmc);
1437 }
1438 #else
1439 #define sh_mmcif_suspend        NULL
1440 #define sh_mmcif_resume         NULL
1441 #endif  /* CONFIG_PM */
1442
1443 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
1444         .suspend = sh_mmcif_suspend,
1445         .resume = sh_mmcif_resume,
1446 };
1447
1448 static struct platform_driver sh_mmcif_driver = {
1449         .probe          = sh_mmcif_probe,
1450         .remove         = sh_mmcif_remove,
1451         .driver         = {
1452                 .name   = DRIVER_NAME,
1453                 .pm     = &sh_mmcif_dev_pm_ops,
1454         },
1455 };
1456
1457 module_platform_driver(sh_mmcif_driver);
1458
1459 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1460 MODULE_LICENSE("GPL");
1461 MODULE_ALIAS("platform:" DRIVER_NAME);
1462 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");