4 * Copyright (c) 2013 Texas Instruments Inc.
6 * David Griego, <dagriego@biglakesoftware.com>
7 * Dale Farnsworth, <dale@farnsworth.org>
8 * Archit Taneja, <archit@ti.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/firmware.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/videodev2.h>
27 #include "vpdma_priv.h"
29 #define VPDMA_FIRMWARE "vpdma-1b8.bin"
31 const struct vpdma_data_format vpdma_yuv_fmts[] = {
32 [VPDMA_DATA_FMT_Y444] = {
33 .data_type = DATA_TYPE_Y444,
36 [VPDMA_DATA_FMT_Y422] = {
37 .data_type = DATA_TYPE_Y422,
40 [VPDMA_DATA_FMT_Y420] = {
41 .data_type = DATA_TYPE_Y420,
44 [VPDMA_DATA_FMT_C444] = {
45 .data_type = DATA_TYPE_C444,
48 [VPDMA_DATA_FMT_C422] = {
49 .data_type = DATA_TYPE_C422,
52 [VPDMA_DATA_FMT_C420] = {
53 .data_type = DATA_TYPE_C420,
56 [VPDMA_DATA_FMT_YC422] = {
57 .data_type = DATA_TYPE_YC422,
60 [VPDMA_DATA_FMT_YC444] = {
61 .data_type = DATA_TYPE_YC444,
64 [VPDMA_DATA_FMT_CY422] = {
65 .data_type = DATA_TYPE_CY422,
70 const struct vpdma_data_format vpdma_rgb_fmts[] = {
71 [VPDMA_DATA_FMT_RGB565] = {
72 .data_type = DATA_TYPE_RGB16_565,
75 [VPDMA_DATA_FMT_ARGB16_1555] = {
76 .data_type = DATA_TYPE_ARGB_1555,
79 [VPDMA_DATA_FMT_ARGB16] = {
80 .data_type = DATA_TYPE_ARGB_4444,
83 [VPDMA_DATA_FMT_RGBA16_5551] = {
84 .data_type = DATA_TYPE_RGBA_5551,
87 [VPDMA_DATA_FMT_RGBA16] = {
88 .data_type = DATA_TYPE_RGBA_4444,
91 [VPDMA_DATA_FMT_ARGB24] = {
92 .data_type = DATA_TYPE_ARGB24_6666,
95 [VPDMA_DATA_FMT_RGB24] = {
96 .data_type = DATA_TYPE_RGB24_888,
99 [VPDMA_DATA_FMT_ARGB32] = {
100 .data_type = DATA_TYPE_ARGB32_8888,
103 [VPDMA_DATA_FMT_RGBA24] = {
104 .data_type = DATA_TYPE_RGBA24_6666,
107 [VPDMA_DATA_FMT_RGBA32] = {
108 .data_type = DATA_TYPE_RGBA32_8888,
111 [VPDMA_DATA_FMT_BGR565] = {
112 .data_type = DATA_TYPE_BGR16_565,
115 [VPDMA_DATA_FMT_ABGR16_1555] = {
116 .data_type = DATA_TYPE_ABGR_1555,
119 [VPDMA_DATA_FMT_ABGR16] = {
120 .data_type = DATA_TYPE_ABGR_4444,
123 [VPDMA_DATA_FMT_BGRA16_5551] = {
124 .data_type = DATA_TYPE_BGRA_5551,
127 [VPDMA_DATA_FMT_BGRA16] = {
128 .data_type = DATA_TYPE_BGRA_4444,
131 [VPDMA_DATA_FMT_ABGR24] = {
132 .data_type = DATA_TYPE_ABGR24_6666,
135 [VPDMA_DATA_FMT_BGR24] = {
136 .data_type = DATA_TYPE_BGR24_888,
139 [VPDMA_DATA_FMT_ABGR32] = {
140 .data_type = DATA_TYPE_ABGR32_8888,
143 [VPDMA_DATA_FMT_BGRA24] = {
144 .data_type = DATA_TYPE_BGRA24_6666,
147 [VPDMA_DATA_FMT_BGRA32] = {
148 .data_type = DATA_TYPE_BGRA32_8888,
153 const struct vpdma_data_format vpdma_misc_fmts[] = {
154 [VPDMA_DATA_FMT_MV] = {
155 .data_type = DATA_TYPE_MV,
160 struct vpdma_channel_info {
161 int num; /* VPDMA channel number */
162 int cstat_offset; /* client CSTAT register offset */
165 static const struct vpdma_channel_info chan_info[] = {
166 [VPE_CHAN_LUMA1_IN] = {
167 .num = VPE_CHAN_NUM_LUMA1_IN,
168 .cstat_offset = VPDMA_DEI_LUMA1_CSTAT,
170 [VPE_CHAN_CHROMA1_IN] = {
171 .num = VPE_CHAN_NUM_CHROMA1_IN,
172 .cstat_offset = VPDMA_DEI_CHROMA1_CSTAT,
174 [VPE_CHAN_LUMA2_IN] = {
175 .num = VPE_CHAN_NUM_LUMA2_IN,
176 .cstat_offset = VPDMA_DEI_LUMA2_CSTAT,
178 [VPE_CHAN_CHROMA2_IN] = {
179 .num = VPE_CHAN_NUM_CHROMA2_IN,
180 .cstat_offset = VPDMA_DEI_CHROMA2_CSTAT,
182 [VPE_CHAN_LUMA3_IN] = {
183 .num = VPE_CHAN_NUM_LUMA3_IN,
184 .cstat_offset = VPDMA_DEI_LUMA3_CSTAT,
186 [VPE_CHAN_CHROMA3_IN] = {
187 .num = VPE_CHAN_NUM_CHROMA3_IN,
188 .cstat_offset = VPDMA_DEI_CHROMA3_CSTAT,
191 .num = VPE_CHAN_NUM_MV_IN,
192 .cstat_offset = VPDMA_DEI_MV_IN_CSTAT,
194 [VPE_CHAN_MV_OUT] = {
195 .num = VPE_CHAN_NUM_MV_OUT,
196 .cstat_offset = VPDMA_DEI_MV_OUT_CSTAT,
198 [VPE_CHAN_LUMA_OUT] = {
199 .num = VPE_CHAN_NUM_LUMA_OUT,
200 .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
202 [VPE_CHAN_CHROMA_OUT] = {
203 .num = VPE_CHAN_NUM_CHROMA_OUT,
204 .cstat_offset = VPDMA_VIP_UP_UV_CSTAT,
206 [VPE_CHAN_RGB_OUT] = {
207 .num = VPE_CHAN_NUM_RGB_OUT,
208 .cstat_offset = VPDMA_VIP_UP_Y_CSTAT,
212 static u32 read_reg(struct vpdma_data *vpdma, int offset)
214 return ioread32(vpdma->base + offset);
217 static void write_reg(struct vpdma_data *vpdma, int offset, u32 value)
219 iowrite32(value, vpdma->base + offset);
222 static int read_field_reg(struct vpdma_data *vpdma, int offset,
225 return (read_reg(vpdma, offset) & (mask << shift)) >> shift;
228 static void write_field_reg(struct vpdma_data *vpdma, int offset, u32 field,
231 u32 val = read_reg(vpdma, offset);
233 val &= ~(mask << shift);
234 val |= (field & mask) << shift;
236 write_reg(vpdma, offset, val);
239 void vpdma_dump_regs(struct vpdma_data *vpdma)
241 struct device *dev = &vpdma->pdev->dev;
243 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r))
245 dev_dbg(dev, "VPDMA Registers:\n");
250 DUMPREG(LIST_STAT_SYNC);
259 * dumping registers of only group0 and group3, because VPE channels
260 * lie within group0 and group3 registers
262 DUMPREG(INT_CHAN_STAT(0));
263 DUMPREG(INT_CHAN_MASK(0));
264 DUMPREG(INT_CHAN_STAT(3));
265 DUMPREG(INT_CHAN_MASK(3));
266 DUMPREG(INT_CLIENT0_STAT);
267 DUMPREG(INT_CLIENT0_MASK);
268 DUMPREG(INT_CLIENT1_STAT);
269 DUMPREG(INT_CLIENT1_MASK);
270 DUMPREG(INT_LIST0_STAT);
271 DUMPREG(INT_LIST0_MASK);
274 * these are registers specific to VPE clients, we can make this
275 * function dump client registers specific to VPE or VIP based on
278 DUMPREG(DEI_CHROMA1_CSTAT);
279 DUMPREG(DEI_LUMA1_CSTAT);
280 DUMPREG(DEI_CHROMA2_CSTAT);
281 DUMPREG(DEI_LUMA2_CSTAT);
282 DUMPREG(DEI_CHROMA3_CSTAT);
283 DUMPREG(DEI_LUMA3_CSTAT);
284 DUMPREG(DEI_MV_IN_CSTAT);
285 DUMPREG(DEI_MV_OUT_CSTAT);
286 DUMPREG(VIP_UP_Y_CSTAT);
287 DUMPREG(VIP_UP_UV_CSTAT);
288 DUMPREG(VPI_CTL_CSTAT);
292 * Allocate a DMA buffer
294 int vpdma_alloc_desc_buf(struct vpdma_buf *buf, size_t size)
298 buf->addr = kzalloc(size, GFP_KERNEL);
302 WARN_ON((u32) buf->addr & VPDMA_DESC_ALIGN);
307 void vpdma_free_desc_buf(struct vpdma_buf *buf)
309 WARN_ON(buf->mapped);
316 * map descriptor/payload DMA buffer, enabling DMA access
318 int vpdma_map_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
320 struct device *dev = &vpdma->pdev->dev;
322 WARN_ON(buf->mapped);
323 buf->dma_addr = dma_map_single(dev, buf->addr, buf->size,
325 if (dma_mapping_error(dev, buf->dma_addr)) {
326 dev_err(dev, "failed to map buffer\n");
336 * unmap descriptor/payload DMA buffer, disabling DMA access and
337 * allowing the main processor to acces the data
339 void vpdma_unmap_desc_buf(struct vpdma_data *vpdma, struct vpdma_buf *buf)
341 struct device *dev = &vpdma->pdev->dev;
344 dma_unmap_single(dev, buf->dma_addr, buf->size, DMA_TO_DEVICE);
350 * create a descriptor list, the user of this list will append configuration,
351 * control and data descriptors to this list, this list will be submitted to
352 * VPDMA. VPDMA's list parser will go through each descriptor and perform the
353 * required DMA operations
355 int vpdma_create_desc_list(struct vpdma_desc_list *list, size_t size, int type)
359 r = vpdma_alloc_desc_buf(&list->buf, size);
363 list->next = list->buf.addr;
371 * once a descriptor list is parsed by VPDMA, we reset the list by emptying it,
372 * to allow new descriptors to be added to the list.
374 void vpdma_reset_desc_list(struct vpdma_desc_list *list)
376 list->next = list->buf.addr;
380 * free the buffer allocated fot the VPDMA descriptor list, this should be
381 * called when the user doesn't want to use VPDMA any more.
383 void vpdma_free_desc_list(struct vpdma_desc_list *list)
385 vpdma_free_desc_buf(&list->buf);
390 static bool vpdma_list_busy(struct vpdma_data *vpdma, int list_num)
392 return read_reg(vpdma, VPDMA_LIST_STAT_SYNC) & BIT(list_num + 16);
396 * submit a list of DMA descriptors to the VPE VPDMA, do not wait for completion
398 int vpdma_submit_descs(struct vpdma_data *vpdma, struct vpdma_desc_list *list)
400 /* we always use the first list */
404 if (vpdma_list_busy(vpdma, list_num))
407 /* 16-byte granularity */
408 list_size = (list->next - list->buf.addr) >> 4;
410 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) list->buf.dma_addr);
412 write_reg(vpdma, VPDMA_LIST_ATTR,
413 (list_num << VPDMA_LIST_NUM_SHFT) |
414 (list->type << VPDMA_LIST_TYPE_SHFT) |
420 static void dump_cfd(struct vpdma_cfd *cfd)
424 class = cfd_get_class(cfd);
426 pr_debug("config descriptor of payload class: %s\n",
427 class == CFD_CLS_BLOCK ? "simple block" :
428 "address data block");
430 if (class == CFD_CLS_BLOCK)
431 pr_debug("word0: dst_addr_offset = 0x%08x\n",
432 cfd->dest_addr_offset);
434 if (class == CFD_CLS_BLOCK)
435 pr_debug("word1: num_data_wrds = %d\n", cfd->block_len);
437 pr_debug("word2: payload_addr = 0x%08x\n", cfd->payload_addr);
439 pr_debug("word3: pkt_type = %d, direct = %d, class = %d, dest = %d, "
440 "payload_len = %d\n", cfd_get_pkt_type(cfd),
441 cfd_get_direct(cfd), class, cfd_get_dest(cfd),
442 cfd_get_payload_len(cfd));
446 * append a configuration descriptor to the given descriptor list, where the
447 * payload is in the form of a simple data block specified in the descriptor
448 * header, this is used to upload scaler coefficients to the scaler module
450 void vpdma_add_cfd_block(struct vpdma_desc_list *list, int client,
451 struct vpdma_buf *blk, u32 dest_offset)
453 struct vpdma_cfd *cfd;
456 WARN_ON(blk->dma_addr & VPDMA_DESC_ALIGN);
459 WARN_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
461 cfd->dest_addr_offset = dest_offset;
462 cfd->block_len = len;
463 cfd->payload_addr = (u32) blk->dma_addr;
464 cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_BLOCK,
467 list->next = cfd + 1;
473 * append a configuration descriptor to the given descriptor list, where the
474 * payload is in the address data block format, this is used to a configure a
475 * discontiguous set of MMRs
477 void vpdma_add_cfd_adb(struct vpdma_desc_list *list, int client,
478 struct vpdma_buf *adb)
480 struct vpdma_cfd *cfd;
481 unsigned int len = adb->size;
483 WARN_ON(len & VPDMA_ADB_SIZE_ALIGN);
484 WARN_ON(adb->dma_addr & VPDMA_DESC_ALIGN);
487 BUG_ON((void *)(cfd + 1) > (list->buf.addr + list->buf.size));
491 cfd->payload_addr = (u32) adb->dma_addr;
492 cfd->ctl_payload_len = cfd_pkt_payload_len(CFD_INDIRECT, CFD_CLS_ADB,
495 list->next = cfd + 1;
501 * control descriptor format change based on what type of control descriptor it
502 * is, we only use 'sync on channel' control descriptors for now, so assume it's
505 static void dump_ctd(struct vpdma_ctd *ctd)
507 pr_debug("control descriptor\n");
509 pr_debug("word3: pkt_type = %d, source = %d, ctl_type = %d\n",
510 ctd_get_pkt_type(ctd), ctd_get_source(ctd), ctd_get_ctl(ctd));
514 * append a 'sync on channel' type control descriptor to the given descriptor
515 * list, this descriptor stalls the VPDMA list till the time DMA is completed
516 * on the specified channel
518 void vpdma_add_sync_on_channel_ctd(struct vpdma_desc_list *list,
519 enum vpdma_channel chan)
521 struct vpdma_ctd *ctd;
524 WARN_ON((void *)(ctd + 1) > (list->buf.addr + list->buf.size));
529 ctd->type_source_ctl = ctd_type_source_ctl(chan_info[chan].num,
530 CTD_TYPE_SYNC_ON_CHANNEL);
532 list->next = ctd + 1;
537 static void dump_dtd(struct vpdma_dtd *dtd)
541 dir = dtd_get_dir(dtd);
542 chan = dtd_get_chan(dtd);
544 pr_debug("%s data transfer descriptor for channel %d\n",
545 dir == DTD_DIR_OUT ? "outbound" : "inbound", chan);
547 pr_debug("word0: data_type = %d, notify = %d, field = %d, 1D = %d, "
548 "even_ln_skp = %d, odd_ln_skp = %d, line_stride = %d\n",
549 dtd_get_data_type(dtd), dtd_get_notify(dtd), dtd_get_field(dtd),
550 dtd_get_1d(dtd), dtd_get_even_line_skip(dtd),
551 dtd_get_odd_line_skip(dtd), dtd_get_line_stride(dtd));
553 if (dir == DTD_DIR_IN)
554 pr_debug("word1: line_length = %d, xfer_height = %d\n",
555 dtd_get_line_length(dtd), dtd_get_xfer_height(dtd));
557 pr_debug("word2: start_addr = 0x%08x\n", dtd->start_addr);
559 pr_debug("word3: pkt_type = %d, mode = %d, dir = %d, chan = %d, "
560 "pri = %d, next_chan = %d\n", dtd_get_pkt_type(dtd),
561 dtd_get_mode(dtd), dir, chan, dtd_get_priority(dtd),
562 dtd_get_next_chan(dtd));
564 if (dir == DTD_DIR_IN)
565 pr_debug("word4: frame_width = %d, frame_height = %d\n",
566 dtd_get_frame_width(dtd), dtd_get_frame_height(dtd));
568 pr_debug("word4: desc_write_addr = 0x%08x, write_desc = %d, "
569 "drp_data = %d, use_desc_reg = %d\n",
570 dtd_get_desc_write_addr(dtd), dtd_get_write_desc(dtd),
571 dtd_get_drop_data(dtd), dtd_get_use_desc(dtd));
573 if (dir == DTD_DIR_IN)
574 pr_debug("word5: hor_start = %d, ver_start = %d\n",
575 dtd_get_h_start(dtd), dtd_get_v_start(dtd));
577 pr_debug("word5: max_width %d, max_height %d\n",
578 dtd_get_max_width(dtd), dtd_get_max_height(dtd));
580 pr_debug("word6: client specific attr0 = 0x%08x\n", dtd->client_attr0);
581 pr_debug("word7: client specific attr1 = 0x%08x\n", dtd->client_attr1);
585 * append an outbound data transfer descriptor to the given descriptor list,
586 * this sets up a 'client to memory' VPDMA transfer for the given VPDMA channel
588 void vpdma_add_out_dtd(struct vpdma_desc_list *list, struct v4l2_rect *c_rect,
589 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
590 enum vpdma_channel chan, u32 flags)
595 int channel, next_chan;
596 int depth = fmt->depth;
598 struct vpdma_dtd *dtd;
600 channel = next_chan = chan_info[chan].num;
602 if (fmt->data_type == DATA_TYPE_C420)
605 stride = (depth * c_rect->width) >> 3;
606 dma_addr += (c_rect->left * depth) >> 3;
609 WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
611 dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
614 !!(flags & VPDMA_DATA_FRAME_1D),
615 !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
616 !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
619 dtd->start_addr = (u32) dma_addr;
620 dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
621 DTD_DIR_OUT, channel, priority, next_chan);
622 dtd->desc_write_addr = dtd_desc_write_addr(0, 0, 0, 0);
623 dtd->max_width_height = dtd_max_width_height(MAX_OUT_WIDTH_1920,
624 MAX_OUT_HEIGHT_1080);
625 dtd->client_attr0 = 0;
626 dtd->client_attr1 = 0;
628 list->next = dtd + 1;
634 * append an inbound data transfer descriptor to the given descriptor list,
635 * this sets up a 'memory to client' VPDMA transfer for the given VPDMA channel
637 void vpdma_add_in_dtd(struct vpdma_desc_list *list, int frame_width,
638 int frame_height, struct v4l2_rect *c_rect,
639 const struct vpdma_data_format *fmt, dma_addr_t dma_addr,
640 enum vpdma_channel chan, int field, u32 flags)
644 int depth = fmt->depth;
645 int channel, next_chan;
647 int height = c_rect->height;
648 struct vpdma_dtd *dtd;
650 channel = next_chan = chan_info[chan].num;
652 if (fmt->data_type == DATA_TYPE_C420) {
658 stride = (depth * c_rect->width) >> 3;
659 dma_addr += (c_rect->left * depth) >> 3;
662 WARN_ON((void *)(dtd + 1) > (list->buf.addr + list->buf.size));
664 dtd->type_ctl_stride = dtd_type_ctl_stride(fmt->data_type,
667 !!(flags & VPDMA_DATA_FRAME_1D),
668 !!(flags & VPDMA_DATA_EVEN_LINE_SKIP),
669 !!(flags & VPDMA_DATA_ODD_LINE_SKIP),
672 dtd->xfer_length_height = dtd_xfer_length_height(c_rect->width, height);
673 dtd->start_addr = (u32) dma_addr;
674 dtd->pkt_ctl = dtd_pkt_ctl(!!(flags & VPDMA_DATA_MODE_TILED),
675 DTD_DIR_IN, channel, priority, next_chan);
676 dtd->frame_width_height = dtd_frame_width_height(frame_width,
678 dtd->start_h_v = dtd_start_h_v(c_rect->left, c_rect->top);
679 dtd->client_attr0 = 0;
680 dtd->client_attr1 = 0;
682 list->next = dtd + 1;
687 /* set or clear the mask for list complete interrupt */
688 void vpdma_enable_list_complete_irq(struct vpdma_data *vpdma, int list_num,
693 val = read_reg(vpdma, VPDMA_INT_LIST0_MASK);
695 val |= (1 << (list_num * 2));
697 val &= ~(1 << (list_num * 2));
698 write_reg(vpdma, VPDMA_INT_LIST0_MASK, val);
701 /* clear previosuly occured list intterupts in the LIST_STAT register */
702 void vpdma_clear_list_stat(struct vpdma_data *vpdma)
704 write_reg(vpdma, VPDMA_INT_LIST0_STAT,
705 read_reg(vpdma, VPDMA_INT_LIST0_STAT));
709 * configures the output mode of the line buffer for the given client, the
710 * line buffer content can either be mirrored(each line repeated twice) or
711 * passed to the client as is
713 void vpdma_set_line_mode(struct vpdma_data *vpdma, int line_mode,
714 enum vpdma_channel chan)
716 int client_cstat = chan_info[chan].cstat_offset;
718 write_field_reg(vpdma, client_cstat, line_mode,
719 VPDMA_CSTAT_LINE_MODE_MASK, VPDMA_CSTAT_LINE_MODE_SHIFT);
723 * configures the event which should trigger VPDMA transfer for the given
726 void vpdma_set_frame_start_event(struct vpdma_data *vpdma,
727 enum vpdma_frame_start_event fs_event,
728 enum vpdma_channel chan)
730 int client_cstat = chan_info[chan].cstat_offset;
732 write_field_reg(vpdma, client_cstat, fs_event,
733 VPDMA_CSTAT_FRAME_START_MASK, VPDMA_CSTAT_FRAME_START_SHIFT);
736 static void vpdma_firmware_cb(const struct firmware *f, void *context)
738 struct vpdma_data *vpdma = context;
739 struct vpdma_buf fw_dma_buf;
742 dev_dbg(&vpdma->pdev->dev, "firmware callback\n");
744 if (!f || !f->data) {
745 dev_err(&vpdma->pdev->dev, "couldn't get firmware\n");
749 /* already initialized */
750 if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
751 VPDMA_LIST_RDY_SHFT)) {
756 r = vpdma_alloc_desc_buf(&fw_dma_buf, f->size);
758 dev_err(&vpdma->pdev->dev,
759 "failed to allocate dma buffer for firmware\n");
763 memcpy(fw_dma_buf.addr, f->data, f->size);
765 vpdma_map_desc_buf(vpdma, &fw_dma_buf);
767 write_reg(vpdma, VPDMA_LIST_ADDR, (u32) fw_dma_buf.dma_addr);
769 for (i = 0; i < 100; i++) { /* max 1 second */
770 msleep_interruptible(10);
772 if (read_field_reg(vpdma, VPDMA_LIST_ATTR, VPDMA_LIST_RDY_MASK,
773 VPDMA_LIST_RDY_SHFT))
778 dev_err(&vpdma->pdev->dev, "firmware upload failed\n");
785 vpdma_unmap_desc_buf(vpdma, &fw_dma_buf);
787 vpdma_free_desc_buf(&fw_dma_buf);
792 static int vpdma_load_firmware(struct vpdma_data *vpdma)
795 struct device *dev = &vpdma->pdev->dev;
797 r = request_firmware_nowait(THIS_MODULE, 1,
798 (const char *) VPDMA_FIRMWARE, dev, GFP_KERNEL, vpdma,
801 dev_err(dev, "firmware not available %s\n", VPDMA_FIRMWARE);
804 dev_info(dev, "loading firmware %s\n", VPDMA_FIRMWARE);
810 struct vpdma_data *vpdma_create(struct platform_device *pdev)
812 struct resource *res;
813 struct vpdma_data *vpdma;
816 dev_dbg(&pdev->dev, "vpdma_create\n");
818 vpdma = devm_kzalloc(&pdev->dev, sizeof(*vpdma), GFP_KERNEL);
820 dev_err(&pdev->dev, "couldn't alloc vpdma_dev\n");
821 return ERR_PTR(-ENOMEM);
826 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpdma");
828 dev_err(&pdev->dev, "missing platform resources data\n");
829 return ERR_PTR(-ENODEV);
832 vpdma->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
834 dev_err(&pdev->dev, "failed to ioremap\n");
835 return ERR_PTR(-ENOMEM);
838 r = vpdma_load_firmware(vpdma);
840 pr_err("failed to load firmware %s\n", VPDMA_FIRMWARE);
846 MODULE_FIRMWARE(VPDMA_FIRMWARE);