Pileus Git - ~andy/linux/blob - drivers/iommu/arm-smmu.c

   1 /*
   2  * IOMMU API for ARM architected SMMU implementations.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16  *
  17  * Copyright (C) 2013 ARM Limited
  18  *
  19  * Author: Will Deacon <will.deacon@arm.com>
  20  *
  21  * This driver currently supports:
  22  *      - SMMUv1 and v2 implementations
  23  *      - Stream-matching and stream-indexing
  24  *      - v7/v8 long-descriptor format
  25  *      - Non-secure access to the SMMU
  26  *      - 4k and 64k pages, with contiguous pte hints.
  27  *      - Up to 39-bit addressing
  28  *      - Context fault reporting
  29  */
  30
  31 #define pr_fmt(fmt) "arm-smmu: " fmt
  32
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/err.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/io.h>
  38 #include <linux/iommu.h>
  39 #include <linux/mm.h>
  40 #include <linux/module.h>
  41 #include <linux/of.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/slab.h>
  44 #include <linux/spinlock.h>
  45
  46 #include <linux/amba/bus.h>
  47
  48 #include <asm/pgalloc.h>
  49
  50 /* Maximum number of stream IDs assigned to a single device */
  51 #define MAX_MASTER_STREAMIDS            8
  52
  53 /* Maximum number of context banks per SMMU */
  54 #define ARM_SMMU_MAX_CBS                128
  55
  56 /* Maximum number of mapping groups per SMMU */
  57 #define ARM_SMMU_MAX_SMRS               128
  58
  59 /* Number of VMIDs per SMMU */
  60 #define ARM_SMMU_NUM_VMIDS              256
  61
  62 /* SMMU global address space */
  63 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
  64 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
  65
  66 /* Page table bits */
  67 #define ARM_SMMU_PTE_PAGE               (((pteval_t)3) << 0)
  68 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
  69 #define ARM_SMMU_PTE_AF                 (((pteval_t)1) << 10)
  70 #define ARM_SMMU_PTE_SH_NS              (((pteval_t)0) << 8)
  71 #define ARM_SMMU_PTE_SH_OS              (((pteval_t)2) << 8)
  72 #define ARM_SMMU_PTE_SH_IS              (((pteval_t)3) << 8)
  73
  74 #if PAGE_SIZE == SZ_4K
  75 #define ARM_SMMU_PTE_CONT_ENTRIES       16
  76 #elif PAGE_SIZE == SZ_64K
  77 #define ARM_SMMU_PTE_CONT_ENTRIES       32
  78 #else
  79 #define ARM_SMMU_PTE_CONT_ENTRIES       1
  80 #endif
  81
  82 #define ARM_SMMU_PTE_CONT_SIZE          (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
  83 #define ARM_SMMU_PTE_CONT_MASK          (~(ARM_SMMU_PTE_CONT_SIZE - 1))
  84 #define ARM_SMMU_PTE_HWTABLE_SIZE       (PTRS_PER_PTE * sizeof(pte_t))
  85
  86 /* Stage-1 PTE */
  87 #define ARM_SMMU_PTE_AP_UNPRIV          (((pteval_t)1) << 6)
  88 #define ARM_SMMU_PTE_AP_RDONLY          (((pteval_t)2) << 6)
  89 #define ARM_SMMU_PTE_ATTRINDX_SHIFT     2
  90
  91 /* Stage-2 PTE */
  92 #define ARM_SMMU_PTE_HAP_FAULT          (((pteval_t)0) << 6)
  93 #define ARM_SMMU_PTE_HAP_READ           (((pteval_t)1) << 6)
  94 #define ARM_SMMU_PTE_HAP_WRITE          (((pteval_t)2) << 6)
  95 #define ARM_SMMU_PTE_MEMATTR_OIWB       (((pteval_t)0xf) << 2)
  96 #define ARM_SMMU_PTE_MEMATTR_NC         (((pteval_t)0x5) << 2)
  97 #define ARM_SMMU_PTE_MEMATTR_DEV        (((pteval_t)0x1) << 2)
  98
  99 /* Configuration registers */
 100 #define ARM_SMMU_GR0_sCR0               0x0
 101 #define sCR0_CLIENTPD                   (1 << 0)
 102 #define sCR0_GFRE                       (1 << 1)
 103 #define sCR0_GFIE                       (1 << 2)
 104 #define sCR0_GCFGFRE                    (1 << 4)
 105 #define sCR0_GCFGFIE                    (1 << 5)
 106 #define sCR0_USFCFG                     (1 << 10)
 107 #define sCR0_VMIDPNE                    (1 << 11)
 108 #define sCR0_PTM                        (1 << 12)
 109 #define sCR0_FB                         (1 << 13)
 110 #define sCR0_BSU_SHIFT                  14
 111 #define sCR0_BSU_MASK                   0x3
 112
 113 /* Identification registers */
 114 #define ARM_SMMU_GR0_ID0                0x20
 115 #define ARM_SMMU_GR0_ID1                0x24
 116 #define ARM_SMMU_GR0_ID2                0x28
 117 #define ARM_SMMU_GR0_ID3                0x2c
 118 #define ARM_SMMU_GR0_ID4                0x30
 119 #define ARM_SMMU_GR0_ID5                0x34
 120 #define ARM_SMMU_GR0_ID6                0x38
 121 #define ARM_SMMU_GR0_ID7                0x3c
 122 #define ARM_SMMU_GR0_sGFSR              0x48
 123 #define ARM_SMMU_GR0_sGFSYNR0           0x50
 124 #define ARM_SMMU_GR0_sGFSYNR1           0x54
 125 #define ARM_SMMU_GR0_sGFSYNR2           0x58
 126 #define ARM_SMMU_GR0_PIDR0              0xfe0
 127 #define ARM_SMMU_GR0_PIDR1              0xfe4
 128 #define ARM_SMMU_GR0_PIDR2              0xfe8
 129
 130 #define ID0_S1TS                        (1 << 30)
 131 #define ID0_S2TS                        (1 << 29)
 132 #define ID0_NTS                         (1 << 28)
 133 #define ID0_SMS                         (1 << 27)
 134 #define ID0_PTFS_SHIFT                  24
 135 #define ID0_PTFS_MASK                   0x2
 136 #define ID0_PTFS_V8_ONLY                0x2
 137 #define ID0_CTTW                        (1 << 14)
 138 #define ID0_NUMIRPT_SHIFT               16
 139 #define ID0_NUMIRPT_MASK                0xff
 140 #define ID0_NUMSMRG_SHIFT               0
 141 #define ID0_NUMSMRG_MASK                0xff
 142
 143 #define ID1_PAGESIZE                    (1 << 31)
 144 #define ID1_NUMPAGENDXB_SHIFT           28
 145 #define ID1_NUMPAGENDXB_MASK            7
 146 #define ID1_NUMS2CB_SHIFT               16
 147 #define ID1_NUMS2CB_MASK                0xff
 148 #define ID1_NUMCB_SHIFT                 0
 149 #define ID1_NUMCB_MASK                  0xff
 150
 151 #define ID2_OAS_SHIFT                   4
 152 #define ID2_OAS_MASK                    0xf
 153 #define ID2_IAS_SHIFT                   0
 154 #define ID2_IAS_MASK                    0xf
 155 #define ID2_UBS_SHIFT                   8
 156 #define ID2_UBS_MASK                    0xf
 157 #define ID2_PTFS_4K                     (1 << 12)
 158 #define ID2_PTFS_16K                    (1 << 13)
 159 #define ID2_PTFS_64K                    (1 << 14)
 160
 161 #define PIDR2_ARCH_SHIFT                4
 162 #define PIDR2_ARCH_MASK                 0xf
 163
 164 /* Global TLB invalidation */
 165 #define ARM_SMMU_GR0_STLBIALL           0x60
 166 #define ARM_SMMU_GR0_TLBIVMID           0x64
 167 #define ARM_SMMU_GR0_TLBIALLNSNH        0x68
 168 #define ARM_SMMU_GR0_TLBIALLH           0x6c
 169 #define ARM_SMMU_GR0_sTLBGSYNC          0x70
 170 #define ARM_SMMU_GR0_sTLBGSTATUS        0x74
 171 #define sTLBGSTATUS_GSACTIVE            (1 << 0)
 172 #define TLB_LOOP_TIMEOUT                1000000 /* 1s! */
 173
 174 /* Stream mapping registers */
 175 #define ARM_SMMU_GR0_SMR(n)             (0x800 + ((n) << 2))
 176 #define SMR_VALID                       (1 << 31)
 177 #define SMR_MASK_SHIFT                  16
 178 #define SMR_MASK_MASK                   0x7fff
 179 #define SMR_ID_SHIFT                    0
 180 #define SMR_ID_MASK                     0x7fff
 181
 182 #define ARM_SMMU_GR0_S2CR(n)            (0xc00 + ((n) << 2))
 183 #define S2CR_CBNDX_SHIFT                0
 184 #define S2CR_CBNDX_MASK                 0xff
 185 #define S2CR_TYPE_SHIFT                 16
 186 #define S2CR_TYPE_MASK                  0x3
 187 #define S2CR_TYPE_TRANS                 (0 << S2CR_TYPE_SHIFT)
 188 #define S2CR_TYPE_BYPASS                (1 << S2CR_TYPE_SHIFT)
 189 #define S2CR_TYPE_FAULT                 (2 << S2CR_TYPE_SHIFT)
 190
 191 /* Context bank attribute registers */
 192 #define ARM_SMMU_GR1_CBAR(n)            (0x0 + ((n) << 2))
 193 #define CBAR_VMID_SHIFT                 0
 194 #define CBAR_VMID_MASK                  0xff
 195 #define CBAR_S1_MEMATTR_SHIFT           12
 196 #define CBAR_S1_MEMATTR_MASK            0xf
 197 #define CBAR_S1_MEMATTR_WB              0xf
 198 #define CBAR_TYPE_SHIFT                 16
 199 #define CBAR_TYPE_MASK                  0x3
 200 #define CBAR_TYPE_S2_TRANS              (0 << CBAR_TYPE_SHIFT)
 201 #define CBAR_TYPE_S1_TRANS_S2_BYPASS    (1 << CBAR_TYPE_SHIFT)
 202 #define CBAR_TYPE_S1_TRANS_S2_FAULT     (2 << CBAR_TYPE_SHIFT)
 203 #define CBAR_TYPE_S1_TRANS_S2_TRANS     (3 << CBAR_TYPE_SHIFT)
 204 #define CBAR_IRPTNDX_SHIFT              24
 205 #define CBAR_IRPTNDX_MASK               0xff
 206
 207 #define ARM_SMMU_GR1_CBA2R(n)           (0x800 + ((n) << 2))
 208 #define CBA2R_RW64_32BIT                (0 << 0)
 209 #define CBA2R_RW64_64BIT                (1 << 0)
 210
 211 /* Translation context bank */
 212 #define ARM_SMMU_CB_BASE(smmu)          ((smmu)->base + ((smmu)->size >> 1))
 213 #define ARM_SMMU_CB(smmu, n)            ((n) * (smmu)->pagesize)
 214
 215 #define ARM_SMMU_CB_SCTLR               0x0
 216 #define ARM_SMMU_CB_RESUME              0x8
 217 #define ARM_SMMU_CB_TTBCR2              0x10
 218 #define ARM_SMMU_CB_TTBR0_LO            0x20
 219 #define ARM_SMMU_CB_TTBR0_HI            0x24
 220 #define ARM_SMMU_CB_TTBCR               0x30
 221 #define ARM_SMMU_CB_S1_MAIR0            0x38
 222 #define ARM_SMMU_CB_FSR                 0x58
 223 #define ARM_SMMU_CB_FAR_LO              0x60
 224 #define ARM_SMMU_CB_FAR_HI              0x64
 225 #define ARM_SMMU_CB_FSYNR0              0x68
 226
 227 #define SCTLR_S1_ASIDPNE                (1 << 12)
 228 #define SCTLR_CFCFG                     (1 << 7)
 229 #define SCTLR_CFIE                      (1 << 6)
 230 #define SCTLR_CFRE                      (1 << 5)
 231 #define SCTLR_E                         (1 << 4)
 232 #define SCTLR_AFE                       (1 << 2)
 233 #define SCTLR_TRE                       (1 << 1)
 234 #define SCTLR_M                         (1 << 0)
 235 #define SCTLR_EAE_SBOP                  (SCTLR_AFE | SCTLR_TRE)
 236
 237 #define RESUME_RETRY                    (0 << 0)
 238 #define RESUME_TERMINATE                (1 << 0)
 239
 240 #define TTBCR_EAE                       (1 << 31)
 241
 242 #define TTBCR_PASIZE_SHIFT              16
 243 #define TTBCR_PASIZE_MASK               0x7
 244
 245 #define TTBCR_TG0_4K                    (0 << 14)
 246 #define TTBCR_TG0_64K                   (1 << 14)
 247
 248 #define TTBCR_SH0_SHIFT                 12
 249 #define TTBCR_SH0_MASK                  0x3
 250 #define TTBCR_SH_NS                     0
 251 #define TTBCR_SH_OS                     2
 252 #define TTBCR_SH_IS                     3
 253
 254 #define TTBCR_ORGN0_SHIFT               10
 255 #define TTBCR_IRGN0_SHIFT               8
 256 #define TTBCR_RGN_MASK                  0x3
 257 #define TTBCR_RGN_NC                    0
 258 #define TTBCR_RGN_WBWA                  1
 259 #define TTBCR_RGN_WT                    2
 260 #define TTBCR_RGN_WB                    3
 261
 262 #define TTBCR_SL0_SHIFT                 6
 263 #define TTBCR_SL0_MASK                  0x3
 264 #define TTBCR_SL0_LVL_2                 0
 265 #define TTBCR_SL0_LVL_1                 1
 266
 267 #define TTBCR_T1SZ_SHIFT                16
 268 #define TTBCR_T0SZ_SHIFT                0
 269 #define TTBCR_SZ_MASK                   0xf
 270
 271 #define TTBCR2_SEP_SHIFT                15
 272 #define TTBCR2_SEP_MASK                 0x7
 273
 274 #define TTBCR2_PASIZE_SHIFT             0
 275 #define TTBCR2_PASIZE_MASK              0x7
 276
 277 /* Common definitions for PASize and SEP fields */
 278 #define TTBCR2_ADDR_32                  0
 279 #define TTBCR2_ADDR_36                  1
 280 #define TTBCR2_ADDR_40                  2
 281 #define TTBCR2_ADDR_42                  3
 282 #define TTBCR2_ADDR_44                  4
 283 #define TTBCR2_ADDR_48                  5
 284
 285 #define MAIR_ATTR_SHIFT(n)              ((n) << 3)
 286 #define MAIR_ATTR_MASK                  0xff
 287 #define MAIR_ATTR_DEVICE                0x04
 288 #define MAIR_ATTR_NC                    0x44
 289 #define MAIR_ATTR_WBRWA                 0xff
 290 #define MAIR_ATTR_IDX_NC                0
 291 #define MAIR_ATTR_IDX_CACHE             1
 292 #define MAIR_ATTR_IDX_DEV               2
 293
 294 #define FSR_MULTI                       (1 << 31)
 295 #define FSR_SS                          (1 << 30)
 296 #define FSR_UUT                         (1 << 8)
 297 #define FSR_ASF                         (1 << 7)
 298 #define FSR_TLBLKF                      (1 << 6)
 299 #define FSR_TLBMCF                      (1 << 5)
 300 #define FSR_EF                          (1 << 4)
 301 #define FSR_PF                          (1 << 3)
 302 #define FSR_AFF                         (1 << 2)
 303 #define FSR_TF                          (1 << 1)
 304
 305 #define FSR_IGN                         (FSR_AFF | FSR_ASF | FSR_TLBMCF |       \
 306                                          FSR_TLBLKF)
 307 #define FSR_FAULT                       (FSR_MULTI | FSR_SS | FSR_UUT |         \
 308                                          FSR_EF | FSR_PF | FSR_TF)
 309
 310 #define FSYNR0_WNR                      (1 << 4)
 311
 312 struct arm_smmu_smr {
 313         u8                              idx;
 314         u16                             mask;
 315         u16                             id;
 316 };
 317
 318 struct arm_smmu_master {
 319         struct device_node              *of_node;
 320
 321         /*
 322          * The following is specific to the master's position in the
 323          * SMMU chain.
 324          */
 325         struct rb_node                  node;
 326         int                             num_streamids;
 327         u16                             streamids[MAX_MASTER_STREAMIDS];
 328
 329         /*
 330          * We only need to allocate these on the root SMMU, as we
 331          * configure unmatched streams to bypass translation.
 332          */
 333         struct arm_smmu_smr             *smrs;
 334 };
 335
 336 struct arm_smmu_device {
 337         struct device                   *dev;
 338         struct device_node              *parent_of_node;
 339
 340         void __iomem                    *base;
 341         unsigned long                   size;
 342         unsigned long                   pagesize;
 343
 344 #define ARM_SMMU_FEAT_COHERENT_WALK     (1 << 0)
 345 #define ARM_SMMU_FEAT_STREAM_MATCH      (1 << 1)
 346 #define ARM_SMMU_FEAT_TRANS_S1          (1 << 2)
 347 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 348 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
 349         u32                             features;
 350         int                             version;
 351
 352         u32                             num_context_banks;
 353         u32                             num_s2_context_banks;
 354         DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
 355         atomic_t                        irptndx;
 356
 357         u32                             num_mapping_groups;
 358         DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
 359
 360         unsigned long                   input_size;
 361         unsigned long                   s1_output_size;
 362         unsigned long                   s2_output_size;
 363
 364         u32                             num_global_irqs;
 365         u32                             num_context_irqs;
 366         unsigned int                    *irqs;
 367
 368         DECLARE_BITMAP(vmid_map, ARM_SMMU_NUM_VMIDS);
 369
 370         struct list_head                list;
 371         struct rb_root                  masters;
 372 };
 373
 374 struct arm_smmu_cfg {
 375         struct arm_smmu_device          *smmu;
 376         u8                              vmid;
 377         u8                              cbndx;
 378         u8                              irptndx;
 379         u32                             cbar;
 380         pgd_t                           *pgd;
 381 };
 382
 383 struct arm_smmu_domain {
 384         /*
 385          * A domain can span across multiple, chained SMMUs and requires
 386          * all devices within the domain to follow the same translation
 387          * path.
 388          */
 389         struct arm_smmu_device          *leaf_smmu;
 390         struct arm_smmu_cfg             root_cfg;
 391         phys_addr_t                     output_mask;
 392
 393         spinlock_t                      lock;
 394 };
 395
 396 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 397 static LIST_HEAD(arm_smmu_devices);
 398
 399 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
 400                                                 struct device_node *dev_node)
 401 {
 402         struct rb_node *node = smmu->masters.rb_node;
 403
 404         while (node) {
 405                 struct arm_smmu_master *master;
 406                 master = container_of(node, struct arm_smmu_master, node);
 407
 408                 if (dev_node < master->of_node)
 409                         node = node->rb_left;
 410                 else if (dev_node > master->of_node)
 411                         node = node->rb_right;
 412                 else
 413                         return master;
 414         }
 415
 416         return NULL;
 417 }
 418
 419 static int insert_smmu_master(struct arm_smmu_device *smmu,
 420                               struct arm_smmu_master *master)
 421 {
 422         struct rb_node **new, *parent;
 423
 424         new = &smmu->masters.rb_node;
 425         parent = NULL;
 426         while (*new) {
 427                 struct arm_smmu_master *this;
 428                 this = container_of(*new, struct arm_smmu_master, node);
 429
 430                 parent = *new;
 431                 if (master->of_node < this->of_node)
 432                         new = &((*new)->rb_left);
 433                 else if (master->of_node > this->of_node)
 434                         new = &((*new)->rb_right);
 435                 else
 436                         return -EEXIST;
 437         }
 438
 439         rb_link_node(&master->node, parent, new);
 440         rb_insert_color(&master->node, &smmu->masters);
 441         return 0;
 442 }
 443
 444 static int register_smmu_master(struct arm_smmu_device *smmu,
 445                                 struct device *dev,
 446                                 struct of_phandle_args *masterspec)
 447 {
 448         int i;
 449         struct arm_smmu_master *master;
 450
 451         master = find_smmu_master(smmu, masterspec->np);
 452         if (master) {
 453                 dev_err(dev,
 454                         "rejecting multiple registrations for master device %s\n",
 455                         masterspec->np->name);
 456                 return -EBUSY;
 457         }
 458
 459         if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
 460                 dev_err(dev,
 461                         "reached maximum number (%d) of stream IDs for master device %s\n",
 462                         MAX_MASTER_STREAMIDS, masterspec->np->name);
 463                 return -ENOSPC;
 464         }
 465
 466         master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
 467         if (!master)
 468                 return -ENOMEM;
 469
 470         master->of_node         = masterspec->np;
 471         master->num_streamids   = masterspec->args_count;
 472
 473         for (i = 0; i < master->num_streamids; ++i)
 474                 master->streamids[i] = masterspec->args[i];
 475
 476         return insert_smmu_master(smmu, master);
 477 }
 478
 479 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
 480 {
 481         struct arm_smmu_device *parent;
 482
 483         if (!smmu->parent_of_node)
 484                 return NULL;
 485
 486         spin_lock(&arm_smmu_devices_lock);
 487         list_for_each_entry(parent, &arm_smmu_devices, list)
 488                 if (parent->dev->of_node == smmu->parent_of_node)
 489                         goto out_unlock;
 490
 491         parent = NULL;
 492         dev_warn(smmu->dev,
 493                  "Failed to find SMMU parent despite parent in DT\n");
 494 out_unlock:
 495         spin_unlock(&arm_smmu_devices_lock);
 496         return parent;
 497 }
 498
 499 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
 500 {
 501         int idx;
 502
 503         do {
 504                 idx = find_next_zero_bit(map, end, start);
 505                 if (idx == end)
 506                         return -ENOSPC;
 507         } while (test_and_set_bit(idx, map));
 508
 509         return idx;
 510 }
 511
 512 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
 513 {
 514         clear_bit(idx, map);
 515 }
 516
 517 /* Wait for any pending TLB invalidations to complete */
 518 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
 519 {
 520         int count = 0;
 521         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 522
 523         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
 524         while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
 525                & sTLBGSTATUS_GSACTIVE) {
 526                 cpu_relax();
 527                 if (++count == TLB_LOOP_TIMEOUT) {
 528                         dev_err_ratelimited(smmu->dev,
 529                         "TLB sync timed out -- SMMU may be deadlocked\n");
 530                         return;
 531                 }
 532                 udelay(1);
 533         }
 534 }
 535
 536 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
 537 {
 538         int flags, ret;
 539         u32 fsr, far, fsynr, resume;
 540         unsigned long iova;
 541         struct iommu_domain *domain = dev;
 542         struct arm_smmu_domain *smmu_domain = domain->priv;
 543         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 544         struct arm_smmu_device *smmu = root_cfg->smmu;
 545         void __iomem *cb_base;
 546
 547         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 548         fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
 549
 550         if (!(fsr & FSR_FAULT))
 551                 return IRQ_NONE;
 552
 553         if (fsr & FSR_IGN)
 554                 dev_err_ratelimited(smmu->dev,
 555                                     "Unexpected context fault (fsr 0x%u)\n",
 556                                     fsr);
 557
 558         fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
 559         flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 560
 561         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
 562         iova = far;
 563 #ifdef CONFIG_64BIT
 564         far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
 565         iova |= ((unsigned long)far << 32);
 566 #endif
 567
 568         if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
 569                 ret = IRQ_HANDLED;
 570                 resume = RESUME_RETRY;
 571         } else {
 572                 ret = IRQ_NONE;
 573                 resume = RESUME_TERMINATE;
 574         }
 575
 576         /* Clear the faulting FSR */
 577         writel(fsr, cb_base + ARM_SMMU_CB_FSR);
 578
 579         /* Retry or terminate any stalled transactions */
 580         if (fsr & FSR_SS)
 581                 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
 582
 583         return ret;
 584 }
 585
 586 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 587 {
 588         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
 589         struct arm_smmu_device *smmu = dev;
 590         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 591
 592         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
 593         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
 594         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
 595         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 596
 597         dev_err_ratelimited(smmu->dev,
 598                 "Unexpected global fault, this could be serious\n");
 599         dev_err_ratelimited(smmu->dev,
 600                 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
 601                 gfsr, gfsynr0, gfsynr1, gfsynr2);
 602
 603         writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
 604         return IRQ_NONE;
 605 }
 606
 607 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 608 {
 609         u32 reg;
 610         bool stage1;
 611         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 612         struct arm_smmu_device *smmu = root_cfg->smmu;
 613         void __iomem *cb_base, *gr0_base, *gr1_base;
 614
 615         gr0_base = ARM_SMMU_GR0(smmu);
 616         gr1_base = ARM_SMMU_GR1(smmu);
 617         stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
 618         cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
 619
 620         /* CBAR */
 621         reg = root_cfg->cbar |
 622               (root_cfg->vmid << CBAR_VMID_SHIFT);
 623         if (smmu->version == 1)
 624               reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
 625
 626         /* Use the weakest memory type, so it is overridden by the pte */
 627         if (stage1)
 628                 reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
 629         writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
 630
 631         if (smmu->version > 1) {
 632                 /* CBA2R */
 633 #ifdef CONFIG_64BIT
 634                 reg = CBA2R_RW64_64BIT;
 635 #else
 636                 reg = CBA2R_RW64_32BIT;
 637 #endif
 638                 writel_relaxed(reg,
 639                                gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
 640
 641                 /* TTBCR2 */
 642                 switch (smmu->input_size) {
 643                 case 32:
 644                         reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
 645                         break;
 646                 case 36:
 647                         reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
 648                         break;
 649                 case 39:
 650                         reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
 651                         break;
 652                 case 42:
 653                         reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
 654                         break;
 655                 case 44:
 656                         reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
 657                         break;
 658                 case 48:
 659                         reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
 660                         break;
 661                 }
 662
 663                 switch (smmu->s1_output_size) {
 664                 case 32:
 665                         reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 666                         break;
 667                 case 36:
 668                         reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
 669                         break;
 670                 case 39:
 671                         reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
 672                         break;
 673                 case 42:
 674                         reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
 675                         break;
 676                 case 44:
 677                         reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
 678                         break;
 679                 case 48:
 680                         reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
 681                         break;
 682                 }
 683
 684                 if (stage1)
 685                         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
 686         }
 687
 688         /* TTBR0 */
 689         reg = __pa(root_cfg->pgd);
 690         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
 691         reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
 692         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
 693
 694         /*
 695          * TTBCR
 696          * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
 697          */
 698         if (smmu->version > 1) {
 699                 if (PAGE_SIZE == SZ_4K)
 700                         reg = TTBCR_TG0_4K;
 701                 else
 702                         reg = TTBCR_TG0_64K;
 703
 704                 if (!stage1) {
 705                         switch (smmu->s2_output_size) {
 706                         case 32:
 707                                 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
 708                                 break;
 709                         case 36:
 710                                 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
 711                                 break;
 712                         case 40:
 713                                 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
 714                                 break;
 715                         case 42:
 716                                 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
 717                                 break;
 718                         case 44:
 719                                 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
 720                                 break;
 721                         case 48:
 722                                 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
 723                                 break;
 724                         }
 725                 } else {
 726                         reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
 727                 }
 728         } else {
 729                 reg = 0;
 730         }
 731
 732         reg |= TTBCR_EAE |
 733               (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
 734               (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
 735               (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
 736               (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
 737         writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
 738
 739         /* MAIR0 (stage-1 only) */
 740         if (stage1) {
 741                 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
 742                       (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
 743                       (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
 744                 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
 745         }
 746
 747         /* Nuke the TLB */
 748         writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID);
 749         arm_smmu_tlb_sync(smmu);
 750
 751         /* SCTLR */
 752         reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
 753         if (stage1)
 754                 reg |= SCTLR_S1_ASIDPNE;
 755 #ifdef __BIG_ENDIAN
 756         reg |= SCTLR_E;
 757 #endif
 758         writel(reg, cb_base + ARM_SMMU_CB_SCTLR);
 759 }
 760
 761 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
 762                                         struct device *dev)
 763 {
 764         int irq, ret, start;
 765         struct arm_smmu_domain *smmu_domain = domain->priv;
 766         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 767         struct arm_smmu_device *smmu, *parent;
 768
 769         /*
 770          * Walk the SMMU chain to find the root device for this chain.
 771          * We assume that no masters have translations which terminate
 772          * early, and therefore check that the root SMMU does indeed have
 773          * a StreamID for the master in question.
 774          */
 775         parent = dev->archdata.iommu;
 776         smmu_domain->output_mask = -1;
 777         do {
 778                 smmu = parent;
 779                 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
 780         } while ((parent = find_parent_smmu(smmu)));
 781
 782         if (!find_smmu_master(smmu, dev->of_node)) {
 783                 dev_err(dev, "unable to find root SMMU for device\n");
 784                 return -ENODEV;
 785         }
 786
 787         ret = __arm_smmu_alloc_bitmap(smmu->vmid_map, 0, ARM_SMMU_NUM_VMIDS);
 788         if (IS_ERR_VALUE(ret))
 789                 return ret;
 790
 791         root_cfg->vmid = ret;
 792         if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
 793                 /*
 794                  * We will likely want to change this if/when KVM gets
 795                  * involved.
 796                  */
 797                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 798                 start = smmu->num_s2_context_banks;
 799         } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
 800                 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
 801                 start = 0;
 802         } else {
 803                 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
 804                 start = smmu->num_s2_context_banks;
 805         }
 806
 807         ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
 808                                       smmu->num_context_banks);
 809         if (IS_ERR_VALUE(ret))
 810                 goto out_free_vmid;
 811
 812         root_cfg->cbndx = ret;
 813
 814         if (smmu->version == 1) {
 815                 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
 816                 root_cfg->irptndx %= smmu->num_context_irqs;
 817         } else {
 818                 root_cfg->irptndx = root_cfg->cbndx;
 819         }
 820
 821         irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 822         ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
 823                           "arm-smmu-context-fault", domain);
 824         if (IS_ERR_VALUE(ret)) {
 825                 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
 826                         root_cfg->irptndx, irq);
 827                 root_cfg->irptndx = -1;
 828                 goto out_free_context;
 829         }
 830
 831         root_cfg->smmu = smmu;
 832         arm_smmu_init_context_bank(smmu_domain);
 833         return ret;
 834
 835 out_free_context:
 836         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 837 out_free_vmid:
 838         __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid);
 839         return ret;
 840 }
 841
 842 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
 843 {
 844         struct arm_smmu_domain *smmu_domain = domain->priv;
 845         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 846         struct arm_smmu_device *smmu = root_cfg->smmu;
 847         int irq;
 848
 849         if (!smmu)
 850                 return;
 851
 852         if (root_cfg->irptndx != -1) {
 853                 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
 854                 free_irq(irq, domain);
 855         }
 856
 857         __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid);
 858         __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
 859 }
 860
 861 static int arm_smmu_domain_init(struct iommu_domain *domain)
 862 {
 863         struct arm_smmu_domain *smmu_domain;
 864         pgd_t *pgd;
 865
 866         /*
 867          * Allocate the domain and initialise some of its data structures.
 868          * We can't really do anything meaningful until we've added a
 869          * master.
 870          */
 871         smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
 872         if (!smmu_domain)
 873                 return -ENOMEM;
 874
 875         pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
 876         if (!pgd)
 877                 goto out_free_domain;
 878         smmu_domain->root_cfg.pgd = pgd;
 879
 880         spin_lock_init(&smmu_domain->lock);
 881         domain->priv = smmu_domain;
 882         return 0;
 883
 884 out_free_domain:
 885         kfree(smmu_domain);
 886         return -ENOMEM;
 887 }
 888
 889 static void arm_smmu_free_ptes(pmd_t *pmd)
 890 {
 891         pgtable_t table = pmd_pgtable(*pmd);
 892         pgtable_page_dtor(table);
 893         __free_page(table);
 894 }
 895
 896 static void arm_smmu_free_pmds(pud_t *pud)
 897 {
 898         int i;
 899         pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
 900
 901         pmd = pmd_base;
 902         for (i = 0; i < PTRS_PER_PMD; ++i) {
 903                 if (pmd_none(*pmd))
 904                         continue;
 905
 906                 arm_smmu_free_ptes(pmd);
 907                 pmd++;
 908         }
 909
 910         pmd_free(NULL, pmd_base);
 911 }
 912
 913 static void arm_smmu_free_puds(pgd_t *pgd)
 914 {
 915         int i;
 916         pud_t *pud, *pud_base = pud_offset(pgd, 0);
 917
 918         pud = pud_base;
 919         for (i = 0; i < PTRS_PER_PUD; ++i) {
 920                 if (pud_none(*pud))
 921                         continue;
 922
 923                 arm_smmu_free_pmds(pud);
 924                 pud++;
 925         }
 926
 927         pud_free(NULL, pud_base);
 928 }
 929
 930 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
 931 {
 932         int i;
 933         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
 934         pgd_t *pgd, *pgd_base = root_cfg->pgd;
 935
 936         /*
 937          * Recursively free the page tables for this domain. We don't
 938          * care about speculative TLB filling, because the TLB will be
 939          * nuked next time this context bank is re-allocated and no devices
 940          * currently map to these tables.
 941          */
 942         pgd = pgd_base;
 943         for (i = 0; i < PTRS_PER_PGD; ++i) {
 944                 if (pgd_none(*pgd))
 945                         continue;
 946                 arm_smmu_free_puds(pgd);
 947                 pgd++;
 948         }
 949
 950         kfree(pgd_base);
 951 }
 952
 953 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
 954 {
 955         struct arm_smmu_domain *smmu_domain = domain->priv;
 956         arm_smmu_destroy_domain_context(domain);
 957         arm_smmu_free_pgtables(smmu_domain);
 958         kfree(smmu_domain);
 959 }
 960
 961 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
 962                                           struct arm_smmu_master *master)
 963 {
 964         int i;
 965         struct arm_smmu_smr *smrs;
 966         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
 967
 968         if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
 969                 return 0;
 970
 971         if (master->smrs)
 972                 return -EEXIST;
 973
 974         smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
 975         if (!smrs) {
 976                 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
 977                         master->num_streamids, master->of_node->name);
 978                 return -ENOMEM;
 979         }
 980
 981         /* Allocate the SMRs on the root SMMU */
 982         for (i = 0; i < master->num_streamids; ++i) {
 983                 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
 984                                                   smmu->num_mapping_groups);
 985                 if (IS_ERR_VALUE(idx)) {
 986                         dev_err(smmu->dev, "failed to allocate free SMR\n");
 987                         goto err_free_smrs;
 988                 }
 989
 990                 smrs[i] = (struct arm_smmu_smr) {
 991                         .idx    = idx,
 992                         .mask   = 0, /* We don't currently share SMRs */
 993                         .id     = master->streamids[i],
 994                 };
 995         }
 996
 997         /* It worked! Now, poke the actual hardware */
 998         for (i = 0; i < master->num_streamids; ++i) {
 999                 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1000                           smrs[i].mask << SMR_MASK_SHIFT;
1001                 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1002         }
1003
1004         master->smrs = smrs;
1005         return 0;
1006
1007 err_free_smrs:
1008         while (--i >= 0)
1009                 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1010         kfree(smrs);
1011         return -ENOSPC;
1012 }
1013
1014 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1015                                       struct arm_smmu_master *master)
1016 {
1017         int i;
1018         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1019         struct arm_smmu_smr *smrs = master->smrs;
1020
1021         /* Invalidate the SMRs before freeing back to the allocator */
1022         for (i = 0; i < master->num_streamids; ++i) {
1023                 u8 idx = smrs[i].idx;
1024                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1025                 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1026         }
1027
1028         master->smrs = NULL;
1029         kfree(smrs);
1030 }
1031
1032 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1033                                            struct arm_smmu_master *master)
1034 {
1035         int i;
1036         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1037
1038         for (i = 0; i < master->num_streamids; ++i) {
1039                 u16 sid = master->streamids[i];
1040                 writel_relaxed(S2CR_TYPE_BYPASS,
1041                                gr0_base + ARM_SMMU_GR0_S2CR(sid));
1042         }
1043 }
1044
1045 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1046                                       struct arm_smmu_master *master)
1047 {
1048         int i, ret;
1049         struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1050         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1051
1052         ret = arm_smmu_master_configure_smrs(smmu, master);
1053         if (ret)
1054                 return ret;
1055
1056         /* Bypass the leaves */
1057         smmu = smmu_domain->leaf_smmu;
1058         while ((parent = find_parent_smmu(smmu))) {
1059                 /*
1060                  * We won't have a StreamID match for anything but the root
1061                  * smmu, so we only need to worry about StreamID indexing,
1062                  * where we must install bypass entries in the S2CRs.
1063                  */
1064                 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1065                         continue;
1066
1067                 arm_smmu_bypass_stream_mapping(smmu, master);
1068                 smmu = parent;
1069         }
1070
1071         /* Now we're at the root, time to point at our context bank */
1072         for (i = 0; i < master->num_streamids; ++i) {
1073                 u32 idx, s2cr;
1074                 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1075                 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1076                        (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1077                 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1078         }
1079
1080         return 0;
1081 }
1082
1083 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1084                                           struct arm_smmu_master *master)
1085 {
1086         struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1087
1088         /*
1089          * We *must* clear the S2CR first, because freeing the SMR means
1090          * that it can be re-allocated immediately.
1091          */
1092         arm_smmu_bypass_stream_mapping(smmu, master);
1093         arm_smmu_master_free_smrs(smmu, master);
1094 }
1095
1096 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1097 {
1098         int ret = -EINVAL;
1099         struct arm_smmu_domain *smmu_domain = domain->priv;
1100         struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1101         struct arm_smmu_master *master;
1102
1103         if (!device_smmu) {
1104                 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1105                 return -ENXIO;
1106         }
1107
1108         /*
1109          * Sanity check the domain. We don't currently support domains
1110          * that cross between different SMMU chains.
1111          */
1112         spin_lock(&smmu_domain->lock);
1113         if (!smmu_domain->leaf_smmu) {
1114                 /* Now that we have a master, we can finalise the domain */
1115                 ret = arm_smmu_init_domain_context(domain, dev);
1116                 if (IS_ERR_VALUE(ret))
1117                         goto err_unlock;
1118
1119                 smmu_domain->leaf_smmu = device_smmu;
1120         } else if (smmu_domain->leaf_smmu != device_smmu) {
1121                 dev_err(dev,
1122                         "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1123                         dev_name(smmu_domain->leaf_smmu->dev),
1124                         dev_name(device_smmu->dev));
1125                 goto err_unlock;
1126         }
1127         spin_unlock(&smmu_domain->lock);
1128
1129         /* Looks ok, so add the device to the domain */
1130         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1131         if (!master)
1132                 return -ENODEV;
1133
1134         return arm_smmu_domain_add_master(smmu_domain, master);
1135
1136 err_unlock:
1137         spin_unlock(&smmu_domain->lock);
1138         return ret;
1139 }
1140
1141 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1142 {
1143         struct arm_smmu_domain *smmu_domain = domain->priv;
1144         struct arm_smmu_master *master;
1145
1146         master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1147         if (master)
1148                 arm_smmu_domain_remove_master(smmu_domain, master);
1149 }
1150
1151 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
1152                                    size_t size)
1153 {
1154         unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
1155
1156         /*
1157          * If the SMMU can't walk tables in the CPU caches, treat them
1158          * like non-coherent DMA since we need to flush the new entries
1159          * all the way out to memory. There's no possibility of recursion
1160          * here as the SMMU table walker will not be wired through another
1161          * SMMU.
1162          */
1163         if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK))
1164                 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
1165                              DMA_TO_DEVICE);
1166 }
1167
1168 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1169                                              unsigned long end)
1170 {
1171         return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1172                 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1173 }
1174
1175 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1176                                    unsigned long addr, unsigned long end,
1177                                    unsigned long pfn, int flags, int stage)
1178 {
1179         pte_t *pte, *start;
1180         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF;
1181
1182         if (pmd_none(*pmd)) {
1183                 /* Allocate a new set of tables */
1184                 pgtable_t table = alloc_page(PGALLOC_GFP);
1185                 if (!table)
1186                         return -ENOMEM;
1187
1188                 arm_smmu_flush_pgtable(smmu, page_address(table),
1189                                        ARM_SMMU_PTE_HWTABLE_SIZE);
1190                 pgtable_page_ctor(table);
1191                 pmd_populate(NULL, pmd, table);
1192                 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1193         }
1194
1195         if (stage == 1) {
1196                 pteval |= ARM_SMMU_PTE_AP_UNPRIV;
1197                 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
1198                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
1199
1200                 if (flags & IOMMU_CACHE)
1201                         pteval |= (MAIR_ATTR_IDX_CACHE <<
1202                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
1203         } else {
1204                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1205                 if (flags & IOMMU_READ)
1206                         pteval |= ARM_SMMU_PTE_HAP_READ;
1207                 if (flags & IOMMU_WRITE)
1208                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
1209                 if (flags & IOMMU_CACHE)
1210                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1211                 else
1212                         pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1213         }
1214
1215         /* If no access, create a faulting entry to avoid TLB fills */
1216         if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1217                 pteval &= ~ARM_SMMU_PTE_PAGE;
1218
1219         pteval |= ARM_SMMU_PTE_SH_IS;
1220         start = pmd_page_vaddr(*pmd) + pte_index(addr);
1221         pte = start;
1222
1223         /*
1224          * Install the page table entries. This is fairly complicated
1225          * since we attempt to make use of the contiguous hint in the
1226          * ptes where possible. The contiguous hint indicates a series
1227          * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1228          * contiguous region with the following constraints:
1229          *
1230          *   - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1231          *   - Each pte in the region has the contiguous hint bit set
1232          *
1233          * This complicates unmapping (also handled by this code, when
1234          * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1235          * possible, yet highly unlikely, that a client may unmap only
1236          * part of a contiguous range. This requires clearing of the
1237          * contiguous hint bits in the range before installing the new
1238          * faulting entries.
1239          *
1240          * Note that re-mapping an address range without first unmapping
1241          * it is not supported, so TLB invalidation is not required here
1242          * and is instead performed at unmap and domain-init time.
1243          */
1244         do {
1245                 int i = 1;
1246                 pteval &= ~ARM_SMMU_PTE_CONT;
1247
1248                 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1249                         i = ARM_SMMU_PTE_CONT_ENTRIES;
1250                         pteval |= ARM_SMMU_PTE_CONT;
1251                 } else if (pte_val(*pte) &
1252                            (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1253                         int j;
1254                         pte_t *cont_start;
1255                         unsigned long idx = pte_index(addr);
1256
1257                         idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1258                         cont_start = pmd_page_vaddr(*pmd) + idx;
1259                         for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1260                                 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1261
1262                         arm_smmu_flush_pgtable(smmu, cont_start,
1263                                                sizeof(*pte) *
1264                                                ARM_SMMU_PTE_CONT_ENTRIES);
1265                 }
1266
1267                 do {
1268                         *pte = pfn_pte(pfn, __pgprot(pteval));
1269                 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1270         } while (addr != end);
1271
1272         arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1273         return 0;
1274 }
1275
1276 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1277                                    unsigned long addr, unsigned long end,
1278                                    phys_addr_t phys, int flags, int stage)
1279 {
1280         int ret;
1281         pmd_t *pmd;
1282         unsigned long next, pfn = __phys_to_pfn(phys);
1283
1284 #ifndef __PAGETABLE_PMD_FOLDED
1285         if (pud_none(*pud)) {
1286                 pmd = pmd_alloc_one(NULL, addr);
1287                 if (!pmd)
1288                         return -ENOMEM;
1289         } else
1290 #endif
1291                 pmd = pmd_offset(pud, addr);
1292
1293         do {
1294                 next = pmd_addr_end(addr, end);
1295                 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1296                                               flags, stage);
1297                 pud_populate(NULL, pud, pmd);
1298                 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1299                 phys += next - addr;
1300         } while (pmd++, addr = next, addr < end);
1301
1302         return ret;
1303 }
1304
1305 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1306                                    unsigned long addr, unsigned long end,
1307                                    phys_addr_t phys, int flags, int stage)
1308 {
1309         int ret = 0;
1310         pud_t *pud;
1311         unsigned long next;
1312
1313 #ifndef __PAGETABLE_PUD_FOLDED
1314         if (pgd_none(*pgd)) {
1315                 pud = pud_alloc_one(NULL, addr);
1316                 if (!pud)
1317                         return -ENOMEM;
1318         } else
1319 #endif
1320                 pud = pud_offset(pgd, addr);
1321
1322         do {
1323                 next = pud_addr_end(addr, end);
1324                 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1325                                               flags, stage);
1326                 pgd_populate(NULL, pud, pgd);
1327                 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1328                 phys += next - addr;
1329         } while (pud++, addr = next, addr < end);
1330
1331         return ret;
1332 }
1333
1334 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1335                                    unsigned long iova, phys_addr_t paddr,
1336                                    size_t size, int flags)
1337 {
1338         int ret, stage;
1339         unsigned long end;
1340         phys_addr_t input_mask, output_mask;
1341         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1342         pgd_t *pgd = root_cfg->pgd;
1343         struct arm_smmu_device *smmu = root_cfg->smmu;
1344
1345         if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1346                 stage = 2;
1347                 output_mask = (1ULL << smmu->s2_output_size) - 1;
1348         } else {
1349                 stage = 1;
1350                 output_mask = (1ULL << smmu->s1_output_size) - 1;
1351         }
1352
1353         if (!pgd)
1354                 return -EINVAL;
1355
1356         if (size & ~PAGE_MASK)
1357                 return -EINVAL;
1358
1359         input_mask = (1ULL << smmu->input_size) - 1;
1360         if ((phys_addr_t)iova & ~input_mask)
1361                 return -ERANGE;
1362
1363         if (paddr & ~output_mask)
1364                 return -ERANGE;
1365
1366         spin_lock(&smmu_domain->lock);
1367         pgd += pgd_index(iova);
1368         end = iova + size;
1369         do {
1370                 unsigned long next = pgd_addr_end(iova, end);
1371
1372                 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1373                                               flags, stage);
1374                 if (ret)
1375                         goto out_unlock;
1376
1377                 paddr += next - iova;
1378                 iova = next;
1379         } while (pgd++, iova != end);
1380
1381 out_unlock:
1382         spin_unlock(&smmu_domain->lock);
1383
1384         /* Ensure new page tables are visible to the hardware walker */
1385         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1386                 dsb();
1387
1388         return ret;
1389 }
1390
1391 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1392                         phys_addr_t paddr, size_t size, int flags)
1393 {
1394         struct arm_smmu_domain *smmu_domain = domain->priv;
1395         struct arm_smmu_device *smmu = smmu_domain->leaf_smmu;
1396
1397         if (!smmu_domain || !smmu)
1398                 return -ENODEV;
1399
1400         /* Check for silent address truncation up the SMMU chain. */
1401         if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1402                 return -ERANGE;
1403
1404         return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
1405 }
1406
1407 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1408                              size_t size)
1409 {
1410         int ret;
1411         struct arm_smmu_domain *smmu_domain = domain->priv;
1412         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1413         struct arm_smmu_device *smmu = root_cfg->smmu;
1414         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1415
1416         ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1417         writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID);
1418         arm_smmu_tlb_sync(smmu);
1419         return ret ? ret : size;
1420 }
1421
1422 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1423                                          dma_addr_t iova)
1424 {
1425         pgd_t *pgd;
1426         pud_t *pud;
1427         pmd_t *pmd;
1428         pte_t *pte;
1429         struct arm_smmu_domain *smmu_domain = domain->priv;
1430         struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1431         struct arm_smmu_device *smmu = root_cfg->smmu;
1432
1433         spin_lock(&smmu_domain->lock);
1434         pgd = root_cfg->pgd;
1435         if (!pgd)
1436                 goto err_unlock;
1437
1438         pgd += pgd_index(iova);
1439         if (pgd_none_or_clear_bad(pgd))
1440                 goto err_unlock;
1441
1442         pud = pud_offset(pgd, iova);
1443         if (pud_none_or_clear_bad(pud))
1444                 goto err_unlock;
1445
1446         pmd = pmd_offset(pud, iova);
1447         if (pmd_none_or_clear_bad(pmd))
1448                 goto err_unlock;
1449
1450         pte = pmd_page_vaddr(*pmd) + pte_index(iova);
1451         if (pte_none(pte))
1452                 goto err_unlock;
1453
1454         spin_unlock(&smmu_domain->lock);
1455         return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK);
1456
1457 err_unlock:
1458         spin_unlock(&smmu_domain->lock);
1459         dev_warn(smmu->dev,
1460                  "invalid (corrupt?) page tables detected for iova 0x%llx\n",
1461                  (unsigned long long)iova);
1462         return -EINVAL;
1463 }
1464
1465 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1466                                    unsigned long cap)
1467 {
1468         unsigned long caps = 0;
1469         struct arm_smmu_domain *smmu_domain = domain->priv;
1470
1471         if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1472                 caps |= IOMMU_CAP_CACHE_COHERENCY;
1473
1474         return !!(cap & caps);
1475 }
1476
1477 static int arm_smmu_add_device(struct device *dev)
1478 {
1479         struct arm_smmu_device *child, *parent, *smmu;
1480         struct arm_smmu_master *master = NULL;
1481
1482         spin_lock(&arm_smmu_devices_lock);
1483         list_for_each_entry(parent, &arm_smmu_devices, list) {
1484                 smmu = parent;
1485
1486                 /* Try to find a child of the current SMMU. */
1487                 list_for_each_entry(child, &arm_smmu_devices, list) {
1488                         if (child->parent_of_node == parent->dev->of_node) {
1489                                 /* Does the child sit above our master? */
1490                                 master = find_smmu_master(child, dev->of_node);
1491                                 if (master) {
1492                                         smmu = NULL;
1493                                         break;
1494                                 }
1495                         }
1496                 }
1497
1498                 /* We found some children, so keep searching. */
1499                 if (!smmu) {
1500                         master = NULL;
1501                         continue;
1502                 }
1503
1504                 master = find_smmu_master(smmu, dev->of_node);
1505                 if (master)
1506                         break;
1507         }
1508         spin_unlock(&arm_smmu_devices_lock);
1509
1510         if (!master)
1511                 return -ENODEV;
1512
1513         dev->archdata.iommu = smmu;
1514         return 0;
1515 }
1516
1517 static void arm_smmu_remove_device(struct device *dev)
1518 {
1519         dev->archdata.iommu = NULL;
1520 }
1521
1522 static struct iommu_ops arm_smmu_ops = {
1523         .domain_init    = arm_smmu_domain_init,
1524         .domain_destroy = arm_smmu_domain_destroy,
1525         .attach_dev     = arm_smmu_attach_dev,
1526         .detach_dev     = arm_smmu_detach_dev,
1527         .map            = arm_smmu_map,
1528         .unmap          = arm_smmu_unmap,
1529         .iova_to_phys   = arm_smmu_iova_to_phys,
1530         .domain_has_cap = arm_smmu_domain_has_cap,
1531         .add_device     = arm_smmu_add_device,
1532         .remove_device  = arm_smmu_remove_device,
1533         .pgsize_bitmap  = (SECTION_SIZE |
1534                            ARM_SMMU_PTE_CONT_SIZE |
1535                            PAGE_SIZE),
1536 };
1537
1538 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1539 {
1540         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1541         int i = 0;
1542         u32 scr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
1543
1544         /* Mark all SMRn as invalid and all S2CRn as bypass */
1545         for (i = 0; i < smmu->num_mapping_groups; ++i) {
1546                 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1547                 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1548         }
1549
1550         /* Invalidate the TLB, just in case */
1551         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1552         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1553         writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1554
1555         /* Enable fault reporting */
1556         scr0 |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1557
1558         /* Disable TLB broadcasting. */
1559         scr0 |= (sCR0_VMIDPNE | sCR0_PTM);
1560
1561         /* Enable client access, but bypass when no mapping is found */
1562         scr0 &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1563
1564         /* Disable forced broadcasting */
1565         scr0 &= ~sCR0_FB;
1566
1567         /* Don't upgrade barriers */
1568         scr0 &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1569
1570         /* Push the button */
1571         arm_smmu_tlb_sync(smmu);
1572         writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
1573 }
1574
1575 static int arm_smmu_id_size_to_bits(int size)
1576 {
1577         switch (size) {
1578         case 0:
1579                 return 32;
1580         case 1:
1581                 return 36;
1582         case 2:
1583                 return 40;
1584         case 3:
1585                 return 42;
1586         case 4:
1587                 return 44;
1588         case 5:
1589         default:
1590                 return 48;
1591         }
1592 }
1593
1594 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1595 {
1596         unsigned long size;
1597         void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1598         u32 id;
1599
1600         dev_notice(smmu->dev, "probing hardware configuration...\n");
1601
1602         /* Primecell ID */
1603         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1604         smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1605         dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1606
1607         /* ID0 */
1608         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1609 #ifndef CONFIG_64BIT
1610         if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1611                 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1612                 return -ENODEV;
1613         }
1614 #endif
1615         if (id & ID0_S1TS) {
1616                 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1617                 dev_notice(smmu->dev, "\tstage 1 translation\n");
1618         }
1619
1620         if (id & ID0_S2TS) {
1621                 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1622                 dev_notice(smmu->dev, "\tstage 2 translation\n");
1623         }
1624
1625         if (id & ID0_NTS) {
1626                 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1627                 dev_notice(smmu->dev, "\tnested translation\n");
1628         }
1629
1630         if (!(smmu->features &
1631                 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1632                  ARM_SMMU_FEAT_TRANS_NESTED))) {
1633                 dev_err(smmu->dev, "\tno translation support!\n");
1634                 return -ENODEV;
1635         }
1636
1637         if (id & ID0_CTTW) {
1638                 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1639                 dev_notice(smmu->dev, "\tcoherent table walk\n");
1640         }
1641
1642         if (id & ID0_SMS) {
1643                 u32 smr, sid, mask;
1644
1645                 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1646                 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1647                                            ID0_NUMSMRG_MASK;
1648                 if (smmu->num_mapping_groups == 0) {
1649                         dev_err(smmu->dev,
1650                                 "stream-matching supported, but no SMRs present!\n");
1651                         return -ENODEV;
1652                 }
1653
1654                 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1655                 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1656                 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1657                 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1658
1659                 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1660                 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1661                 if ((mask & sid) != sid) {
1662                         dev_err(smmu->dev,
1663                                 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1664                                 mask, sid);
1665                         return -ENODEV;
1666                 }
1667
1668                 dev_notice(smmu->dev,
1669                            "\tstream matching with %u register groups, mask 0x%x",
1670                            smmu->num_mapping_groups, mask);
1671         }
1672
1673         /* ID1 */
1674         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1675         smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1676
1677         /* Check that we ioremapped enough */
1678         size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1679         size *= (smmu->pagesize << 1);
1680         if (smmu->size < size)
1681                 dev_warn(smmu->dev,
1682                          "device is 0x%lx bytes but only mapped 0x%lx!\n",
1683                          size, smmu->size);
1684
1685         smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1686                                       ID1_NUMS2CB_MASK;
1687         smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1688         if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1689                 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1690                 return -ENODEV;
1691         }
1692         dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1693                    smmu->num_context_banks, smmu->num_s2_context_banks);
1694
1695         /* ID2 */
1696         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1697         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1698
1699         /*
1700          * Stage-1 output limited by stage-2 input size due to pgd
1701          * allocation (PTRS_PER_PGD).
1702          */
1703 #ifdef CONFIG_64BIT
1704         /* Current maximum output size of 39 bits */
1705         smmu->s1_output_size = min(39UL, size);
1706 #else
1707         smmu->s1_output_size = min(32UL, size);
1708 #endif
1709
1710         /* The stage-2 output mask is also applied for bypass */
1711         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1712         smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1713
1714         if (smmu->version == 1) {
1715                 smmu->input_size = 32;
1716         } else {
1717 #ifdef CONFIG_64BIT
1718                 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1719                 size = min(39, arm_smmu_id_size_to_bits(size));
1720 #else
1721                 size = 32;
1722 #endif
1723                 smmu->input_size = size;
1724
1725                 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1726                     (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1727                     (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1728                         dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1729                                 PAGE_SIZE);
1730                         return -ENODEV;
1731                 }
1732         }
1733
1734         dev_notice(smmu->dev,
1735                    "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1736                    smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1737         return 0;
1738 }
1739
1740 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1741 {
1742         struct resource *res;
1743         struct arm_smmu_device *smmu;
1744         struct device_node *dev_node;
1745         struct device *dev = &pdev->dev;
1746         struct rb_node *node;
1747         struct of_phandle_args masterspec;
1748         int num_irqs, i, err;
1749
1750         smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1751         if (!smmu) {
1752                 dev_err(dev, "failed to allocate arm_smmu_device\n");
1753                 return -ENOMEM;
1754         }
1755         smmu->dev = dev;
1756
1757         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1758         if (!res) {
1759                 dev_err(dev, "missing base address/size\n");
1760                 return -ENODEV;
1761         }
1762
1763         smmu->size = resource_size(res);
1764         smmu->base = devm_request_and_ioremap(dev, res);
1765         if (!smmu->base)
1766                 return -EADDRNOTAVAIL;
1767
1768         if (of_property_read_u32(dev->of_node, "#global-interrupts",
1769                                  &smmu->num_global_irqs)) {
1770                 dev_err(dev, "missing #global-interrupts property\n");
1771                 return -ENODEV;
1772         }
1773
1774         num_irqs = 0;
1775         while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1776                 num_irqs++;
1777                 if (num_irqs > smmu->num_global_irqs)
1778                         smmu->num_context_irqs++;
1779         }
1780
1781         if (num_irqs < smmu->num_global_irqs) {
1782                 dev_warn(dev, "found %d interrupts but expected at least %d\n",
1783                          num_irqs, smmu->num_global_irqs);
1784                 smmu->num_global_irqs = num_irqs;
1785         }
1786         smmu->num_context_irqs = num_irqs - smmu->num_global_irqs;
1787
1788         smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1789                                   GFP_KERNEL);
1790         if (!smmu->irqs) {
1791                 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1792                 return -ENOMEM;
1793         }
1794
1795         for (i = 0; i < num_irqs; ++i) {
1796                 int irq = platform_get_irq(pdev, i);
1797                 if (irq < 0) {
1798                         dev_err(dev, "failed to get irq index %d\n", i);
1799                         return -ENODEV;
1800                 }
1801                 smmu->irqs[i] = irq;
1802         }
1803
1804         i = 0;
1805         smmu->masters = RB_ROOT;
1806         while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1807                                            "#stream-id-cells", i,
1808                                            &masterspec)) {
1809                 err = register_smmu_master(smmu, dev, &masterspec);
1810                 if (err) {
1811                         dev_err(dev, "failed to add master %s\n",
1812                                 masterspec.np->name);
1813                         goto out_put_masters;
1814                 }
1815
1816                 i++;
1817         }
1818         dev_notice(dev, "registered %d master devices\n", i);
1819
1820         if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1821                 smmu->parent_of_node = dev_node;
1822
1823         err = arm_smmu_device_cfg_probe(smmu);
1824         if (err)
1825                 goto out_put_parent;
1826
1827         if (smmu->version > 1 &&
1828             smmu->num_context_banks != smmu->num_context_irqs) {
1829                 dev_err(dev,
1830                         "found only %d context interrupt(s) but %d required\n",
1831                         smmu->num_context_irqs, smmu->num_context_banks);
1832                 goto out_put_parent;
1833         }
1834
1835         arm_smmu_device_reset(smmu);
1836
1837         for (i = 0; i < smmu->num_global_irqs; ++i) {
1838                 err = request_irq(smmu->irqs[i],
1839                                   arm_smmu_global_fault,
1840                                   IRQF_SHARED,
1841                                   "arm-smmu global fault",
1842                                   smmu);
1843                 if (err) {
1844                         dev_err(dev, "failed to request global IRQ %d (%u)\n",
1845                                 i, smmu->irqs[i]);
1846                         goto out_free_irqs;
1847                 }
1848         }
1849
1850         INIT_LIST_HEAD(&smmu->list);
1851         spin_lock(&arm_smmu_devices_lock);
1852         list_add(&smmu->list, &arm_smmu_devices);
1853         spin_unlock(&arm_smmu_devices_lock);
1854         return 0;
1855
1856 out_free_irqs:
1857         while (i--)
1858                 free_irq(smmu->irqs[i], smmu);
1859
1860 out_put_parent:
1861         if (smmu->parent_of_node)
1862                 of_node_put(smmu->parent_of_node);
1863
1864 out_put_masters:
1865         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1866                 struct arm_smmu_master *master;
1867                 master = container_of(node, struct arm_smmu_master, node);
1868                 of_node_put(master->of_node);
1869         }
1870
1871         return err;
1872 }
1873
1874 static int arm_smmu_device_remove(struct platform_device *pdev)
1875 {
1876         int i;
1877         struct device *dev = &pdev->dev;
1878         struct arm_smmu_device *curr, *smmu = NULL;
1879         struct rb_node *node;
1880
1881         spin_lock(&arm_smmu_devices_lock);
1882         list_for_each_entry(curr, &arm_smmu_devices, list) {
1883                 if (curr->dev == dev) {
1884                         smmu = curr;
1885                         list_del(&smmu->list);
1886                         break;
1887                 }
1888         }
1889         spin_unlock(&arm_smmu_devices_lock);
1890
1891         if (!smmu)
1892                 return -ENODEV;
1893
1894         if (smmu->parent_of_node)
1895                 of_node_put(smmu->parent_of_node);
1896
1897         for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1898                 struct arm_smmu_master *master;
1899                 master = container_of(node, struct arm_smmu_master, node);
1900                 of_node_put(master->of_node);
1901         }
1902
1903         if (!bitmap_empty(smmu->vmid_map, ARM_SMMU_NUM_VMIDS))
1904                 dev_err(dev, "removing device with active domains!\n");
1905
1906         for (i = 0; i < smmu->num_global_irqs; ++i)
1907                 free_irq(smmu->irqs[i], smmu);
1908
1909         /* Turn the thing off */
1910         writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
1911         return 0;
1912 }
1913
1914 #ifdef CONFIG_OF
1915 static struct of_device_id arm_smmu_of_match[] = {
1916         { .compatible = "arm,smmu-v1", },
1917         { .compatible = "arm,smmu-v2", },
1918         { .compatible = "arm,mmu-400", },
1919         { .compatible = "arm,mmu-500", },
1920         { },
1921 };
1922 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1923 #endif
1924
1925 static struct platform_driver arm_smmu_driver = {
1926         .driver = {
1927                 .owner          = THIS_MODULE,
1928                 .name           = "arm-smmu",
1929                 .of_match_table = of_match_ptr(arm_smmu_of_match),
1930         },
1931         .probe  = arm_smmu_device_dt_probe,
1932         .remove = arm_smmu_device_remove,
1933 };
1934
1935 static int __init arm_smmu_init(void)
1936 {
1937         int ret;
1938
1939         ret = platform_driver_register(&arm_smmu_driver);
1940         if (ret)
1941                 return ret;
1942
1943         /* Oh, for a proper bus abstraction */
1944         if (!iommu_present(&platform_bus_type));
1945                 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1946
1947         if (!iommu_present(&amba_bustype));
1948                 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1949
1950         return 0;
1951 }
1952
1953 static void __exit arm_smmu_exit(void)
1954 {
1955         return platform_driver_unregister(&arm_smmu_driver);
1956 }
1957
1958 module_init(arm_smmu_init);
1959 module_exit(arm_smmu_exit);
1960
1961 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1962 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1963 MODULE_LICENSE("GPL v2");