Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-mv64xxx.c

   1 /*
   2  * Driver for the i2c controller on the Marvell line of host bridges
   3  * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
   4  *
   5  * Author: Mark A. Greer <mgreer@mvista.com>
   6  *
   7  * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/module.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/mv643xx_i2c.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/io.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/delay.h>
  27
  28 #define MV64XXX_I2C_ADDR_ADDR(val)                      ((val & 0x7f) << 1)
  29 #define MV64XXX_I2C_BAUD_DIV_N(val)                     (val & 0x7)
  30 #define MV64XXX_I2C_BAUD_DIV_M(val)                     ((val & 0xf) << 3)
  31
  32 #define MV64XXX_I2C_REG_CONTROL_ACK                     0x00000004
  33 #define MV64XXX_I2C_REG_CONTROL_IFLG                    0x00000008
  34 #define MV64XXX_I2C_REG_CONTROL_STOP                    0x00000010
  35 #define MV64XXX_I2C_REG_CONTROL_START                   0x00000020
  36 #define MV64XXX_I2C_REG_CONTROL_TWSIEN                  0x00000040
  37 #define MV64XXX_I2C_REG_CONTROL_INTEN                   0x00000080
  38
  39 /* Ctlr status values */
  40 #define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
  41 #define MV64XXX_I2C_STATUS_MAST_START                   0x08
  42 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START            0x10
  43 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
  44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
  45 #define MV64XXX_I2C_STATUS_MAST_WR_ACK                  0x28
  46 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK               0x30
  47 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB                0x38
  48 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
  49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
  50 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK             0x50
  51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
  52 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
  53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
  54 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
  55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
  56 #define MV64XXX_I2C_STATUS_NO_STATUS                    0xf8
  57
  58 /* Register defines (I2C bridge) */
  59 #define MV64XXX_I2C_REG_TX_DATA_LO                      0xc0
  60 #define MV64XXX_I2C_REG_TX_DATA_HI                      0xc4
  61 #define MV64XXX_I2C_REG_RX_DATA_LO                      0xc8
  62 #define MV64XXX_I2C_REG_RX_DATA_HI                      0xcc
  63 #define MV64XXX_I2C_REG_BRIDGE_CONTROL                  0xd0
  64 #define MV64XXX_I2C_REG_BRIDGE_STATUS                   0xd4
  65 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE               0xd8
  66 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK                0xdC
  67 #define MV64XXX_I2C_REG_BRIDGE_TIMING                   0xe0
  68
  69 /* Bridge Control values */
  70 #define MV64XXX_I2C_BRIDGE_CONTROL_WR                   0x00000001
  71 #define MV64XXX_I2C_BRIDGE_CONTROL_RD                   0x00000002
  72 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT           2
  73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT             0x00001000
  74 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT        13
  75 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT        16
  76 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE               0x00080000
  77
  78 /* Bridge Status values */
  79 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR                 0x00000001
  80 #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR                0xf0000001
  81 #define MV64XXX_I2C_STATUS_OFFLOAD_OK                   0xf0000000
  82
  83
  84 /* Driver states */
  85 enum {
  86         MV64XXX_I2C_STATE_INVALID,
  87         MV64XXX_I2C_STATE_IDLE,
  88         MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
  89         MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
  90         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
  91         MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
  92         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
  93         MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
  94 };
  95
  96 /* Driver actions */
  97 enum {
  98         MV64XXX_I2C_ACTION_INVALID,
  99         MV64XXX_I2C_ACTION_CONTINUE,
 100         MV64XXX_I2C_ACTION_OFFLOAD_SEND_START,
 101         MV64XXX_I2C_ACTION_SEND_START,
 102         MV64XXX_I2C_ACTION_SEND_RESTART,
 103         MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
 104         MV64XXX_I2C_ACTION_SEND_ADDR_1,
 105         MV64XXX_I2C_ACTION_SEND_ADDR_2,
 106         MV64XXX_I2C_ACTION_SEND_DATA,
 107         MV64XXX_I2C_ACTION_RCV_DATA,
 108         MV64XXX_I2C_ACTION_RCV_DATA_STOP,
 109         MV64XXX_I2C_ACTION_SEND_STOP,
 110         MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
 111 };
 112
 113 struct mv64xxx_i2c_regs {
 114         u8      addr;
 115         u8      ext_addr;
 116         u8      data;
 117         u8      control;
 118         u8      status;
 119         u8      clock;
 120         u8      soft_reset;
 121 };
 122
 123 struct mv64xxx_i2c_data {
 124         struct i2c_msg          *msgs;
 125         int                     num_msgs;
 126         int                     irq;
 127         u32                     state;
 128         u32                     action;
 129         u32                     aborting;
 130         u32                     cntl_bits;
 131         void __iomem            *reg_base;
 132         struct mv64xxx_i2c_regs reg_offsets;
 133         u32                     addr1;
 134         u32                     addr2;
 135         u32                     bytes_left;
 136         u32                     byte_posn;
 137         u32                     send_stop;
 138         u32                     block;
 139         int                     rc;
 140         u32                     freq_m;
 141         u32                     freq_n;
 142 #if defined(CONFIG_HAVE_CLK)
 143         struct clk              *clk;
 144 #endif
 145         wait_queue_head_t       waitq;
 146         spinlock_t              lock;
 147         struct i2c_msg          *msg;
 148         struct i2c_adapter      adapter;
 149         bool                    offload_enabled;
 150 /* 5us delay in order to avoid repeated start timing violation */
 151         bool                    errata_delay;
 152 };
 153
 154 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
 155         .addr           = 0x00,
 156         .ext_addr       = 0x10,
 157         .data           = 0x04,
 158         .control        = 0x08,
 159         .status         = 0x0c,
 160         .clock          = 0x0c,
 161         .soft_reset     = 0x1c,
 162 };
 163
 164 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
 165         .addr           = 0x00,
 166         .ext_addr       = 0x04,
 167         .data           = 0x08,
 168         .control        = 0x0c,
 169         .status         = 0x10,
 170         .clock          = 0x14,
 171         .soft_reset     = 0x18,
 172 };
 173
 174 static void
 175 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
 176         struct i2c_msg *msg)
 177 {
 178         u32     dir = 0;
 179
 180         drv_data->msg = msg;
 181         drv_data->byte_posn = 0;
 182         drv_data->bytes_left = msg->len;
 183         drv_data->aborting = 0;
 184         drv_data->rc = 0;
 185         drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
 186                 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
 187
 188         if (msg->flags & I2C_M_RD)
 189                 dir = 1;
 190
 191         if (msg->flags & I2C_M_TEN) {
 192                 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
 193                 drv_data->addr2 = (u32)msg->addr & 0xff;
 194         } else {
 195                 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
 196                 drv_data->addr2 = 0;
 197         }
 198 }
 199
 200 static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
 201 {
 202         unsigned long data_reg_hi = 0;
 203         unsigned long data_reg_lo = 0;
 204         unsigned long ctrl_reg;
 205         struct i2c_msg *msg = drv_data->msgs;
 206
 207         drv_data->msg = msg;
 208         drv_data->byte_posn = 0;
 209         drv_data->bytes_left = msg->len;
 210         drv_data->aborting = 0;
 211         drv_data->rc = 0;
 212         /* Only regular transactions can be offloaded */
 213         if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
 214                 return -EINVAL;
 215
 216         /* Only 1-8 byte transfers can be offloaded */
 217         if (msg->len < 1 || msg->len > 8)
 218                 return -EINVAL;
 219
 220         /* Build transaction */
 221         ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
 222                    (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
 223
 224         if ((msg->flags & I2C_M_TEN) != 0)
 225                 ctrl_reg |=  MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
 226
 227         if ((msg->flags & I2C_M_RD) == 0) {
 228                 u8 local_buf[8] = { 0 };
 229
 230                 memcpy(local_buf, msg->buf, msg->len);
 231                 data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
 232                 data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
 233
 234                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
 235                     (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
 236
 237                 writel(data_reg_lo,
 238                         drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
 239                 writel(data_reg_hi,
 240                         drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
 241
 242         } else {
 243                 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
 244                     (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
 245         }
 246
 247         /* Execute transaction */
 248         writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 249
 250         return 0;
 251 }
 252
 253 static void
 254 mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
 255 {
 256         struct i2c_msg *msg = drv_data->msg;
 257
 258         if (msg->flags & I2C_M_RD) {
 259                 u32 data_reg_lo = readl(drv_data->reg_base +
 260                                 MV64XXX_I2C_REG_RX_DATA_LO);
 261                 u32 data_reg_hi = readl(drv_data->reg_base +
 262                                 MV64XXX_I2C_REG_RX_DATA_HI);
 263                 u8 local_buf[8] = { 0 };
 264
 265                 *((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
 266                 *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
 267                 memcpy(msg->buf, local_buf, msg->len);
 268         }
 269
 270 }
 271 /*
 272  *****************************************************************************
 273  *
 274  *      Finite State Machine & Interrupt Routines
 275  *
 276  *****************************************************************************
 277  */
 278
 279 /* Reset hardware and initialize FSM */
 280 static void
 281 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
 282 {
 283         if (drv_data->offload_enabled) {
 284                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
 285                 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
 286                 writel(0, drv_data->reg_base +
 287                         MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 288                 writel(0, drv_data->reg_base +
 289                         MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
 290         }
 291
 292         writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
 293         writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
 294                 drv_data->reg_base + drv_data->reg_offsets.clock);
 295         writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
 296         writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
 297         writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
 298                 drv_data->reg_base + drv_data->reg_offsets.control);
 299         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 300 }
 301
 302 static void
 303 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
 304 {
 305         /*
 306          * If state is idle, then this is likely the remnants of an old
 307          * operation that driver has given up on or the user has killed.
 308          * If so, issue the stop condition and go to idle.
 309          */
 310         if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
 311                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 312                 return;
 313         }
 314
 315         /* The status from the ctlr [mostly] tells us what to do next */
 316         switch (status) {
 317         /* Start condition interrupt */
 318         case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
 319         case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
 320                 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
 321                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
 322                 break;
 323
 324         /* Performing a write */
 325         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
 326                 if (drv_data->msg->flags & I2C_M_TEN) {
 327                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 328                         drv_data->state =
 329                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 330                         break;
 331                 }
 332                 /* FALLTHRU */
 333         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
 334         case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
 335                 if ((drv_data->bytes_left == 0)
 336                                 || (drv_data->aborting
 337                                         && (drv_data->byte_posn != 0))) {
 338                         if (drv_data->send_stop || drv_data->aborting) {
 339                                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 340                                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 341                         } else {
 342                                 drv_data->action =
 343                                         MV64XXX_I2C_ACTION_SEND_RESTART;
 344                                 drv_data->state =
 345                                         MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
 346                         }
 347                 } else {
 348                         drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
 349                         drv_data->state =
 350                                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
 351                         drv_data->bytes_left--;
 352                 }
 353                 break;
 354
 355         /* Performing a read */
 356         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
 357                 if (drv_data->msg->flags & I2C_M_TEN) {
 358                         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
 359                         drv_data->state =
 360                                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
 361                         break;
 362                 }
 363                 /* FALLTHRU */
 364         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
 365                 if (drv_data->bytes_left == 0) {
 366                         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 367                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 368                         break;
 369                 }
 370                 /* FALLTHRU */
 371         case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
 372                 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
 373                         drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
 374                 else {
 375                         drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
 376                         drv_data->bytes_left--;
 377                 }
 378                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
 379
 380                 if ((drv_data->bytes_left == 1) || drv_data->aborting)
 381                         drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
 382                 break;
 383
 384         case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
 385                 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
 386                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 387                 break;
 388
 389         case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
 390         case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
 391         case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
 392                 /* Doesn't seem to be a device at other end */
 393                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 394                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
 395                 drv_data->rc = -ENXIO;
 396                 break;
 397
 398         case MV64XXX_I2C_STATUS_OFFLOAD_OK:
 399                 if (drv_data->send_stop || drv_data->aborting) {
 400                         drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
 401                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 402                 } else {
 403                         drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
 404                         drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
 405                 }
 406                 break;
 407
 408         default:
 409                 dev_err(&drv_data->adapter.dev,
 410                         "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
 411                         "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
 412                          drv_data->state, status, drv_data->msg->addr,
 413                          drv_data->msg->flags);
 414                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
 415                 mv64xxx_i2c_hw_init(drv_data);
 416                 drv_data->rc = -EIO;
 417         }
 418 }
 419
 420 static void
 421 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
 422 {
 423         switch(drv_data->action) {
 424         case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
 425                 mv64xxx_i2c_update_offload_data(drv_data);
 426                 writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
 427                 writel(0, drv_data->reg_base +
 428                         MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 429                 /* FALLTHRU */
 430         case MV64XXX_I2C_ACTION_SEND_RESTART:
 431                 /* We should only get here if we have further messages */
 432                 BUG_ON(drv_data->num_msgs == 0);
 433
 434                 drv_data->msgs++;
 435                 drv_data->num_msgs--;
 436                 if (!(drv_data->offload_enabled &&
 437                                 mv64xxx_i2c_offload_msg(drv_data))) {
 438                         drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
 439                         writel(drv_data->cntl_bits,
 440                         drv_data->reg_base + drv_data->reg_offsets.control);
 441
 442                         /* Setup for the next message */
 443                         mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
 444                 }
 445                 if (drv_data->errata_delay)
 446                         udelay(5);
 447
 448                 /*
 449                  * We're never at the start of the message here, and by this
 450                  * time it's already too late to do any protocol mangling.
 451                  * Thankfully, do not advertise support for that feature.
 452                  */
 453                 drv_data->send_stop = drv_data->num_msgs == 1;
 454                 break;
 455
 456         case MV64XXX_I2C_ACTION_CONTINUE:
 457                 writel(drv_data->cntl_bits,
 458                         drv_data->reg_base + drv_data->reg_offsets.control);
 459                 break;
 460
 461         case MV64XXX_I2C_ACTION_OFFLOAD_SEND_START:
 462                 if (!mv64xxx_i2c_offload_msg(drv_data))
 463                         break;
 464                 else
 465                         drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
 466                 /* FALLTHRU */
 467         case MV64XXX_I2C_ACTION_SEND_START:
 468                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
 469                         drv_data->reg_base + drv_data->reg_offsets.control);
 470                 break;
 471
 472         case MV64XXX_I2C_ACTION_SEND_ADDR_1:
 473                 writel(drv_data->addr1,
 474                         drv_data->reg_base + drv_data->reg_offsets.data);
 475                 writel(drv_data->cntl_bits,
 476                         drv_data->reg_base + drv_data->reg_offsets.control);
 477                 break;
 478
 479         case MV64XXX_I2C_ACTION_SEND_ADDR_2:
 480                 writel(drv_data->addr2,
 481                         drv_data->reg_base + drv_data->reg_offsets.data);
 482                 writel(drv_data->cntl_bits,
 483                         drv_data->reg_base + drv_data->reg_offsets.control);
 484                 break;
 485
 486         case MV64XXX_I2C_ACTION_SEND_DATA:
 487                 writel(drv_data->msg->buf[drv_data->byte_posn++],
 488                         drv_data->reg_base + drv_data->reg_offsets.data);
 489                 writel(drv_data->cntl_bits,
 490                         drv_data->reg_base + drv_data->reg_offsets.control);
 491                 break;
 492
 493         case MV64XXX_I2C_ACTION_RCV_DATA:
 494                 drv_data->msg->buf[drv_data->byte_posn++] =
 495                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 496                 writel(drv_data->cntl_bits,
 497                         drv_data->reg_base + drv_data->reg_offsets.control);
 498                 break;
 499
 500         case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
 501                 drv_data->msg->buf[drv_data->byte_posn++] =
 502                         readl(drv_data->reg_base + drv_data->reg_offsets.data);
 503                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 504                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 505                         drv_data->reg_base + drv_data->reg_offsets.control);
 506                 drv_data->block = 0;
 507                 if (drv_data->errata_delay)
 508                         udelay(5);
 509
 510                 wake_up(&drv_data->waitq);
 511                 break;
 512
 513         case MV64XXX_I2C_ACTION_INVALID:
 514         default:
 515                 dev_err(&drv_data->adapter.dev,
 516                         "mv64xxx_i2c_do_action: Invalid action: %d\n",
 517                         drv_data->action);
 518                 drv_data->rc = -EIO;
 519
 520                 /* FALLTHRU */
 521         case MV64XXX_I2C_ACTION_SEND_STOP:
 522                 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
 523                 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
 524                         drv_data->reg_base + drv_data->reg_offsets.control);
 525                 drv_data->block = 0;
 526                 wake_up(&drv_data->waitq);
 527                 break;
 528
 529         case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
 530                 mv64xxx_i2c_update_offload_data(drv_data);
 531                 writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
 532                 writel(0, drv_data->reg_base +
 533                         MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
 534                 drv_data->block = 0;
 535                 wake_up(&drv_data->waitq);
 536                 break;
 537         }
 538 }
 539
 540 static irqreturn_t
 541 mv64xxx_i2c_intr(int irq, void *dev_id)
 542 {
 543         struct mv64xxx_i2c_data *drv_data = dev_id;
 544         unsigned long   flags;
 545         u32             status;
 546         irqreturn_t     rc = IRQ_NONE;
 547
 548         spin_lock_irqsave(&drv_data->lock, flags);
 549
 550         if (drv_data->offload_enabled) {
 551                 while (readl(drv_data->reg_base +
 552                                 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
 553                         int reg_status = readl(drv_data->reg_base +
 554                                         MV64XXX_I2C_REG_BRIDGE_STATUS);
 555                         if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
 556                                 status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
 557                         else
 558                                 status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
 559                         mv64xxx_i2c_fsm(drv_data, status);
 560                         mv64xxx_i2c_do_action(drv_data);
 561                         rc = IRQ_HANDLED;
 562                 }
 563         }
 564         while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
 565                                                 MV64XXX_I2C_REG_CONTROL_IFLG) {
 566                 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
 567                 mv64xxx_i2c_fsm(drv_data, status);
 568                 mv64xxx_i2c_do_action(drv_data);
 569                 rc = IRQ_HANDLED;
 570         }
 571         spin_unlock_irqrestore(&drv_data->lock, flags);
 572
 573         return rc;
 574 }
 575
 576 /*
 577  *****************************************************************************
 578  *
 579  *      I2C Msg Execution Routines
 580  *
 581  *****************************************************************************
 582  */
 583 static void
 584 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
 585 {
 586         long            time_left;
 587         unsigned long   flags;
 588         char            abort = 0;
 589
 590         time_left = wait_event_timeout(drv_data->waitq,
 591                 !drv_data->block, drv_data->adapter.timeout);
 592
 593         spin_lock_irqsave(&drv_data->lock, flags);
 594         if (!time_left) { /* Timed out */
 595                 drv_data->rc = -ETIMEDOUT;
 596                 abort = 1;
 597         } else if (time_left < 0) { /* Interrupted/Error */
 598                 drv_data->rc = time_left; /* errno value */
 599                 abort = 1;
 600         }
 601
 602         if (abort && drv_data->block) {
 603                 drv_data->aborting = 1;
 604                 spin_unlock_irqrestore(&drv_data->lock, flags);
 605
 606                 time_left = wait_event_timeout(drv_data->waitq,
 607                         !drv_data->block, drv_data->adapter.timeout);
 608
 609                 if ((time_left <= 0) && drv_data->block) {
 610                         drv_data->state = MV64XXX_I2C_STATE_IDLE;
 611                         dev_err(&drv_data->adapter.dev,
 612                                 "mv64xxx: I2C bus locked, block: %d, "
 613                                 "time_left: %d\n", drv_data->block,
 614                                 (int)time_left);
 615                         mv64xxx_i2c_hw_init(drv_data);
 616                 }
 617         } else
 618                 spin_unlock_irqrestore(&drv_data->lock, flags);
 619 }
 620
 621 static int
 622 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
 623                                 int is_last)
 624 {
 625         unsigned long   flags;
 626
 627         spin_lock_irqsave(&drv_data->lock, flags);
 628         if (drv_data->offload_enabled) {
 629                 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_START;
 630                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 631         } else {
 632                 mv64xxx_i2c_prepare_for_io(drv_data, msg);
 633
 634                 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
 635                 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
 636         }
 637         drv_data->send_stop = is_last;
 638         drv_data->block = 1;
 639         mv64xxx_i2c_do_action(drv_data);
 640         spin_unlock_irqrestore(&drv_data->lock, flags);
 641
 642         mv64xxx_i2c_wait_for_completion(drv_data);
 643         return drv_data->rc;
 644 }
 645
 646 /*
 647  *****************************************************************************
 648  *
 649  *      I2C Core Support Routines (Interface to higher level I2C code)
 650  *
 651  *****************************************************************************
 652  */
 653 static u32
 654 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
 655 {
 656         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
 657 }
 658
 659 static int
 660 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 661 {
 662         struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
 663         int rc, ret = num;
 664
 665         BUG_ON(drv_data->msgs != NULL);
 666         drv_data->msgs = msgs;
 667         drv_data->num_msgs = num;
 668
 669         rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
 670         if (rc < 0)
 671                 ret = rc;
 672
 673         drv_data->num_msgs = 0;
 674         drv_data->msgs = NULL;
 675
 676         return ret;
 677 }
 678
 679 static const struct i2c_algorithm mv64xxx_i2c_algo = {
 680         .master_xfer = mv64xxx_i2c_xfer,
 681         .functionality = mv64xxx_i2c_functionality,
 682 };
 683
 684 /*
 685  *****************************************************************************
 686  *
 687  *      Driver Interface & Early Init Routines
 688  *
 689  *****************************************************************************
 690  */
 691 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
 692         { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
 693         { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 694         { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 695         { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
 696         {}
 697 };
 698 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
 699
 700 #ifdef CONFIG_OF
 701 #ifdef CONFIG_HAVE_CLK
 702 static int
 703 mv64xxx_calc_freq(const int tclk, const int n, const int m)
 704 {
 705         return tclk / (10 * (m + 1) * (2 << n));
 706 }
 707
 708 static bool
 709 mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
 710                           u32 *best_m)
 711 {
 712         int freq, delta, best_delta = INT_MAX;
 713         int m, n;
 714
 715         for (n = 0; n <= 7; n++)
 716                 for (m = 0; m <= 15; m++) {
 717                         freq = mv64xxx_calc_freq(tclk, n, m);
 718                         delta = req_freq - freq;
 719                         if (delta >= 0 && delta < best_delta) {
 720                                 *best_m = m;
 721                                 *best_n = n;
 722                                 best_delta = delta;
 723                         }
 724                         if (best_delta == 0)
 725                                 return true;
 726                 }
 727         if (best_delta == INT_MAX)
 728                 return false;
 729         return true;
 730 }
 731 #endif /* CONFIG_HAVE_CLK */
 732
 733 static int
 734 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 735                   struct device *dev)
 736 {
 737         /* CLK is mandatory when using DT to describe the i2c bus. We
 738          * need to know tclk in order to calculate bus clock
 739          * factors.
 740          */
 741 #if !defined(CONFIG_HAVE_CLK)
 742         /* Have OF but no CLK */
 743         return -ENODEV;
 744 #else
 745         const struct of_device_id *device;
 746         struct device_node *np = dev->of_node;
 747         u32 bus_freq, tclk;
 748         int rc = 0;
 749
 750         if (IS_ERR(drv_data->clk)) {
 751                 rc = -ENODEV;
 752                 goto out;
 753         }
 754         tclk = clk_get_rate(drv_data->clk);
 755
 756         rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
 757         if (rc)
 758                 bus_freq = 100000; /* 100kHz by default */
 759
 760         if (!mv64xxx_find_baud_factors(bus_freq, tclk,
 761                                        &drv_data->freq_n, &drv_data->freq_m)) {
 762                 rc = -EINVAL;
 763                 goto out;
 764         }
 765         drv_data->irq = irq_of_parse_and_map(np, 0);
 766
 767         /* Its not yet defined how timeouts will be specified in device tree.
 768          * So hard code the value to 1 second.
 769          */
 770         drv_data->adapter.timeout = HZ;
 771
 772         device = of_match_device(mv64xxx_i2c_of_match_table, dev);
 773         if (!device)
 774                 return -ENODEV;
 775
 776         memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
 777
 778         /*
 779          * For controllers embedded in new SoCs activate the
 780          * Transaction Generator support and the errata fix.
 781          */
 782         if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
 783                 drv_data->offload_enabled = true;
 784                 drv_data->errata_delay = true;
 785         }
 786
 787         if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
 788                 drv_data->offload_enabled = false;
 789                 drv_data->errata_delay = true;
 790         }
 791 out:
 792         return rc;
 793 #endif
 794 }
 795 #else /* CONFIG_OF */
 796 static int
 797 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
 798                   struct device *dev)
 799 {
 800         return -ENODEV;
 801 }
 802 #endif /* CONFIG_OF */
 803
 804 static int
 805 mv64xxx_i2c_probe(struct platform_device *pd)
 806 {
 807         struct mv64xxx_i2c_data         *drv_data;
 808         struct mv64xxx_i2c_pdata        *pdata = dev_get_platdata(&pd->dev);
 809         struct resource *r;
 810         int     rc;
 811
 812         if ((!pdata && !pd->dev.of_node))
 813                 return -ENODEV;
 814
 815         drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
 816                                 GFP_KERNEL);
 817         if (!drv_data)
 818                 return -ENOMEM;
 819
 820         r = platform_get_resource(pd, IORESOURCE_MEM, 0);
 821         drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
 822         if (IS_ERR(drv_data->reg_base))
 823                 return PTR_ERR(drv_data->reg_base);
 824
 825         strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
 826                 sizeof(drv_data->adapter.name));
 827
 828         init_waitqueue_head(&drv_data->waitq);
 829         spin_lock_init(&drv_data->lock);
 830
 831 #if defined(CONFIG_HAVE_CLK)
 832         /* Not all platforms have a clk */
 833         drv_data->clk = devm_clk_get(&pd->dev, NULL);
 834         if (!IS_ERR(drv_data->clk)) {
 835                 clk_prepare(drv_data->clk);
 836                 clk_enable(drv_data->clk);
 837         }
 838 #endif
 839         if (pdata) {
 840                 drv_data->freq_m = pdata->freq_m;
 841                 drv_data->freq_n = pdata->freq_n;
 842                 drv_data->irq = platform_get_irq(pd, 0);
 843                 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
 844                 drv_data->offload_enabled = false;
 845                 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
 846         } else if (pd->dev.of_node) {
 847                 rc = mv64xxx_of_config(drv_data, &pd->dev);
 848                 if (rc)
 849                         goto exit_clk;
 850         }
 851         if (drv_data->irq < 0) {
 852                 rc = -ENXIO;
 853                 goto exit_clk;
 854         }
 855
 856         drv_data->adapter.dev.parent = &pd->dev;
 857         drv_data->adapter.algo = &mv64xxx_i2c_algo;
 858         drv_data->adapter.owner = THIS_MODULE;
 859         drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 860         drv_data->adapter.nr = pd->id;
 861         drv_data->adapter.dev.of_node = pd->dev.of_node;
 862         platform_set_drvdata(pd, drv_data);
 863         i2c_set_adapdata(&drv_data->adapter, drv_data);
 864
 865         mv64xxx_i2c_hw_init(drv_data);
 866
 867         rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
 868                          MV64XXX_I2C_CTLR_NAME, drv_data);
 869         if (rc) {
 870                 dev_err(&drv_data->adapter.dev,
 871                         "mv64xxx: Can't register intr handler irq%d: %d\n",
 872                         drv_data->irq, rc);
 873                 goto exit_clk;
 874         } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
 875                 dev_err(&drv_data->adapter.dev,
 876                         "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
 877                 goto exit_free_irq;
 878         }
 879
 880         return 0;
 881
 882 exit_free_irq:
 883         free_irq(drv_data->irq, drv_data);
 884 exit_clk:
 885 #if defined(CONFIG_HAVE_CLK)
 886         /* Not all platforms have a clk */
 887         if (!IS_ERR(drv_data->clk)) {
 888                 clk_disable(drv_data->clk);
 889                 clk_unprepare(drv_data->clk);
 890         }
 891 #endif
 892         return rc;
 893 }
 894
 895 static int
 896 mv64xxx_i2c_remove(struct platform_device *dev)
 897 {
 898         struct mv64xxx_i2c_data         *drv_data = platform_get_drvdata(dev);
 899
 900         i2c_del_adapter(&drv_data->adapter);
 901         free_irq(drv_data->irq, drv_data);
 902 #if defined(CONFIG_HAVE_CLK)
 903         /* Not all platforms have a clk */
 904         if (!IS_ERR(drv_data->clk)) {
 905                 clk_disable(drv_data->clk);
 906                 clk_unprepare(drv_data->clk);
 907         }
 908 #endif
 909
 910         return 0;
 911 }
 912
 913 static struct platform_driver mv64xxx_i2c_driver = {
 914         .probe  = mv64xxx_i2c_probe,
 915         .remove = mv64xxx_i2c_remove,
 916         .driver = {
 917                 .owner  = THIS_MODULE,
 918                 .name   = MV64XXX_I2C_CTLR_NAME,
 919                 .of_match_table = mv64xxx_i2c_of_match_table,
 920         },
 921 };
 922
 923 module_platform_driver(mv64xxx_i2c_driver);
 924
 925 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
 926 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
 927 MODULE_LICENSE("GPL");