Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-cpm.c

   1 /*
   2  * Freescale CPM1/CPM2 I2C interface.
   3  * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
   4  *
   5  * moved into proper i2c interface;
   6  * Brad Parker (brad@heeltoe.com)
   7  *
   8  * Parts from dbox2_i2c.c (cvs.tuxbox.org)
   9  * (C) 2000-2001 Felix Domke (tmbinc@gmx.net), Gillem (htoa@gmx.net)
  10  *
  11  * (C) 2007 Montavista Software, Inc.
  12  * Vitaly Bordug <vitb@kernel.crashing.org>
  13  *
  14  * Converted to of_platform_device. Renamed to i2c-cpm.c.
  15  * (C) 2007,2008 Jochen Friedrich <jochen@scram.de>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify
  18  *  it under the terms of the GNU General Public License as published by
  19  *  the Free Software Foundation; either version 2 of the License, or
  20  *  (at your option) any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful,
  23  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  24  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25  *  GNU General Public License for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software
  29  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30  */
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/delay.h>
  35 #include <linux/slab.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/errno.h>
  38 #include <linux/stddef.h>
  39 #include <linux/i2c.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/of_device.h>
  43 #include <linux/of_platform.h>
  44 #include <sysdev/fsl_soc.h>
  45 #include <asm/cpm.h>
  46
  47 /* Try to define this if you have an older CPU (earlier than rev D4) */
  48 /* However, better use a GPIO based bitbang driver in this case :/   */
  49 #undef  I2C_CHIP_ERRATA
  50
  51 #define CPM_MAX_READ    513
  52 #define CPM_MAXBD       4
  53
  54 #define I2C_EB                  (0x10) /* Big endian mode */
  55 #define I2C_EB_CPM2             (0x30) /* Big endian mode, memory snoop */
  56
  57 #define DPRAM_BASE              ((u8 __iomem __force *)cpm_muram_addr(0))
  58
  59 /* I2C parameter RAM. */
  60 struct i2c_ram {
  61         ushort  rbase;          /* Rx Buffer descriptor base address */
  62         ushort  tbase;          /* Tx Buffer descriptor base address */
  63         u_char  rfcr;           /* Rx function code */
  64         u_char  tfcr;           /* Tx function code */
  65         ushort  mrblr;          /* Max receive buffer length */
  66         uint    rstate;         /* Internal */
  67         uint    rdp;            /* Internal */
  68         ushort  rbptr;          /* Rx Buffer descriptor pointer */
  69         ushort  rbc;            /* Internal */
  70         uint    rxtmp;          /* Internal */
  71         uint    tstate;         /* Internal */
  72         uint    tdp;            /* Internal */
  73         ushort  tbptr;          /* Tx Buffer descriptor pointer */
  74         ushort  tbc;            /* Internal */
  75         uint    txtmp;          /* Internal */
  76         char    res1[4];        /* Reserved */
  77         ushort  rpbase;         /* Relocation pointer */
  78         char    res2[2];        /* Reserved */
  79 };
  80
  81 #define I2COM_START     0x80
  82 #define I2COM_MASTER    0x01
  83 #define I2CER_TXE       0x10
  84 #define I2CER_BUSY      0x04
  85 #define I2CER_TXB       0x02
  86 #define I2CER_RXB       0x01
  87 #define I2MOD_EN        0x01
  88
  89 /* I2C Registers */
  90 struct i2c_reg {
  91         u8      i2mod;
  92         u8      res1[3];
  93         u8      i2add;
  94         u8      res2[3];
  95         u8      i2brg;
  96         u8      res3[3];
  97         u8      i2com;
  98         u8      res4[3];
  99         u8      i2cer;
 100         u8      res5[3];
 101         u8      i2cmr;
 102 };
 103
 104 struct cpm_i2c {
 105         char *base;
 106         struct platform_device *ofdev;
 107         struct i2c_adapter adap;
 108         uint dp_addr;
 109         int version; /* CPM1=1, CPM2=2 */
 110         int irq;
 111         int cp_command;
 112         int freq;
 113         struct i2c_reg __iomem *i2c_reg;
 114         struct i2c_ram __iomem *i2c_ram;
 115         u16 i2c_addr;
 116         wait_queue_head_t i2c_wait;
 117         cbd_t __iomem *tbase;
 118         cbd_t __iomem *rbase;
 119         u_char *txbuf[CPM_MAXBD];
 120         u_char *rxbuf[CPM_MAXBD];
 121         u32 txdma[CPM_MAXBD];
 122         u32 rxdma[CPM_MAXBD];
 123 };
 124
 125 static irqreturn_t cpm_i2c_interrupt(int irq, void *dev_id)
 126 {
 127         struct cpm_i2c *cpm;
 128         struct i2c_reg __iomem *i2c_reg;
 129         struct i2c_adapter *adap = dev_id;
 130         int i;
 131
 132         cpm = i2c_get_adapdata(dev_id);
 133         i2c_reg = cpm->i2c_reg;
 134
 135         /* Clear interrupt. */
 136         i = in_8(&i2c_reg->i2cer);
 137         out_8(&i2c_reg->i2cer, i);
 138
 139         dev_dbg(&adap->dev, "Interrupt: %x\n", i);
 140
 141         wake_up(&cpm->i2c_wait);
 142
 143         return i ? IRQ_HANDLED : IRQ_NONE;
 144 }
 145
 146 static void cpm_reset_i2c_params(struct cpm_i2c *cpm)
 147 {
 148         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
 149
 150         /* Set up the I2C parameters in the parameter ram. */
 151         out_be16(&i2c_ram->tbase, (u8 __iomem *)cpm->tbase - DPRAM_BASE);
 152         out_be16(&i2c_ram->rbase, (u8 __iomem *)cpm->rbase - DPRAM_BASE);
 153
 154         if (cpm->version == 1) {
 155                 out_8(&i2c_ram->tfcr, I2C_EB);
 156                 out_8(&i2c_ram->rfcr, I2C_EB);
 157         } else {
 158                 out_8(&i2c_ram->tfcr, I2C_EB_CPM2);
 159                 out_8(&i2c_ram->rfcr, I2C_EB_CPM2);
 160         }
 161
 162         out_be16(&i2c_ram->mrblr, CPM_MAX_READ);
 163
 164         out_be32(&i2c_ram->rstate, 0);
 165         out_be32(&i2c_ram->rdp, 0);
 166         out_be16(&i2c_ram->rbptr, 0);
 167         out_be16(&i2c_ram->rbc, 0);
 168         out_be32(&i2c_ram->rxtmp, 0);
 169         out_be32(&i2c_ram->tstate, 0);
 170         out_be32(&i2c_ram->tdp, 0);
 171         out_be16(&i2c_ram->tbptr, 0);
 172         out_be16(&i2c_ram->tbc, 0);
 173         out_be32(&i2c_ram->txtmp, 0);
 174 }
 175
 176 static void cpm_i2c_force_close(struct i2c_adapter *adap)
 177 {
 178         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 179         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
 180
 181         dev_dbg(&adap->dev, "cpm_i2c_force_close()\n");
 182
 183         cpm_command(cpm->cp_command, CPM_CR_CLOSE_RX_BD);
 184
 185         out_8(&i2c_reg->i2cmr, 0x00);   /* Disable all interrupts */
 186         out_8(&i2c_reg->i2cer, 0xff);
 187 }
 188
 189 static void cpm_i2c_parse_message(struct i2c_adapter *adap,
 190         struct i2c_msg *pmsg, int num, int tx, int rx)
 191 {
 192         cbd_t __iomem *tbdf;
 193         cbd_t __iomem *rbdf;
 194         u_char addr;
 195         u_char *tb;
 196         u_char *rb;
 197         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 198
 199         tbdf = cpm->tbase + tx;
 200         rbdf = cpm->rbase + rx;
 201
 202         addr = pmsg->addr << 1;
 203         if (pmsg->flags & I2C_M_RD)
 204                 addr |= 1;
 205
 206         tb = cpm->txbuf[tx];
 207         rb = cpm->rxbuf[rx];
 208
 209         /* Align read buffer */
 210         rb = (u_char *) (((ulong) rb + 1) & ~1);
 211
 212         tb[0] = addr;           /* Device address byte w/rw flag */
 213
 214         out_be16(&tbdf->cbd_datlen, pmsg->len + 1);
 215         out_be16(&tbdf->cbd_sc, 0);
 216
 217         if (!(pmsg->flags & I2C_M_NOSTART))
 218                 setbits16(&tbdf->cbd_sc, BD_I2C_START);
 219
 220         if (tx + 1 == num)
 221                 setbits16(&tbdf->cbd_sc, BD_SC_LAST | BD_SC_WRAP);
 222
 223         if (pmsg->flags & I2C_M_RD) {
 224                 /*
 225                  * To read, we need an empty buffer of the proper length.
 226                  * All that is used is the first byte for address, the remainder
 227                  * is just used for timing (and doesn't really have to exist).
 228                  */
 229
 230                 dev_dbg(&adap->dev, "cpm_i2c_read(abyte=0x%x)\n", addr);
 231
 232                 out_be16(&rbdf->cbd_datlen, 0);
 233                 out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
 234
 235                 if (rx + 1 == CPM_MAXBD)
 236                         setbits16(&rbdf->cbd_sc, BD_SC_WRAP);
 237
 238                 eieio();
 239                 setbits16(&tbdf->cbd_sc, BD_SC_READY);
 240         } else {
 241                 dev_dbg(&adap->dev, "cpm_i2c_write(abyte=0x%x)\n", addr);
 242
 243                 memcpy(tb+1, pmsg->buf, pmsg->len);
 244
 245                 eieio();
 246                 setbits16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_INTRPT);
 247         }
 248 }
 249
 250 static int cpm_i2c_check_message(struct i2c_adapter *adap,
 251         struct i2c_msg *pmsg, int tx, int rx)
 252 {
 253         cbd_t __iomem *tbdf;
 254         cbd_t __iomem *rbdf;
 255         u_char *tb;
 256         u_char *rb;
 257         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 258
 259         tbdf = cpm->tbase + tx;
 260         rbdf = cpm->rbase + rx;
 261
 262         tb = cpm->txbuf[tx];
 263         rb = cpm->rxbuf[rx];
 264
 265         /* Align read buffer */
 266         rb = (u_char *) (((uint) rb + 1) & ~1);
 267
 268         eieio();
 269         if (pmsg->flags & I2C_M_RD) {
 270                 dev_dbg(&adap->dev, "tx sc 0x%04x, rx sc 0x%04x\n",
 271                         in_be16(&tbdf->cbd_sc), in_be16(&rbdf->cbd_sc));
 272
 273                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
 274                         dev_dbg(&adap->dev, "I2C read; No ack\n");
 275                         return -ENXIO;
 276                 }
 277                 if (in_be16(&rbdf->cbd_sc) & BD_SC_EMPTY) {
 278                         dev_err(&adap->dev,
 279                                 "I2C read; complete but rbuf empty\n");
 280                         return -EREMOTEIO;
 281                 }
 282                 if (in_be16(&rbdf->cbd_sc) & BD_SC_OV) {
 283                         dev_err(&adap->dev, "I2C read; Overrun\n");
 284                         return -EREMOTEIO;
 285                 }
 286                 memcpy(pmsg->buf, rb, pmsg->len);
 287         } else {
 288                 dev_dbg(&adap->dev, "tx sc %d 0x%04x\n", tx,
 289                         in_be16(&tbdf->cbd_sc));
 290
 291                 if (in_be16(&tbdf->cbd_sc) & BD_SC_NAK) {
 292                         dev_dbg(&adap->dev, "I2C write; No ack\n");
 293                         return -ENXIO;
 294                 }
 295                 if (in_be16(&tbdf->cbd_sc) & BD_SC_UN) {
 296                         dev_err(&adap->dev, "I2C write; Underrun\n");
 297                         return -EIO;
 298                 }
 299                 if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
 300                         dev_err(&adap->dev, "I2C write; Collision\n");
 301                         return -EIO;
 302                 }
 303         }
 304         return 0;
 305 }
 306
 307 static int cpm_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 308 {
 309         struct cpm_i2c *cpm = i2c_get_adapdata(adap);
 310         struct i2c_reg __iomem *i2c_reg = cpm->i2c_reg;
 311         struct i2c_ram __iomem *i2c_ram = cpm->i2c_ram;
 312         struct i2c_msg *pmsg;
 313         int ret, i;
 314         int tptr;
 315         int rptr;
 316         cbd_t __iomem *tbdf;
 317         cbd_t __iomem *rbdf;
 318
 319         if (num > CPM_MAXBD)
 320                 return -EINVAL;
 321
 322         /* Check if we have any oversized READ requests */
 323         for (i = 0; i < num; i++) {
 324                 pmsg = &msgs[i];
 325                 if (pmsg->len >= CPM_MAX_READ)
 326                         return -EINVAL;
 327         }
 328
 329         /* Reset to use first buffer */
 330         out_be16(&i2c_ram->rbptr, in_be16(&i2c_ram->rbase));
 331         out_be16(&i2c_ram->tbptr, in_be16(&i2c_ram->tbase));
 332
 333         tbdf = cpm->tbase;
 334         rbdf = cpm->rbase;
 335
 336         tptr = 0;
 337         rptr = 0;
 338
 339         /*
 340          * If there was a collision in the last i2c transaction,
 341          * Set I2COM_MASTER as it was cleared during collision.
 342          */
 343         if (in_be16(&tbdf->cbd_sc) & BD_SC_CL) {
 344                 out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);
 345         }
 346
 347         while (tptr < num) {
 348                 pmsg = &msgs[tptr];
 349                 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr);
 350
 351                 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr);
 352                 if (pmsg->flags & I2C_M_RD)
 353                         rptr++;
 354                 tptr++;
 355         }
 356         /* Start transfer now */
 357         /* Enable RX/TX/Error interupts */
 358         out_8(&i2c_reg->i2cmr, I2CER_TXE | I2CER_TXB | I2CER_RXB);
 359         out_8(&i2c_reg->i2cer, 0xff);   /* Clear interrupt status */
 360         /* Chip bug, set enable here */
 361         setbits8(&i2c_reg->i2mod, I2MOD_EN);    /* Enable */
 362         /* Begin transmission */
 363         setbits8(&i2c_reg->i2com, I2COM_START);
 364
 365         tptr = 0;
 366         rptr = 0;
 367
 368         while (tptr < num) {
 369                 /* Check for outstanding messages */
 370                 dev_dbg(&adap->dev, "test ready.\n");
 371                 pmsg = &msgs[tptr];
 372                 if (pmsg->flags & I2C_M_RD)
 373                         ret = wait_event_timeout(cpm->i2c_wait,
 374                                 (in_be16(&tbdf[tptr].cbd_sc) & BD_SC_NAK) ||
 375                                 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY),
 376                                 1 * HZ);
 377                 else
 378                         ret = wait_event_timeout(cpm->i2c_wait,
 379                                 !(in_be16(&tbdf[tptr].cbd_sc) & BD_SC_READY),
 380                                 1 * HZ);
 381                 if (ret == 0) {
 382                         ret = -EREMOTEIO;
 383                         dev_err(&adap->dev, "I2C transfer: timeout\n");
 384                         goto out_err;
 385                 }
 386                 if (ret > 0) {
 387                         dev_dbg(&adap->dev, "ready.\n");
 388                         ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr);
 389                         tptr++;
 390                         if (pmsg->flags & I2C_M_RD)
 391                                 rptr++;
 392                         if (ret)
 393                                 goto out_err;
 394                 }
 395         }
 396 #ifdef I2C_CHIP_ERRATA
 397         /*
 398          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
 399          * Disabling I2C too early may cause too short stop condition
 400          */
 401         udelay(4);
 402         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
 403 #endif
 404         return (num);
 405
 406 out_err:
 407         cpm_i2c_force_close(adap);
 408 #ifdef I2C_CHIP_ERRATA
 409         /*
 410          * Chip errata, clear enable. This is not needed on rev D4 CPUs.
 411          */
 412         clrbits8(&i2c_reg->i2mod, I2MOD_EN);
 413 #endif
 414         return ret;
 415 }
 416
 417 static u32 cpm_i2c_func(struct i2c_adapter *adap)
 418 {
 419         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 420 }
 421
 422 /* -----exported algorithm data: -------------------------------------  */
 423
 424 static const struct i2c_algorithm cpm_i2c_algo = {
 425         .master_xfer = cpm_i2c_xfer,
 426         .functionality = cpm_i2c_func,
 427 };
 428
 429 static const struct i2c_adapter cpm_ops = {
 430         .owner          = THIS_MODULE,
 431         .name           = "i2c-cpm",
 432         .algo           = &cpm_i2c_algo,
 433 };
 434
 435 static int cpm_i2c_setup(struct cpm_i2c *cpm)
 436 {
 437         struct platform_device *ofdev = cpm->ofdev;
 438         const u32 *data;
 439         int len, ret, i;
 440         void __iomem *i2c_base;
 441         cbd_t __iomem *tbdf;
 442         cbd_t __iomem *rbdf;
 443         unsigned char brg;
 444
 445         dev_dbg(&cpm->ofdev->dev, "cpm_i2c_setup()\n");
 446
 447         init_waitqueue_head(&cpm->i2c_wait);
 448
 449         cpm->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
 450         if (!cpm->irq)
 451                 return -EINVAL;
 452
 453         /* Install interrupt handler. */
 454         ret = request_irq(cpm->irq, cpm_i2c_interrupt, 0, "cpm_i2c",
 455                           &cpm->adap);
 456         if (ret)
 457                 return ret;
 458
 459         /* I2C parameter RAM */
 460         i2c_base = of_iomap(ofdev->dev.of_node, 1);
 461         if (i2c_base == NULL) {
 462                 ret = -EINVAL;
 463                 goto out_irq;
 464         }
 465
 466         if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
 467
 468                 /* Check for and use a microcode relocation patch. */
 469                 cpm->i2c_ram = i2c_base;
 470                 cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
 471
 472                 /*
 473                  * Maybe should use cpm_muram_alloc instead of hardcoding
 474                  * this in micropatch.c
 475                  */
 476                 if (cpm->i2c_addr) {
 477                         cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
 478                         iounmap(i2c_base);
 479                 }
 480
 481                 cpm->version = 1;
 482
 483         } else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
 484                 cpm->i2c_addr = cpm_muram_alloc(sizeof(struct i2c_ram), 64);
 485                 cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
 486                 out_be16(i2c_base, cpm->i2c_addr);
 487                 iounmap(i2c_base);
 488
 489                 cpm->version = 2;
 490
 491         } else {
 492                 iounmap(i2c_base);
 493                 ret = -EINVAL;
 494                 goto out_irq;
 495         }
 496
 497         /* I2C control/status registers */
 498         cpm->i2c_reg = of_iomap(ofdev->dev.of_node, 0);
 499         if (cpm->i2c_reg == NULL) {
 500                 ret = -EINVAL;
 501                 goto out_ram;
 502         }
 503
 504         data = of_get_property(ofdev->dev.of_node, "fsl,cpm-command", &len);
 505         if (!data || len != 4) {
 506                 ret = -EINVAL;
 507                 goto out_reg;
 508         }
 509         cpm->cp_command = *data;
 510
 511         data = of_get_property(ofdev->dev.of_node, "linux,i2c-class", &len);
 512         if (data && len == 4)
 513                 cpm->adap.class = *data;
 514
 515         data = of_get_property(ofdev->dev.of_node, "clock-frequency", &len);
 516         if (data && len == 4)
 517                 cpm->freq = *data;
 518         else
 519                 cpm->freq = 60000; /* use 60kHz i2c clock by default */
 520
 521         /*
 522          * Allocate space for CPM_MAXBD transmit and receive buffer
 523          * descriptors in the DP ram.
 524          */
 525         cpm->dp_addr = cpm_muram_alloc(sizeof(cbd_t) * 2 * CPM_MAXBD, 8);
 526         if (!cpm->dp_addr) {
 527                 ret = -ENOMEM;
 528                 goto out_reg;
 529         }
 530
 531         cpm->tbase = cpm_muram_addr(cpm->dp_addr);
 532         cpm->rbase = cpm_muram_addr(cpm->dp_addr + sizeof(cbd_t) * CPM_MAXBD);
 533
 534         /* Allocate TX and RX buffers */
 535
 536         tbdf = cpm->tbase;
 537         rbdf = cpm->rbase;
 538
 539         for (i = 0; i < CPM_MAXBD; i++) {
 540                 cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
 541                                                    CPM_MAX_READ + 1,
 542                                                    &cpm->rxdma[i], GFP_KERNEL);
 543                 if (!cpm->rxbuf[i]) {
 544                         ret = -ENOMEM;
 545                         goto out_muram;
 546                 }
 547                 out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
 548
 549                 cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
 550                 if (!cpm->txbuf[i]) {
 551                         ret = -ENOMEM;
 552                         goto out_muram;
 553                 }
 554                 out_be32(&tbdf[i].cbd_bufaddr, cpm->txdma[i]);
 555         }
 556
 557         /* Initialize Tx/Rx parameters. */
 558
 559         cpm_reset_i2c_params(cpm);
 560
 561         dev_dbg(&cpm->ofdev->dev, "i2c_ram 0x%p, i2c_addr 0x%04x, freq %d\n",
 562                 cpm->i2c_ram, cpm->i2c_addr, cpm->freq);
 563         dev_dbg(&cpm->ofdev->dev, "tbase 0x%04x, rbase 0x%04x\n",
 564                 (u8 __iomem *)cpm->tbase - DPRAM_BASE,
 565                 (u8 __iomem *)cpm->rbase - DPRAM_BASE);
 566
 567         cpm_command(cpm->cp_command, CPM_CR_INIT_TRX);
 568
 569         /*
 570          * Select an invalid address. Just make sure we don't use loopback mode
 571          */
 572         out_8(&cpm->i2c_reg->i2add, 0x7f << 1);
 573
 574         /*
 575          * PDIV is set to 00 in i2mod, so brgclk/32 is used as input to the
 576          * i2c baud rate generator. This is divided by 2 x (DIV + 3) to get
 577          * the actual i2c bus frequency.
 578          */
 579         brg = get_brgfreq() / (32 * 2 * cpm->freq) - 3;
 580         out_8(&cpm->i2c_reg->i2brg, brg);
 581
 582         out_8(&cpm->i2c_reg->i2mod, 0x00);
 583         out_8(&cpm->i2c_reg->i2com, I2COM_MASTER);      /* Master mode */
 584
 585         /* Disable interrupts. */
 586         out_8(&cpm->i2c_reg->i2cmr, 0);
 587         out_8(&cpm->i2c_reg->i2cer, 0xff);
 588
 589         return 0;
 590
 591 out_muram:
 592         for (i = 0; i < CPM_MAXBD; i++) {
 593                 if (cpm->rxbuf[i])
 594                         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 595                                 cpm->rxbuf[i], cpm->rxdma[i]);
 596                 if (cpm->txbuf[i])
 597                         dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 598                                 cpm->txbuf[i], cpm->txdma[i]);
 599         }
 600         cpm_muram_free(cpm->dp_addr);
 601 out_reg:
 602         iounmap(cpm->i2c_reg);
 603 out_ram:
 604         if ((cpm->version == 1) && (!cpm->i2c_addr))
 605                 iounmap(cpm->i2c_ram);
 606         if (cpm->version == 2)
 607                 cpm_muram_free(cpm->i2c_addr);
 608 out_irq:
 609         free_irq(cpm->irq, &cpm->adap);
 610         return ret;
 611 }
 612
 613 static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
 614 {
 615         int i;
 616
 617         /* Shut down I2C. */
 618         clrbits8(&cpm->i2c_reg->i2mod, I2MOD_EN);
 619
 620         /* Disable interrupts */
 621         out_8(&cpm->i2c_reg->i2cmr, 0);
 622         out_8(&cpm->i2c_reg->i2cer, 0xff);
 623
 624         free_irq(cpm->irq, &cpm->adap);
 625
 626         /* Free all memory */
 627         for (i = 0; i < CPM_MAXBD; i++) {
 628                 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 629                         cpm->rxbuf[i], cpm->rxdma[i]);
 630                 dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
 631                         cpm->txbuf[i], cpm->txdma[i]);
 632         }
 633
 634         cpm_muram_free(cpm->dp_addr);
 635         iounmap(cpm->i2c_reg);
 636
 637         if ((cpm->version == 1) && (!cpm->i2c_addr))
 638                 iounmap(cpm->i2c_ram);
 639         if (cpm->version == 2)
 640                 cpm_muram_free(cpm->i2c_addr);
 641 }
 642
 643 static int cpm_i2c_probe(struct platform_device *ofdev)
 644 {
 645         int result, len;
 646         struct cpm_i2c *cpm;
 647         const u32 *data;
 648
 649         cpm = kzalloc(sizeof(struct cpm_i2c), GFP_KERNEL);
 650         if (!cpm)
 651                 return -ENOMEM;
 652
 653         cpm->ofdev = ofdev;
 654
 655         platform_set_drvdata(ofdev, cpm);
 656
 657         cpm->adap = cpm_ops;
 658         i2c_set_adapdata(&cpm->adap, cpm);
 659         cpm->adap.dev.parent = &ofdev->dev;
 660         cpm->adap.dev.of_node = of_node_get(ofdev->dev.of_node);
 661
 662         result = cpm_i2c_setup(cpm);
 663         if (result) {
 664                 dev_err(&ofdev->dev, "Unable to init hardware\n");
 665                 goto out_free;
 666         }
 667
 668         /* register new adapter to i2c module... */
 669
 670         data = of_get_property(ofdev->dev.of_node, "linux,i2c-index", &len);
 671         cpm->adap.nr = (data && len == 4) ? be32_to_cpup(data) : -1;
 672         result = i2c_add_numbered_adapter(&cpm->adap);
 673
 674         if (result < 0) {
 675                 dev_err(&ofdev->dev, "Unable to register with I2C\n");
 676                 goto out_shut;
 677         }
 678
 679         dev_dbg(&ofdev->dev, "hw routines for %s registered.\n",
 680                 cpm->adap.name);
 681
 682         return 0;
 683 out_shut:
 684         cpm_i2c_shutdown(cpm);
 685 out_free:
 686         kfree(cpm);
 687
 688         return result;
 689 }
 690
 691 static int cpm_i2c_remove(struct platform_device *ofdev)
 692 {
 693         struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
 694
 695         i2c_del_adapter(&cpm->adap);
 696
 697         cpm_i2c_shutdown(cpm);
 698
 699         kfree(cpm);
 700
 701         return 0;
 702 }
 703
 704 static const struct of_device_id cpm_i2c_match[] = {
 705         {
 706                 .compatible = "fsl,cpm1-i2c",
 707         },
 708         {
 709                 .compatible = "fsl,cpm2-i2c",
 710         },
 711         {},
 712 };
 713
 714 MODULE_DEVICE_TABLE(of, cpm_i2c_match);
 715
 716 static struct platform_driver cpm_i2c_driver = {
 717         .probe          = cpm_i2c_probe,
 718         .remove         = cpm_i2c_remove,
 719         .driver = {
 720                 .name = "fsl-i2c-cpm",
 721                 .owner = THIS_MODULE,
 722                 .of_match_table = cpm_i2c_match,
 723         },
 724 };
 725
 726 module_platform_driver(cpm_i2c_driver);
 727
 728 MODULE_AUTHOR("Jochen Friedrich <jochen@scram.de>");
 729 MODULE_DESCRIPTION("I2C-Bus adapter routines for CPM boards");
 730 MODULE_LICENSE("GPL");