Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36 /**
  37  * radeon_driver_unload_kms - Main unload function for KMS.
  38  *
  39  * @dev: drm dev pointer
  40  *
  41  * This is the main unload function for KMS (all asics).
  42  * It calls radeon_modeset_fini() to tear down the
  43  * displays, and radeon_device_fini() to tear down
  44  * the rest of the device (CP, writeback, etc.).
  45  * Returns 0 on success.
  46  */
  47 int radeon_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct radeon_device *rdev = dev->dev_private;
  50
  51         if (rdev == NULL)
  52                 return 0;
  53
  54         if (rdev->rmmio == NULL)
  55                 goto done_free;
  56
  57         pm_runtime_get_sync(dev->dev);
  58
  59         radeon_acpi_fini(rdev);
  60
  61         radeon_modeset_fini(rdev);
  62         radeon_device_fini(rdev);
  63
  64 done_free:
  65         kfree(rdev);
  66         dev->dev_private = NULL;
  67         return 0;
  68 }
  69
  70 /**
  71  * radeon_driver_load_kms - Main load function for KMS.
  72  *
  73  * @dev: drm dev pointer
  74  * @flags: device flags
  75  *
  76  * This is the main load function for KMS (all asics).
  77  * It calls radeon_device_init() to set up the non-display
  78  * parts of the chip (asic init, CP, writeback, etc.), and
  79  * radeon_modeset_init() to set up the display parts
  80  * (crtcs, encoders, hotplug detect, etc.).
  81  * Returns 0 on success, error on failure.
  82  */
  83 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  84 {
  85         struct radeon_device *rdev;
  86         int r, acpi_status;
  87
  88         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  89         if (rdev == NULL) {
  90                 return -ENOMEM;
  91         }
  92         dev->dev_private = (void *)rdev;
  93
  94         /* update BUS flag */
  95         if (drm_pci_device_is_agp(dev)) {
  96                 flags |= RADEON_IS_AGP;
  97         } else if (pci_is_pcie(dev->pdev)) {
  98                 flags |= RADEON_IS_PCIE;
  99         } else {
 100                 flags |= RADEON_IS_PCI;
 101         }
 102
 103         /* radeon_device_init should report only fatal error
 104          * like memory allocation failure or iomapping failure,
 105          * or memory manager initialization failure, it must
 106          * properly initialize the GPU MC controller and permit
 107          * VRAM allocation
 108          */
 109         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 110         if (r) {
 111                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 112                 goto out;
 113         }
 114
 115         /* Again modeset_init should fail only on fatal error
 116          * otherwise it should provide enough functionalities
 117          * for shadowfb to run
 118          */
 119         r = radeon_modeset_init(rdev);
 120         if (r)
 121                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 122
 123         /* Call ACPI methods: require modeset init
 124          * but failure is not fatal
 125          */
 126         if (!r) {
 127                 acpi_status = radeon_acpi_init(rdev);
 128                 if (acpi_status)
 129                 dev_dbg(&dev->pdev->dev,
 130                                 "Error during ACPI methods call\n");
 131         }
 132
 133         if (radeon_runtime_pm != 0) {
 134                 pm_runtime_use_autosuspend(dev->dev);
 135                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 136                 pm_runtime_set_active(dev->dev);
 137                 pm_runtime_allow(dev->dev);
 138                 pm_runtime_mark_last_busy(dev->dev);
 139                 pm_runtime_put_autosuspend(dev->dev);
 140         }
 141
 142 out:
 143         if (r)
 144                 radeon_driver_unload_kms(dev);
 145
 146
 147         return r;
 148 }
 149
 150 /**
 151  * radeon_set_filp_rights - Set filp right.
 152  *
 153  * @dev: drm dev pointer
 154  * @owner: drm file
 155  * @applier: drm file
 156  * @value: value
 157  *
 158  * Sets the filp rights for the device (all asics).
 159  */
 160 static void radeon_set_filp_rights(struct drm_device *dev,
 161                                    struct drm_file **owner,
 162                                    struct drm_file *applier,
 163                                    uint32_t *value)
 164 {
 165         mutex_lock(&dev->struct_mutex);
 166         if (*value == 1) {
 167                 /* wants rights */
 168                 if (!*owner)
 169                         *owner = applier;
 170         } else if (*value == 0) {
 171                 /* revokes rights */
 172                 if (*owner == applier)
 173                         *owner = NULL;
 174         }
 175         *value = *owner == applier ? 1 : 0;
 176         mutex_unlock(&dev->struct_mutex);
 177 }
 178
 179 /*
 180  * Userspace get information ioctl
 181  */
 182 /**
 183  * radeon_info_ioctl - answer a device specific request.
 184  *
 185  * @rdev: radeon device pointer
 186  * @data: request object
 187  * @filp: drm filp
 188  *
 189  * This function is used to pass device specific parameters to the userspace
 190  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 191  * etc. (all asics).
 192  * Returns 0 on success, -EINVAL on failure.
 193  */
 194 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 195 {
 196         struct radeon_device *rdev = dev->dev_private;
 197         struct drm_radeon_info *info = data;
 198         struct radeon_mode_info *minfo = &rdev->mode_info;
 199         uint32_t *value, value_tmp, *value_ptr, value_size;
 200         uint64_t value64;
 201         struct drm_crtc *crtc;
 202         int i, found;
 203
 204         value_ptr = (uint32_t *)((unsigned long)info->value);
 205         value = &value_tmp;
 206         value_size = sizeof(uint32_t);
 207
 208         switch (info->request) {
 209         case RADEON_INFO_DEVICE_ID:
 210                 *value = dev->pdev->device;
 211                 break;
 212         case RADEON_INFO_NUM_GB_PIPES:
 213                 *value = rdev->num_gb_pipes;
 214                 break;
 215         case RADEON_INFO_NUM_Z_PIPES:
 216                 *value = rdev->num_z_pipes;
 217                 break;
 218         case RADEON_INFO_ACCEL_WORKING:
 219                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 220                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 221                         *value = false;
 222                 else
 223                         *value = rdev->accel_working;
 224                 break;
 225         case RADEON_INFO_CRTC_FROM_ID:
 226                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 227                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 228                         return -EFAULT;
 229                 }
 230                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 231                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 232                         if (crtc && crtc->base.id == *value) {
 233                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 234                                 *value = radeon_crtc->crtc_id;
 235                                 found = 1;
 236                                 break;
 237                         }
 238                 }
 239                 if (!found) {
 240                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 241                         return -EINVAL;
 242                 }
 243                 break;
 244         case RADEON_INFO_ACCEL_WORKING2:
 245                 *value = rdev->accel_working;
 246                 break;
 247         case RADEON_INFO_TILING_CONFIG:
 248                 if (rdev->family >= CHIP_BONAIRE)
 249                         *value = rdev->config.cik.tile_config;
 250                 else if (rdev->family >= CHIP_TAHITI)
 251                         *value = rdev->config.si.tile_config;
 252                 else if (rdev->family >= CHIP_CAYMAN)
 253                         *value = rdev->config.cayman.tile_config;
 254                 else if (rdev->family >= CHIP_CEDAR)
 255                         *value = rdev->config.evergreen.tile_config;
 256                 else if (rdev->family >= CHIP_RV770)
 257                         *value = rdev->config.rv770.tile_config;
 258                 else if (rdev->family >= CHIP_R600)
 259                         *value = rdev->config.r600.tile_config;
 260                 else {
 261                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 262                         return -EINVAL;
 263                 }
 264                 break;
 265         case RADEON_INFO_WANT_HYPERZ:
 266                 /* The "value" here is both an input and output parameter.
 267                  * If the input value is 1, filp requests hyper-z access.
 268                  * If the input value is 0, filp revokes its hyper-z access.
 269                  *
 270                  * When returning, the value is 1 if filp owns hyper-z access,
 271                  * 0 otherwise. */
 272                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 273                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 274                         return -EFAULT;
 275                 }
 276                 if (*value >= 2) {
 277                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 278                         return -EINVAL;
 279                 }
 280                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 281                 break;
 282         case RADEON_INFO_WANT_CMASK:
 283                 /* The same logic as Hyper-Z. */
 284                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 285                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 286                         return -EFAULT;
 287                 }
 288                 if (*value >= 2) {
 289                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 290                         return -EINVAL;
 291                 }
 292                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 293                 break;
 294         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 295                 /* return clock value in KHz */
 296                 if (rdev->asic->get_xclk)
 297                         *value = radeon_get_xclk(rdev) * 10;
 298                 else
 299                         *value = rdev->clock.spll.reference_freq * 10;
 300                 break;
 301         case RADEON_INFO_NUM_BACKENDS:
 302                 if (rdev->family >= CHIP_BONAIRE)
 303                         *value = rdev->config.cik.max_backends_per_se *
 304                                 rdev->config.cik.max_shader_engines;
 305                 else if (rdev->family >= CHIP_TAHITI)
 306                         *value = rdev->config.si.max_backends_per_se *
 307                                 rdev->config.si.max_shader_engines;
 308                 else if (rdev->family >= CHIP_CAYMAN)
 309                         *value = rdev->config.cayman.max_backends_per_se *
 310                                 rdev->config.cayman.max_shader_engines;
 311                 else if (rdev->family >= CHIP_CEDAR)
 312                         *value = rdev->config.evergreen.max_backends;
 313                 else if (rdev->family >= CHIP_RV770)
 314                         *value = rdev->config.rv770.max_backends;
 315                 else if (rdev->family >= CHIP_R600)
 316                         *value = rdev->config.r600.max_backends;
 317                 else {
 318                         return -EINVAL;
 319                 }
 320                 break;
 321         case RADEON_INFO_NUM_TILE_PIPES:
 322                 if (rdev->family >= CHIP_BONAIRE)
 323                         *value = rdev->config.cik.max_tile_pipes;
 324                 else if (rdev->family >= CHIP_TAHITI)
 325                         *value = rdev->config.si.max_tile_pipes;
 326                 else if (rdev->family >= CHIP_CAYMAN)
 327                         *value = rdev->config.cayman.max_tile_pipes;
 328                 else if (rdev->family >= CHIP_CEDAR)
 329                         *value = rdev->config.evergreen.max_tile_pipes;
 330                 else if (rdev->family >= CHIP_RV770)
 331                         *value = rdev->config.rv770.max_tile_pipes;
 332                 else if (rdev->family >= CHIP_R600)
 333                         *value = rdev->config.r600.max_tile_pipes;
 334                 else {
 335                         return -EINVAL;
 336                 }
 337                 break;
 338         case RADEON_INFO_FUSION_GART_WORKING:
 339                 *value = 1;
 340                 break;
 341         case RADEON_INFO_BACKEND_MAP:
 342                 if (rdev->family >= CHIP_BONAIRE)
 343                         *value = rdev->config.cik.backend_map;
 344                 else if (rdev->family >= CHIP_TAHITI)
 345                         *value = rdev->config.si.backend_map;
 346                 else if (rdev->family >= CHIP_CAYMAN)
 347                         *value = rdev->config.cayman.backend_map;
 348                 else if (rdev->family >= CHIP_CEDAR)
 349                         *value = rdev->config.evergreen.backend_map;
 350                 else if (rdev->family >= CHIP_RV770)
 351                         *value = rdev->config.rv770.backend_map;
 352                 else if (rdev->family >= CHIP_R600)
 353                         *value = rdev->config.r600.backend_map;
 354                 else {
 355                         return -EINVAL;
 356                 }
 357                 break;
 358         case RADEON_INFO_VA_START:
 359                 /* this is where we report if vm is supported or not */
 360                 if (rdev->family < CHIP_CAYMAN)
 361                         return -EINVAL;
 362                 *value = RADEON_VA_RESERVED_SIZE;
 363                 break;
 364         case RADEON_INFO_IB_VM_MAX_SIZE:
 365                 /* this is where we report if vm is supported or not */
 366                 if (rdev->family < CHIP_CAYMAN)
 367                         return -EINVAL;
 368                 *value = RADEON_IB_VM_MAX_SIZE;
 369                 break;
 370         case RADEON_INFO_MAX_PIPES:
 371                 if (rdev->family >= CHIP_BONAIRE)
 372                         *value = rdev->config.cik.max_cu_per_sh;
 373                 else if (rdev->family >= CHIP_TAHITI)
 374                         *value = rdev->config.si.max_cu_per_sh;
 375                 else if (rdev->family >= CHIP_CAYMAN)
 376                         *value = rdev->config.cayman.max_pipes_per_simd;
 377                 else if (rdev->family >= CHIP_CEDAR)
 378                         *value = rdev->config.evergreen.max_pipes;
 379                 else if (rdev->family >= CHIP_RV770)
 380                         *value = rdev->config.rv770.max_pipes;
 381                 else if (rdev->family >= CHIP_R600)
 382                         *value = rdev->config.r600.max_pipes;
 383                 else {
 384                         return -EINVAL;
 385                 }
 386                 break;
 387         case RADEON_INFO_TIMESTAMP:
 388                 if (rdev->family < CHIP_R600) {
 389                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 390                         return -EINVAL;
 391                 }
 392                 value = (uint32_t*)&value64;
 393                 value_size = sizeof(uint64_t);
 394                 value64 = radeon_get_gpu_clock_counter(rdev);
 395                 break;
 396         case RADEON_INFO_MAX_SE:
 397                 if (rdev->family >= CHIP_BONAIRE)
 398                         *value = rdev->config.cik.max_shader_engines;
 399                 else if (rdev->family >= CHIP_TAHITI)
 400                         *value = rdev->config.si.max_shader_engines;
 401                 else if (rdev->family >= CHIP_CAYMAN)
 402                         *value = rdev->config.cayman.max_shader_engines;
 403                 else if (rdev->family >= CHIP_CEDAR)
 404                         *value = rdev->config.evergreen.num_ses;
 405                 else
 406                         *value = 1;
 407                 break;
 408         case RADEON_INFO_MAX_SH_PER_SE:
 409                 if (rdev->family >= CHIP_BONAIRE)
 410                         *value = rdev->config.cik.max_sh_per_se;
 411                 else if (rdev->family >= CHIP_TAHITI)
 412                         *value = rdev->config.si.max_sh_per_se;
 413                 else
 414                         return -EINVAL;
 415                 break;
 416         case RADEON_INFO_FASTFB_WORKING:
 417                 *value = rdev->fastfb_working;
 418                 break;
 419         case RADEON_INFO_RING_WORKING:
 420                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 421                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 422                         return -EFAULT;
 423                 }
 424                 switch (*value) {
 425                 case RADEON_CS_RING_GFX:
 426                 case RADEON_CS_RING_COMPUTE:
 427                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 428                         break;
 429                 case RADEON_CS_RING_DMA:
 430                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 431                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 432                         break;
 433                 case RADEON_CS_RING_UVD:
 434                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 435                         break;
 436                 default:
 437                         return -EINVAL;
 438                 }
 439                 break;
 440         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 441                 if (rdev->family >= CHIP_BONAIRE) {
 442                         value = rdev->config.cik.tile_mode_array;
 443                         value_size = sizeof(uint32_t)*32;
 444                 } else if (rdev->family >= CHIP_TAHITI) {
 445                         value = rdev->config.si.tile_mode_array;
 446                         value_size = sizeof(uint32_t)*32;
 447                 } else {
 448                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 449                         return -EINVAL;
 450                 }
 451                 break;
 452         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 453                 if (rdev->family >= CHIP_BONAIRE) {
 454                         value = rdev->config.cik.macrotile_mode_array;
 455                         value_size = sizeof(uint32_t)*16;
 456                 } else {
 457                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 458                         return -EINVAL;
 459                 }
 460                 break;
 461         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 462                 *value = 1;
 463                 break;
 464         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 465                 if (rdev->family >= CHIP_BONAIRE) {
 466                         *value = rdev->config.cik.backend_enable_mask;
 467                 } else if (rdev->family >= CHIP_TAHITI) {
 468                         *value = rdev->config.si.backend_enable_mask;
 469                 } else {
 470                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 471                 }
 472                 break;
 473         case RADEON_INFO_MAX_SCLK:
 474                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 475                     rdev->pm.dpm_enabled)
 476                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 477                 else
 478                         *value = rdev->pm.default_sclk * 10;
 479                 break;
 480         default:
 481                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 482                 return -EINVAL;
 483         }
 484         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 485                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 486                 return -EFAULT;
 487         }
 488         return 0;
 489 }
 490
 491
 492 /*
 493  * Outdated mess for old drm with Xorg being in charge (void function now).
 494  */
 495 /**
 496  * radeon_driver_firstopen_kms - drm callback for last close
 497  *
 498  * @dev: drm dev pointer
 499  *
 500  * Switch vga switcheroo state after last close (all asics).
 501  */
 502 void radeon_driver_lastclose_kms(struct drm_device *dev)
 503 {
 504         vga_switcheroo_process_delayed_switch();
 505 }
 506
 507 /**
 508  * radeon_driver_open_kms - drm callback for open
 509  *
 510  * @dev: drm dev pointer
 511  * @file_priv: drm file
 512  *
 513  * On device open, init vm on cayman+ (all asics).
 514  * Returns 0 on success, error on failure.
 515  */
 516 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 517 {
 518         struct radeon_device *rdev = dev->dev_private;
 519         int r;
 520
 521         file_priv->driver_priv = NULL;
 522
 523         r = pm_runtime_get_sync(dev->dev);
 524         if (r < 0)
 525                 return r;
 526
 527         /* new gpu have virtual address space support */
 528         if (rdev->family >= CHIP_CAYMAN) {
 529                 struct radeon_fpriv *fpriv;
 530                 struct radeon_bo_va *bo_va;
 531                 int r;
 532
 533                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 534                 if (unlikely(!fpriv)) {
 535                         return -ENOMEM;
 536                 }
 537
 538                 radeon_vm_init(rdev, &fpriv->vm);
 539
 540                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 541                 if (r)
 542                         return r;
 543
 544                 /* map the ib pool buffer read only into
 545                  * virtual address space */
 546                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 547                                          rdev->ring_tmp_bo.bo);
 548                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 549                                           RADEON_VM_PAGE_READABLE |
 550                                           RADEON_VM_PAGE_SNOOPED);
 551
 552                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 553                 if (r) {
 554                         radeon_vm_fini(rdev, &fpriv->vm);
 555                         kfree(fpriv);
 556                         return r;
 557                 }
 558
 559                 file_priv->driver_priv = fpriv;
 560         }
 561
 562         pm_runtime_mark_last_busy(dev->dev);
 563         pm_runtime_put_autosuspend(dev->dev);
 564         return 0;
 565 }
 566
 567 /**
 568  * radeon_driver_postclose_kms - drm callback for post close
 569  *
 570  * @dev: drm dev pointer
 571  * @file_priv: drm file
 572  *
 573  * On device post close, tear down vm on cayman+ (all asics).
 574  */
 575 void radeon_driver_postclose_kms(struct drm_device *dev,
 576                                  struct drm_file *file_priv)
 577 {
 578         struct radeon_device *rdev = dev->dev_private;
 579
 580         /* new gpu have virtual address space support */
 581         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 582                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 583                 struct radeon_bo_va *bo_va;
 584                 int r;
 585
 586                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 587                 if (!r) {
 588                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 589                                                   rdev->ring_tmp_bo.bo);
 590                         if (bo_va)
 591                                 radeon_vm_bo_rmv(rdev, bo_va);
 592                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 593                 }
 594
 595                 radeon_vm_fini(rdev, &fpriv->vm);
 596                 kfree(fpriv);
 597                 file_priv->driver_priv = NULL;
 598         }
 599 }
 600
 601 /**
 602  * radeon_driver_preclose_kms - drm callback for pre close
 603  *
 604  * @dev: drm dev pointer
 605  * @file_priv: drm file
 606  *
 607  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 608  * (all asics).
 609  */
 610 void radeon_driver_preclose_kms(struct drm_device *dev,
 611                                 struct drm_file *file_priv)
 612 {
 613         struct radeon_device *rdev = dev->dev_private;
 614         if (rdev->hyperz_filp == file_priv)
 615                 rdev->hyperz_filp = NULL;
 616         if (rdev->cmask_filp == file_priv)
 617                 rdev->cmask_filp = NULL;
 618         radeon_uvd_free_handles(rdev, file_priv);
 619 }
 620
 621 /*
 622  * VBlank related functions.
 623  */
 624 /**
 625  * radeon_get_vblank_counter_kms - get frame count
 626  *
 627  * @dev: drm dev pointer
 628  * @crtc: crtc to get the frame count from
 629  *
 630  * Gets the frame count on the requested crtc (all asics).
 631  * Returns frame count on success, -EINVAL on failure.
 632  */
 633 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 634 {
 635         struct radeon_device *rdev = dev->dev_private;
 636
 637         if (crtc < 0 || crtc >= rdev->num_crtc) {
 638                 DRM_ERROR("Invalid crtc %d\n", crtc);
 639                 return -EINVAL;
 640         }
 641
 642         return radeon_get_vblank_counter(rdev, crtc);
 643 }
 644
 645 /**
 646  * radeon_enable_vblank_kms - enable vblank interrupt
 647  *
 648  * @dev: drm dev pointer
 649  * @crtc: crtc to enable vblank interrupt for
 650  *
 651  * Enable the interrupt on the requested crtc (all asics).
 652  * Returns 0 on success, -EINVAL on failure.
 653  */
 654 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 655 {
 656         struct radeon_device *rdev = dev->dev_private;
 657         unsigned long irqflags;
 658         int r;
 659
 660         if (crtc < 0 || crtc >= rdev->num_crtc) {
 661                 DRM_ERROR("Invalid crtc %d\n", crtc);
 662                 return -EINVAL;
 663         }
 664
 665         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 666         rdev->irq.crtc_vblank_int[crtc] = true;
 667         r = radeon_irq_set(rdev);
 668         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 669         return r;
 670 }
 671
 672 /**
 673  * radeon_disable_vblank_kms - disable vblank interrupt
 674  *
 675  * @dev: drm dev pointer
 676  * @crtc: crtc to disable vblank interrupt for
 677  *
 678  * Disable the interrupt on the requested crtc (all asics).
 679  */
 680 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 681 {
 682         struct radeon_device *rdev = dev->dev_private;
 683         unsigned long irqflags;
 684
 685         if (crtc < 0 || crtc >= rdev->num_crtc) {
 686                 DRM_ERROR("Invalid crtc %d\n", crtc);
 687                 return;
 688         }
 689
 690         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 691         rdev->irq.crtc_vblank_int[crtc] = false;
 692         radeon_irq_set(rdev);
 693         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 694 }
 695
 696 /**
 697  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 698  *
 699  * @dev: drm dev pointer
 700  * @crtc: crtc to get the timestamp for
 701  * @max_error: max error
 702  * @vblank_time: time value
 703  * @flags: flags passed to the driver
 704  *
 705  * Gets the timestamp on the requested crtc based on the
 706  * scanout position.  (all asics).
 707  * Returns postive status flags on success, negative error on failure.
 708  */
 709 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 710                                     int *max_error,
 711                                     struct timeval *vblank_time,
 712                                     unsigned flags)
 713 {
 714         struct drm_crtc *drmcrtc;
 715         struct radeon_device *rdev = dev->dev_private;
 716
 717         if (crtc < 0 || crtc >= dev->num_crtcs) {
 718                 DRM_ERROR("Invalid crtc %d\n", crtc);
 719                 return -EINVAL;
 720         }
 721
 722         /* Get associated drm_crtc: */
 723         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 724
 725         /* Helper routine in DRM core does all the work: */
 726         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 727                                                      vblank_time, flags,
 728                                                      drmcrtc, &drmcrtc->hwmode);
 729 }
 730
 731 #define KMS_INVALID_IOCTL(name)                                         \
 732 static int name(struct drm_device *dev, void *data, struct drm_file     \
 733                 *file_priv)                                             \
 734 {                                                                       \
 735         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 736         return -EINVAL;                                                 \
 737 }
 738
 739 /*
 740  * All these ioctls are invalid in kms world.
 741  */
 742 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 743 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 744 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 745 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 746 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 747 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 748 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 749 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 750 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 751 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 752 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 753 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 754 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 755 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 756 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 757 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 758 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 759 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 760 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 761 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 762 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 763 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 764 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 765 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 766 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 767 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 768 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 769
 770
 771 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 772         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 773         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 774         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 775         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 776         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 777         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 778         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 779         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 780         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 781         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 782         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 783         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 784         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 785         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 786         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 787         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 788         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 789         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 790         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 791         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 792         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 793         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 794         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 795         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 796         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 797         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 798         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 799         /* KMS */
 800         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 801         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 802         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 803         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 804         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 805         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 806         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 807         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 808         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 809         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 810         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 811         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 812         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 813 };
 814 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);