Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/r300.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include <drm/radeon_drm.h>
  37 #include "r100_track.h"
  38 #include "r300d.h"
  39 #include "rv350d.h"
  40 #include "r300_reg_safe.h"
  41
  42 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  43  *
  44  * GPU Errata:
  45  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  46  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  47  *   However, scheduling such write to the ring seems harmless, i suspect
  48  *   the CP read collide with the flush somehow, or maybe the MC, hard to
  49  *   tell. (Jerome Glisse)
  50  */
  51
  52 /*
  53  * rv370,rv380 PCIE GART
  54  */
  55 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  56
  57 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  58 {
  59         uint32_t tmp;
  60         int i;
  61
  62         /* Workaround HW bug do flush 2 times */
  63         for (i = 0; i < 2; i++) {
  64                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  66                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  67                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  68         }
  69         mb();
  70 }
  71
  72 #define R300_PTE_WRITEABLE (1 << 2)
  73 #define R300_PTE_READABLE  (1 << 3)
  74
  75 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  76 {
  77         void __iomem *ptr = rdev->gart.ptr;
  78
  79         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  80                 return -EINVAL;
  81         }
  82         addr = (lower_32_bits(addr) >> 8) |
  83                ((upper_32_bits(addr) & 0xff) << 24) |
  84                R300_PTE_WRITEABLE | R300_PTE_READABLE;
  85         /* on x86 we want this to be CPU endian, on powerpc
  86          * on powerpc without HW swappers, it'll get swapped on way
  87          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  88         writel(addr, ((void __iomem *)ptr) + (i * 4));
  89         return 0;
  90 }
  91
  92 int rv370_pcie_gart_init(struct radeon_device *rdev)
  93 {
  94         int r;
  95
  96         if (rdev->gart.robj) {
  97                 WARN(1, "RV370 PCIE GART already initialized\n");
  98                 return 0;
  99         }
 100         /* Initialize common gart structure */
 101         r = radeon_gart_init(rdev);
 102         if (r)
 103                 return r;
 104         r = rv370_debugfs_pcie_gart_info_init(rdev);
 105         if (r)
 106                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
 107         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 108         rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 109         rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 110         return radeon_gart_table_vram_alloc(rdev);
 111 }
 112
 113 int rv370_pcie_gart_enable(struct radeon_device *rdev)
 114 {
 115         uint32_t table_addr;
 116         uint32_t tmp;
 117         int r;
 118
 119         if (rdev->gart.robj == NULL) {
 120                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 121                 return -EINVAL;
 122         }
 123         r = radeon_gart_table_vram_pin(rdev);
 124         if (r)
 125                 return r;
 126         radeon_gart_restore(rdev);
 127         /* discard memory request outside of configured range */
 128         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 129         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 130         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
 131         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
 132         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
 133         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 134         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 135         table_addr = rdev->gart.table_addr;
 136         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
 137         /* FIXME: setup default page */
 138         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
 139         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
 140         /* Clear error */
 141         WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
 142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 143         tmp |= RADEON_PCIE_TX_GART_EN;
 144         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 145         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
 146         rv370_pcie_gart_tlb_flush(rdev);
 147         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 148                  (unsigned)(rdev->mc.gtt_size >> 20),
 149                  (unsigned long long)table_addr);
 150         rdev->gart.ready = true;
 151         return 0;
 152 }
 153
 154 void rv370_pcie_gart_disable(struct radeon_device *rdev)
 155 {
 156         u32 tmp;
 157
 158         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
 159         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
 160         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
 161         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
 162         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 163         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
 164         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
 165         radeon_gart_table_vram_unpin(rdev);
 166 }
 167
 168 void rv370_pcie_gart_fini(struct radeon_device *rdev)
 169 {
 170         radeon_gart_fini(rdev);
 171         rv370_pcie_gart_disable(rdev);
 172         radeon_gart_table_vram_free(rdev);
 173 }
 174
 175 void r300_fence_ring_emit(struct radeon_device *rdev,
 176                           struct radeon_fence *fence)
 177 {
 178         struct radeon_ring *ring = &rdev->ring[fence->ring];
 179
 180         /* Who ever call radeon_fence_emit should call ring_lock and ask
 181          * for enough space (today caller are ib schedule and buffer move) */
 182         /* Write SC register so SC & US assert idle */
 183         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
 184         radeon_ring_write(ring, 0);
 185         radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
 186         radeon_ring_write(ring, 0);
 187         /* Flush 3D cache */
 188         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 189         radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
 190         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 191         radeon_ring_write(ring, R300_ZC_FLUSH);
 192         /* Wait until IDLE & CLEAN */
 193         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 194         radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
 195                                  RADEON_WAIT_2D_IDLECLEAN |
 196                                  RADEON_WAIT_DMA_GUI_IDLE));
 197         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 198         radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
 199                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 200         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 201         radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
 202         /* Emit fence sequence & fire IRQ */
 203         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 204         radeon_ring_write(ring, fence->seq);
 205         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 206         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 207 }
 208
 209 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 210 {
 211         unsigned gb_tile_config;
 212         int r;
 213
 214         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
 215         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 216         switch(rdev->num_gb_pipes) {
 217         case 2:
 218                 gb_tile_config |= R300_PIPE_COUNT_R300;
 219                 break;
 220         case 3:
 221                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 222                 break;
 223         case 4:
 224                 gb_tile_config |= R300_PIPE_COUNT_R420;
 225                 break;
 226         case 1:
 227         default:
 228                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 229                 break;
 230         }
 231
 232         r = radeon_ring_lock(rdev, ring, 64);
 233         if (r) {
 234                 return;
 235         }
 236         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 237         radeon_ring_write(ring,
 238                           RADEON_ISYNC_ANY2D_IDLE3D |
 239                           RADEON_ISYNC_ANY3D_IDLE2D |
 240                           RADEON_ISYNC_WAIT_IDLEGUI |
 241                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 242         radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
 243         radeon_ring_write(ring, gb_tile_config);
 244         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 245         radeon_ring_write(ring,
 246                           RADEON_WAIT_2D_IDLECLEAN |
 247                           RADEON_WAIT_3D_IDLECLEAN);
 248         radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
 249         radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
 250         radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
 251         radeon_ring_write(ring, 0);
 252         radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
 253         radeon_ring_write(ring, 0);
 254         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 255         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 256         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 257         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 258         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 259         radeon_ring_write(ring,
 260                           RADEON_WAIT_2D_IDLECLEAN |
 261                           RADEON_WAIT_3D_IDLECLEAN);
 262         radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
 263         radeon_ring_write(ring, 0);
 264         radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
 265         radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
 266         radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
 267         radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
 268         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
 269         radeon_ring_write(ring,
 270                           ((6 << R300_MS_X0_SHIFT) |
 271                            (6 << R300_MS_Y0_SHIFT) |
 272                            (6 << R300_MS_X1_SHIFT) |
 273                            (6 << R300_MS_Y1_SHIFT) |
 274                            (6 << R300_MS_X2_SHIFT) |
 275                            (6 << R300_MS_Y2_SHIFT) |
 276                            (6 << R300_MSBD0_Y_SHIFT) |
 277                            (6 << R300_MSBD0_X_SHIFT)));
 278         radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
 279         radeon_ring_write(ring,
 280                           ((6 << R300_MS_X3_SHIFT) |
 281                            (6 << R300_MS_Y3_SHIFT) |
 282                            (6 << R300_MS_X4_SHIFT) |
 283                            (6 << R300_MS_Y4_SHIFT) |
 284                            (6 << R300_MS_X5_SHIFT) |
 285                            (6 << R300_MS_Y5_SHIFT) |
 286                            (6 << R300_MSBD1_SHIFT)));
 287         radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
 288         radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
 289         radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
 290         radeon_ring_write(ring,
 291                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
 292         radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
 293         radeon_ring_write(ring,
 294                           R300_GEOMETRY_ROUND_NEAREST |
 295                           R300_COLOR_ROUND_NEAREST);
 296         radeon_ring_unlock_commit(rdev, ring);
 297 }
 298
 299 static void r300_errata(struct radeon_device *rdev)
 300 {
 301         rdev->pll_errata = 0;
 302
 303         if (rdev->family == CHIP_R300 &&
 304             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
 305                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
 306         }
 307 }
 308
 309 int r300_mc_wait_for_idle(struct radeon_device *rdev)
 310 {
 311         unsigned i;
 312         uint32_t tmp;
 313
 314         for (i = 0; i < rdev->usec_timeout; i++) {
 315                 /* read MC_STATUS */
 316                 tmp = RREG32(RADEON_MC_STATUS);
 317                 if (tmp & R300_MC_IDLE) {
 318                         return 0;
 319                 }
 320                 DRM_UDELAY(1);
 321         }
 322         return -1;
 323 }
 324
 325 static void r300_gpu_init(struct radeon_device *rdev)
 326 {
 327         uint32_t gb_tile_config, tmp;
 328
 329         if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
 330             (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
 331                 /* r300,r350 */
 332                 rdev->num_gb_pipes = 2;
 333         } else {
 334                 /* rv350,rv370,rv380,r300 AD, r350 AH */
 335                 rdev->num_gb_pipes = 1;
 336         }
 337         rdev->num_z_pipes = 1;
 338         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
 339         switch (rdev->num_gb_pipes) {
 340         case 2:
 341                 gb_tile_config |= R300_PIPE_COUNT_R300;
 342                 break;
 343         case 3:
 344                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
 345                 break;
 346         case 4:
 347                 gb_tile_config |= R300_PIPE_COUNT_R420;
 348                 break;
 349         default:
 350         case 1:
 351                 gb_tile_config |= R300_PIPE_COUNT_RV350;
 352                 break;
 353         }
 354         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 355
 356         if (r100_gui_wait_for_idle(rdev)) {
 357                 printk(KERN_WARNING "Failed to wait GUI idle while "
 358                        "programming pipes. Bad things might happen.\n");
 359         }
 360
 361         tmp = RREG32(R300_DST_PIPE_CONFIG);
 362         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
 363
 364         WREG32(R300_RB2D_DSTCACHE_MODE,
 365                R300_DC_AUTOFLUSH_ENABLE |
 366                R300_DC_DC_DISABLE_IGNORE_PE);
 367
 368         if (r100_gui_wait_for_idle(rdev)) {
 369                 printk(KERN_WARNING "Failed to wait GUI idle while "
 370                        "programming pipes. Bad things might happen.\n");
 371         }
 372         if (r300_mc_wait_for_idle(rdev)) {
 373                 printk(KERN_WARNING "Failed to wait MC idle while "
 374                        "programming pipes. Bad things might happen.\n");
 375         }
 376         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
 377                  rdev->num_gb_pipes, rdev->num_z_pipes);
 378 }
 379
 380 int r300_asic_reset(struct radeon_device *rdev)
 381 {
 382         struct r100_mc_save save;
 383         u32 status, tmp;
 384         int ret = 0;
 385
 386         status = RREG32(R_000E40_RBBM_STATUS);
 387         if (!G_000E40_GUI_ACTIVE(status)) {
 388                 return 0;
 389         }
 390         r100_mc_stop(rdev, &save);
 391         status = RREG32(R_000E40_RBBM_STATUS);
 392         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 393         /* stop CP */
 394         WREG32(RADEON_CP_CSQ_CNTL, 0);
 395         tmp = RREG32(RADEON_CP_RB_CNTL);
 396         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
 397         WREG32(RADEON_CP_RB_RPTR_WR, 0);
 398         WREG32(RADEON_CP_RB_WPTR, 0);
 399         WREG32(RADEON_CP_RB_CNTL, tmp);
 400         /* save PCI state */
 401         pci_save_state(rdev->pdev);
 402         /* disable bus mastering */
 403         r100_bm_disable(rdev);
 404         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
 405                                         S_0000F0_SOFT_RESET_GA(1));
 406         RREG32(R_0000F0_RBBM_SOFT_RESET);
 407         mdelay(500);
 408         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 409         mdelay(1);
 410         status = RREG32(R_000E40_RBBM_STATUS);
 411         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 412         /* resetting the CP seems to be problematic sometimes it end up
 413          * hard locking the computer, but it's necessary for successful
 414          * reset more test & playing is needed on R3XX/R4XX to find a
 415          * reliable (if any solution)
 416          */
 417         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
 418         RREG32(R_0000F0_RBBM_SOFT_RESET);
 419         mdelay(500);
 420         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
 421         mdelay(1);
 422         status = RREG32(R_000E40_RBBM_STATUS);
 423         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
 424         /* restore PCI & busmastering */
 425         pci_restore_state(rdev->pdev);
 426         r100_enable_bm(rdev);
 427         /* Check if GPU is idle */
 428         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
 429                 dev_err(rdev->dev, "failed to reset GPU\n");
 430                 ret = -1;
 431         } else
 432                 dev_info(rdev->dev, "GPU reset succeed\n");
 433         r100_mc_resume(rdev, &save);
 434         return ret;
 435 }
 436
 437 /*
 438  * r300,r350,rv350,rv380 VRAM info
 439  */
 440 void r300_mc_init(struct radeon_device *rdev)
 441 {
 442         u64 base;
 443         u32 tmp;
 444
 445         /* DDR for all card after R300 & IGP */
 446         rdev->mc.vram_is_ddr = true;
 447         tmp = RREG32(RADEON_MEM_CNTL);
 448         tmp &= R300_MEM_NUM_CHANNELS_MASK;
 449         switch (tmp) {
 450         case 0: rdev->mc.vram_width = 64; break;
 451         case 1: rdev->mc.vram_width = 128; break;
 452         case 2: rdev->mc.vram_width = 256; break;
 453         default:  rdev->mc.vram_width = 128; break;
 454         }
 455         r100_vram_init_sizes(rdev);
 456         base = rdev->mc.aper_base;
 457         if (rdev->flags & RADEON_IS_IGP)
 458                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
 459         radeon_vram_location(rdev, &rdev->mc, base);
 460         rdev->mc.gtt_base_align = 0;
 461         if (!(rdev->flags & RADEON_IS_AGP))
 462                 radeon_gtt_location(rdev, &rdev->mc);
 463         radeon_update_bandwidth_info(rdev);
 464 }
 465
 466 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
 467 {
 468         uint32_t link_width_cntl, mask;
 469
 470         if (rdev->flags & RADEON_IS_IGP)
 471                 return;
 472
 473         if (!(rdev->flags & RADEON_IS_PCIE))
 474                 return;
 475
 476         /* FIXME wait for idle */
 477
 478         switch (lanes) {
 479         case 0:
 480                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
 481                 break;
 482         case 1:
 483                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
 484                 break;
 485         case 2:
 486                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
 487                 break;
 488         case 4:
 489                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
 490                 break;
 491         case 8:
 492                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
 493                 break;
 494         case 12:
 495                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
 496                 break;
 497         case 16:
 498         default:
 499                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
 500                 break;
 501         }
 502
 503         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 504
 505         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
 506             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
 507                 return;
 508
 509         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
 510                              RADEON_PCIE_LC_RECONFIG_NOW |
 511                              RADEON_PCIE_LC_RECONFIG_LATER |
 512                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
 513         link_width_cntl |= mask;
 514         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 515         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
 516                                                      RADEON_PCIE_LC_RECONFIG_NOW));
 517
 518         /* wait for lane set to complete */
 519         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 520         while (link_width_cntl == 0xffffffff)
 521                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 522
 523 }
 524
 525 int rv370_get_pcie_lanes(struct radeon_device *rdev)
 526 {
 527         u32 link_width_cntl;
 528
 529         if (rdev->flags & RADEON_IS_IGP)
 530                 return 0;
 531
 532         if (!(rdev->flags & RADEON_IS_PCIE))
 533                 return 0;
 534
 535         /* FIXME wait for idle */
 536
 537         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 538
 539         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 540         case RADEON_PCIE_LC_LINK_WIDTH_X0:
 541                 return 0;
 542         case RADEON_PCIE_LC_LINK_WIDTH_X1:
 543                 return 1;
 544         case RADEON_PCIE_LC_LINK_WIDTH_X2:
 545                 return 2;
 546         case RADEON_PCIE_LC_LINK_WIDTH_X4:
 547                 return 4;
 548         case RADEON_PCIE_LC_LINK_WIDTH_X8:
 549                 return 8;
 550         case RADEON_PCIE_LC_LINK_WIDTH_X16:
 551         default:
 552                 return 16;
 553         }
 554 }
 555
 556 #if defined(CONFIG_DEBUG_FS)
 557 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
 558 {
 559         struct drm_info_node *node = (struct drm_info_node *) m->private;
 560         struct drm_device *dev = node->minor->dev;
 561         struct radeon_device *rdev = dev->dev_private;
 562         uint32_t tmp;
 563
 564         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
 565         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
 566         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
 567         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
 568         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
 569         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
 570         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
 571         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
 572         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
 573         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
 574         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
 575         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
 576         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
 577         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
 578         return 0;
 579 }
 580
 581 static struct drm_info_list rv370_pcie_gart_info_list[] = {
 582         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
 583 };
 584 #endif
 585
 586 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
 587 {
 588 #if defined(CONFIG_DEBUG_FS)
 589         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
 590 #else
 591         return 0;
 592 #endif
 593 }
 594
 595 static int r300_packet0_check(struct radeon_cs_parser *p,
 596                 struct radeon_cs_packet *pkt,
 597                 unsigned idx, unsigned reg)
 598 {
 599         struct radeon_cs_reloc *reloc;
 600         struct r100_cs_track *track;
 601         volatile uint32_t *ib;
 602         uint32_t tmp, tile_flags = 0;
 603         unsigned i;
 604         int r;
 605         u32 idx_value;
 606
 607         ib = p->ib.ptr;
 608         track = (struct r100_cs_track *)p->track;
 609         idx_value = radeon_get_ib_value(p, idx);
 610
 611         switch(reg) {
 612         case AVIVO_D1MODE_VLINE_START_END:
 613         case RADEON_CRTC_GUI_TRIG_VLINE:
 614                 r = r100_cs_packet_parse_vline(p);
 615                 if (r) {
 616                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 617                                         idx, reg);
 618                         radeon_cs_dump_packet(p, pkt);
 619                         return r;
 620                 }
 621                 break;
 622         case RADEON_DST_PITCH_OFFSET:
 623         case RADEON_SRC_PITCH_OFFSET:
 624                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
 625                 if (r)
 626                         return r;
 627                 break;
 628         case R300_RB3D_COLOROFFSET0:
 629         case R300_RB3D_COLOROFFSET1:
 630         case R300_RB3D_COLOROFFSET2:
 631         case R300_RB3D_COLOROFFSET3:
 632                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
 633                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 634                 if (r) {
 635                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 636                                         idx, reg);
 637                         radeon_cs_dump_packet(p, pkt);
 638                         return r;
 639                 }
 640                 track->cb[i].robj = reloc->robj;
 641                 track->cb[i].offset = idx_value;
 642                 track->cb_dirty = true;
 643                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 644                 break;
 645         case R300_ZB_DEPTHOFFSET:
 646                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 647                 if (r) {
 648                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 649                                         idx, reg);
 650                         radeon_cs_dump_packet(p, pkt);
 651                         return r;
 652                 }
 653                 track->zb.robj = reloc->robj;
 654                 track->zb.offset = idx_value;
 655                 track->zb_dirty = true;
 656                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
 657                 break;
 658         case R300_TX_OFFSET_0:
 659         case R300_TX_OFFSET_0+4:
 660         case R300_TX_OFFSET_0+8:
 661         case R300_TX_OFFSET_0+12:
 662         case R300_TX_OFFSET_0+16:
 663         case R300_TX_OFFSET_0+20:
 664         case R300_TX_OFFSET_0+24:
 665         case R300_TX_OFFSET_0+28:
 666         case R300_TX_OFFSET_0+32:
 667         case R300_TX_OFFSET_0+36:
 668         case R300_TX_OFFSET_0+40:
 669         case R300_TX_OFFSET_0+44:
 670         case R300_TX_OFFSET_0+48:
 671         case R300_TX_OFFSET_0+52:
 672         case R300_TX_OFFSET_0+56:
 673         case R300_TX_OFFSET_0+60:
 674                 i = (reg - R300_TX_OFFSET_0) >> 2;
 675                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 676                 if (r) {
 677                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 678                                         idx, reg);
 679                         radeon_cs_dump_packet(p, pkt);
 680                         return r;
 681                 }
 682
 683                 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
 684                         ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
 685                                   ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset);
 686                 } else {
 687                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 688                                 tile_flags |= R300_TXO_MACRO_TILE;
 689                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 690                                 tile_flags |= R300_TXO_MICRO_TILE;
 691                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 692                                 tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
 693
 694                         tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
 695                         tmp |= tile_flags;
 696                         ib[idx] = tmp;
 697                 }
 698                 track->textures[i].robj = reloc->robj;
 699                 track->tex_dirty = true;
 700                 break;
 701         /* Tracked registers */
 702         case 0x2084:
 703                 /* VAP_VF_CNTL */
 704                 track->vap_vf_cntl = idx_value;
 705                 break;
 706         case 0x20B4:
 707                 /* VAP_VTX_SIZE */
 708                 track->vtx_size = idx_value & 0x7F;
 709                 break;
 710         case 0x2134:
 711                 /* VAP_VF_MAX_VTX_INDX */
 712                 track->max_indx = idx_value & 0x00FFFFFFUL;
 713                 break;
 714         case 0x2088:
 715                 /* VAP_ALT_NUM_VERTICES - only valid on r500 */
 716                 if (p->rdev->family < CHIP_RV515)
 717                         goto fail;
 718                 track->vap_alt_nverts = idx_value & 0xFFFFFF;
 719                 break;
 720         case 0x43E4:
 721                 /* SC_SCISSOR1 */
 722                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
 723                 if (p->rdev->family < CHIP_RV515) {
 724                         track->maxy -= 1440;
 725                 }
 726                 track->cb_dirty = true;
 727                 track->zb_dirty = true;
 728                 break;
 729         case 0x4E00:
 730                 /* RB3D_CCTL */
 731                 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
 732                     p->rdev->cmask_filp != p->filp) {
 733                         DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
 734                         return -EINVAL;
 735                 }
 736                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
 737                 track->cb_dirty = true;
 738                 break;
 739         case 0x4E38:
 740         case 0x4E3C:
 741         case 0x4E40:
 742         case 0x4E44:
 743                 /* RB3D_COLORPITCH0 */
 744                 /* RB3D_COLORPITCH1 */
 745                 /* RB3D_COLORPITCH2 */
 746                 /* RB3D_COLORPITCH3 */
 747                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 748                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 749                         if (r) {
 750                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 751                                           idx, reg);
 752                                 radeon_cs_dump_packet(p, pkt);
 753                                 return r;
 754                         }
 755
 756                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 757                                 tile_flags |= R300_COLOR_TILE_ENABLE;
 758                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 759                                 tile_flags |= R300_COLOR_MICROTILE_ENABLE;
 760                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 761                                 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
 762
 763                         tmp = idx_value & ~(0x7 << 16);
 764                         tmp |= tile_flags;
 765                         ib[idx] = tmp;
 766                 }
 767                 i = (reg - 0x4E38) >> 2;
 768                 track->cb[i].pitch = idx_value & 0x3FFE;
 769                 switch (((idx_value >> 21) & 0xF)) {
 770                 case 9:
 771                 case 11:
 772                 case 12:
 773                         track->cb[i].cpp = 1;
 774                         break;
 775                 case 3:
 776                 case 4:
 777                 case 13:
 778                 case 15:
 779                         track->cb[i].cpp = 2;
 780                         break;
 781                 case 5:
 782                         if (p->rdev->family < CHIP_RV515) {
 783                                 DRM_ERROR("Invalid color buffer format (%d)!\n",
 784                                           ((idx_value >> 21) & 0xF));
 785                                 return -EINVAL;
 786                         }
 787                         /* Pass through. */
 788                 case 6:
 789                         track->cb[i].cpp = 4;
 790                         break;
 791                 case 10:
 792                         track->cb[i].cpp = 8;
 793                         break;
 794                 case 7:
 795                         track->cb[i].cpp = 16;
 796                         break;
 797                 default:
 798                         DRM_ERROR("Invalid color buffer format (%d) !\n",
 799                                   ((idx_value >> 21) & 0xF));
 800                         return -EINVAL;
 801                 }
 802                 track->cb_dirty = true;
 803                 break;
 804         case 0x4F00:
 805                 /* ZB_CNTL */
 806                 if (idx_value & 2) {
 807                         track->z_enabled = true;
 808                 } else {
 809                         track->z_enabled = false;
 810                 }
 811                 track->zb_dirty = true;
 812                 break;
 813         case 0x4F10:
 814                 /* ZB_FORMAT */
 815                 switch ((idx_value & 0xF)) {
 816                 case 0:
 817                 case 1:
 818                         track->zb.cpp = 2;
 819                         break;
 820                 case 2:
 821                         track->zb.cpp = 4;
 822                         break;
 823                 default:
 824                         DRM_ERROR("Invalid z buffer format (%d) !\n",
 825                                   (idx_value & 0xF));
 826                         return -EINVAL;
 827                 }
 828                 track->zb_dirty = true;
 829                 break;
 830         case 0x4F24:
 831                 /* ZB_DEPTHPITCH */
 832                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
 833                         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
 834                         if (r) {
 835                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
 836                                           idx, reg);
 837                                 radeon_cs_dump_packet(p, pkt);
 838                                 return r;
 839                         }
 840
 841                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
 842                                 tile_flags |= R300_DEPTHMACROTILE_ENABLE;
 843                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
 844                                 tile_flags |= R300_DEPTHMICROTILE_TILED;
 845                         else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
 846                                 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
 847
 848                         tmp = idx_value & ~(0x7 << 16);
 849                         tmp |= tile_flags;
 850                         ib[idx] = tmp;
 851                 }
 852                 track->zb.pitch = idx_value & 0x3FFC;
 853                 track->zb_dirty = true;
 854                 break;
 855         case 0x4104:
 856                 /* TX_ENABLE */
 857                 for (i = 0; i < 16; i++) {
 858                         bool enabled;
 859
 860                         enabled = !!(idx_value & (1 << i));
 861                         track->textures[i].enabled = enabled;
 862                 }
 863                 track->tex_dirty = true;
 864                 break;
 865         case 0x44C0:
 866         case 0x44C4:
 867         case 0x44C8:
 868         case 0x44CC:
 869         case 0x44D0:
 870         case 0x44D4:
 871         case 0x44D8:
 872         case 0x44DC:
 873         case 0x44E0:
 874         case 0x44E4:
 875         case 0x44E8:
 876         case 0x44EC:
 877         case 0x44F0:
 878         case 0x44F4:
 879         case 0x44F8:
 880         case 0x44FC:
 881                 /* TX_FORMAT1_[0-15] */
 882                 i = (reg - 0x44C0) >> 2;
 883                 tmp = (idx_value >> 25) & 0x3;
 884                 track->textures[i].tex_coord_type = tmp;
 885                 switch ((idx_value & 0x1F)) {
 886                 case R300_TX_FORMAT_X8:
 887                 case R300_TX_FORMAT_Y4X4:
 888                 case R300_TX_FORMAT_Z3Y3X2:
 889                         track->textures[i].cpp = 1;
 890                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 891                         break;
 892                 case R300_TX_FORMAT_X16:
 893                 case R300_TX_FORMAT_FL_I16:
 894                 case R300_TX_FORMAT_Y8X8:
 895                 case R300_TX_FORMAT_Z5Y6X5:
 896                 case R300_TX_FORMAT_Z6Y5X5:
 897                 case R300_TX_FORMAT_W4Z4Y4X4:
 898                 case R300_TX_FORMAT_W1Z5Y5X5:
 899                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
 900                 case R300_TX_FORMAT_B8G8_B8G8:
 901                 case R300_TX_FORMAT_G8R8_G8B8:
 902                         track->textures[i].cpp = 2;
 903                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 904                         break;
 905                 case R300_TX_FORMAT_Y16X16:
 906                 case R300_TX_FORMAT_FL_I16A16:
 907                 case R300_TX_FORMAT_Z11Y11X10:
 908                 case R300_TX_FORMAT_Z10Y11X11:
 909                 case R300_TX_FORMAT_W8Z8Y8X8:
 910                 case R300_TX_FORMAT_W2Z10Y10X10:
 911                 case 0x17:
 912                 case R300_TX_FORMAT_FL_I32:
 913                 case 0x1e:
 914                         track->textures[i].cpp = 4;
 915                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 916                         break;
 917                 case R300_TX_FORMAT_W16Z16Y16X16:
 918                 case R300_TX_FORMAT_FL_R16G16B16A16:
 919                 case R300_TX_FORMAT_FL_I32A32:
 920                         track->textures[i].cpp = 8;
 921                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 922                         break;
 923                 case R300_TX_FORMAT_FL_R32G32B32A32:
 924                         track->textures[i].cpp = 16;
 925                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
 926                         break;
 927                 case R300_TX_FORMAT_DXT1:
 928                         track->textures[i].cpp = 1;
 929                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
 930                         break;
 931                 case R300_TX_FORMAT_ATI2N:
 932                         if (p->rdev->family < CHIP_R420) {
 933                                 DRM_ERROR("Invalid texture format %u\n",
 934                                           (idx_value & 0x1F));
 935                                 return -EINVAL;
 936                         }
 937                         /* The same rules apply as for DXT3/5. */
 938                         /* Pass through. */
 939                 case R300_TX_FORMAT_DXT3:
 940                 case R300_TX_FORMAT_DXT5:
 941                         track->textures[i].cpp = 1;
 942                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
 943                         break;
 944                 default:
 945                         DRM_ERROR("Invalid texture format %u\n",
 946                                   (idx_value & 0x1F));
 947                         return -EINVAL;
 948                 }
 949                 track->tex_dirty = true;
 950                 break;
 951         case 0x4400:
 952         case 0x4404:
 953         case 0x4408:
 954         case 0x440C:
 955         case 0x4410:
 956         case 0x4414:
 957         case 0x4418:
 958         case 0x441C:
 959         case 0x4420:
 960         case 0x4424:
 961         case 0x4428:
 962         case 0x442C:
 963         case 0x4430:
 964         case 0x4434:
 965         case 0x4438:
 966         case 0x443C:
 967                 /* TX_FILTER0_[0-15] */
 968                 i = (reg - 0x4400) >> 2;
 969                 tmp = idx_value & 0x7;
 970                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 971                         track->textures[i].roundup_w = false;
 972                 }
 973                 tmp = (idx_value >> 3) & 0x7;
 974                 if (tmp == 2 || tmp == 4 || tmp == 6) {
 975                         track->textures[i].roundup_h = false;
 976                 }
 977                 track->tex_dirty = true;
 978                 break;
 979         case 0x4500:
 980         case 0x4504:
 981         case 0x4508:
 982         case 0x450C:
 983         case 0x4510:
 984         case 0x4514:
 985         case 0x4518:
 986         case 0x451C:
 987         case 0x4520:
 988         case 0x4524:
 989         case 0x4528:
 990         case 0x452C:
 991         case 0x4530:
 992         case 0x4534:
 993         case 0x4538:
 994         case 0x453C:
 995                 /* TX_FORMAT2_[0-15] */
 996                 i = (reg - 0x4500) >> 2;
 997                 tmp = idx_value & 0x3FFF;
 998                 track->textures[i].pitch = tmp + 1;
 999                 if (p->rdev->family >= CHIP_RV515) {
1000                         tmp = ((idx_value >> 15) & 1) << 11;
1001                         track->textures[i].width_11 = tmp;
1002                         tmp = ((idx_value >> 16) & 1) << 11;
1003                         track->textures[i].height_11 = tmp;
1004
1005                         /* ATI1N */
1006                         if (idx_value & (1 << 14)) {
1007                                 /* The same rules apply as for DXT1. */
1008                                 track->textures[i].compress_format =
1009                                         R100_TRACK_COMP_DXT1;
1010                         }
1011                 } else if (idx_value & (1 << 14)) {
1012                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
1013                         return -EINVAL;
1014                 }
1015                 track->tex_dirty = true;
1016                 break;
1017         case 0x4480:
1018         case 0x4484:
1019         case 0x4488:
1020         case 0x448C:
1021         case 0x4490:
1022         case 0x4494:
1023         case 0x4498:
1024         case 0x449C:
1025         case 0x44A0:
1026         case 0x44A4:
1027         case 0x44A8:
1028         case 0x44AC:
1029         case 0x44B0:
1030         case 0x44B4:
1031         case 0x44B8:
1032         case 0x44BC:
1033                 /* TX_FORMAT0_[0-15] */
1034                 i = (reg - 0x4480) >> 2;
1035                 tmp = idx_value & 0x7FF;
1036                 track->textures[i].width = tmp + 1;
1037                 tmp = (idx_value >> 11) & 0x7FF;
1038                 track->textures[i].height = tmp + 1;
1039                 tmp = (idx_value >> 26) & 0xF;
1040                 track->textures[i].num_levels = tmp;
1041                 tmp = idx_value & (1 << 31);
1042                 track->textures[i].use_pitch = !!tmp;
1043                 tmp = (idx_value >> 22) & 0xF;
1044                 track->textures[i].txdepth = tmp;
1045                 track->tex_dirty = true;
1046                 break;
1047         case R300_ZB_ZPASS_ADDR:
1048                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1049                 if (r) {
1050                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1051                                         idx, reg);
1052                         radeon_cs_dump_packet(p, pkt);
1053                         return r;
1054                 }
1055                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1056                 break;
1057         case 0x4e0c:
1058                 /* RB3D_COLOR_CHANNEL_MASK */
1059                 track->color_channel_mask = idx_value;
1060                 track->cb_dirty = true;
1061                 break;
1062         case 0x43a4:
1063                 /* SC_HYPERZ_EN */
1064                 /* r300c emits this register - we need to disable hyperz for it
1065                  * without complaining */
1066                 if (p->rdev->hyperz_filp != p->filp) {
1067                         if (idx_value & 0x1)
1068                                 ib[idx] = idx_value & ~1;
1069                 }
1070                 break;
1071         case 0x4f1c:
1072                 /* ZB_BW_CNTL */
1073                 track->zb_cb_clear = !!(idx_value & (1 << 5));
1074                 track->cb_dirty = true;
1075                 track->zb_dirty = true;
1076                 if (p->rdev->hyperz_filp != p->filp) {
1077                         if (idx_value & (R300_HIZ_ENABLE |
1078                                          R300_RD_COMP_ENABLE |
1079                                          R300_WR_COMP_ENABLE |
1080                                          R300_FAST_FILL_ENABLE))
1081                                 goto fail;
1082                 }
1083                 break;
1084         case 0x4e04:
1085                 /* RB3D_BLENDCNTL */
1086                 track->blend_read_enable = !!(idx_value & (1 << 2));
1087                 track->cb_dirty = true;
1088                 break;
1089         case R300_RB3D_AARESOLVE_OFFSET:
1090                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1091                 if (r) {
1092                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1093                                   idx, reg);
1094                         radeon_cs_dump_packet(p, pkt);
1095                         return r;
1096                 }
1097                 track->aa.robj = reloc->robj;
1098                 track->aa.offset = idx_value;
1099                 track->aa_dirty = true;
1100                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1101                 break;
1102         case R300_RB3D_AARESOLVE_PITCH:
1103                 track->aa.pitch = idx_value & 0x3FFE;
1104                 track->aa_dirty = true;
1105                 break;
1106         case R300_RB3D_AARESOLVE_CTL:
1107                 track->aaresolve = idx_value & 0x1;
1108                 track->aa_dirty = true;
1109                 break;
1110         case 0x4f30: /* ZB_MASK_OFFSET */
1111         case 0x4f34: /* ZB_ZMASK_PITCH */
1112         case 0x4f44: /* ZB_HIZ_OFFSET */
1113         case 0x4f54: /* ZB_HIZ_PITCH */
1114                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1115                         goto fail;
1116                 break;
1117         case 0x4028:
1118                 if (idx_value && (p->rdev->hyperz_filp != p->filp))
1119                         goto fail;
1120                 /* GB_Z_PEQ_CONFIG */
1121                 if (p->rdev->family >= CHIP_RV350)
1122                         break;
1123                 goto fail;
1124                 break;
1125         case 0x4be8:
1126                 /* valid register only on RV530 */
1127                 if (p->rdev->family == CHIP_RV530)
1128                         break;
1129                 /* fallthrough do not move */
1130         default:
1131                 goto fail;
1132         }
1133         return 0;
1134 fail:
1135         printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
1136                reg, idx, idx_value);
1137         return -EINVAL;
1138 }
1139
1140 static int r300_packet3_check(struct radeon_cs_parser *p,
1141                               struct radeon_cs_packet *pkt)
1142 {
1143         struct radeon_cs_reloc *reloc;
1144         struct r100_cs_track *track;
1145         volatile uint32_t *ib;
1146         unsigned idx;
1147         int r;
1148
1149         ib = p->ib.ptr;
1150         idx = pkt->idx + 1;
1151         track = (struct r100_cs_track *)p->track;
1152         switch(pkt->opcode) {
1153         case PACKET3_3D_LOAD_VBPNTR:
1154                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1155                 if (r)
1156                         return r;
1157                 break;
1158         case PACKET3_INDX_BUFFER:
1159                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1160                 if (r) {
1161                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1162                         radeon_cs_dump_packet(p, pkt);
1163                         return r;
1164                 }
1165                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1166                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1167                 if (r) {
1168                         return r;
1169                 }
1170                 break;
1171         /* Draw packet */
1172         case PACKET3_3D_DRAW_IMMD:
1173                 /* Number of dwords is vtx_size * (num_vertices - 1)
1174                  * PRIM_WALK must be equal to 3 vertex data in embedded
1175                  * in cmd stream */
1176                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1177                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1178                         return -EINVAL;
1179                 }
1180                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1181                 track->immd_dwords = pkt->count - 1;
1182                 r = r100_cs_track_check(p->rdev, track);
1183                 if (r) {
1184                         return r;
1185                 }
1186                 break;
1187         case PACKET3_3D_DRAW_IMMD_2:
1188                 /* Number of dwords is vtx_size * (num_vertices - 1)
1189                  * PRIM_WALK must be equal to 3 vertex data in embedded
1190                  * in cmd stream */
1191                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1192                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1193                         return -EINVAL;
1194                 }
1195                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1196                 track->immd_dwords = pkt->count;
1197                 r = r100_cs_track_check(p->rdev, track);
1198                 if (r) {
1199                         return r;
1200                 }
1201                 break;
1202         case PACKET3_3D_DRAW_VBUF:
1203                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1204                 r = r100_cs_track_check(p->rdev, track);
1205                 if (r) {
1206                         return r;
1207                 }
1208                 break;
1209         case PACKET3_3D_DRAW_VBUF_2:
1210                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1211                 r = r100_cs_track_check(p->rdev, track);
1212                 if (r) {
1213                         return r;
1214                 }
1215                 break;
1216         case PACKET3_3D_DRAW_INDX:
1217                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1218                 r = r100_cs_track_check(p->rdev, track);
1219                 if (r) {
1220                         return r;
1221                 }
1222                 break;
1223         case PACKET3_3D_DRAW_INDX_2:
1224                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1225                 r = r100_cs_track_check(p->rdev, track);
1226                 if (r) {
1227                         return r;
1228                 }
1229                 break;
1230         case PACKET3_3D_CLEAR_HIZ:
1231         case PACKET3_3D_CLEAR_ZMASK:
1232                 if (p->rdev->hyperz_filp != p->filp)
1233                         return -EINVAL;
1234                 break;
1235         case PACKET3_3D_CLEAR_CMASK:
1236                 if (p->rdev->cmask_filp != p->filp)
1237                         return -EINVAL;
1238                 break;
1239         case PACKET3_NOP:
1240                 break;
1241         default:
1242                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1243                 return -EINVAL;
1244         }
1245         return 0;
1246 }
1247
1248 int r300_cs_parse(struct radeon_cs_parser *p)
1249 {
1250         struct radeon_cs_packet pkt;
1251         struct r100_cs_track *track;
1252         int r;
1253
1254         track = kzalloc(sizeof(*track), GFP_KERNEL);
1255         if (track == NULL)
1256                 return -ENOMEM;
1257         r100_cs_track_clear(p->rdev, track);
1258         p->track = track;
1259         do {
1260                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
1261                 if (r) {
1262                         return r;
1263                 }
1264                 p->idx += pkt.count + 2;
1265                 switch (pkt.type) {
1266                 case RADEON_PACKET_TYPE0:
1267                         r = r100_cs_parse_packet0(p, &pkt,
1268                                                   p->rdev->config.r300.reg_safe_bm,
1269                                                   p->rdev->config.r300.reg_safe_bm_size,
1270                                                   &r300_packet0_check);
1271                         break;
1272                 case RADEON_PACKET_TYPE2:
1273                         break;
1274                 case RADEON_PACKET_TYPE3:
1275                         r = r300_packet3_check(p, &pkt);
1276                         break;
1277                 default:
1278                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1279                         return -EINVAL;
1280                 }
1281                 if (r) {
1282                         return r;
1283                 }
1284         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1285         return 0;
1286 }
1287
1288 void r300_set_reg_safe(struct radeon_device *rdev)
1289 {
1290         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1291         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1292 }
1293
1294 void r300_mc_program(struct radeon_device *rdev)
1295 {
1296         struct r100_mc_save save;
1297         int r;
1298
1299         r = r100_debugfs_mc_info_init(rdev);
1300         if (r) {
1301                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1302         }
1303
1304         /* Stops all mc clients */
1305         r100_mc_stop(rdev, &save);
1306         if (rdev->flags & RADEON_IS_AGP) {
1307                 WREG32(R_00014C_MC_AGP_LOCATION,
1308                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1309                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1310                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1311                 WREG32(R_00015C_AGP_BASE_2,
1312                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1313         } else {
1314                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1315                 WREG32(R_000170_AGP_BASE, 0);
1316                 WREG32(R_00015C_AGP_BASE_2, 0);
1317         }
1318         /* Wait for mc idle */
1319         if (r300_mc_wait_for_idle(rdev))
1320                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1321         /* Program MC, should be a 32bits limited address space */
1322         WREG32(R_000148_MC_FB_LOCATION,
1323                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1324                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1325         r100_mc_resume(rdev, &save);
1326 }
1327
1328 void r300_clock_startup(struct radeon_device *rdev)
1329 {
1330         u32 tmp;
1331
1332         if (radeon_dynclks != -1 && radeon_dynclks)
1333                 radeon_legacy_set_clock_gating(rdev, 1);
1334         /* We need to force on some of the block */
1335         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1336         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1337         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1338                 tmp |= S_00000D_FORCE_VAP(1);
1339         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1340 }
1341
1342 static int r300_startup(struct radeon_device *rdev)
1343 {
1344         int r;
1345
1346         /* set common regs */
1347         r100_set_common_regs(rdev);
1348         /* program mc */
1349         r300_mc_program(rdev);
1350         /* Resume clock */
1351         r300_clock_startup(rdev);
1352         /* Initialize GPU configuration (# pipes, ...) */
1353         r300_gpu_init(rdev);
1354         /* Initialize GART (initialize after TTM so we can allocate
1355          * memory through TTM but finalize after TTM) */
1356         if (rdev->flags & RADEON_IS_PCIE) {
1357                 r = rv370_pcie_gart_enable(rdev);
1358                 if (r)
1359                         return r;
1360         }
1361
1362         if (rdev->family == CHIP_R300 ||
1363             rdev->family == CHIP_R350 ||
1364             rdev->family == CHIP_RV350)
1365                 r100_enable_bm(rdev);
1366
1367         if (rdev->flags & RADEON_IS_PCI) {
1368                 r = r100_pci_gart_enable(rdev);
1369                 if (r)
1370                         return r;
1371         }
1372
1373         /* allocate wb buffer */
1374         r = radeon_wb_init(rdev);
1375         if (r)
1376                 return r;
1377
1378         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1379         if (r) {
1380                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1381                 return r;
1382         }
1383
1384         /* Enable IRQ */
1385         if (!rdev->irq.installed) {
1386                 r = radeon_irq_kms_init(rdev);
1387                 if (r)
1388                         return r;
1389         }
1390
1391         r100_irq_set(rdev);
1392         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1393         /* 1M ring buffer */
1394         r = r100_cp_init(rdev, 1024 * 1024);
1395         if (r) {
1396                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1397                 return r;
1398         }
1399
1400         r = radeon_ib_pool_init(rdev);
1401         if (r) {
1402                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1403                 return r;
1404         }
1405
1406         return 0;
1407 }
1408
1409 int r300_resume(struct radeon_device *rdev)
1410 {
1411         int r;
1412
1413         /* Make sur GART are not working */
1414         if (rdev->flags & RADEON_IS_PCIE)
1415                 rv370_pcie_gart_disable(rdev);
1416         if (rdev->flags & RADEON_IS_PCI)
1417                 r100_pci_gart_disable(rdev);
1418         /* Resume clock before doing reset */
1419         r300_clock_startup(rdev);
1420         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1421         if (radeon_asic_reset(rdev)) {
1422                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1423                         RREG32(R_000E40_RBBM_STATUS),
1424                         RREG32(R_0007C0_CP_STAT));
1425         }
1426         /* post */
1427         radeon_combios_asic_init(rdev->ddev);
1428         /* Resume clock after posting */
1429         r300_clock_startup(rdev);
1430         /* Initialize surface registers */
1431         radeon_surface_init(rdev);
1432
1433         radeon_pm_resume(rdev);
1434
1435         rdev->accel_working = true;
1436         r = r300_startup(rdev);
1437         if (r) {
1438                 rdev->accel_working = false;
1439         }
1440         return r;
1441 }
1442
1443 int r300_suspend(struct radeon_device *rdev)
1444 {
1445         radeon_pm_suspend(rdev);
1446         r100_cp_disable(rdev);
1447         radeon_wb_disable(rdev);
1448         r100_irq_disable(rdev);
1449         if (rdev->flags & RADEON_IS_PCIE)
1450                 rv370_pcie_gart_disable(rdev);
1451         if (rdev->flags & RADEON_IS_PCI)
1452                 r100_pci_gart_disable(rdev);
1453         return 0;
1454 }
1455
1456 void r300_fini(struct radeon_device *rdev)
1457 {
1458         radeon_pm_fini(rdev);
1459         r100_cp_fini(rdev);
1460         radeon_wb_fini(rdev);
1461         radeon_ib_pool_fini(rdev);
1462         radeon_gem_fini(rdev);
1463         if (rdev->flags & RADEON_IS_PCIE)
1464                 rv370_pcie_gart_fini(rdev);
1465         if (rdev->flags & RADEON_IS_PCI)
1466                 r100_pci_gart_fini(rdev);
1467         radeon_agp_fini(rdev);
1468         radeon_irq_kms_fini(rdev);
1469         radeon_fence_driver_fini(rdev);
1470         radeon_bo_fini(rdev);
1471         radeon_atombios_fini(rdev);
1472         kfree(rdev->bios);
1473         rdev->bios = NULL;
1474 }
1475
1476 int r300_init(struct radeon_device *rdev)
1477 {
1478         int r;
1479
1480         /* Disable VGA */
1481         r100_vga_render_disable(rdev);
1482         /* Initialize scratch registers */
1483         radeon_scratch_init(rdev);
1484         /* Initialize surface registers */
1485         radeon_surface_init(rdev);
1486         /* TODO: disable VGA need to use VGA request */
1487         /* restore some register to sane defaults */
1488         r100_restore_sanity(rdev);
1489         /* BIOS*/
1490         if (!radeon_get_bios(rdev)) {
1491                 if (ASIC_IS_AVIVO(rdev))
1492                         return -EINVAL;
1493         }
1494         if (rdev->is_atom_bios) {
1495                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1496                 return -EINVAL;
1497         } else {
1498                 r = radeon_combios_init(rdev);
1499                 if (r)
1500                         return r;
1501         }
1502         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1503         if (radeon_asic_reset(rdev)) {
1504                 dev_warn(rdev->dev,
1505                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1506                         RREG32(R_000E40_RBBM_STATUS),
1507                         RREG32(R_0007C0_CP_STAT));
1508         }
1509         /* check if cards are posted or not */
1510         if (radeon_boot_test_post_card(rdev) == false)
1511                 return -EINVAL;
1512         /* Set asic errata */
1513         r300_errata(rdev);
1514         /* Initialize clocks */
1515         radeon_get_clock_info(rdev->ddev);
1516         /* initialize AGP */
1517         if (rdev->flags & RADEON_IS_AGP) {
1518                 r = radeon_agp_init(rdev);
1519                 if (r) {
1520                         radeon_agp_disable(rdev);
1521                 }
1522         }
1523         /* initialize memory controller */
1524         r300_mc_init(rdev);
1525         /* Fence driver */
1526         r = radeon_fence_driver_init(rdev);
1527         if (r)
1528                 return r;
1529         /* Memory manager */
1530         r = radeon_bo_init(rdev);
1531         if (r)
1532                 return r;
1533         if (rdev->flags & RADEON_IS_PCIE) {
1534                 r = rv370_pcie_gart_init(rdev);
1535                 if (r)
1536                         return r;
1537         }
1538         if (rdev->flags & RADEON_IS_PCI) {
1539                 r = r100_pci_gart_init(rdev);
1540                 if (r)
1541                         return r;
1542         }
1543         r300_set_reg_safe(rdev);
1544
1545         /* Initialize power management */
1546         radeon_pm_init(rdev);
1547
1548         rdev->accel_working = true;
1549         r = r300_startup(rdev);
1550         if (r) {
1551                 /* Something went wrong with the accel init, so stop accel */
1552                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1553                 r100_cp_fini(rdev);
1554                 radeon_wb_fini(rdev);
1555                 radeon_ib_pool_fini(rdev);
1556                 radeon_irq_kms_fini(rdev);
1557                 if (rdev->flags & RADEON_IS_PCIE)
1558                         rv370_pcie_gart_fini(rdev);
1559                 if (rdev->flags & RADEON_IS_PCI)
1560                         r100_pci_gart_fini(rdev);
1561                 radeon_agp_fini(rdev);
1562                 rdev->accel_working = false;
1563         }
1564         return 0;
1565 }