Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86         struct radeon_encoder *radeon_encoder =
  87                 to_radeon_encoder(radeon_crtc->encoder);
  88         /* fixme - fill in enc_priv for atom dac */
  89         enum radeon_tv_std tv_std = TV_STD_NTSC;
  90         bool is_tv = false, is_cv = false;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
  96                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  97                 tv_std = tv_dac->tv_std;
  98                 is_tv = true;
  99         }
 100
 101         memset(&args, 0, sizeof(args));
 102
 103         args.ucScaler = radeon_crtc->crtc_id;
 104
 105         if (is_tv) {
 106                 switch (tv_std) {
 107                 case TV_STD_NTSC:
 108                 default:
 109                         args.ucTVStandard = ATOM_TV_NTSC;
 110                         break;
 111                 case TV_STD_PAL:
 112                         args.ucTVStandard = ATOM_TV_PAL;
 113                         break;
 114                 case TV_STD_PAL_M:
 115                         args.ucTVStandard = ATOM_TV_PALM;
 116                         break;
 117                 case TV_STD_PAL_60:
 118                         args.ucTVStandard = ATOM_TV_PAL60;
 119                         break;
 120                 case TV_STD_NTSC_J:
 121                         args.ucTVStandard = ATOM_TV_NTSCJ;
 122                         break;
 123                 case TV_STD_SCART_PAL:
 124                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 125                         break;
 126                 case TV_STD_SECAM:
 127                         args.ucTVStandard = ATOM_TV_SECAM;
 128                         break;
 129                 case TV_STD_PAL_CN:
 130                         args.ucTVStandard = ATOM_TV_PALCN;
 131                         break;
 132                 }
 133                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 134         } else if (is_cv) {
 135                 args.ucTVStandard = ATOM_TV_CV;
 136                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 137         } else {
 138                 switch (radeon_crtc->rmx_type) {
 139                 case RMX_FULL:
 140                         args.ucEnable = ATOM_SCALER_EXPANSION;
 141                         break;
 142                 case RMX_CENTER:
 143                         args.ucEnable = ATOM_SCALER_CENTER;
 144                         break;
 145                 case RMX_ASPECT:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 default:
 149                         if (ASIC_IS_AVIVO(rdev))
 150                                 args.ucEnable = ATOM_SCALER_DISABLE;
 151                         else
 152                                 args.ucEnable = ATOM_SCALER_CENTER;
 153                         break;
 154                 }
 155         }
 156         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 157         if ((is_tv || is_cv)
 158             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 159                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 160         }
 161 }
 162
 163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 164 {
 165         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 166         struct drm_device *dev = crtc->dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168         int index =
 169             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 170         ENABLE_CRTC_PS_ALLOCATION args;
 171
 172         memset(&args, 0, sizeof(args));
 173
 174         args.ucCRTC = radeon_crtc->crtc_id;
 175         args.ucEnable = lock;
 176
 177         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 178 }
 179
 180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 181 {
 182         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 183         struct drm_device *dev = crtc->dev;
 184         struct radeon_device *rdev = dev->dev_private;
 185         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 186         ENABLE_CRTC_PS_ALLOCATION args;
 187
 188         memset(&args, 0, sizeof(args));
 189
 190         args.ucCRTC = radeon_crtc->crtc_id;
 191         args.ucEnable = state;
 192
 193         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 194 }
 195
 196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 197 {
 198         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 199         struct drm_device *dev = crtc->dev;
 200         struct radeon_device *rdev = dev->dev_private;
 201         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 202         ENABLE_CRTC_PS_ALLOCATION args;
 203
 204         memset(&args, 0, sizeof(args));
 205
 206         args.ucCRTC = radeon_crtc->crtc_id;
 207         args.ucEnable = state;
 208
 209         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 210 }
 211
 212 static const u32 vga_control_regs[6] =
 213 {
 214         AVIVO_D1VGA_CONTROL,
 215         AVIVO_D2VGA_CONTROL,
 216         EVERGREEN_D3VGA_CONTROL,
 217         EVERGREEN_D4VGA_CONTROL,
 218         EVERGREEN_D5VGA_CONTROL,
 219         EVERGREEN_D6VGA_CONTROL,
 220 };
 221
 222 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 223 {
 224         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 225         struct drm_device *dev = crtc->dev;
 226         struct radeon_device *rdev = dev->dev_private;
 227         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 228         BLANK_CRTC_PS_ALLOCATION args;
 229         u32 vga_control = 0;
 230
 231         memset(&args, 0, sizeof(args));
 232
 233         if (ASIC_IS_DCE8(rdev)) {
 234                 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
 235                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
 236         }
 237
 238         args.ucCRTC = radeon_crtc->crtc_id;
 239         args.ucBlanking = state;
 240
 241         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 242
 243         if (ASIC_IS_DCE8(rdev)) {
 244                 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
 245         }
 246 }
 247
 248 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 249 {
 250         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 251         struct drm_device *dev = crtc->dev;
 252         struct radeon_device *rdev = dev->dev_private;
 253         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 254         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 255
 256         memset(&args, 0, sizeof(args));
 257
 258         args.ucDispPipeId = radeon_crtc->crtc_id;
 259         args.ucEnable = state;
 260
 261         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 262 }
 263
 264 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 265 {
 266         struct drm_device *dev = crtc->dev;
 267         struct radeon_device *rdev = dev->dev_private;
 268         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 269
 270         switch (mode) {
 271         case DRM_MODE_DPMS_ON:
 272                 radeon_crtc->enabled = true;
 273                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 274                 radeon_pm_compute_clocks(rdev);
 275                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 276                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 277                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 278                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 279                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 280                 radeon_crtc_load_lut(crtc);
 281                 break;
 282         case DRM_MODE_DPMS_STANDBY:
 283         case DRM_MODE_DPMS_SUSPEND:
 284         case DRM_MODE_DPMS_OFF:
 285                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 286                 if (radeon_crtc->enabled)
 287                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 288                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 289                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 290                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 291                 radeon_crtc->enabled = false;
 292                 /* adjust pm to dpms changes AFTER disabling crtcs */
 293                 radeon_pm_compute_clocks(rdev);
 294                 break;
 295         }
 296 }
 297
 298 static void
 299 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 300                              struct drm_display_mode *mode)
 301 {
 302         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 303         struct drm_device *dev = crtc->dev;
 304         struct radeon_device *rdev = dev->dev_private;
 305         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 306         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 307         u16 misc = 0;
 308
 309         memset(&args, 0, sizeof(args));
 310         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 311         args.usH_Blanking_Time =
 312                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 313         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 314         args.usV_Blanking_Time =
 315                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 316         args.usH_SyncOffset =
 317                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 318         args.usH_SyncWidth =
 319                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 320         args.usV_SyncOffset =
 321                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 322         args.usV_SyncWidth =
 323                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 324         args.ucH_Border = radeon_crtc->h_border;
 325         args.ucV_Border = radeon_crtc->v_border;
 326
 327         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 328                 misc |= ATOM_VSYNC_POLARITY;
 329         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 330                 misc |= ATOM_HSYNC_POLARITY;
 331         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 332                 misc |= ATOM_COMPOSITESYNC;
 333         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 334                 misc |= ATOM_INTERLACE;
 335         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 336                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 337
 338         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 339         args.ucCRTC = radeon_crtc->crtc_id;
 340
 341         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 342 }
 343
 344 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 345                                      struct drm_display_mode *mode)
 346 {
 347         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 348         struct drm_device *dev = crtc->dev;
 349         struct radeon_device *rdev = dev->dev_private;
 350         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 351         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 352         u16 misc = 0;
 353
 354         memset(&args, 0, sizeof(args));
 355         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 356         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 357         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 358         args.usH_SyncWidth =
 359                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 360         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 361         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 362         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 363         args.usV_SyncWidth =
 364                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 365
 366         args.ucOverscanRight = radeon_crtc->h_border;
 367         args.ucOverscanLeft = radeon_crtc->h_border;
 368         args.ucOverscanBottom = radeon_crtc->v_border;
 369         args.ucOverscanTop = radeon_crtc->v_border;
 370
 371         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 372                 misc |= ATOM_VSYNC_POLARITY;
 373         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 374                 misc |= ATOM_HSYNC_POLARITY;
 375         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 376                 misc |= ATOM_COMPOSITESYNC;
 377         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 378                 misc |= ATOM_INTERLACE;
 379         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 380                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 381
 382         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 383         args.ucCRTC = radeon_crtc->crtc_id;
 384
 385         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 386 }
 387
 388 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 389 {
 390         u32 ss_cntl;
 391
 392         if (ASIC_IS_DCE4(rdev)) {
 393                 switch (pll_id) {
 394                 case ATOM_PPLL1:
 395                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 396                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 397                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 398                         break;
 399                 case ATOM_PPLL2:
 400                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 401                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 402                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 403                         break;
 404                 case ATOM_DCPLL:
 405                 case ATOM_PPLL_INVALID:
 406                         return;
 407                 }
 408         } else if (ASIC_IS_AVIVO(rdev)) {
 409                 switch (pll_id) {
 410                 case ATOM_PPLL1:
 411                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 412                         ss_cntl &= ~1;
 413                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 414                         break;
 415                 case ATOM_PPLL2:
 416                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 417                         ss_cntl &= ~1;
 418                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 419                         break;
 420                 case ATOM_DCPLL:
 421                 case ATOM_PPLL_INVALID:
 422                         return;
 423                 }
 424         }
 425 }
 426
 427
 428 union atom_enable_ss {
 429         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 430         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 431         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 432         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 433         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 434 };
 435
 436 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 437                                      int enable,
 438                                      int pll_id,
 439                                      int crtc_id,
 440                                      struct radeon_atom_ss *ss)
 441 {
 442         unsigned i;
 443         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 444         union atom_enable_ss args;
 445
 446         if (enable) {
 447                 /* Don't mess with SS if percentage is 0 or external ss.
 448                  * SS is already disabled previously, and disabling it
 449                  * again can cause display problems if the pll is already
 450                  * programmed.
 451                  */
 452                 if (ss->percentage == 0)
 453                         return;
 454                 if (ss->type & ATOM_EXTERNAL_SS_MASK)
 455                         return;
 456         } else {
 457                 for (i = 0; i < rdev->num_crtc; i++) {
 458                         if (rdev->mode_info.crtcs[i] &&
 459                             rdev->mode_info.crtcs[i]->enabled &&
 460                             i != crtc_id &&
 461                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
 462                                 /* one other crtc is using this pll don't turn
 463                                  * off spread spectrum as it might turn off
 464                                  * display on active crtc
 465                                  */
 466                                 return;
 467                         }
 468                 }
 469         }
 470
 471         memset(&args, 0, sizeof(args));
 472
 473         if (ASIC_IS_DCE5(rdev)) {
 474                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 475                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 476                 switch (pll_id) {
 477                 case ATOM_PPLL1:
 478                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 479                         break;
 480                 case ATOM_PPLL2:
 481                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 482                         break;
 483                 case ATOM_DCPLL:
 484                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 485                         break;
 486                 case ATOM_PPLL_INVALID:
 487                         return;
 488                 }
 489                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 490                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 491                 args.v3.ucEnable = enable;
 492         } else if (ASIC_IS_DCE4(rdev)) {
 493                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 494                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 495                 switch (pll_id) {
 496                 case ATOM_PPLL1:
 497                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 498                         break;
 499                 case ATOM_PPLL2:
 500                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 501                         break;
 502                 case ATOM_DCPLL:
 503                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 504                         break;
 505                 case ATOM_PPLL_INVALID:
 506                         return;
 507                 }
 508                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 509                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 510                 args.v2.ucEnable = enable;
 511         } else if (ASIC_IS_DCE3(rdev)) {
 512                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 513                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 514                 args.v1.ucSpreadSpectrumStep = ss->step;
 515                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 516                 args.v1.ucSpreadSpectrumRange = ss->range;
 517                 args.v1.ucPpll = pll_id;
 518                 args.v1.ucEnable = enable;
 519         } else if (ASIC_IS_AVIVO(rdev)) {
 520                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 521                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 522                         atombios_disable_ss(rdev, pll_id);
 523                         return;
 524                 }
 525                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 526                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 527                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 528                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 529                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 530                 args.lvds_ss_2.ucEnable = enable;
 531         } else {
 532                 if (enable == ATOM_DISABLE) {
 533                         atombios_disable_ss(rdev, pll_id);
 534                         return;
 535                 }
 536                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 537                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 538                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 539                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 540                 args.lvds_ss.ucEnable = enable;
 541         }
 542         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 543 }
 544
 545 union adjust_pixel_clock {
 546         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 547         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 548 };
 549
 550 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 551                                struct drm_display_mode *mode)
 552 {
 553         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 554         struct drm_device *dev = crtc->dev;
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct drm_encoder *encoder = radeon_crtc->encoder;
 557         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 558         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 559         u32 adjusted_clock = mode->clock;
 560         int encoder_mode = atombios_get_encoder_mode(encoder);
 561         u32 dp_clock = mode->clock;
 562         int bpc = radeon_crtc->bpc;
 563         bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 564
 565         /* reset the pll flags */
 566         radeon_crtc->pll_flags = 0;
 567
 568         if (ASIC_IS_AVIVO(rdev)) {
 569                 if ((rdev->family == CHIP_RS600) ||
 570                     (rdev->family == CHIP_RS690) ||
 571                     (rdev->family == CHIP_RS740))
 572                         radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 573                                 RADEON_PLL_PREFER_CLOSEST_LOWER);
 574
 575                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 576                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 577                 else
 578                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 579
 580                 if (rdev->family < CHIP_RV770)
 581                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 582                 /* use frac fb div on APUs */
 583                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 584                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 585                 /* use frac fb div on RS780/RS880 */
 586                 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
 587                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 588                 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
 589                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 590         } else {
 591                 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
 592
 593                 if (mode->clock > 200000)       /* range limits??? */
 594                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 595                 else
 596                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 597         }
 598
 599         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 600             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 601                 if (connector) {
 602                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 603                         struct radeon_connector_atom_dig *dig_connector =
 604                                 radeon_connector->con_priv;
 605
 606                         dp_clock = dig_connector->dp_clock;
 607                 }
 608         }
 609
 610         /* use recommended ref_div for ss */
 611         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 612                 if (radeon_crtc->ss_enabled) {
 613                         if (radeon_crtc->ss.refdiv) {
 614                                 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 615                                 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
 616                                 if (ASIC_IS_AVIVO(rdev))
 617                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 618                         }
 619                 }
 620         }
 621
 622         if (ASIC_IS_AVIVO(rdev)) {
 623                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 624                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 625                         adjusted_clock = mode->clock * 2;
 626                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 627                         radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 628                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 629                         radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
 630         } else {
 631                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 632                         radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 633                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 634                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 635         }
 636
 637         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 638          * accordingly based on the encoder/transmitter to work around
 639          * special hw requirements.
 640          */
 641         if (ASIC_IS_DCE3(rdev)) {
 642                 union adjust_pixel_clock args;
 643                 u8 frev, crev;
 644                 int index;
 645
 646                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 647                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 648                                            &crev))
 649                         return adjusted_clock;
 650
 651                 memset(&args, 0, sizeof(args));
 652
 653                 switch (frev) {
 654                 case 1:
 655                         switch (crev) {
 656                         case 1:
 657                         case 2:
 658                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 659                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 660                                 args.v1.ucEncodeMode = encoder_mode;
 661                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 662                                         args.v1.ucConfig |=
 663                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 664
 665                                 atom_execute_table(rdev->mode_info.atom_context,
 666                                                    index, (uint32_t *)&args);
 667                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 668                                 break;
 669                         case 3:
 670                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 671                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 672                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 673                                 args.v3.sInput.ucDispPllConfig = 0;
 674                                 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
 675                                         args.v3.sInput.ucDispPllConfig |=
 676                                                 DISPPLL_CONFIG_SS_ENABLE;
 677                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 678                                         args.v3.sInput.ucDispPllConfig |=
 679                                                 DISPPLL_CONFIG_COHERENT_MODE;
 680                                         /* 16200 or 27000 */
 681                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 682                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 683                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 684                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 685                                                 /* deep color support */
 686                                                 args.v3.sInput.usPixelClock =
 687                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 688                                         if (dig->coherent_mode)
 689                                                 args.v3.sInput.ucDispPllConfig |=
 690                                                         DISPPLL_CONFIG_COHERENT_MODE;
 691                                         if (is_duallink)
 692                                                 args.v3.sInput.ucDispPllConfig |=
 693                                                         DISPPLL_CONFIG_DUAL_LINK;
 694                                 }
 695                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 696                                     ENCODER_OBJECT_ID_NONE)
 697                                         args.v3.sInput.ucExtTransmitterID =
 698                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 699                                 else
 700                                         args.v3.sInput.ucExtTransmitterID = 0;
 701
 702                                 atom_execute_table(rdev->mode_info.atom_context,
 703                                                    index, (uint32_t *)&args);
 704                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 705                                 if (args.v3.sOutput.ucRefDiv) {
 706                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 707                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
 708                                         radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
 709                                 }
 710                                 if (args.v3.sOutput.ucPostDiv) {
 711                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 712                                         radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
 713                                         radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
 714                                 }
 715                                 break;
 716                         default:
 717                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 718                                 return adjusted_clock;
 719                         }
 720                         break;
 721                 default:
 722                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 723                         return adjusted_clock;
 724                 }
 725         }
 726         return adjusted_clock;
 727 }
 728
 729 union set_pixel_clock {
 730         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 731         PIXEL_CLOCK_PARAMETERS v1;
 732         PIXEL_CLOCK_PARAMETERS_V2 v2;
 733         PIXEL_CLOCK_PARAMETERS_V3 v3;
 734         PIXEL_CLOCK_PARAMETERS_V5 v5;
 735         PIXEL_CLOCK_PARAMETERS_V6 v6;
 736 };
 737
 738 /* on DCE5, make sure the voltage is high enough to support the
 739  * required disp clk.
 740  */
 741 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 742                                     u32 dispclk)
 743 {
 744         u8 frev, crev;
 745         int index;
 746         union set_pixel_clock args;
 747
 748         memset(&args, 0, sizeof(args));
 749
 750         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 751         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 752                                    &crev))
 753                 return;
 754
 755         switch (frev) {
 756         case 1:
 757                 switch (crev) {
 758                 case 5:
 759                         /* if the default dcpll clock is specified,
 760                          * SetPixelClock provides the dividers
 761                          */
 762                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 763                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 764                         args.v5.ucPpll = ATOM_DCPLL;
 765                         break;
 766                 case 6:
 767                         /* if the default dcpll clock is specified,
 768                          * SetPixelClock provides the dividers
 769                          */
 770                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 771                         if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
 772                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 773                         else if (ASIC_IS_DCE6(rdev))
 774                                 args.v6.ucPpll = ATOM_PPLL0;
 775                         else
 776                                 args.v6.ucPpll = ATOM_DCPLL;
 777                         break;
 778                 default:
 779                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 780                         return;
 781                 }
 782                 break;
 783         default:
 784                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 785                 return;
 786         }
 787         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 788 }
 789
 790 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 791                                       u32 crtc_id,
 792                                       int pll_id,
 793                                       u32 encoder_mode,
 794                                       u32 encoder_id,
 795                                       u32 clock,
 796                                       u32 ref_div,
 797                                       u32 fb_div,
 798                                       u32 frac_fb_div,
 799                                       u32 post_div,
 800                                       int bpc,
 801                                       bool ss_enabled,
 802                                       struct radeon_atom_ss *ss)
 803 {
 804         struct drm_device *dev = crtc->dev;
 805         struct radeon_device *rdev = dev->dev_private;
 806         u8 frev, crev;
 807         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 808         union set_pixel_clock args;
 809
 810         memset(&args, 0, sizeof(args));
 811
 812         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 813                                    &crev))
 814                 return;
 815
 816         switch (frev) {
 817         case 1:
 818                 switch (crev) {
 819                 case 1:
 820                         if (clock == ATOM_DISABLE)
 821                                 return;
 822                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 823                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 824                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 825                         args.v1.ucFracFbDiv = frac_fb_div;
 826                         args.v1.ucPostDiv = post_div;
 827                         args.v1.ucPpll = pll_id;
 828                         args.v1.ucCRTC = crtc_id;
 829                         args.v1.ucRefDivSrc = 1;
 830                         break;
 831                 case 2:
 832                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 833                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 834                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 835                         args.v2.ucFracFbDiv = frac_fb_div;
 836                         args.v2.ucPostDiv = post_div;
 837                         args.v2.ucPpll = pll_id;
 838                         args.v2.ucCRTC = crtc_id;
 839                         args.v2.ucRefDivSrc = 1;
 840                         break;
 841                 case 3:
 842                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 843                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 844                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 845                         args.v3.ucFracFbDiv = frac_fb_div;
 846                         args.v3.ucPostDiv = post_div;
 847                         args.v3.ucPpll = pll_id;
 848                         if (crtc_id == ATOM_CRTC2)
 849                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
 850                         else
 851                                 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
 852                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 853                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 854                         args.v3.ucTransmitterId = encoder_id;
 855                         args.v3.ucEncoderMode = encoder_mode;
 856                         break;
 857                 case 5:
 858                         args.v5.ucCRTC = crtc_id;
 859                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 860                         args.v5.ucRefDiv = ref_div;
 861                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 862                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 863                         args.v5.ucPostDiv = post_div;
 864                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 865                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 866                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 867                         switch (bpc) {
 868                         case 8:
 869                         default:
 870                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 871                                 break;
 872                         case 10:
 873                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 874                                 break;
 875                         }
 876                         args.v5.ucTransmitterID = encoder_id;
 877                         args.v5.ucEncoderMode = encoder_mode;
 878                         args.v5.ucPpll = pll_id;
 879                         break;
 880                 case 6:
 881                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 882                         args.v6.ucRefDiv = ref_div;
 883                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 884                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 885                         args.v6.ucPostDiv = post_div;
 886                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 887                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 888                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 889                         switch (bpc) {
 890                         case 8:
 891                         default:
 892                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 893                                 break;
 894                         case 10:
 895                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 896                                 break;
 897                         case 12:
 898                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 899                                 break;
 900                         case 16:
 901                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 902                                 break;
 903                         }
 904                         args.v6.ucTransmitterID = encoder_id;
 905                         args.v6.ucEncoderMode = encoder_mode;
 906                         args.v6.ucPpll = pll_id;
 907                         break;
 908                 default:
 909                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 910                         return;
 911                 }
 912                 break;
 913         default:
 914                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 915                 return;
 916         }
 917
 918         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 919 }
 920
 921 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 922 {
 923         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 924         struct drm_device *dev = crtc->dev;
 925         struct radeon_device *rdev = dev->dev_private;
 926         struct radeon_encoder *radeon_encoder =
 927                 to_radeon_encoder(radeon_crtc->encoder);
 928         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
 929
 930         radeon_crtc->bpc = 8;
 931         radeon_crtc->ss_enabled = false;
 932
 933         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 934             (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
 935                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 936                 struct drm_connector *connector =
 937                         radeon_get_connector_for_encoder(radeon_crtc->encoder);
 938                 struct radeon_connector *radeon_connector =
 939                         to_radeon_connector(connector);
 940                 struct radeon_connector_atom_dig *dig_connector =
 941                         radeon_connector->con_priv;
 942                 int dp_clock;
 943                 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
 944
 945                 switch (encoder_mode) {
 946                 case ATOM_ENCODER_MODE_DP_MST:
 947                 case ATOM_ENCODER_MODE_DP:
 948                         /* DP/eDP */
 949                         dp_clock = dig_connector->dp_clock / 10;
 950                         if (ASIC_IS_DCE4(rdev))
 951                                 radeon_crtc->ss_enabled =
 952                                         radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 953                                                                          ASIC_INTERNAL_SS_ON_DP,
 954                                                                          dp_clock);
 955                         else {
 956                                 if (dp_clock == 16200) {
 957                                         radeon_crtc->ss_enabled =
 958                                                 radeon_atombios_get_ppll_ss_info(rdev,
 959                                                                                  &radeon_crtc->ss,
 960                                                                                  ATOM_DP_SS_ID2);
 961                                         if (!radeon_crtc->ss_enabled)
 962                                                 radeon_crtc->ss_enabled =
 963                                                         radeon_atombios_get_ppll_ss_info(rdev,
 964                                                                                          &radeon_crtc->ss,
 965                                                                                          ATOM_DP_SS_ID1);
 966                                 } else {
 967                                         radeon_crtc->ss_enabled =
 968                                                 radeon_atombios_get_ppll_ss_info(rdev,
 969                                                                                  &radeon_crtc->ss,
 970                                                                                  ATOM_DP_SS_ID1);
 971                                 }
 972                                 /* disable spread spectrum on DCE3 DP */
 973                                 radeon_crtc->ss_enabled = false;
 974                         }
 975                         break;
 976                 case ATOM_ENCODER_MODE_LVDS:
 977                         if (ASIC_IS_DCE4(rdev))
 978                                 radeon_crtc->ss_enabled =
 979                                         radeon_atombios_get_asic_ss_info(rdev,
 980                                                                          &radeon_crtc->ss,
 981                                                                          dig->lcd_ss_id,
 982                                                                          mode->clock / 10);
 983                         else
 984                                 radeon_crtc->ss_enabled =
 985                                         radeon_atombios_get_ppll_ss_info(rdev,
 986                                                                          &radeon_crtc->ss,
 987                                                                          dig->lcd_ss_id);
 988                         break;
 989                 case ATOM_ENCODER_MODE_DVI:
 990                         if (ASIC_IS_DCE4(rdev))
 991                                 radeon_crtc->ss_enabled =
 992                                         radeon_atombios_get_asic_ss_info(rdev,
 993                                                                          &radeon_crtc->ss,
 994                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 995                                                                          mode->clock / 10);
 996                         break;
 997                 case ATOM_ENCODER_MODE_HDMI:
 998                         if (ASIC_IS_DCE4(rdev))
 999                                 radeon_crtc->ss_enabled =
1000                                         radeon_atombios_get_asic_ss_info(rdev,
1001                                                                          &radeon_crtc->ss,
1002                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1003                                                                          mode->clock / 10);
1004                         break;
1005                 default:
1006                         break;
1007                 }
1008         }
1009
1010         /* adjust pixel clock as needed */
1011         radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1012
1013         return true;
1014 }
1015
1016 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1017 {
1018         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1019         struct drm_device *dev = crtc->dev;
1020         struct radeon_device *rdev = dev->dev_private;
1021         struct radeon_encoder *radeon_encoder =
1022                 to_radeon_encoder(radeon_crtc->encoder);
1023         u32 pll_clock = mode->clock;
1024         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1025         struct radeon_pll *pll;
1026         int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1027
1028         switch (radeon_crtc->pll_id) {
1029         case ATOM_PPLL1:
1030                 pll = &rdev->clock.p1pll;
1031                 break;
1032         case ATOM_PPLL2:
1033                 pll = &rdev->clock.p2pll;
1034                 break;
1035         case ATOM_DCPLL:
1036         case ATOM_PPLL_INVALID:
1037         default:
1038                 pll = &rdev->clock.dcpll;
1039                 break;
1040         }
1041
1042         /* update pll params */
1043         pll->flags = radeon_crtc->pll_flags;
1044         pll->reference_div = radeon_crtc->pll_reference_div;
1045         pll->post_div = radeon_crtc->pll_post_div;
1046
1047         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1048                 /* TV seems to prefer the legacy algo on some boards */
1049                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1050                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1051         else if (ASIC_IS_AVIVO(rdev))
1052                 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1053                                          &fb_div, &frac_fb_div, &ref_div, &post_div);
1054         else
1055                 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1056                                           &fb_div, &frac_fb_div, &ref_div, &post_div);
1057
1058         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1059                                  radeon_crtc->crtc_id, &radeon_crtc->ss);
1060
1061         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1062                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1063                                   ref_div, fb_div, frac_fb_div, post_div,
1064                                   radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1065
1066         if (radeon_crtc->ss_enabled) {
1067                 /* calculate ss amount and step size */
1068                 if (ASIC_IS_DCE4(rdev)) {
1069                         u32 step_size;
1070                         u32 amount = (((fb_div * 10) + frac_fb_div) *
1071                                       (u32)radeon_crtc->ss.percentage) /
1072                                 (100 * (u32)radeon_crtc->ss.percentage_divider);
1073                         radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1074                         radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1075                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1076                         if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1077                                 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1078                                         (125 * 25 * pll->reference_freq / 100);
1079                         else
1080                                 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1081                                         (125 * 25 * pll->reference_freq / 100);
1082                         radeon_crtc->ss.step = step_size;
1083                 }
1084
1085                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1086                                          radeon_crtc->crtc_id, &radeon_crtc->ss);
1087         }
1088 }
1089
1090 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1091                                  struct drm_framebuffer *fb,
1092                                  int x, int y, int atomic)
1093 {
1094         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1095         struct drm_device *dev = crtc->dev;
1096         struct radeon_device *rdev = dev->dev_private;
1097         struct radeon_framebuffer *radeon_fb;
1098         struct drm_framebuffer *target_fb;
1099         struct drm_gem_object *obj;
1100         struct radeon_bo *rbo;
1101         uint64_t fb_location;
1102         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1103         unsigned bankw, bankh, mtaspect, tile_split;
1104         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1105         u32 tmp, viewport_w, viewport_h;
1106         int r;
1107
1108         /* no fb bound */
1109         if (!atomic && !crtc->fb) {
1110                 DRM_DEBUG_KMS("No FB bound\n");
1111                 return 0;
1112         }
1113
1114         if (atomic) {
1115                 radeon_fb = to_radeon_framebuffer(fb);
1116                 target_fb = fb;
1117         }
1118         else {
1119                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1120                 target_fb = crtc->fb;
1121         }
1122
1123         /* If atomic, assume fb object is pinned & idle & fenced and
1124          * just update base pointers
1125          */
1126         obj = radeon_fb->obj;
1127         rbo = gem_to_radeon_bo(obj);
1128         r = radeon_bo_reserve(rbo, false);
1129         if (unlikely(r != 0))
1130                 return r;
1131
1132         if (atomic)
1133                 fb_location = radeon_bo_gpu_offset(rbo);
1134         else {
1135                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1136                 if (unlikely(r != 0)) {
1137                         radeon_bo_unreserve(rbo);
1138                         return -EINVAL;
1139                 }
1140         }
1141
1142         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1143         radeon_bo_unreserve(rbo);
1144
1145         switch (target_fb->bits_per_pixel) {
1146         case 8:
1147                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1148                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1149                 break;
1150         case 15:
1151                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1152                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1153                 break;
1154         case 16:
1155                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1156                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1157 #ifdef __BIG_ENDIAN
1158                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1159 #endif
1160                 break;
1161         case 24:
1162         case 32:
1163                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1164                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1165 #ifdef __BIG_ENDIAN
1166                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1167 #endif
1168                 break;
1169         default:
1170                 DRM_ERROR("Unsupported screen depth %d\n",
1171                           target_fb->bits_per_pixel);
1172                 return -EINVAL;
1173         }
1174
1175         if (tiling_flags & RADEON_TILING_MACRO) {
1176                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1177
1178                 /* Set NUM_BANKS. */
1179                 if (rdev->family >= CHIP_TAHITI) {
1180                         unsigned tileb, index, num_banks, tile_split_bytes;
1181
1182                         /* Calculate the macrotile mode index. */
1183                         tile_split_bytes = 64 << tile_split;
1184                         tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1185                         tileb = min(tile_split_bytes, tileb);
1186
1187                         for (index = 0; tileb > 64; index++) {
1188                                 tileb >>= 1;
1189                         }
1190
1191                         if (index >= 16) {
1192                                 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1193                                           target_fb->bits_per_pixel, tile_split);
1194                                 return -EINVAL;
1195                         }
1196
1197                         if (rdev->family >= CHIP_BONAIRE)
1198                                 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1199                         else
1200                                 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1201                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1202                 } else {
1203                         /* NI and older. */
1204                         if (rdev->family >= CHIP_CAYMAN)
1205                                 tmp = rdev->config.cayman.tile_config;
1206                         else
1207                                 tmp = rdev->config.evergreen.tile_config;
1208
1209                         switch ((tmp & 0xf0) >> 4) {
1210                         case 0: /* 4 banks */
1211                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1212                                 break;
1213                         case 1: /* 8 banks */
1214                         default:
1215                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1216                                 break;
1217                         case 2: /* 16 banks */
1218                                 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1219                                 break;
1220                         }
1221                 }
1222
1223                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1224                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1225                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1226                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1227                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1228                 if (rdev->family >= CHIP_BONAIRE) {
1229                         /* XXX need to know more about the surface tiling mode */
1230                         fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1231                 }
1232         } else if (tiling_flags & RADEON_TILING_MICRO)
1233                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1234
1235         if (rdev->family >= CHIP_BONAIRE) {
1236                 /* Read the pipe config from the 2D TILED SCANOUT mode.
1237                  * It should be the same for the other modes too, but not all
1238                  * modes set the pipe config field. */
1239                 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1240
1241                 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1242         } else if ((rdev->family == CHIP_TAHITI) ||
1243                    (rdev->family == CHIP_PITCAIRN))
1244                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1245         else if ((rdev->family == CHIP_VERDE) ||
1246                  (rdev->family == CHIP_OLAND) ||
1247                  (rdev->family == CHIP_HAINAN)) /* for completeness.  HAINAN has no display hw */
1248                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1249
1250         switch (radeon_crtc->crtc_id) {
1251         case 0:
1252                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1253                 break;
1254         case 1:
1255                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1256                 break;
1257         case 2:
1258                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1259                 break;
1260         case 3:
1261                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1262                 break;
1263         case 4:
1264                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1265                 break;
1266         case 5:
1267                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1268                 break;
1269         default:
1270                 break;
1271         }
1272
1273         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1274                upper_32_bits(fb_location));
1275         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1276                upper_32_bits(fb_location));
1277         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1278                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1279         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1280                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1281         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1282         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1283
1284         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1285         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1286         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1287         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1288         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1289         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1290
1291         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1292         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1293         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1294
1295         if (rdev->family >= CHIP_BONAIRE)
1296                 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1297                        target_fb->height);
1298         else
1299                 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1300                        target_fb->height);
1301         x &= ~3;
1302         y &= ~1;
1303         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1304                (x << 16) | y);
1305         viewport_w = crtc->mode.hdisplay;
1306         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1307         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1308                (viewport_w << 16) | viewport_h);
1309
1310         /* pageflip setup */
1311         /* make sure flip is at vb rather than hb */
1312         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1313         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1314         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1315
1316         /* set pageflip to happen anywhere in vblank interval */
1317         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1318
1319         if (!atomic && fb && fb != crtc->fb) {
1320                 radeon_fb = to_radeon_framebuffer(fb);
1321                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1322                 r = radeon_bo_reserve(rbo, false);
1323                 if (unlikely(r != 0))
1324                         return r;
1325                 radeon_bo_unpin(rbo);
1326                 radeon_bo_unreserve(rbo);
1327         }
1328
1329         /* Bytes per pixel may have changed */
1330         radeon_bandwidth_update(rdev);
1331
1332         return 0;
1333 }
1334
1335 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1336                                   struct drm_framebuffer *fb,
1337                                   int x, int y, int atomic)
1338 {
1339         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1340         struct drm_device *dev = crtc->dev;
1341         struct radeon_device *rdev = dev->dev_private;
1342         struct radeon_framebuffer *radeon_fb;
1343         struct drm_gem_object *obj;
1344         struct radeon_bo *rbo;
1345         struct drm_framebuffer *target_fb;
1346         uint64_t fb_location;
1347         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1348         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1349         u32 tmp, viewport_w, viewport_h;
1350         int r;
1351
1352         /* no fb bound */
1353         if (!atomic && !crtc->fb) {
1354                 DRM_DEBUG_KMS("No FB bound\n");
1355                 return 0;
1356         }
1357
1358         if (atomic) {
1359                 radeon_fb = to_radeon_framebuffer(fb);
1360                 target_fb = fb;
1361         }
1362         else {
1363                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1364                 target_fb = crtc->fb;
1365         }
1366
1367         obj = radeon_fb->obj;
1368         rbo = gem_to_radeon_bo(obj);
1369         r = radeon_bo_reserve(rbo, false);
1370         if (unlikely(r != 0))
1371                 return r;
1372
1373         /* If atomic, assume fb object is pinned & idle & fenced and
1374          * just update base pointers
1375          */
1376         if (atomic)
1377                 fb_location = radeon_bo_gpu_offset(rbo);
1378         else {
1379                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1380                 if (unlikely(r != 0)) {
1381                         radeon_bo_unreserve(rbo);
1382                         return -EINVAL;
1383                 }
1384         }
1385         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1386         radeon_bo_unreserve(rbo);
1387
1388         switch (target_fb->bits_per_pixel) {
1389         case 8:
1390                 fb_format =
1391                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1392                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1393                 break;
1394         case 15:
1395                 fb_format =
1396                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1397                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1398                 break;
1399         case 16:
1400                 fb_format =
1401                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1402                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1403 #ifdef __BIG_ENDIAN
1404                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1405 #endif
1406                 break;
1407         case 24:
1408         case 32:
1409                 fb_format =
1410                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1411                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1412 #ifdef __BIG_ENDIAN
1413                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1414 #endif
1415                 break;
1416         default:
1417                 DRM_ERROR("Unsupported screen depth %d\n",
1418                           target_fb->bits_per_pixel);
1419                 return -EINVAL;
1420         }
1421
1422         if (rdev->family >= CHIP_R600) {
1423                 if (tiling_flags & RADEON_TILING_MACRO)
1424                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1425                 else if (tiling_flags & RADEON_TILING_MICRO)
1426                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1427         } else {
1428                 if (tiling_flags & RADEON_TILING_MACRO)
1429                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1430
1431                 if (tiling_flags & RADEON_TILING_MICRO)
1432                         fb_format |= AVIVO_D1GRPH_TILED;
1433         }
1434
1435         if (radeon_crtc->crtc_id == 0)
1436                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1437         else
1438                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1439
1440         if (rdev->family >= CHIP_RV770) {
1441                 if (radeon_crtc->crtc_id) {
1442                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1443                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1444                 } else {
1445                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1446                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1447                 }
1448         }
1449         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1450                (u32) fb_location);
1451         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1452                radeon_crtc->crtc_offset, (u32) fb_location);
1453         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1454         if (rdev->family >= CHIP_R600)
1455                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1456
1457         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1458         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1459         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1460         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1461         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1462         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1463
1464         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1465         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1466         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1467
1468         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1469                target_fb->height);
1470         x &= ~3;
1471         y &= ~1;
1472         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1473                (x << 16) | y);
1474         viewport_w = crtc->mode.hdisplay;
1475         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1476         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1477                (viewport_w << 16) | viewport_h);
1478
1479         /* pageflip setup */
1480         /* make sure flip is at vb rather than hb */
1481         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1482         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1483         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1484
1485         /* set pageflip to happen anywhere in vblank interval */
1486         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1487
1488         if (!atomic && fb && fb != crtc->fb) {
1489                 radeon_fb = to_radeon_framebuffer(fb);
1490                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1491                 r = radeon_bo_reserve(rbo, false);
1492                 if (unlikely(r != 0))
1493                         return r;
1494                 radeon_bo_unpin(rbo);
1495                 radeon_bo_unreserve(rbo);
1496         }
1497
1498         /* Bytes per pixel may have changed */
1499         radeon_bandwidth_update(rdev);
1500
1501         return 0;
1502 }
1503
1504 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1505                            struct drm_framebuffer *old_fb)
1506 {
1507         struct drm_device *dev = crtc->dev;
1508         struct radeon_device *rdev = dev->dev_private;
1509
1510         if (ASIC_IS_DCE4(rdev))
1511                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1512         else if (ASIC_IS_AVIVO(rdev))
1513                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1514         else
1515                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1516 }
1517
1518 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1519                                   struct drm_framebuffer *fb,
1520                                   int x, int y, enum mode_set_atomic state)
1521 {
1522        struct drm_device *dev = crtc->dev;
1523        struct radeon_device *rdev = dev->dev_private;
1524
1525         if (ASIC_IS_DCE4(rdev))
1526                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1527         else if (ASIC_IS_AVIVO(rdev))
1528                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1529         else
1530                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1531 }
1532
1533 /* properly set additional regs when using atombios */
1534 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1535 {
1536         struct drm_device *dev = crtc->dev;
1537         struct radeon_device *rdev = dev->dev_private;
1538         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1539         u32 disp_merge_cntl;
1540
1541         switch (radeon_crtc->crtc_id) {
1542         case 0:
1543                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1544                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1545                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1546                 break;
1547         case 1:
1548                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1549                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1550                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1551                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1552                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1553                 break;
1554         }
1555 }
1556
1557 /**
1558  * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1559  *
1560  * @crtc: drm crtc
1561  *
1562  * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1563  */
1564 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1565 {
1566         struct drm_device *dev = crtc->dev;
1567         struct drm_crtc *test_crtc;
1568         struct radeon_crtc *test_radeon_crtc;
1569         u32 pll_in_use = 0;
1570
1571         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1572                 if (crtc == test_crtc)
1573                         continue;
1574
1575                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1576                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1577                         pll_in_use |= (1 << test_radeon_crtc->pll_id);
1578         }
1579         return pll_in_use;
1580 }
1581
1582 /**
1583  * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1584  *
1585  * @crtc: drm crtc
1586  *
1587  * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1588  * also in DP mode.  For DP, a single PPLL can be used for all DP
1589  * crtcs/encoders.
1590  */
1591 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1592 {
1593         struct drm_device *dev = crtc->dev;
1594         struct drm_crtc *test_crtc;
1595         struct radeon_crtc *test_radeon_crtc;
1596
1597         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1598                 if (crtc == test_crtc)
1599                         continue;
1600                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1601                 if (test_radeon_crtc->encoder &&
1602                     ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1603                         /* for DP use the same PLL for all */
1604                         if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1605                                 return test_radeon_crtc->pll_id;
1606                 }
1607         }
1608         return ATOM_PPLL_INVALID;
1609 }
1610
1611 /**
1612  * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1613  *
1614  * @crtc: drm crtc
1615  * @encoder: drm encoder
1616  *
1617  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1618  * be shared (i.e., same clock).
1619  */
1620 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1621 {
1622         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1623         struct drm_device *dev = crtc->dev;
1624         struct drm_crtc *test_crtc;
1625         struct radeon_crtc *test_radeon_crtc;
1626         u32 adjusted_clock, test_adjusted_clock;
1627
1628         adjusted_clock = radeon_crtc->adjusted_clock;
1629
1630         if (adjusted_clock == 0)
1631                 return ATOM_PPLL_INVALID;
1632
1633         list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1634                 if (crtc == test_crtc)
1635                         continue;
1636                 test_radeon_crtc = to_radeon_crtc(test_crtc);
1637                 if (test_radeon_crtc->encoder &&
1638                     !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1639                         /* check if we are already driving this connector with another crtc */
1640                         if (test_radeon_crtc->connector == radeon_crtc->connector) {
1641                                 /* if we are, return that pll */
1642                                 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1643                                         return test_radeon_crtc->pll_id;
1644                         }
1645                         /* for non-DP check the clock */
1646                         test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1647                         if ((crtc->mode.clock == test_crtc->mode.clock) &&
1648                             (adjusted_clock == test_adjusted_clock) &&
1649                             (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1650                             (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1651                                 return test_radeon_crtc->pll_id;
1652                 }
1653         }
1654         return ATOM_PPLL_INVALID;
1655 }
1656
1657 /**
1658  * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1659  *
1660  * @crtc: drm crtc
1661  *
1662  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
1663  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
1664  * monitors a dedicated PPLL must be used.  If a particular board has
1665  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1666  * as there is no need to program the PLL itself.  If we are not able to
1667  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1668  * avoid messing up an existing monitor.
1669  *
1670  * Asic specific PLL information
1671  *
1672  * DCE 8.x
1673  * KB/KV
1674  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1675  * CI
1676  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1677  *
1678  * DCE 6.1
1679  * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1680  * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1681  *
1682  * DCE 6.0
1683  * - PPLL0 is available to all UNIPHY (DP only)
1684  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1685  *
1686  * DCE 5.0
1687  * - DCPLL is available to all UNIPHY (DP only)
1688  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1689  *
1690  * DCE 3.0/4.0/4.1
1691  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1692  *
1693  */
1694 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1695 {
1696         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1697         struct drm_device *dev = crtc->dev;
1698         struct radeon_device *rdev = dev->dev_private;
1699         struct radeon_encoder *radeon_encoder =
1700                 to_radeon_encoder(radeon_crtc->encoder);
1701         u32 pll_in_use;
1702         int pll;
1703
1704         if (ASIC_IS_DCE8(rdev)) {
1705                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1706                         if (rdev->clock.dp_extclk)
1707                                 /* skip PPLL programming if using ext clock */
1708                                 return ATOM_PPLL_INVALID;
1709                         else {
1710                                 /* use the same PPLL for all DP monitors */
1711                                 pll = radeon_get_shared_dp_ppll(crtc);
1712                                 if (pll != ATOM_PPLL_INVALID)
1713                                         return pll;
1714                         }
1715                 } else {
1716                         /* use the same PPLL for all monitors with the same clock */
1717                         pll = radeon_get_shared_nondp_ppll(crtc);
1718                         if (pll != ATOM_PPLL_INVALID)
1719                                 return pll;
1720                 }
1721                 /* otherwise, pick one of the plls */
1722                 if ((rdev->family == CHIP_KAVERI) ||
1723                     (rdev->family == CHIP_KABINI)) {
1724                         /* KB/KV has PPLL1 and PPLL2 */
1725                         pll_in_use = radeon_get_pll_use_mask(crtc);
1726                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1727                                 return ATOM_PPLL2;
1728                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1729                                 return ATOM_PPLL1;
1730                         DRM_ERROR("unable to allocate a PPLL\n");
1731                         return ATOM_PPLL_INVALID;
1732                 } else {
1733                         /* CI has PPLL0, PPLL1, and PPLL2 */
1734                         pll_in_use = radeon_get_pll_use_mask(crtc);
1735                         if (!(pll_in_use & (1 << ATOM_PPLL2)))
1736                                 return ATOM_PPLL2;
1737                         if (!(pll_in_use & (1 << ATOM_PPLL1)))
1738                                 return ATOM_PPLL1;
1739                         if (!(pll_in_use & (1 << ATOM_PPLL0)))
1740                                 return ATOM_PPLL0;
1741                         DRM_ERROR("unable to allocate a PPLL\n");
1742                         return ATOM_PPLL_INVALID;
1743                 }
1744         } else if (ASIC_IS_DCE61(rdev)) {
1745                 struct radeon_encoder_atom_dig *dig =
1746                         radeon_encoder->enc_priv;
1747
1748                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1749                     (dig->linkb == false))
1750                         /* UNIPHY A uses PPLL2 */
1751                         return ATOM_PPLL2;
1752                 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1753                         /* UNIPHY B/C/D/E/F */
1754                         if (rdev->clock.dp_extclk)
1755                                 /* skip PPLL programming if using ext clock */
1756                                 return ATOM_PPLL_INVALID;
1757                         else {
1758                                 /* use the same PPLL for all DP monitors */
1759                                 pll = radeon_get_shared_dp_ppll(crtc);
1760                                 if (pll != ATOM_PPLL_INVALID)
1761                                         return pll;
1762                         }
1763                 } else {
1764                         /* use the same PPLL for all monitors with the same clock */
1765                         pll = radeon_get_shared_nondp_ppll(crtc);
1766                         if (pll != ATOM_PPLL_INVALID)
1767                                 return pll;
1768                 }
1769                 /* UNIPHY B/C/D/E/F */
1770                 pll_in_use = radeon_get_pll_use_mask(crtc);
1771                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1772                         return ATOM_PPLL0;
1773                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1774                         return ATOM_PPLL1;
1775                 DRM_ERROR("unable to allocate a PPLL\n");
1776                 return ATOM_PPLL_INVALID;
1777         } else if (ASIC_IS_DCE41(rdev)) {
1778                 /* Don't share PLLs on DCE4.1 chips */
1779                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1780                         if (rdev->clock.dp_extclk)
1781                                 /* skip PPLL programming if using ext clock */
1782                                 return ATOM_PPLL_INVALID;
1783                 }
1784                 pll_in_use = radeon_get_pll_use_mask(crtc);
1785                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1786                         return ATOM_PPLL1;
1787                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1788                         return ATOM_PPLL2;
1789                 DRM_ERROR("unable to allocate a PPLL\n");
1790                 return ATOM_PPLL_INVALID;
1791         } else if (ASIC_IS_DCE4(rdev)) {
1792                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1793                  * depending on the asic:
1794                  * DCE4: PPLL or ext clock
1795                  * DCE5: PPLL, DCPLL, or ext clock
1796                  * DCE6: PPLL, PPLL0, or ext clock
1797                  *
1798                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1799                  * PPLL/DCPLL programming and only program the DP DTO for the
1800                  * crtc virtual pixel clock.
1801                  */
1802                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1803                         if (rdev->clock.dp_extclk)
1804                                 /* skip PPLL programming if using ext clock */
1805                                 return ATOM_PPLL_INVALID;
1806                         else if (ASIC_IS_DCE6(rdev))
1807                                 /* use PPLL0 for all DP */
1808                                 return ATOM_PPLL0;
1809                         else if (ASIC_IS_DCE5(rdev))
1810                                 /* use DCPLL for all DP */
1811                                 return ATOM_DCPLL;
1812                         else {
1813                                 /* use the same PPLL for all DP monitors */
1814                                 pll = radeon_get_shared_dp_ppll(crtc);
1815                                 if (pll != ATOM_PPLL_INVALID)
1816                                         return pll;
1817                         }
1818                 } else {
1819                         /* use the same PPLL for all monitors with the same clock */
1820                         pll = radeon_get_shared_nondp_ppll(crtc);
1821                         if (pll != ATOM_PPLL_INVALID)
1822                                 return pll;
1823                 }
1824                 /* all other cases */
1825                 pll_in_use = radeon_get_pll_use_mask(crtc);
1826                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1827                         return ATOM_PPLL1;
1828                 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1829                         return ATOM_PPLL2;
1830                 DRM_ERROR("unable to allocate a PPLL\n");
1831                 return ATOM_PPLL_INVALID;
1832         } else {
1833                 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1834                 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1835                  * the matching btw pll and crtc is done through
1836                  * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1837                  * pll (1 or 2) to select which register to write. ie if using
1838                  * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1839                  * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1840                  * choose which value to write. Which is reverse order from
1841                  * register logic. So only case that works is when pllid is
1842                  * same as crtcid or when both pll and crtc are enabled and
1843                  * both use same clock.
1844                  *
1845                  * So just return crtc id as if crtc and pll were hard linked
1846                  * together even if they aren't
1847                  */
1848                 return radeon_crtc->crtc_id;
1849         }
1850 }
1851
1852 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1853 {
1854         /* always set DCPLL */
1855         if (ASIC_IS_DCE6(rdev))
1856                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1857         else if (ASIC_IS_DCE4(rdev)) {
1858                 struct radeon_atom_ss ss;
1859                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1860                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1861                                                                    rdev->clock.default_dispclk);
1862                 if (ss_enabled)
1863                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1864                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1865                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1866                 if (ss_enabled)
1867                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1868         }
1869
1870 }
1871
1872 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1873                            struct drm_display_mode *mode,
1874                            struct drm_display_mode *adjusted_mode,
1875                            int x, int y, struct drm_framebuffer *old_fb)
1876 {
1877         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1878         struct drm_device *dev = crtc->dev;
1879         struct radeon_device *rdev = dev->dev_private;
1880         struct radeon_encoder *radeon_encoder =
1881                 to_radeon_encoder(radeon_crtc->encoder);
1882         bool is_tvcv = false;
1883
1884         if (radeon_encoder->active_device &
1885             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1886                 is_tvcv = true;
1887
1888         atombios_crtc_set_pll(crtc, adjusted_mode);
1889
1890         if (ASIC_IS_DCE4(rdev))
1891                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1892         else if (ASIC_IS_AVIVO(rdev)) {
1893                 if (is_tvcv)
1894                         atombios_crtc_set_timing(crtc, adjusted_mode);
1895                 else
1896                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1897         } else {
1898                 atombios_crtc_set_timing(crtc, adjusted_mode);
1899                 if (radeon_crtc->crtc_id == 0)
1900                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1901                 radeon_legacy_atom_fixup(crtc);
1902         }
1903         atombios_crtc_set_base(crtc, x, y, old_fb);
1904         atombios_overscan_setup(crtc, mode, adjusted_mode);
1905         atombios_scaler_setup(crtc);
1906         /* update the hw version fpr dpm */
1907         radeon_crtc->hw_mode = *adjusted_mode;
1908
1909         return 0;
1910 }
1911
1912 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1913                                      const struct drm_display_mode *mode,
1914                                      struct drm_display_mode *adjusted_mode)
1915 {
1916         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1917         struct drm_device *dev = crtc->dev;
1918         struct drm_encoder *encoder;
1919
1920         /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1921         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1922                 if (encoder->crtc == crtc) {
1923                         radeon_crtc->encoder = encoder;
1924                         radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1925                         break;
1926                 }
1927         }
1928         if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1929                 radeon_crtc->encoder = NULL;
1930                 radeon_crtc->connector = NULL;
1931                 return false;
1932         }
1933         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1934                 return false;
1935         if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1936                 return false;
1937         /* pick pll */
1938         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1939         /* if we can't get a PPLL for a non-DP encoder, fail */
1940         if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1941             !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1942                 return false;
1943
1944         return true;
1945 }
1946
1947 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1948 {
1949         struct drm_device *dev = crtc->dev;
1950         struct radeon_device *rdev = dev->dev_private;
1951
1952         /* disable crtc pair power gating before programming */
1953         if (ASIC_IS_DCE6(rdev))
1954                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1955
1956         atombios_lock_crtc(crtc, ATOM_ENABLE);
1957         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1958 }
1959
1960 static void atombios_crtc_commit(struct drm_crtc *crtc)
1961 {
1962         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1963         atombios_lock_crtc(crtc, ATOM_DISABLE);
1964 }
1965
1966 static void atombios_crtc_disable(struct drm_crtc *crtc)
1967 {
1968         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1969         struct drm_device *dev = crtc->dev;
1970         struct radeon_device *rdev = dev->dev_private;
1971         struct radeon_atom_ss ss;
1972         int i;
1973
1974         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1975         if (crtc->fb) {
1976                 int r;
1977                 struct radeon_framebuffer *radeon_fb;
1978                 struct radeon_bo *rbo;
1979
1980                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1981                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1982                 r = radeon_bo_reserve(rbo, false);
1983                 if (unlikely(r))
1984                         DRM_ERROR("failed to reserve rbo before unpin\n");
1985                 else {
1986                         radeon_bo_unpin(rbo);
1987                         radeon_bo_unreserve(rbo);
1988                 }
1989         }
1990         /* disable the GRPH */
1991         if (ASIC_IS_DCE4(rdev))
1992                 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1993         else if (ASIC_IS_AVIVO(rdev))
1994                 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1995
1996         if (ASIC_IS_DCE6(rdev))
1997                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1998
1999         for (i = 0; i < rdev->num_crtc; i++) {
2000                 if (rdev->mode_info.crtcs[i] &&
2001                     rdev->mode_info.crtcs[i]->enabled &&
2002                     i != radeon_crtc->crtc_id &&
2003                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2004                         /* one other crtc is using this pll don't turn
2005                          * off the pll
2006                          */
2007                         goto done;
2008                 }
2009         }
2010
2011         switch (radeon_crtc->pll_id) {
2012         case ATOM_PPLL1:
2013         case ATOM_PPLL2:
2014                 /* disable the ppll */
2015                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2016                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2017                 break;
2018         case ATOM_PPLL0:
2019                 /* disable the ppll */
2020                 if ((rdev->family == CHIP_ARUBA) ||
2021                     (rdev->family == CHIP_BONAIRE) ||
2022                     (rdev->family == CHIP_HAWAII))
2023                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2024                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2025                 break;
2026         default:
2027                 break;
2028         }
2029 done:
2030         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2031         radeon_crtc->adjusted_clock = 0;
2032         radeon_crtc->encoder = NULL;
2033         radeon_crtc->connector = NULL;
2034 }
2035
2036 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2037         .dpms = atombios_crtc_dpms,
2038         .mode_fixup = atombios_crtc_mode_fixup,
2039         .mode_set = atombios_crtc_mode_set,
2040         .mode_set_base = atombios_crtc_set_base,
2041         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2042         .prepare = atombios_crtc_prepare,
2043         .commit = atombios_crtc_commit,
2044         .load_lut = radeon_crtc_load_lut,
2045         .disable = atombios_crtc_disable,
2046 };
2047
2048 void radeon_atombios_init_crtc(struct drm_device *dev,
2049                                struct radeon_crtc *radeon_crtc)
2050 {
2051         struct radeon_device *rdev = dev->dev_private;
2052
2053         if (ASIC_IS_DCE4(rdev)) {
2054                 switch (radeon_crtc->crtc_id) {
2055                 case 0:
2056                 default:
2057                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2058                         break;
2059                 case 1:
2060                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2061                         break;
2062                 case 2:
2063                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2064                         break;
2065                 case 3:
2066                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2067                         break;
2068                 case 4:
2069                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2070                         break;
2071                 case 5:
2072                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2073                         break;
2074                 }
2075         } else {
2076                 if (radeon_crtc->crtc_id == 1)
2077                         radeon_crtc->crtc_offset =
2078                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2079                 else
2080                         radeon_crtc->crtc_offset = 0;
2081         }
2082         radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2083         radeon_crtc->adjusted_clock = 0;
2084         radeon_crtc->encoder = NULL;
2085         radeon_crtc->connector = NULL;
2086         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2087 }