Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static bool intel_crtc_active(struct drm_crtc *crtc)
  48 {
  49         /* Be paranoid as we can arrive here with only partial
  50          * state retrieved from the hardware during setup.
  51          */
  52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  53 }
  54
  55 static void i8xx_disable_fbc(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         u32 fbc_ctl;
  59
  60         /* Disable compression */
  61         fbc_ctl = I915_READ(FBC_CONTROL);
  62         if ((fbc_ctl & FBC_CTL_EN) == 0)
  63                 return;
  64
  65         fbc_ctl &= ~FBC_CTL_EN;
  66         I915_WRITE(FBC_CONTROL, fbc_ctl);
  67
  68         /* Wait for compressing bit to clear */
  69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  70                 DRM_DEBUG_KMS("FBC idle timed out\n");
  71                 return;
  72         }
  73
  74         DRM_DEBUG_KMS("disabled FBC\n");
  75 }
  76
  77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  78 {
  79         struct drm_device *dev = crtc->dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct drm_framebuffer *fb = crtc->fb;
  82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  83         struct drm_i915_gem_object *obj = intel_fb->obj;
  84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  85         int cfb_pitch;
  86         int plane, i;
  87         u32 fbc_ctl, fbc_ctl2;
  88
  89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  90         if (fb->pitches[0] < cfb_pitch)
  91                 cfb_pitch = fb->pitches[0];
  92
  93         /* FBC_CTL wants 64B units */
  94         cfb_pitch = (cfb_pitch / 64) - 1;
  95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  96
  97         /* Clear old tags */
  98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  99                 I915_WRITE(FBC_TAG + (i * 4), 0);
 100
 101         /* Set it up... */
 102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 103         fbc_ctl2 |= plane;
 104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 106
 107         /* enable it... */
 108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 109         if (IS_I945GM(dev))
 110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->fb;
 132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 133         struct drm_i915_gem_object *obj = intel_fb->obj;
 134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 136         unsigned long stall_watermark = 200;
 137         u32 dpfc_ctl;
 138
 139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 142
 143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 147
 148         /* enable it... */
 149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 150
 151         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 152 }
 153
 154 static void g4x_disable_fbc(struct drm_device *dev)
 155 {
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         u32 dpfc_ctl;
 158
 159         /* Disable compression */
 160         dpfc_ctl = I915_READ(DPFC_CONTROL);
 161         if (dpfc_ctl & DPFC_CTL_EN) {
 162                 dpfc_ctl &= ~DPFC_CTL_EN;
 163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 164
 165                 DRM_DEBUG_KMS("disabled FBC\n");
 166         }
 167 }
 168
 169 static bool g4x_fbc_enabled(struct drm_device *dev)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172
 173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 174 }
 175
 176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 177 {
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         u32 blt_ecoskpd;
 180
 181         /* Make sure blitter notifies FBC of writes */
 182         gen6_gt_force_wake_get(dev_priv);
 183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 185                 GEN6_BLITTER_LOCK_SHIFT;
 186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 190                          GEN6_BLITTER_LOCK_SHIFT);
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 193         gen6_gt_force_wake_put(dev_priv);
 194 }
 195
 196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->fb;
 201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 202         struct drm_i915_gem_object *obj = intel_fb->obj;
 203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 205         unsigned long stall_watermark = 200;
 206         u32 dpfc_ctl;
 207
 208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 209         dpfc_ctl &= DPFC_RESERVED;
 210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 211         /* Set persistent mode for front-buffer rendering, ala X. */
 212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 215
 216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 221         /* enable it... */
 222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 223
 224         if (IS_GEN6(dev)) {
 225                 I915_WRITE(SNB_DPFC_CTL_SA,
 226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 228                 sandybridge_blit_fbc_update(dev);
 229         }
 230
 231         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 232 }
 233
 234 static void ironlake_disable_fbc(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         u32 dpfc_ctl;
 238
 239         /* Disable compression */
 240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 241         if (dpfc_ctl & DPFC_CTL_EN) {
 242                 dpfc_ctl &= ~DPFC_CTL_EN;
 243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 244
 245                 if (IS_IVYBRIDGE(dev))
 246                         /* WaFbcDisableDpfcClockGating:ivb */
 247                         I915_WRITE(ILK_DSPCLK_GATE_D,
 248                                    I915_READ(ILK_DSPCLK_GATE_D) &
 249                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 250
 251                 if (IS_HASWELL(dev))
 252                         /* WaFbcDisableDpfcClockGating:hsw */
 253                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 254                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 255                                    ~HSW_DPFC_GATING_DISABLE);
 256
 257                 DRM_DEBUG_KMS("disabled FBC\n");
 258         }
 259 }
 260
 261 static bool ironlake_fbc_enabled(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264
 265         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 266 }
 267
 268 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 269 {
 270         struct drm_device *dev = crtc->dev;
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         struct drm_framebuffer *fb = crtc->fb;
 273         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 274         struct drm_i915_gem_object *obj = intel_fb->obj;
 275         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 276
 277         I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 278
 279         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 280                    IVB_DPFC_CTL_FENCE_EN |
 281                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 282
 283         if (IS_IVYBRIDGE(dev)) {
 284                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 285                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 286                 /* WaFbcDisableDpfcClockGating:ivb */
 287                 I915_WRITE(ILK_DSPCLK_GATE_D,
 288                            I915_READ(ILK_DSPCLK_GATE_D) |
 289                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 290         } else {
 291                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 292                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 293                            HSW_BYPASS_FBC_QUEUE);
 294                 /* WaFbcDisableDpfcClockGating:hsw */
 295                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 296                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 297                            HSW_DPFC_GATING_DISABLE);
 298         }
 299
 300         I915_WRITE(SNB_DPFC_CTL_SA,
 301                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 302         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 303
 304         sandybridge_blit_fbc_update(dev);
 305
 306         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 307 }
 308
 309 bool intel_fbc_enabled(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312
 313         if (!dev_priv->display.fbc_enabled)
 314                 return false;
 315
 316         return dev_priv->display.fbc_enabled(dev);
 317 }
 318
 319 static void intel_fbc_work_fn(struct work_struct *__work)
 320 {
 321         struct intel_fbc_work *work =
 322                 container_of(to_delayed_work(__work),
 323                              struct intel_fbc_work, work);
 324         struct drm_device *dev = work->crtc->dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         mutex_lock(&dev->struct_mutex);
 328         if (work == dev_priv->fbc_work) {
 329                 /* Double check that we haven't switched fb without cancelling
 330                  * the prior work.
 331                  */
 332                 if (work->crtc->fb == work->fb) {
 333                         dev_priv->display.enable_fbc(work->crtc,
 334                                                      work->interval);
 335
 336                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 337                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 338                         dev_priv->cfb_y = work->crtc->y;
 339                 }
 340
 341                 dev_priv->fbc_work = NULL;
 342         }
 343         mutex_unlock(&dev->struct_mutex);
 344
 345         kfree(work);
 346 }
 347
 348 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 349 {
 350         if (dev_priv->fbc_work == NULL)
 351                 return;
 352
 353         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 354
 355         /* Synchronisation is provided by struct_mutex and checking of
 356          * dev_priv->fbc_work, so we can perform the cancellation
 357          * entirely asynchronously.
 358          */
 359         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 360                 /* tasklet was killed before being run, clean up */
 361                 kfree(dev_priv->fbc_work);
 362
 363         /* Mark the work as no longer wanted so that if it does
 364          * wake-up (because the work was already running and waiting
 365          * for our mutex), it will discover that is no longer
 366          * necessary to run.
 367          */
 368         dev_priv->fbc_work = NULL;
 369 }
 370
 371 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 372 {
 373         struct intel_fbc_work *work;
 374         struct drm_device *dev = crtc->dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376
 377         if (!dev_priv->display.enable_fbc)
 378                 return;
 379
 380         intel_cancel_fbc_work(dev_priv);
 381
 382         work = kzalloc(sizeof *work, GFP_KERNEL);
 383         if (work == NULL) {
 384                 dev_priv->display.enable_fbc(crtc, interval);
 385                 return;
 386         }
 387
 388         work->crtc = crtc;
 389         work->fb = crtc->fb;
 390         work->interval = interval;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc_work = work;
 394
 395         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 396
 397         /* Delay the actual enabling to let pageflipping cease and the
 398          * display to settle before starting the compression. Note that
 399          * this delay also serves a second purpose: it allows for a
 400          * vblank to pass after disabling the FBC before we attempt
 401          * to modify the control registers.
 402          *
 403          * A more complicated solution would involve tracking vblanks
 404          * following the termination of the page-flipping sequence
 405          * and indeed performing the enable as a co-routine and not
 406          * waiting synchronously upon the vblank.
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->cfb_plane = -1;
 422 }
 423
 424 /**
 425  * intel_update_fbc - enable/disable FBC as needed
 426  * @dev: the drm_device
 427  *
 428  * Set up the framebuffer compression hardware at mode set time.  We
 429  * enable it if possible:
 430  *   - plane A only (on pre-965)
 431  *   - no pixel mulitply/line duplication
 432  *   - no alpha buffer discard
 433  *   - no dual wide
 434  *   - framebuffer <= 2048 in width, 1536 in height
 435  *
 436  * We can't assume that any compression will take place (worst case),
 437  * so the compressed buffer has to be the same size as the uncompressed
 438  * one.  It also must reside (along with the line length buffer) in
 439  * stolen memory.
 440  *
 441  * We need to enable/disable FBC on a global basis.
 442  */
 443 void intel_update_fbc(struct drm_device *dev)
 444 {
 445         struct drm_i915_private *dev_priv = dev->dev_private;
 446         struct drm_crtc *crtc = NULL, *tmp_crtc;
 447         struct intel_crtc *intel_crtc;
 448         struct drm_framebuffer *fb;
 449         struct intel_framebuffer *intel_fb;
 450         struct drm_i915_gem_object *obj;
 451         int enable_fbc;
 452
 453         if (!i915_powersave)
 454                 return;
 455
 456         if (!I915_HAS_FBC(dev))
 457                 return;
 458
 459         /*
 460          * If FBC is already on, we just have to verify that we can
 461          * keep it that way...
 462          * Need to disable if:
 463          *   - more than one pipe is active
 464          *   - changing FBC params (stride, fence, mode)
 465          *   - new fb is too large to fit in compressed buffer
 466          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 467          */
 468         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 469                 if (intel_crtc_active(tmp_crtc) &&
 470                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 471                         if (crtc) {
 472                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 473                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 474                                 goto out_disable;
 475                         }
 476                         crtc = tmp_crtc;
 477                 }
 478         }
 479
 480         if (!crtc || crtc->fb == NULL) {
 481                 DRM_DEBUG_KMS("no output, disabling\n");
 482                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 483                 goto out_disable;
 484         }
 485
 486         intel_crtc = to_intel_crtc(crtc);
 487         fb = crtc->fb;
 488         intel_fb = to_intel_framebuffer(fb);
 489         obj = intel_fb->obj;
 490
 491         enable_fbc = i915_enable_fbc;
 492         if (enable_fbc < 0) {
 493                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 494                 enable_fbc = 1;
 495                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
 496                         enable_fbc = 0;
 497         }
 498         if (!enable_fbc) {
 499                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 500                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 501                 goto out_disable;
 502         }
 503         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 504             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 505                 DRM_DEBUG_KMS("mode incompatible with compression, "
 506                               "disabling\n");
 507                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 508                 goto out_disable;
 509         }
 510         if ((crtc->mode.hdisplay > 2048) ||
 511             (crtc->mode.vdisplay > 1536)) {
 512                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 513                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 514                 goto out_disable;
 515         }
 516         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 517             intel_crtc->plane != 0) {
 518                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 519                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 520                 goto out_disable;
 521         }
 522
 523         /* The use of a CPU fence is mandatory in order to detect writes
 524          * by the CPU to the scanout and trigger updates to the FBC.
 525          */
 526         if (obj->tiling_mode != I915_TILING_X ||
 527             obj->fence_reg == I915_FENCE_REG_NONE) {
 528                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 529                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 530                 goto out_disable;
 531         }
 532
 533         /* If the kernel debugger is active, always disable compression */
 534         if (in_dbg_master())
 535                 goto out_disable;
 536
 537         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 538                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 539                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 540                 goto out_disable;
 541         }
 542
 543         /* If the scanout has not changed, don't modify the FBC settings.
 544          * Note that we make the fundamental assumption that the fb->obj
 545          * cannot be unpinned (and have its GTT offset and fence revoked)
 546          * without first being decoupled from the scanout and FBC disabled.
 547          */
 548         if (dev_priv->cfb_plane == intel_crtc->plane &&
 549             dev_priv->cfb_fb == fb->base.id &&
 550             dev_priv->cfb_y == crtc->y)
 551                 return;
 552
 553         if (intel_fbc_enabled(dev)) {
 554                 /* We update FBC along two paths, after changing fb/crtc
 555                  * configuration (modeswitching) and after page-flipping
 556                  * finishes. For the latter, we know that not only did
 557                  * we disable the FBC at the start of the page-flip
 558                  * sequence, but also more than one vblank has passed.
 559                  *
 560                  * For the former case of modeswitching, it is possible
 561                  * to switch between two FBC valid configurations
 562                  * instantaneously so we do need to disable the FBC
 563                  * before we can modify its control registers. We also
 564                  * have to wait for the next vblank for that to take
 565                  * effect. However, since we delay enabling FBC we can
 566                  * assume that a vblank has passed since disabling and
 567                  * that we can safely alter the registers in the deferred
 568                  * callback.
 569                  *
 570                  * In the scenario that we go from a valid to invalid
 571                  * and then back to valid FBC configuration we have
 572                  * no strict enforcement that a vblank occurred since
 573                  * disabling the FBC. However, along all current pipe
 574                  * disabling paths we do need to wait for a vblank at
 575                  * some point. And we wait before enabling FBC anyway.
 576                  */
 577                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 578                 intel_disable_fbc(dev);
 579         }
 580
 581         intel_enable_fbc(crtc, 500);
 582         return;
 583
 584 out_disable:
 585         /* Multiple disables should be harmless */
 586         if (intel_fbc_enabled(dev)) {
 587                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 588                 intel_disable_fbc(dev);
 589         }
 590         i915_gem_stolen_cleanup_compression(dev);
 591 }
 592
 593 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 594 {
 595         drm_i915_private_t *dev_priv = dev->dev_private;
 596         u32 tmp;
 597
 598         tmp = I915_READ(CLKCFG);
 599
 600         switch (tmp & CLKCFG_FSB_MASK) {
 601         case CLKCFG_FSB_533:
 602                 dev_priv->fsb_freq = 533; /* 133*4 */
 603                 break;
 604         case CLKCFG_FSB_800:
 605                 dev_priv->fsb_freq = 800; /* 200*4 */
 606                 break;
 607         case CLKCFG_FSB_667:
 608                 dev_priv->fsb_freq =  667; /* 167*4 */
 609                 break;
 610         case CLKCFG_FSB_400:
 611                 dev_priv->fsb_freq = 400; /* 100*4 */
 612                 break;
 613         }
 614
 615         switch (tmp & CLKCFG_MEM_MASK) {
 616         case CLKCFG_MEM_533:
 617                 dev_priv->mem_freq = 533;
 618                 break;
 619         case CLKCFG_MEM_667:
 620                 dev_priv->mem_freq = 667;
 621                 break;
 622         case CLKCFG_MEM_800:
 623                 dev_priv->mem_freq = 800;
 624                 break;
 625         }
 626
 627         /* detect pineview DDR3 setting */
 628         tmp = I915_READ(CSHRDDR3CTL);
 629         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 630 }
 631
 632 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 633 {
 634         drm_i915_private_t *dev_priv = dev->dev_private;
 635         u16 ddrpll, csipll;
 636
 637         ddrpll = I915_READ16(DDRMPLL1);
 638         csipll = I915_READ16(CSIPLL0);
 639
 640         switch (ddrpll & 0xff) {
 641         case 0xc:
 642                 dev_priv->mem_freq = 800;
 643                 break;
 644         case 0x10:
 645                 dev_priv->mem_freq = 1066;
 646                 break;
 647         case 0x14:
 648                 dev_priv->mem_freq = 1333;
 649                 break;
 650         case 0x18:
 651                 dev_priv->mem_freq = 1600;
 652                 break;
 653         default:
 654                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 655                                  ddrpll & 0xff);
 656                 dev_priv->mem_freq = 0;
 657                 break;
 658         }
 659
 660         dev_priv->ips.r_t = dev_priv->mem_freq;
 661
 662         switch (csipll & 0x3ff) {
 663         case 0x00c:
 664                 dev_priv->fsb_freq = 3200;
 665                 break;
 666         case 0x00e:
 667                 dev_priv->fsb_freq = 3733;
 668                 break;
 669         case 0x010:
 670                 dev_priv->fsb_freq = 4266;
 671                 break;
 672         case 0x012:
 673                 dev_priv->fsb_freq = 4800;
 674                 break;
 675         case 0x014:
 676                 dev_priv->fsb_freq = 5333;
 677                 break;
 678         case 0x016:
 679                 dev_priv->fsb_freq = 5866;
 680                 break;
 681         case 0x018:
 682                 dev_priv->fsb_freq = 6400;
 683                 break;
 684         default:
 685                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 686                                  csipll & 0x3ff);
 687                 dev_priv->fsb_freq = 0;
 688                 break;
 689         }
 690
 691         if (dev_priv->fsb_freq == 3200) {
 692                 dev_priv->ips.c_m = 0;
 693         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 694                 dev_priv->ips.c_m = 1;
 695         } else {
 696                 dev_priv->ips.c_m = 2;
 697         }
 698 }
 699
 700 static const struct cxsr_latency cxsr_latency_table[] = {
 701         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 702         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 703         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 704         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 705         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 706
 707         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 708         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 709         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 710         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 711         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 712
 713         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 714         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 715         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 716         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 717         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 718
 719         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 720         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 721         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 722         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 723         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 724
 725         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 726         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 727         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 728         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 729         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 730
 731         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 732         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 733         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 734         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 735         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 736 };
 737
 738 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 739                                                          int is_ddr3,
 740                                                          int fsb,
 741                                                          int mem)
 742 {
 743         const struct cxsr_latency *latency;
 744         int i;
 745
 746         if (fsb == 0 || mem == 0)
 747                 return NULL;
 748
 749         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 750                 latency = &cxsr_latency_table[i];
 751                 if (is_desktop == latency->is_desktop &&
 752                     is_ddr3 == latency->is_ddr3 &&
 753                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 754                         return latency;
 755         }
 756
 757         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 758
 759         return NULL;
 760 }
 761
 762 static void pineview_disable_cxsr(struct drm_device *dev)
 763 {
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765
 766         /* deactivate cxsr */
 767         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 768 }
 769
 770 /*
 771  * Latency for FIFO fetches is dependent on several factors:
 772  *   - memory configuration (speed, channels)
 773  *   - chipset
 774  *   - current MCH state
 775  * It can be fairly high in some situations, so here we assume a fairly
 776  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 777  * set this value too high, the FIFO will fetch frequently to stay full)
 778  * and power consumption (set it too low to save power and we might see
 779  * FIFO underruns and display "flicker").
 780  *
 781  * A value of 5us seems to be a good balance; safe for very low end
 782  * platforms but not overly aggressive on lower latency configs.
 783  */
 784 static const int latency_ns = 5000;
 785
 786 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 787 {
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         uint32_t dsparb = I915_READ(DSPARB);
 790         int size;
 791
 792         size = dsparb & 0x7f;
 793         if (plane)
 794                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 795
 796         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 797                       plane ? "B" : "A", size);
 798
 799         return size;
 800 }
 801
 802 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 803 {
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805         uint32_t dsparb = I915_READ(DSPARB);
 806         int size;
 807
 808         size = dsparb & 0x1ff;
 809         if (plane)
 810                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 811         size >>= 1; /* Convert to cachelines */
 812
 813         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 814                       plane ? "B" : "A", size);
 815
 816         return size;
 817 }
 818
 819 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         uint32_t dsparb = I915_READ(DSPARB);
 823         int size;
 824
 825         size = dsparb & 0x7f;
 826         size >>= 2; /* Convert to cachelines */
 827
 828         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 829                       plane ? "B" : "A",
 830                       size);
 831
 832         return size;
 833 }
 834
 835 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 836 {
 837         struct drm_i915_private *dev_priv = dev->dev_private;
 838         uint32_t dsparb = I915_READ(DSPARB);
 839         int size;
 840
 841         size = dsparb & 0x7f;
 842         size >>= 1; /* Convert to cachelines */
 843
 844         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 845                       plane ? "B" : "A", size);
 846
 847         return size;
 848 }
 849
 850 /* Pineview has different values for various configs */
 851 static const struct intel_watermark_params pineview_display_wm = {
 852         PINEVIEW_DISPLAY_FIFO,
 853         PINEVIEW_MAX_WM,
 854         PINEVIEW_DFT_WM,
 855         PINEVIEW_GUARD_WM,
 856         PINEVIEW_FIFO_LINE_SIZE
 857 };
 858 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 859         PINEVIEW_DISPLAY_FIFO,
 860         PINEVIEW_MAX_WM,
 861         PINEVIEW_DFT_HPLLOFF_WM,
 862         PINEVIEW_GUARD_WM,
 863         PINEVIEW_FIFO_LINE_SIZE
 864 };
 865 static const struct intel_watermark_params pineview_cursor_wm = {
 866         PINEVIEW_CURSOR_FIFO,
 867         PINEVIEW_CURSOR_MAX_WM,
 868         PINEVIEW_CURSOR_DFT_WM,
 869         PINEVIEW_CURSOR_GUARD_WM,
 870         PINEVIEW_FIFO_LINE_SIZE,
 871 };
 872 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 873         PINEVIEW_CURSOR_FIFO,
 874         PINEVIEW_CURSOR_MAX_WM,
 875         PINEVIEW_CURSOR_DFT_WM,
 876         PINEVIEW_CURSOR_GUARD_WM,
 877         PINEVIEW_FIFO_LINE_SIZE
 878 };
 879 static const struct intel_watermark_params g4x_wm_info = {
 880         G4X_FIFO_SIZE,
 881         G4X_MAX_WM,
 882         G4X_MAX_WM,
 883         2,
 884         G4X_FIFO_LINE_SIZE,
 885 };
 886 static const struct intel_watermark_params g4x_cursor_wm_info = {
 887         I965_CURSOR_FIFO,
 888         I965_CURSOR_MAX_WM,
 889         I965_CURSOR_DFT_WM,
 890         2,
 891         G4X_FIFO_LINE_SIZE,
 892 };
 893 static const struct intel_watermark_params valleyview_wm_info = {
 894         VALLEYVIEW_FIFO_SIZE,
 895         VALLEYVIEW_MAX_WM,
 896         VALLEYVIEW_MAX_WM,
 897         2,
 898         G4X_FIFO_LINE_SIZE,
 899 };
 900 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 901         I965_CURSOR_FIFO,
 902         VALLEYVIEW_CURSOR_MAX_WM,
 903         I965_CURSOR_DFT_WM,
 904         2,
 905         G4X_FIFO_LINE_SIZE,
 906 };
 907 static const struct intel_watermark_params i965_cursor_wm_info = {
 908         I965_CURSOR_FIFO,
 909         I965_CURSOR_MAX_WM,
 910         I965_CURSOR_DFT_WM,
 911         2,
 912         I915_FIFO_LINE_SIZE,
 913 };
 914 static const struct intel_watermark_params i945_wm_info = {
 915         I945_FIFO_SIZE,
 916         I915_MAX_WM,
 917         1,
 918         2,
 919         I915_FIFO_LINE_SIZE
 920 };
 921 static const struct intel_watermark_params i915_wm_info = {
 922         I915_FIFO_SIZE,
 923         I915_MAX_WM,
 924         1,
 925         2,
 926         I915_FIFO_LINE_SIZE
 927 };
 928 static const struct intel_watermark_params i855_wm_info = {
 929         I855GM_FIFO_SIZE,
 930         I915_MAX_WM,
 931         1,
 932         2,
 933         I830_FIFO_LINE_SIZE
 934 };
 935 static const struct intel_watermark_params i830_wm_info = {
 936         I830_FIFO_SIZE,
 937         I915_MAX_WM,
 938         1,
 939         2,
 940         I830_FIFO_LINE_SIZE
 941 };
 942
 943 static const struct intel_watermark_params ironlake_display_wm_info = {
 944         ILK_DISPLAY_FIFO,
 945         ILK_DISPLAY_MAXWM,
 946         ILK_DISPLAY_DFTWM,
 947         2,
 948         ILK_FIFO_LINE_SIZE
 949 };
 950 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 951         ILK_CURSOR_FIFO,
 952         ILK_CURSOR_MAXWM,
 953         ILK_CURSOR_DFTWM,
 954         2,
 955         ILK_FIFO_LINE_SIZE
 956 };
 957 static const struct intel_watermark_params ironlake_display_srwm_info = {
 958         ILK_DISPLAY_SR_FIFO,
 959         ILK_DISPLAY_MAX_SRWM,
 960         ILK_DISPLAY_DFT_SRWM,
 961         2,
 962         ILK_FIFO_LINE_SIZE
 963 };
 964 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 965         ILK_CURSOR_SR_FIFO,
 966         ILK_CURSOR_MAX_SRWM,
 967         ILK_CURSOR_DFT_SRWM,
 968         2,
 969         ILK_FIFO_LINE_SIZE
 970 };
 971
 972 static const struct intel_watermark_params sandybridge_display_wm_info = {
 973         SNB_DISPLAY_FIFO,
 974         SNB_DISPLAY_MAXWM,
 975         SNB_DISPLAY_DFTWM,
 976         2,
 977         SNB_FIFO_LINE_SIZE
 978 };
 979 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 980         SNB_CURSOR_FIFO,
 981         SNB_CURSOR_MAXWM,
 982         SNB_CURSOR_DFTWM,
 983         2,
 984         SNB_FIFO_LINE_SIZE
 985 };
 986 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 987         SNB_DISPLAY_SR_FIFO,
 988         SNB_DISPLAY_MAX_SRWM,
 989         SNB_DISPLAY_DFT_SRWM,
 990         2,
 991         SNB_FIFO_LINE_SIZE
 992 };
 993 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 994         SNB_CURSOR_SR_FIFO,
 995         SNB_CURSOR_MAX_SRWM,
 996         SNB_CURSOR_DFT_SRWM,
 997         2,
 998         SNB_FIFO_LINE_SIZE
 999 };
1000
1001
1002 /**
1003  * intel_calculate_wm - calculate watermark level
1004  * @clock_in_khz: pixel clock
1005  * @wm: chip FIFO params
1006  * @pixel_size: display pixel size
1007  * @latency_ns: memory latency for the platform
1008  *
1009  * Calculate the watermark level (the level at which the display plane will
1010  * start fetching from memory again).  Each chip has a different display
1011  * FIFO size and allocation, so the caller needs to figure that out and pass
1012  * in the correct intel_watermark_params structure.
1013  *
1014  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1015  * on the pixel size.  When it reaches the watermark level, it'll start
1016  * fetching FIFO line sized based chunks from memory until the FIFO fills
1017  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1018  * will occur, and a display engine hang could result.
1019  */
1020 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1021                                         const struct intel_watermark_params *wm,
1022                                         int fifo_size,
1023                                         int pixel_size,
1024                                         unsigned long latency_ns)
1025 {
1026         long entries_required, wm_size;
1027
1028         /*
1029          * Note: we need to make sure we don't overflow for various clock &
1030          * latency values.
1031          * clocks go from a few thousand to several hundred thousand.
1032          * latency is usually a few thousand
1033          */
1034         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1035                 1000;
1036         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1037
1038         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1039
1040         wm_size = fifo_size - (entries_required + wm->guard_size);
1041
1042         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1043
1044         /* Don't promote wm_size to unsigned... */
1045         if (wm_size > (long)wm->max_wm)
1046                 wm_size = wm->max_wm;
1047         if (wm_size <= 0)
1048                 wm_size = wm->default_wm;
1049         return wm_size;
1050 }
1051
1052 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1053 {
1054         struct drm_crtc *crtc, *enabled = NULL;
1055
1056         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1057                 if (intel_crtc_active(crtc)) {
1058                         if (enabled)
1059                                 return NULL;
1060                         enabled = crtc;
1061                 }
1062         }
1063
1064         return enabled;
1065 }
1066
1067 static void pineview_update_wm(struct drm_device *dev)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         struct drm_crtc *crtc;
1071         const struct cxsr_latency *latency;
1072         u32 reg;
1073         unsigned long wm;
1074
1075         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1076                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1077         if (!latency) {
1078                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1079                 pineview_disable_cxsr(dev);
1080                 return;
1081         }
1082
1083         crtc = single_enabled_crtc(dev);
1084         if (crtc) {
1085                 int clock = crtc->mode.clock;
1086                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1087
1088                 /* Display SR */
1089                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1090                                         pineview_display_wm.fifo_size,
1091                                         pixel_size, latency->display_sr);
1092                 reg = I915_READ(DSPFW1);
1093                 reg &= ~DSPFW_SR_MASK;
1094                 reg |= wm << DSPFW_SR_SHIFT;
1095                 I915_WRITE(DSPFW1, reg);
1096                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1097
1098                 /* cursor SR */
1099                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1100                                         pineview_display_wm.fifo_size,
1101                                         pixel_size, latency->cursor_sr);
1102                 reg = I915_READ(DSPFW3);
1103                 reg &= ~DSPFW_CURSOR_SR_MASK;
1104                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1105                 I915_WRITE(DSPFW3, reg);
1106
1107                 /* Display HPLL off SR */
1108                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1109                                         pineview_display_hplloff_wm.fifo_size,
1110                                         pixel_size, latency->display_hpll_disable);
1111                 reg = I915_READ(DSPFW3);
1112                 reg &= ~DSPFW_HPLL_SR_MASK;
1113                 reg |= wm & DSPFW_HPLL_SR_MASK;
1114                 I915_WRITE(DSPFW3, reg);
1115
1116                 /* cursor HPLL off SR */
1117                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1118                                         pineview_display_hplloff_wm.fifo_size,
1119                                         pixel_size, latency->cursor_hpll_disable);
1120                 reg = I915_READ(DSPFW3);
1121                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1122                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1123                 I915_WRITE(DSPFW3, reg);
1124                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1125
1126                 /* activate cxsr */
1127                 I915_WRITE(DSPFW3,
1128                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1129                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1130         } else {
1131                 pineview_disable_cxsr(dev);
1132                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1133         }
1134 }
1135
1136 static bool g4x_compute_wm0(struct drm_device *dev,
1137                             int plane,
1138                             const struct intel_watermark_params *display,
1139                             int display_latency_ns,
1140                             const struct intel_watermark_params *cursor,
1141                             int cursor_latency_ns,
1142                             int *plane_wm,
1143                             int *cursor_wm)
1144 {
1145         struct drm_crtc *crtc;
1146         int htotal, hdisplay, clock, pixel_size;
1147         int line_time_us, line_count;
1148         int entries, tlb_miss;
1149
1150         crtc = intel_get_crtc_for_plane(dev, plane);
1151         if (!intel_crtc_active(crtc)) {
1152                 *cursor_wm = cursor->guard_size;
1153                 *plane_wm = display->guard_size;
1154                 return false;
1155         }
1156
1157         htotal = crtc->mode.htotal;
1158         hdisplay = crtc->mode.hdisplay;
1159         clock = crtc->mode.clock;
1160         pixel_size = crtc->fb->bits_per_pixel / 8;
1161
1162         /* Use the small buffer method to calculate plane watermark */
1163         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1164         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1165         if (tlb_miss > 0)
1166                 entries += tlb_miss;
1167         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1168         *plane_wm = entries + display->guard_size;
1169         if (*plane_wm > (int)display->max_wm)
1170                 *plane_wm = display->max_wm;
1171
1172         /* Use the large buffer method to calculate cursor watermark */
1173         line_time_us = ((htotal * 1000) / clock);
1174         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1175         entries = line_count * 64 * pixel_size;
1176         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1177         if (tlb_miss > 0)
1178                 entries += tlb_miss;
1179         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1180         *cursor_wm = entries + cursor->guard_size;
1181         if (*cursor_wm > (int)cursor->max_wm)
1182                 *cursor_wm = (int)cursor->max_wm;
1183
1184         return true;
1185 }
1186
1187 /*
1188  * Check the wm result.
1189  *
1190  * If any calculated watermark values is larger than the maximum value that
1191  * can be programmed into the associated watermark register, that watermark
1192  * must be disabled.
1193  */
1194 static bool g4x_check_srwm(struct drm_device *dev,
1195                            int display_wm, int cursor_wm,
1196                            const struct intel_watermark_params *display,
1197                            const struct intel_watermark_params *cursor)
1198 {
1199         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1200                       display_wm, cursor_wm);
1201
1202         if (display_wm > display->max_wm) {
1203                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1204                               display_wm, display->max_wm);
1205                 return false;
1206         }
1207
1208         if (cursor_wm > cursor->max_wm) {
1209                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1210                               cursor_wm, cursor->max_wm);
1211                 return false;
1212         }
1213
1214         if (!(display_wm || cursor_wm)) {
1215                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1216                 return false;
1217         }
1218
1219         return true;
1220 }
1221
1222 static bool g4x_compute_srwm(struct drm_device *dev,
1223                              int plane,
1224                              int latency_ns,
1225                              const struct intel_watermark_params *display,
1226                              const struct intel_watermark_params *cursor,
1227                              int *display_wm, int *cursor_wm)
1228 {
1229         struct drm_crtc *crtc;
1230         int hdisplay, htotal, pixel_size, clock;
1231         unsigned long line_time_us;
1232         int line_count, line_size;
1233         int small, large;
1234         int entries;
1235
1236         if (!latency_ns) {
1237                 *display_wm = *cursor_wm = 0;
1238                 return false;
1239         }
1240
1241         crtc = intel_get_crtc_for_plane(dev, plane);
1242         hdisplay = crtc->mode.hdisplay;
1243         htotal = crtc->mode.htotal;
1244         clock = crtc->mode.clock;
1245         pixel_size = crtc->fb->bits_per_pixel / 8;
1246
1247         line_time_us = (htotal * 1000) / clock;
1248         line_count = (latency_ns / line_time_us + 1000) / 1000;
1249         line_size = hdisplay * pixel_size;
1250
1251         /* Use the minimum of the small and large buffer method for primary */
1252         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1253         large = line_count * line_size;
1254
1255         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1256         *display_wm = entries + display->guard_size;
1257
1258         /* calculate the self-refresh watermark for display cursor */
1259         entries = line_count * pixel_size * 64;
1260         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1261         *cursor_wm = entries + cursor->guard_size;
1262
1263         return g4x_check_srwm(dev,
1264                               *display_wm, *cursor_wm,
1265                               display, cursor);
1266 }
1267
1268 static bool vlv_compute_drain_latency(struct drm_device *dev,
1269                                      int plane,
1270                                      int *plane_prec_mult,
1271                                      int *plane_dl,
1272                                      int *cursor_prec_mult,
1273                                      int *cursor_dl)
1274 {
1275         struct drm_crtc *crtc;
1276         int clock, pixel_size;
1277         int entries;
1278
1279         crtc = intel_get_crtc_for_plane(dev, plane);
1280         if (!intel_crtc_active(crtc))
1281                 return false;
1282
1283         clock = crtc->mode.clock;       /* VESA DOT Clock */
1284         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1285
1286         entries = (clock / 1000) * pixel_size;
1287         *plane_prec_mult = (entries > 256) ?
1288                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1289         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1290                                                      pixel_size);
1291
1292         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1293         *cursor_prec_mult = (entries > 256) ?
1294                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1295         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1296
1297         return true;
1298 }
1299
1300 /*
1301  * Update drain latency registers of memory arbiter
1302  *
1303  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1304  * to be programmed. Each plane has a drain latency multiplier and a drain
1305  * latency value.
1306  */
1307
1308 static void vlv_update_drain_latency(struct drm_device *dev)
1309 {
1310         struct drm_i915_private *dev_priv = dev->dev_private;
1311         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1312         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1313         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1314                                                         either 16 or 32 */
1315
1316         /* For plane A, Cursor A */
1317         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1318                                       &cursor_prec_mult, &cursora_dl)) {
1319                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1320                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1321                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1322                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1323
1324                 I915_WRITE(VLV_DDL1, cursora_prec |
1325                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1326                                 planea_prec | planea_dl);
1327         }
1328
1329         /* For plane B, Cursor B */
1330         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1331                                       &cursor_prec_mult, &cursorb_dl)) {
1332                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1333                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1334                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1335                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1336
1337                 I915_WRITE(VLV_DDL2, cursorb_prec |
1338                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1339                                 planeb_prec | planeb_dl);
1340         }
1341 }
1342
1343 #define single_plane_enabled(mask) is_power_of_2(mask)
1344
1345 static void valleyview_update_wm(struct drm_device *dev)
1346 {
1347         static const int sr_latency_ns = 12000;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1350         int plane_sr, cursor_sr;
1351         int ignore_plane_sr, ignore_cursor_sr;
1352         unsigned int enabled = 0;
1353
1354         vlv_update_drain_latency(dev);
1355
1356         if (g4x_compute_wm0(dev, PIPE_A,
1357                             &valleyview_wm_info, latency_ns,
1358                             &valleyview_cursor_wm_info, latency_ns,
1359                             &planea_wm, &cursora_wm))
1360                 enabled |= 1 << PIPE_A;
1361
1362         if (g4x_compute_wm0(dev, PIPE_B,
1363                             &valleyview_wm_info, latency_ns,
1364                             &valleyview_cursor_wm_info, latency_ns,
1365                             &planeb_wm, &cursorb_wm))
1366                 enabled |= 1 << PIPE_B;
1367
1368         if (single_plane_enabled(enabled) &&
1369             g4x_compute_srwm(dev, ffs(enabled) - 1,
1370                              sr_latency_ns,
1371                              &valleyview_wm_info,
1372                              &valleyview_cursor_wm_info,
1373                              &plane_sr, &ignore_cursor_sr) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              2*sr_latency_ns,
1376                              &valleyview_wm_info,
1377                              &valleyview_cursor_wm_info,
1378                              &ignore_plane_sr, &cursor_sr)) {
1379                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1380         } else {
1381                 I915_WRITE(FW_BLC_SELF_VLV,
1382                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1387                       planea_wm, cursora_wm,
1388                       planeb_wm, cursorb_wm,
1389                       plane_sr, cursor_sr);
1390
1391         I915_WRITE(DSPFW1,
1392                    (plane_sr << DSPFW_SR_SHIFT) |
1393                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1394                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1395                    planea_wm);
1396         I915_WRITE(DSPFW2,
1397                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1398                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1399         I915_WRITE(DSPFW3,
1400                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1401                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402 }
1403
1404 static void g4x_update_wm(struct drm_device *dev)
1405 {
1406         static const int sr_latency_ns = 12000;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1409         int plane_sr, cursor_sr;
1410         unsigned int enabled = 0;
1411
1412         if (g4x_compute_wm0(dev, PIPE_A,
1413                             &g4x_wm_info, latency_ns,
1414                             &g4x_cursor_wm_info, latency_ns,
1415                             &planea_wm, &cursora_wm))
1416                 enabled |= 1 << PIPE_A;
1417
1418         if (g4x_compute_wm0(dev, PIPE_B,
1419                             &g4x_wm_info, latency_ns,
1420                             &g4x_cursor_wm_info, latency_ns,
1421                             &planeb_wm, &cursorb_wm))
1422                 enabled |= 1 << PIPE_B;
1423
1424         if (single_plane_enabled(enabled) &&
1425             g4x_compute_srwm(dev, ffs(enabled) - 1,
1426                              sr_latency_ns,
1427                              &g4x_wm_info,
1428                              &g4x_cursor_wm_info,
1429                              &plane_sr, &cursor_sr)) {
1430                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1431         } else {
1432                 I915_WRITE(FW_BLC_SELF,
1433                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1434                 plane_sr = cursor_sr = 0;
1435         }
1436
1437         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1438                       planea_wm, cursora_wm,
1439                       planeb_wm, cursorb_wm,
1440                       plane_sr, cursor_sr);
1441
1442         I915_WRITE(DSPFW1,
1443                    (plane_sr << DSPFW_SR_SHIFT) |
1444                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1445                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1446                    planea_wm);
1447         I915_WRITE(DSPFW2,
1448                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1449                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1450         /* HPLL off in SR has some issues on G4x... disable it */
1451         I915_WRITE(DSPFW3,
1452                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1453                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1454 }
1455
1456 static void i965_update_wm(struct drm_device *dev)
1457 {
1458         struct drm_i915_private *dev_priv = dev->dev_private;
1459         struct drm_crtc *crtc;
1460         int srwm = 1;
1461         int cursor_sr = 16;
1462
1463         /* Calc sr entries for one plane configs */
1464         crtc = single_enabled_crtc(dev);
1465         if (crtc) {
1466                 /* self-refresh has much higher latency */
1467                 static const int sr_latency_ns = 12000;
1468                 int clock = crtc->mode.clock;
1469                 int htotal = crtc->mode.htotal;
1470                 int hdisplay = crtc->mode.hdisplay;
1471                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1472                 unsigned long line_time_us;
1473                 int entries;
1474
1475                 line_time_us = ((htotal * 1000) / clock);
1476
1477                 /* Use ns/us then divide to preserve precision */
1478                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1479                         pixel_size * hdisplay;
1480                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1481                 srwm = I965_FIFO_SIZE - entries;
1482                 if (srwm < 0)
1483                         srwm = 1;
1484                 srwm &= 0x1ff;
1485                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1486                               entries, srwm);
1487
1488                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1489                         pixel_size * 64;
1490                 entries = DIV_ROUND_UP(entries,
1491                                           i965_cursor_wm_info.cacheline_size);
1492                 cursor_sr = i965_cursor_wm_info.fifo_size -
1493                         (entries + i965_cursor_wm_info.guard_size);
1494
1495                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1496                         cursor_sr = i965_cursor_wm_info.max_wm;
1497
1498                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1499                               "cursor %d\n", srwm, cursor_sr);
1500
1501                 if (IS_CRESTLINE(dev))
1502                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1503         } else {
1504                 /* Turn off self refresh if both pipes are enabled */
1505                 if (IS_CRESTLINE(dev))
1506                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1507                                    & ~FW_BLC_SELF_EN);
1508         }
1509
1510         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1511                       srwm);
1512
1513         /* 965 has limitations... */
1514         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1515                    (8 << 16) | (8 << 8) | (8 << 0));
1516         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1517         /* update cursor SR watermark */
1518         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1519 }
1520
1521 static void i9xx_update_wm(struct drm_device *dev)
1522 {
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         const struct intel_watermark_params *wm_info;
1525         uint32_t fwater_lo;
1526         uint32_t fwater_hi;
1527         int cwm, srwm = 1;
1528         int fifo_size;
1529         int planea_wm, planeb_wm;
1530         struct drm_crtc *crtc, *enabled = NULL;
1531
1532         if (IS_I945GM(dev))
1533                 wm_info = &i945_wm_info;
1534         else if (!IS_GEN2(dev))
1535                 wm_info = &i915_wm_info;
1536         else
1537                 wm_info = &i855_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1540         crtc = intel_get_crtc_for_plane(dev, 0);
1541         if (intel_crtc_active(crtc)) {
1542                 int cpp = crtc->fb->bits_per_pixel / 8;
1543                 if (IS_GEN2(dev))
1544                         cpp = 4;
1545
1546                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1547                                                wm_info, fifo_size, cpp,
1548                                                latency_ns);
1549                 enabled = crtc;
1550         } else
1551                 planea_wm = fifo_size - wm_info->guard_size;
1552
1553         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1554         crtc = intel_get_crtc_for_plane(dev, 1);
1555         if (intel_crtc_active(crtc)) {
1556                 int cpp = crtc->fb->bits_per_pixel / 8;
1557                 if (IS_GEN2(dev))
1558                         cpp = 4;
1559
1560                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1561                                                wm_info, fifo_size, cpp,
1562                                                latency_ns);
1563                 if (enabled == NULL)
1564                         enabled = crtc;
1565                 else
1566                         enabled = NULL;
1567         } else
1568                 planeb_wm = fifo_size - wm_info->guard_size;
1569
1570         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1571
1572         /*
1573          * Overlay gets an aggressive default since video jitter is bad.
1574          */
1575         cwm = 2;
1576
1577         /* Play safe and disable self-refresh before adjusting watermarks. */
1578         if (IS_I945G(dev) || IS_I945GM(dev))
1579                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1580         else if (IS_I915GM(dev))
1581                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1582
1583         /* Calc sr entries for one plane configs */
1584         if (HAS_FW_BLC(dev) && enabled) {
1585                 /* self-refresh has much higher latency */
1586                 static const int sr_latency_ns = 6000;
1587                 int clock = enabled->mode.clock;
1588                 int htotal = enabled->mode.htotal;
1589                 int hdisplay = enabled->mode.hdisplay;
1590                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1591                 unsigned long line_time_us;
1592                 int entries;
1593
1594                 line_time_us = (htotal * 1000) / clock;
1595
1596                 /* Use ns/us then divide to preserve precision */
1597                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598                         pixel_size * hdisplay;
1599                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601                 srwm = wm_info->fifo_size - entries;
1602                 if (srwm < 0)
1603                         srwm = 1;
1604
1605                 if (IS_I945G(dev) || IS_I945GM(dev))
1606                         I915_WRITE(FW_BLC_SELF,
1607                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608                 else if (IS_I915GM(dev))
1609                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610         }
1611
1612         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613                       planea_wm, planeb_wm, cwm, srwm);
1614
1615         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616         fwater_hi = (cwm & 0x1f);
1617
1618         /* Set request length to 8 cachelines per fetch */
1619         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620         fwater_hi = fwater_hi | (1 << 8);
1621
1622         I915_WRITE(FW_BLC, fwater_lo);
1623         I915_WRITE(FW_BLC2, fwater_hi);
1624
1625         if (HAS_FW_BLC(dev)) {
1626                 if (enabled) {
1627                         if (IS_I945G(dev) || IS_I945GM(dev))
1628                                 I915_WRITE(FW_BLC_SELF,
1629                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1630                         else if (IS_I915GM(dev))
1631                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1632                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1633                 } else
1634                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1635         }
1636 }
1637
1638 static void i830_update_wm(struct drm_device *dev)
1639 {
1640         struct drm_i915_private *dev_priv = dev->dev_private;
1641         struct drm_crtc *crtc;
1642         uint32_t fwater_lo;
1643         int planea_wm;
1644
1645         crtc = single_enabled_crtc(dev);
1646         if (crtc == NULL)
1647                 return;
1648
1649         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1650                                        dev_priv->display.get_fifo_size(dev, 0),
1651                                        4, latency_ns);
1652         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1653         fwater_lo |= (3<<8) | planea_wm;
1654
1655         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1656
1657         I915_WRITE(FW_BLC, fwater_lo);
1658 }
1659
1660 #define ILK_LP0_PLANE_LATENCY           700
1661 #define ILK_LP0_CURSOR_LATENCY          1300
1662
1663 /*
1664  * Check the wm result.
1665  *
1666  * If any calculated watermark values is larger than the maximum value that
1667  * can be programmed into the associated watermark register, that watermark
1668  * must be disabled.
1669  */
1670 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1671                                 int fbc_wm, int display_wm, int cursor_wm,
1672                                 const struct intel_watermark_params *display,
1673                                 const struct intel_watermark_params *cursor)
1674 {
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1678                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1679
1680         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1681                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1682                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1683
1684                 /* fbc has it's own way to disable FBC WM */
1685                 I915_WRITE(DISP_ARB_CTL,
1686                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1687                 return false;
1688         } else if (INTEL_INFO(dev)->gen >= 6) {
1689                 /* enable FBC WM (except on ILK, where it must remain off) */
1690                 I915_WRITE(DISP_ARB_CTL,
1691                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1692         }
1693
1694         if (display_wm > display->max_wm) {
1695                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1696                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1697                 return false;
1698         }
1699
1700         if (cursor_wm > cursor->max_wm) {
1701                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1702                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1703                 return false;
1704         }
1705
1706         if (!(fbc_wm || display_wm || cursor_wm)) {
1707                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1708                 return false;
1709         }
1710
1711         return true;
1712 }
1713
1714 /*
1715  * Compute watermark values of WM[1-3],
1716  */
1717 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1718                                   int latency_ns,
1719                                   const struct intel_watermark_params *display,
1720                                   const struct intel_watermark_params *cursor,
1721                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1722 {
1723         struct drm_crtc *crtc;
1724         unsigned long line_time_us;
1725         int hdisplay, htotal, pixel_size, clock;
1726         int line_count, line_size;
1727         int small, large;
1728         int entries;
1729
1730         if (!latency_ns) {
1731                 *fbc_wm = *display_wm = *cursor_wm = 0;
1732                 return false;
1733         }
1734
1735         crtc = intel_get_crtc_for_plane(dev, plane);
1736         hdisplay = crtc->mode.hdisplay;
1737         htotal = crtc->mode.htotal;
1738         clock = crtc->mode.clock;
1739         pixel_size = crtc->fb->bits_per_pixel / 8;
1740
1741         line_time_us = (htotal * 1000) / clock;
1742         line_count = (latency_ns / line_time_us + 1000) / 1000;
1743         line_size = hdisplay * pixel_size;
1744
1745         /* Use the minimum of the small and large buffer method for primary */
1746         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1747         large = line_count * line_size;
1748
1749         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1750         *display_wm = entries + display->guard_size;
1751
1752         /*
1753          * Spec says:
1754          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1755          */
1756         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1757
1758         /* calculate the self-refresh watermark for display cursor */
1759         entries = line_count * pixel_size * 64;
1760         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1761         *cursor_wm = entries + cursor->guard_size;
1762
1763         return ironlake_check_srwm(dev, level,
1764                                    *fbc_wm, *display_wm, *cursor_wm,
1765                                    display, cursor);
1766 }
1767
1768 static void ironlake_update_wm(struct drm_device *dev)
1769 {
1770         struct drm_i915_private *dev_priv = dev->dev_private;
1771         int fbc_wm, plane_wm, cursor_wm;
1772         unsigned int enabled;
1773
1774         enabled = 0;
1775         if (g4x_compute_wm0(dev, PIPE_A,
1776                             &ironlake_display_wm_info,
1777                             ILK_LP0_PLANE_LATENCY,
1778                             &ironlake_cursor_wm_info,
1779                             ILK_LP0_CURSOR_LATENCY,
1780                             &plane_wm, &cursor_wm)) {
1781                 I915_WRITE(WM0_PIPEA_ILK,
1782                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1783                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1784                               " plane %d, " "cursor: %d\n",
1785                               plane_wm, cursor_wm);
1786                 enabled |= 1 << PIPE_A;
1787         }
1788
1789         if (g4x_compute_wm0(dev, PIPE_B,
1790                             &ironlake_display_wm_info,
1791                             ILK_LP0_PLANE_LATENCY,
1792                             &ironlake_cursor_wm_info,
1793                             ILK_LP0_CURSOR_LATENCY,
1794                             &plane_wm, &cursor_wm)) {
1795                 I915_WRITE(WM0_PIPEB_ILK,
1796                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1797                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1798                               " plane %d, cursor: %d\n",
1799                               plane_wm, cursor_wm);
1800                 enabled |= 1 << PIPE_B;
1801         }
1802
1803         /*
1804          * Calculate and update the self-refresh watermark only when one
1805          * display plane is used.
1806          */
1807         I915_WRITE(WM3_LP_ILK, 0);
1808         I915_WRITE(WM2_LP_ILK, 0);
1809         I915_WRITE(WM1_LP_ILK, 0);
1810
1811         if (!single_plane_enabled(enabled))
1812                 return;
1813         enabled = ffs(enabled) - 1;
1814
1815         /* WM1 */
1816         if (!ironlake_compute_srwm(dev, 1, enabled,
1817                                    ILK_READ_WM1_LATENCY() * 500,
1818                                    &ironlake_display_srwm_info,
1819                                    &ironlake_cursor_srwm_info,
1820                                    &fbc_wm, &plane_wm, &cursor_wm))
1821                 return;
1822
1823         I915_WRITE(WM1_LP_ILK,
1824                    WM1_LP_SR_EN |
1825                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1826                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1827                    (plane_wm << WM1_LP_SR_SHIFT) |
1828                    cursor_wm);
1829
1830         /* WM2 */
1831         if (!ironlake_compute_srwm(dev, 2, enabled,
1832                                    ILK_READ_WM2_LATENCY() * 500,
1833                                    &ironlake_display_srwm_info,
1834                                    &ironlake_cursor_srwm_info,
1835                                    &fbc_wm, &plane_wm, &cursor_wm))
1836                 return;
1837
1838         I915_WRITE(WM2_LP_ILK,
1839                    WM2_LP_EN |
1840                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1841                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1842                    (plane_wm << WM1_LP_SR_SHIFT) |
1843                    cursor_wm);
1844
1845         /*
1846          * WM3 is unsupported on ILK, probably because we don't have latency
1847          * data for that power state
1848          */
1849 }
1850
1851 static void sandybridge_update_wm(struct drm_device *dev)
1852 {
1853         struct drm_i915_private *dev_priv = dev->dev_private;
1854         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1855         u32 val;
1856         int fbc_wm, plane_wm, cursor_wm;
1857         unsigned int enabled;
1858
1859         enabled = 0;
1860         if (g4x_compute_wm0(dev, PIPE_A,
1861                             &sandybridge_display_wm_info, latency,
1862                             &sandybridge_cursor_wm_info, latency,
1863                             &plane_wm, &cursor_wm)) {
1864                 val = I915_READ(WM0_PIPEA_ILK);
1865                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1866                 I915_WRITE(WM0_PIPEA_ILK, val |
1867                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1868                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1869                               " plane %d, " "cursor: %d\n",
1870                               plane_wm, cursor_wm);
1871                 enabled |= 1 << PIPE_A;
1872         }
1873
1874         if (g4x_compute_wm0(dev, PIPE_B,
1875                             &sandybridge_display_wm_info, latency,
1876                             &sandybridge_cursor_wm_info, latency,
1877                             &plane_wm, &cursor_wm)) {
1878                 val = I915_READ(WM0_PIPEB_ILK);
1879                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1880                 I915_WRITE(WM0_PIPEB_ILK, val |
1881                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1882                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1883                               " plane %d, cursor: %d\n",
1884                               plane_wm, cursor_wm);
1885                 enabled |= 1 << PIPE_B;
1886         }
1887
1888         /*
1889          * Calculate and update the self-refresh watermark only when one
1890          * display plane is used.
1891          *
1892          * SNB support 3 levels of watermark.
1893          *
1894          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1895          * and disabled in the descending order
1896          *
1897          */
1898         I915_WRITE(WM3_LP_ILK, 0);
1899         I915_WRITE(WM2_LP_ILK, 0);
1900         I915_WRITE(WM1_LP_ILK, 0);
1901
1902         if (!single_plane_enabled(enabled) ||
1903             dev_priv->sprite_scaling_enabled)
1904                 return;
1905         enabled = ffs(enabled) - 1;
1906
1907         /* WM1 */
1908         if (!ironlake_compute_srwm(dev, 1, enabled,
1909                                    SNB_READ_WM1_LATENCY() * 500,
1910                                    &sandybridge_display_srwm_info,
1911                                    &sandybridge_cursor_srwm_info,
1912                                    &fbc_wm, &plane_wm, &cursor_wm))
1913                 return;
1914
1915         I915_WRITE(WM1_LP_ILK,
1916                    WM1_LP_SR_EN |
1917                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1918                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1919                    (plane_wm << WM1_LP_SR_SHIFT) |
1920                    cursor_wm);
1921
1922         /* WM2 */
1923         if (!ironlake_compute_srwm(dev, 2, enabled,
1924                                    SNB_READ_WM2_LATENCY() * 500,
1925                                    &sandybridge_display_srwm_info,
1926                                    &sandybridge_cursor_srwm_info,
1927                                    &fbc_wm, &plane_wm, &cursor_wm))
1928                 return;
1929
1930         I915_WRITE(WM2_LP_ILK,
1931                    WM2_LP_EN |
1932                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1933                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1934                    (plane_wm << WM1_LP_SR_SHIFT) |
1935                    cursor_wm);
1936
1937         /* WM3 */
1938         if (!ironlake_compute_srwm(dev, 3, enabled,
1939                                    SNB_READ_WM3_LATENCY() * 500,
1940                                    &sandybridge_display_srwm_info,
1941                                    &sandybridge_cursor_srwm_info,
1942                                    &fbc_wm, &plane_wm, &cursor_wm))
1943                 return;
1944
1945         I915_WRITE(WM3_LP_ILK,
1946                    WM3_LP_EN |
1947                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1948                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1949                    (plane_wm << WM1_LP_SR_SHIFT) |
1950                    cursor_wm);
1951 }
1952
1953 static void ivybridge_update_wm(struct drm_device *dev)
1954 {
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1957         u32 val;
1958         int fbc_wm, plane_wm, cursor_wm;
1959         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1960         unsigned int enabled;
1961
1962         enabled = 0;
1963         if (g4x_compute_wm0(dev, PIPE_A,
1964                             &sandybridge_display_wm_info, latency,
1965                             &sandybridge_cursor_wm_info, latency,
1966                             &plane_wm, &cursor_wm)) {
1967                 val = I915_READ(WM0_PIPEA_ILK);
1968                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1969                 I915_WRITE(WM0_PIPEA_ILK, val |
1970                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1971                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1972                               " plane %d, " "cursor: %d\n",
1973                               plane_wm, cursor_wm);
1974                 enabled |= 1 << PIPE_A;
1975         }
1976
1977         if (g4x_compute_wm0(dev, PIPE_B,
1978                             &sandybridge_display_wm_info, latency,
1979                             &sandybridge_cursor_wm_info, latency,
1980                             &plane_wm, &cursor_wm)) {
1981                 val = I915_READ(WM0_PIPEB_ILK);
1982                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1983                 I915_WRITE(WM0_PIPEB_ILK, val |
1984                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1985                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1986                               " plane %d, cursor: %d\n",
1987                               plane_wm, cursor_wm);
1988                 enabled |= 1 << PIPE_B;
1989         }
1990
1991         if (g4x_compute_wm0(dev, PIPE_C,
1992                             &sandybridge_display_wm_info, latency,
1993                             &sandybridge_cursor_wm_info, latency,
1994                             &plane_wm, &cursor_wm)) {
1995                 val = I915_READ(WM0_PIPEC_IVB);
1996                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1997                 I915_WRITE(WM0_PIPEC_IVB, val |
1998                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1999                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2000                               " plane %d, cursor: %d\n",
2001                               plane_wm, cursor_wm);
2002                 enabled |= 1 << PIPE_C;
2003         }
2004
2005         /*
2006          * Calculate and update the self-refresh watermark only when one
2007          * display plane is used.
2008          *
2009          * SNB support 3 levels of watermark.
2010          *
2011          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2012          * and disabled in the descending order
2013          *
2014          */
2015         I915_WRITE(WM3_LP_ILK, 0);
2016         I915_WRITE(WM2_LP_ILK, 0);
2017         I915_WRITE(WM1_LP_ILK, 0);
2018
2019         if (!single_plane_enabled(enabled) ||
2020             dev_priv->sprite_scaling_enabled)
2021                 return;
2022         enabled = ffs(enabled) - 1;
2023
2024         /* WM1 */
2025         if (!ironlake_compute_srwm(dev, 1, enabled,
2026                                    SNB_READ_WM1_LATENCY() * 500,
2027                                    &sandybridge_display_srwm_info,
2028                                    &sandybridge_cursor_srwm_info,
2029                                    &fbc_wm, &plane_wm, &cursor_wm))
2030                 return;
2031
2032         I915_WRITE(WM1_LP_ILK,
2033                    WM1_LP_SR_EN |
2034                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2035                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2036                    (plane_wm << WM1_LP_SR_SHIFT) |
2037                    cursor_wm);
2038
2039         /* WM2 */
2040         if (!ironlake_compute_srwm(dev, 2, enabled,
2041                                    SNB_READ_WM2_LATENCY() * 500,
2042                                    &sandybridge_display_srwm_info,
2043                                    &sandybridge_cursor_srwm_info,
2044                                    &fbc_wm, &plane_wm, &cursor_wm))
2045                 return;
2046
2047         I915_WRITE(WM2_LP_ILK,
2048                    WM2_LP_EN |
2049                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2050                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2051                    (plane_wm << WM1_LP_SR_SHIFT) |
2052                    cursor_wm);
2053
2054         /* WM3, note we have to correct the cursor latency */
2055         if (!ironlake_compute_srwm(dev, 3, enabled,
2056                                    SNB_READ_WM3_LATENCY() * 500,
2057                                    &sandybridge_display_srwm_info,
2058                                    &sandybridge_cursor_srwm_info,
2059                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2060             !ironlake_compute_srwm(dev, 3, enabled,
2061                                    2 * SNB_READ_WM3_LATENCY() * 500,
2062                                    &sandybridge_display_srwm_info,
2063                                    &sandybridge_cursor_srwm_info,
2064                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2065                 return;
2066
2067         I915_WRITE(WM3_LP_ILK,
2068                    WM3_LP_EN |
2069                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2070                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2071                    (plane_wm << WM1_LP_SR_SHIFT) |
2072                    cursor_wm);
2073 }
2074
2075 static void
2076 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2077                                  struct drm_display_mode *mode)
2078 {
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080         u32 temp;
2081
2082         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2083         temp &= ~PIPE_WM_LINETIME_MASK;
2084
2085         /* The WM are computed with base on how long it takes to fill a single
2086          * row at the given clock rate, multiplied by 8.
2087          * */
2088         temp |= PIPE_WM_LINETIME_TIME(
2089                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2090
2091         /* IPS watermarks are only used by pipe A, and are ignored by
2092          * pipes B and C.  They are calculated similarly to the common
2093          * linetime values, except that we are using CD clock frequency
2094          * in MHz instead of pixel rate for the division.
2095          *
2096          * This is a placeholder for the IPS watermark calculation code.
2097          */
2098
2099         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2100 }
2101
2102 static bool
2103 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2104                               uint32_t sprite_width, int pixel_size,
2105                               const struct intel_watermark_params *display,
2106                               int display_latency_ns, int *sprite_wm)
2107 {
2108         struct drm_crtc *crtc;
2109         int clock;
2110         int entries, tlb_miss;
2111
2112         crtc = intel_get_crtc_for_plane(dev, plane);
2113         if (!intel_crtc_active(crtc)) {
2114                 *sprite_wm = display->guard_size;
2115                 return false;
2116         }
2117
2118         clock = crtc->mode.clock;
2119
2120         /* Use the small buffer method to calculate the sprite watermark */
2121         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2122         tlb_miss = display->fifo_size*display->cacheline_size -
2123                 sprite_width * 8;
2124         if (tlb_miss > 0)
2125                 entries += tlb_miss;
2126         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2127         *sprite_wm = entries + display->guard_size;
2128         if (*sprite_wm > (int)display->max_wm)
2129                 *sprite_wm = display->max_wm;
2130
2131         return true;
2132 }
2133
2134 static bool
2135 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2136                                 uint32_t sprite_width, int pixel_size,
2137                                 const struct intel_watermark_params *display,
2138                                 int latency_ns, int *sprite_wm)
2139 {
2140         struct drm_crtc *crtc;
2141         unsigned long line_time_us;
2142         int clock;
2143         int line_count, line_size;
2144         int small, large;
2145         int entries;
2146
2147         if (!latency_ns) {
2148                 *sprite_wm = 0;
2149                 return false;
2150         }
2151
2152         crtc = intel_get_crtc_for_plane(dev, plane);
2153         clock = crtc->mode.clock;
2154         if (!clock) {
2155                 *sprite_wm = 0;
2156                 return false;
2157         }
2158
2159         line_time_us = (sprite_width * 1000) / clock;
2160         if (!line_time_us) {
2161                 *sprite_wm = 0;
2162                 return false;
2163         }
2164
2165         line_count = (latency_ns / line_time_us + 1000) / 1000;
2166         line_size = sprite_width * pixel_size;
2167
2168         /* Use the minimum of the small and large buffer method for primary */
2169         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2170         large = line_count * line_size;
2171
2172         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2173         *sprite_wm = entries + display->guard_size;
2174
2175         return *sprite_wm > 0x3ff ? false : true;
2176 }
2177
2178 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2179                                          uint32_t sprite_width, int pixel_size)
2180 {
2181         struct drm_i915_private *dev_priv = dev->dev_private;
2182         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2183         u32 val;
2184         int sprite_wm, reg;
2185         int ret;
2186
2187         switch (pipe) {
2188         case 0:
2189                 reg = WM0_PIPEA_ILK;
2190                 break;
2191         case 1:
2192                 reg = WM0_PIPEB_ILK;
2193                 break;
2194         case 2:
2195                 reg = WM0_PIPEC_IVB;
2196                 break;
2197         default:
2198                 return; /* bad pipe */
2199         }
2200
2201         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2202                                             &sandybridge_display_wm_info,
2203                                             latency, &sprite_wm);
2204         if (!ret) {
2205                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2206                               pipe_name(pipe));
2207                 return;
2208         }
2209
2210         val = I915_READ(reg);
2211         val &= ~WM0_PIPE_SPRITE_MASK;
2212         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2213         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2214
2215
2216         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2217                                               pixel_size,
2218                                               &sandybridge_display_srwm_info,
2219                                               SNB_READ_WM1_LATENCY() * 500,
2220                                               &sprite_wm);
2221         if (!ret) {
2222                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2223                               pipe_name(pipe));
2224                 return;
2225         }
2226         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2227
2228         /* Only IVB has two more LP watermarks for sprite */
2229         if (!IS_IVYBRIDGE(dev))
2230                 return;
2231
2232         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2233                                               pixel_size,
2234                                               &sandybridge_display_srwm_info,
2235                                               SNB_READ_WM2_LATENCY() * 500,
2236                                               &sprite_wm);
2237         if (!ret) {
2238                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2239                               pipe_name(pipe));
2240                 return;
2241         }
2242         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2243
2244         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2245                                               pixel_size,
2246                                               &sandybridge_display_srwm_info,
2247                                               SNB_READ_WM3_LATENCY() * 500,
2248                                               &sprite_wm);
2249         if (!ret) {
2250                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2251                               pipe_name(pipe));
2252                 return;
2253         }
2254         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2255 }
2256
2257 /**
2258  * intel_update_watermarks - update FIFO watermark values based on current modes
2259  *
2260  * Calculate watermark values for the various WM regs based on current mode
2261  * and plane configuration.
2262  *
2263  * There are several cases to deal with here:
2264  *   - normal (i.e. non-self-refresh)
2265  *   - self-refresh (SR) mode
2266  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2267  *   - lines are small relative to FIFO size (buffer can hold more than 2
2268  *     lines), so need to account for TLB latency
2269  *
2270  *   The normal calculation is:
2271  *     watermark = dotclock * bytes per pixel * latency
2272  *   where latency is platform & configuration dependent (we assume pessimal
2273  *   values here).
2274  *
2275  *   The SR calculation is:
2276  *     watermark = (trunc(latency/line time)+1) * surface width *
2277  *       bytes per pixel
2278  *   where
2279  *     line time = htotal / dotclock
2280  *     surface width = hdisplay for normal plane and 64 for cursor
2281  *   and latency is assumed to be high, as above.
2282  *
2283  * The final value programmed to the register should always be rounded up,
2284  * and include an extra 2 entries to account for clock crossings.
2285  *
2286  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2287  * to set the non-SR watermarks to 8.
2288  */
2289 void intel_update_watermarks(struct drm_device *dev)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292
2293         if (dev_priv->display.update_wm)
2294                 dev_priv->display.update_wm(dev);
2295 }
2296
2297 void intel_update_linetime_watermarks(struct drm_device *dev,
2298                 int pipe, struct drm_display_mode *mode)
2299 {
2300         struct drm_i915_private *dev_priv = dev->dev_private;
2301
2302         if (dev_priv->display.update_linetime_wm)
2303                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2304 }
2305
2306 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2307                                     uint32_t sprite_width, int pixel_size)
2308 {
2309         struct drm_i915_private *dev_priv = dev->dev_private;
2310
2311         if (dev_priv->display.update_sprite_wm)
2312                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2313                                                    pixel_size);
2314 }
2315
2316 static struct drm_i915_gem_object *
2317 intel_alloc_context_page(struct drm_device *dev)
2318 {
2319         struct drm_i915_gem_object *ctx;
2320         int ret;
2321
2322         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2323
2324         ctx = i915_gem_alloc_object(dev, 4096);
2325         if (!ctx) {
2326                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2327                 return NULL;
2328         }
2329
2330         ret = i915_gem_object_pin(ctx, 4096, true, false);
2331         if (ret) {
2332                 DRM_ERROR("failed to pin power context: %d\n", ret);
2333                 goto err_unref;
2334         }
2335
2336         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2337         if (ret) {
2338                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2339                 goto err_unpin;
2340         }
2341
2342         return ctx;
2343
2344 err_unpin:
2345         i915_gem_object_unpin(ctx);
2346 err_unref:
2347         drm_gem_object_unreference(&ctx->base);
2348         return NULL;
2349 }
2350
2351 /**
2352  * Lock protecting IPS related data structures
2353  */
2354 DEFINE_SPINLOCK(mchdev_lock);
2355
2356 /* Global for IPS driver to get at the current i915 device. Protected by
2357  * mchdev_lock. */
2358 static struct drm_i915_private *i915_mch_dev;
2359
2360 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2361 {
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         u16 rgvswctl;
2364
2365         assert_spin_locked(&mchdev_lock);
2366
2367         rgvswctl = I915_READ16(MEMSWCTL);
2368         if (rgvswctl & MEMCTL_CMD_STS) {
2369                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2370                 return false; /* still busy with another command */
2371         }
2372
2373         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2374                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2375         I915_WRITE16(MEMSWCTL, rgvswctl);
2376         POSTING_READ16(MEMSWCTL);
2377
2378         rgvswctl |= MEMCTL_CMD_STS;
2379         I915_WRITE16(MEMSWCTL, rgvswctl);
2380
2381         return true;
2382 }
2383
2384 static void ironlake_enable_drps(struct drm_device *dev)
2385 {
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         u32 rgvmodectl = I915_READ(MEMMODECTL);
2388         u8 fmax, fmin, fstart, vstart;
2389
2390         spin_lock_irq(&mchdev_lock);
2391
2392         /* Enable temp reporting */
2393         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2394         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2395
2396         /* 100ms RC evaluation intervals */
2397         I915_WRITE(RCUPEI, 100000);
2398         I915_WRITE(RCDNEI, 100000);
2399
2400         /* Set max/min thresholds to 90ms and 80ms respectively */
2401         I915_WRITE(RCBMAXAVG, 90000);
2402         I915_WRITE(RCBMINAVG, 80000);
2403
2404         I915_WRITE(MEMIHYST, 1);
2405
2406         /* Set up min, max, and cur for interrupt handling */
2407         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2408         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2409         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2410                 MEMMODE_FSTART_SHIFT;
2411
2412         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2413                 PXVFREQ_PX_SHIFT;
2414
2415         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2416         dev_priv->ips.fstart = fstart;
2417
2418         dev_priv->ips.max_delay = fstart;
2419         dev_priv->ips.min_delay = fmin;
2420         dev_priv->ips.cur_delay = fstart;
2421
2422         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2423                          fmax, fmin, fstart);
2424
2425         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2426
2427         /*
2428          * Interrupts will be enabled in ironlake_irq_postinstall
2429          */
2430
2431         I915_WRITE(VIDSTART, vstart);
2432         POSTING_READ(VIDSTART);
2433
2434         rgvmodectl |= MEMMODE_SWMODE_EN;
2435         I915_WRITE(MEMMODECTL, rgvmodectl);
2436
2437         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2438                 DRM_ERROR("stuck trying to change perf mode\n");
2439         mdelay(1);
2440
2441         ironlake_set_drps(dev, fstart);
2442
2443         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2444                 I915_READ(0x112e0);
2445         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2446         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2447         getrawmonotonic(&dev_priv->ips.last_time2);
2448
2449         spin_unlock_irq(&mchdev_lock);
2450 }
2451
2452 static void ironlake_disable_drps(struct drm_device *dev)
2453 {
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         u16 rgvswctl;
2456
2457         spin_lock_irq(&mchdev_lock);
2458
2459         rgvswctl = I915_READ16(MEMSWCTL);
2460
2461         /* Ack interrupts, disable EFC interrupt */
2462         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2463         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2464         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2465         I915_WRITE(DEIIR, DE_PCU_EVENT);
2466         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2467
2468         /* Go back to the starting frequency */
2469         ironlake_set_drps(dev, dev_priv->ips.fstart);
2470         mdelay(1);
2471         rgvswctl |= MEMCTL_CMD_STS;
2472         I915_WRITE(MEMSWCTL, rgvswctl);
2473         mdelay(1);
2474
2475         spin_unlock_irq(&mchdev_lock);
2476 }
2477
2478 /* There's a funny hw issue where the hw returns all 0 when reading from
2479  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2480  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2481  * all limits and the gpu stuck at whatever frequency it is at atm).
2482  */
2483 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2484 {
2485         u32 limits;
2486
2487         limits = 0;
2488
2489         if (*val >= dev_priv->rps.max_delay)
2490                 *val = dev_priv->rps.max_delay;
2491         limits |= dev_priv->rps.max_delay << 24;
2492
2493         /* Only set the down limit when we've reached the lowest level to avoid
2494          * getting more interrupts, otherwise leave this clear. This prevents a
2495          * race in the hw when coming out of rc6: There's a tiny window where
2496          * the hw runs at the minimal clock before selecting the desired
2497          * frequency, if the down threshold expires in that window we will not
2498          * receive a down interrupt. */
2499         if (*val <= dev_priv->rps.min_delay) {
2500                 *val = dev_priv->rps.min_delay;
2501                 limits |= dev_priv->rps.min_delay << 16;
2502         }
2503
2504         return limits;
2505 }
2506
2507 void gen6_set_rps(struct drm_device *dev, u8 val)
2508 {
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         u32 limits = gen6_rps_limits(dev_priv, &val);
2511
2512         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2513         WARN_ON(val > dev_priv->rps.max_delay);
2514         WARN_ON(val < dev_priv->rps.min_delay);
2515
2516         if (val == dev_priv->rps.cur_delay)
2517                 return;
2518
2519         if (IS_HASWELL(dev))
2520                 I915_WRITE(GEN6_RPNSWREQ,
2521                            HSW_FREQUENCY(val));
2522         else
2523                 I915_WRITE(GEN6_RPNSWREQ,
2524                            GEN6_FREQUENCY(val) |
2525                            GEN6_OFFSET(0) |
2526                            GEN6_AGGRESSIVE_TURBO);
2527
2528         /* Make sure we continue to get interrupts
2529          * until we hit the minimum or maximum frequencies.
2530          */
2531         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2532
2533         POSTING_READ(GEN6_RPNSWREQ);
2534
2535         dev_priv->rps.cur_delay = val;
2536
2537         trace_intel_gpu_freq_change(val * 50);
2538 }
2539
2540 void valleyview_set_rps(struct drm_device *dev, u8 val)
2541 {
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         unsigned long timeout = jiffies + msecs_to_jiffies(10);
2544         u32 limits = gen6_rps_limits(dev_priv, &val);
2545         u32 pval;
2546
2547         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2548         WARN_ON(val > dev_priv->rps.max_delay);
2549         WARN_ON(val < dev_priv->rps.min_delay);
2550
2551         DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2552                          vlv_gpu_freq(dev_priv->mem_freq,
2553                                       dev_priv->rps.cur_delay),
2554                          vlv_gpu_freq(dev_priv->mem_freq, val));
2555
2556         if (val == dev_priv->rps.cur_delay)
2557                 return;
2558
2559         valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2560
2561         do {
2562                 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2563                 if (time_after(jiffies, timeout)) {
2564                         DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2565                         break;
2566                 }
2567                 udelay(10);
2568         } while (pval & 1);
2569
2570         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2571         if ((pval >> 8) != val)
2572                 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2573                           val, pval >> 8);
2574
2575         /* Make sure we continue to get interrupts
2576          * until we hit the minimum or maximum frequencies.
2577          */
2578         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2579
2580         dev_priv->rps.cur_delay = pval >> 8;
2581
2582         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2583 }
2584
2585
2586 static void gen6_disable_rps(struct drm_device *dev)
2587 {
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589
2590         I915_WRITE(GEN6_RC_CONTROL, 0);
2591         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2592         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2593         I915_WRITE(GEN6_PMIER, 0);
2594         /* Complete PM interrupt masking here doesn't race with the rps work
2595          * item again unmasking PM interrupts because that is using a different
2596          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2597          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2598
2599         spin_lock_irq(&dev_priv->rps.lock);
2600         dev_priv->rps.pm_iir = 0;
2601         spin_unlock_irq(&dev_priv->rps.lock);
2602
2603         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2604 }
2605
2606 static void valleyview_disable_rps(struct drm_device *dev)
2607 {
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609
2610         I915_WRITE(GEN6_RC_CONTROL, 0);
2611         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2612         I915_WRITE(GEN6_PMIER, 0);
2613         /* Complete PM interrupt masking here doesn't race with the rps work
2614          * item again unmasking PM interrupts because that is using a different
2615          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2616          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2617
2618         spin_lock_irq(&dev_priv->rps.lock);
2619         dev_priv->rps.pm_iir = 0;
2620         spin_unlock_irq(&dev_priv->rps.lock);
2621
2622         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2623
2624         if (dev_priv->vlv_pctx) {
2625                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
2626                 dev_priv->vlv_pctx = NULL;
2627         }
2628 }
2629
2630 int intel_enable_rc6(const struct drm_device *dev)
2631 {
2632         /* Respect the kernel parameter if it is set */
2633         if (i915_enable_rc6 >= 0)
2634                 return i915_enable_rc6;
2635
2636         /* Disable RC6 on Ironlake */
2637         if (INTEL_INFO(dev)->gen == 5)
2638                 return 0;
2639
2640         if (IS_HASWELL(dev)) {
2641                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2642                 return INTEL_RC6_ENABLE;
2643         }
2644
2645         /* snb/ivb have more than one rc6 state. */
2646         if (INTEL_INFO(dev)->gen == 6) {
2647                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2648                 return INTEL_RC6_ENABLE;
2649         }
2650
2651         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2652         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2653 }
2654
2655 static void gen6_enable_rps(struct drm_device *dev)
2656 {
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         struct intel_ring_buffer *ring;
2659         u32 rp_state_cap;
2660         u32 gt_perf_status;
2661         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2662         u32 gtfifodbg;
2663         int rc6_mode;
2664         int i, ret;
2665
2666         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2667
2668         /* Here begins a magic sequence of register writes to enable
2669          * auto-downclocking.
2670          *
2671          * Perhaps there might be some value in exposing these to
2672          * userspace...
2673          */
2674         I915_WRITE(GEN6_RC_STATE, 0);
2675
2676         /* Clear the DBG now so we don't confuse earlier errors */
2677         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2678                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2679                 I915_WRITE(GTFIFODBG, gtfifodbg);
2680         }
2681
2682         gen6_gt_force_wake_get(dev_priv);
2683
2684         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2685         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2686
2687         /* In units of 50MHz */
2688         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2689         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2690         dev_priv->rps.cur_delay = 0;
2691
2692         /* disable the counters and set deterministic thresholds */
2693         I915_WRITE(GEN6_RC_CONTROL, 0);
2694
2695         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2696         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2697         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2698         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2699         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2700
2701         for_each_ring(ring, dev_priv, i)
2702                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2703
2704         I915_WRITE(GEN6_RC_SLEEP, 0);
2705         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2706         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2707         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2708         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2709
2710         /* Check if we are enabling RC6 */
2711         rc6_mode = intel_enable_rc6(dev_priv->dev);
2712         if (rc6_mode & INTEL_RC6_ENABLE)
2713                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2714
2715         /* We don't use those on Haswell */
2716         if (!IS_HASWELL(dev)) {
2717                 if (rc6_mode & INTEL_RC6p_ENABLE)
2718                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2719
2720                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2721                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2722         }
2723
2724         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2725                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2726                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2727                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2728
2729         I915_WRITE(GEN6_RC_CONTROL,
2730                    rc6_mask |
2731                    GEN6_RC_CTL_EI_MODE(1) |
2732                    GEN6_RC_CTL_HW_ENABLE);
2733
2734         if (IS_HASWELL(dev)) {
2735                 I915_WRITE(GEN6_RPNSWREQ,
2736                            HSW_FREQUENCY(10));
2737                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2738                            HSW_FREQUENCY(12));
2739         } else {
2740                 I915_WRITE(GEN6_RPNSWREQ,
2741                            GEN6_FREQUENCY(10) |
2742                            GEN6_OFFSET(0) |
2743                            GEN6_AGGRESSIVE_TURBO);
2744                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2745                            GEN6_FREQUENCY(12));
2746         }
2747
2748         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2749         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2750                    dev_priv->rps.max_delay << 24 |
2751                    dev_priv->rps.min_delay << 16);
2752
2753         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2754         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2755         I915_WRITE(GEN6_RP_UP_EI, 66000);
2756         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2757
2758         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2759         I915_WRITE(GEN6_RP_CONTROL,
2760                    GEN6_RP_MEDIA_TURBO |
2761                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2762                    GEN6_RP_MEDIA_IS_GFX |
2763                    GEN6_RP_ENABLE |
2764                    GEN6_RP_UP_BUSY_AVG |
2765                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2766
2767         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2768         if (!ret) {
2769                 pcu_mbox = 0;
2770                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2771                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2772                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2773                                          (dev_priv->rps.max_delay & 0xff) * 50,
2774                                          (pcu_mbox & 0xff) * 50);
2775                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
2776                 }
2777         } else {
2778                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2779         }
2780
2781         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2782
2783         /* requires MSI enabled */
2784         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2785         spin_lock_irq(&dev_priv->rps.lock);
2786         WARN_ON(dev_priv->rps.pm_iir != 0);
2787         I915_WRITE(GEN6_PMIMR, 0);
2788         spin_unlock_irq(&dev_priv->rps.lock);
2789         /* enable all PM interrupts */
2790         I915_WRITE(GEN6_PMINTRMSK, 0);
2791
2792         rc6vids = 0;
2793         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2794         if (IS_GEN6(dev) && ret) {
2795                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2796         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2797                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2798                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2799                 rc6vids &= 0xffff00;
2800                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2801                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2802                 if (ret)
2803                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2804         }
2805
2806         gen6_gt_force_wake_put(dev_priv);
2807 }
2808
2809 static void gen6_update_ring_freq(struct drm_device *dev)
2810 {
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         int min_freq = 15;
2813         unsigned int gpu_freq;
2814         unsigned int max_ia_freq, min_ring_freq;
2815         int scaling_factor = 180;
2816
2817         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2818
2819         max_ia_freq = cpufreq_quick_get_max(0);
2820         /*
2821          * Default to measured freq if none found, PCU will ensure we don't go
2822          * over
2823          */
2824         if (!max_ia_freq)
2825                 max_ia_freq = tsc_khz;
2826
2827         /* Convert from kHz to MHz */
2828         max_ia_freq /= 1000;
2829
2830         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2831         /* convert DDR frequency from units of 133.3MHz to bandwidth */
2832         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2833
2834         /*
2835          * For each potential GPU frequency, load a ring frequency we'd like
2836          * to use for memory access.  We do this by specifying the IA frequency
2837          * the PCU should use as a reference to determine the ring frequency.
2838          */
2839         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2840              gpu_freq--) {
2841                 int diff = dev_priv->rps.max_delay - gpu_freq;
2842                 unsigned int ia_freq = 0, ring_freq = 0;
2843
2844                 if (IS_HASWELL(dev)) {
2845                         ring_freq = (gpu_freq * 5 + 3) / 4;
2846                         ring_freq = max(min_ring_freq, ring_freq);
2847                         /* leave ia_freq as the default, chosen by cpufreq */
2848                 } else {
2849                         /* On older processors, there is no separate ring
2850                          * clock domain, so in order to boost the bandwidth
2851                          * of the ring, we need to upclock the CPU (ia_freq).
2852                          *
2853                          * For GPU frequencies less than 750MHz,
2854                          * just use the lowest ring freq.
2855                          */
2856                         if (gpu_freq < min_freq)
2857                                 ia_freq = 800;
2858                         else
2859                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2860                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2861                 }
2862
2863                 sandybridge_pcode_write(dev_priv,
2864                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2865                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2866                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2867                                         gpu_freq);
2868         }
2869 }
2870
2871 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2872 {
2873         u32 val, rp0;
2874
2875         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2876
2877         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2878         /* Clamp to max */
2879         rp0 = min_t(u32, rp0, 0xea);
2880
2881         return rp0;
2882 }
2883
2884 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2885 {
2886         u32 val, rpe;
2887
2888         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2889         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2890         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2891         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2892
2893         return rpe;
2894 }
2895
2896 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2897 {
2898         u32 val;
2899
2900         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2901
2902         return val & 0xff;
2903 }
2904
2905 static void vlv_rps_timer_work(struct work_struct *work)
2906 {
2907         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
2908                                                     rps.vlv_work.work);
2909
2910         /*
2911          * Timer fired, we must be idle.  Drop to min voltage state.
2912          * Note: we use RPe here since it should match the
2913          * Vmin we were shooting for.  That should give us better
2914          * perf when we come back out of RC6 than if we used the
2915          * min freq available.
2916          */
2917         mutex_lock(&dev_priv->rps.hw_lock);
2918         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
2919         mutex_unlock(&dev_priv->rps.hw_lock);
2920 }
2921
2922 static void valleyview_setup_pctx(struct drm_device *dev)
2923 {
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925         struct drm_i915_gem_object *pctx;
2926         unsigned long pctx_paddr;
2927         u32 pcbr;
2928         int pctx_size = 24*1024;
2929
2930         pcbr = I915_READ(VLV_PCBR);
2931         if (pcbr) {
2932                 /* BIOS set it up already, grab the pre-alloc'd space */
2933                 int pcbr_offset;
2934
2935                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
2936                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
2937                                                                       pcbr_offset,
2938                                                                       -1,
2939                                                                       pctx_size);
2940                 goto out;
2941         }
2942
2943         /*
2944          * From the Gunit register HAS:
2945          * The Gfx driver is expected to program this register and ensure
2946          * proper allocation within Gfx stolen memory.  For example, this
2947          * register should be programmed such than the PCBR range does not
2948          * overlap with other ranges, such as the frame buffer, protected
2949          * memory, or any other relevant ranges.
2950          */
2951         pctx = i915_gem_object_create_stolen(dev, pctx_size);
2952         if (!pctx) {
2953                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
2954                 return;
2955         }
2956
2957         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
2958         I915_WRITE(VLV_PCBR, pctx_paddr);
2959
2960 out:
2961         dev_priv->vlv_pctx = pctx;
2962 }
2963
2964 static void valleyview_enable_rps(struct drm_device *dev)
2965 {
2966         struct drm_i915_private *dev_priv = dev->dev_private;
2967         struct intel_ring_buffer *ring;
2968         u32 gtfifodbg, val, rpe;
2969         int i;
2970
2971         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2972
2973         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2974                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2975                 I915_WRITE(GTFIFODBG, gtfifodbg);
2976         }
2977
2978         valleyview_setup_pctx(dev);
2979
2980         gen6_gt_force_wake_get(dev_priv);
2981
2982         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2983         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2984         I915_WRITE(GEN6_RP_UP_EI, 66000);
2985         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2986
2987         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2988
2989         I915_WRITE(GEN6_RP_CONTROL,
2990                    GEN6_RP_MEDIA_TURBO |
2991                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2992                    GEN6_RP_MEDIA_IS_GFX |
2993                    GEN6_RP_ENABLE |
2994                    GEN6_RP_UP_BUSY_AVG |
2995                    GEN6_RP_DOWN_IDLE_CONT);
2996
2997         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2998         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2999         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3000
3001         for_each_ring(ring, dev_priv, i)
3002                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3003
3004         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3005
3006         /* allows RC6 residency counter to work */
3007         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3008         I915_WRITE(GEN6_RC_CONTROL,
3009                    GEN7_RC_CTL_TO_MODE);
3010
3011         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
3012         switch ((val >> 6) & 3) {
3013         case 0:
3014         case 1:
3015                 dev_priv->mem_freq = 800;
3016                 break;
3017         case 2:
3018                 dev_priv->mem_freq = 1066;
3019                 break;
3020         case 3:
3021                 dev_priv->mem_freq = 1333;
3022                 break;
3023         }
3024         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3025
3026         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3027         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3028
3029         DRM_DEBUG_DRIVER("current GPU freq: %d\n",
3030                          vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
3031         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3032
3033         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3034         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3035         DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3036                                                      dev_priv->rps.max_delay));
3037
3038         rpe = valleyview_rps_rpe_freq(dev_priv);
3039         DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
3040                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3041         dev_priv->rps.rpe_delay = rpe;
3042
3043         val = valleyview_rps_min_freq(dev_priv);
3044         DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
3045                                                             val));
3046         dev_priv->rps.min_delay = val;
3047
3048         DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
3049                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
3050
3051         INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3052
3053         valleyview_set_rps(dev_priv->dev, rpe);
3054
3055         /* requires MSI enabled */
3056         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
3057         spin_lock_irq(&dev_priv->rps.lock);
3058         WARN_ON(dev_priv->rps.pm_iir != 0);
3059         I915_WRITE(GEN6_PMIMR, 0);
3060         spin_unlock_irq(&dev_priv->rps.lock);
3061         /* enable all PM interrupts */
3062         I915_WRITE(GEN6_PMINTRMSK, 0);
3063
3064         gen6_gt_force_wake_put(dev_priv);
3065 }
3066
3067 void ironlake_teardown_rc6(struct drm_device *dev)
3068 {
3069         struct drm_i915_private *dev_priv = dev->dev_private;
3070
3071         if (dev_priv->ips.renderctx) {
3072                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3073                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3074                 dev_priv->ips.renderctx = NULL;
3075         }
3076
3077         if (dev_priv->ips.pwrctx) {
3078                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3079                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3080                 dev_priv->ips.pwrctx = NULL;
3081         }
3082 }
3083
3084 static void ironlake_disable_rc6(struct drm_device *dev)
3085 {
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087
3088         if (I915_READ(PWRCTXA)) {
3089                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3090                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3091                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3092                          50);
3093
3094                 I915_WRITE(PWRCTXA, 0);
3095                 POSTING_READ(PWRCTXA);
3096
3097                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3098                 POSTING_READ(RSTDBYCTL);
3099         }
3100 }
3101
3102 static int ironlake_setup_rc6(struct drm_device *dev)
3103 {
3104         struct drm_i915_private *dev_priv = dev->dev_private;
3105
3106         if (dev_priv->ips.renderctx == NULL)
3107                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3108         if (!dev_priv->ips.renderctx)
3109                 return -ENOMEM;
3110
3111         if (dev_priv->ips.pwrctx == NULL)
3112                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3113         if (!dev_priv->ips.pwrctx) {
3114                 ironlake_teardown_rc6(dev);
3115                 return -ENOMEM;
3116         }
3117
3118         return 0;
3119 }
3120
3121 static void ironlake_enable_rc6(struct drm_device *dev)
3122 {
3123         struct drm_i915_private *dev_priv = dev->dev_private;
3124         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3125         bool was_interruptible;
3126         int ret;
3127
3128         /* rc6 disabled by default due to repeated reports of hanging during
3129          * boot and resume.
3130          */
3131         if (!intel_enable_rc6(dev))
3132                 return;
3133
3134         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3135
3136         ret = ironlake_setup_rc6(dev);
3137         if (ret)
3138                 return;
3139
3140         was_interruptible = dev_priv->mm.interruptible;
3141         dev_priv->mm.interruptible = false;
3142
3143         /*
3144          * GPU can automatically power down the render unit if given a page
3145          * to save state.
3146          */
3147         ret = intel_ring_begin(ring, 6);
3148         if (ret) {
3149                 ironlake_teardown_rc6(dev);
3150                 dev_priv->mm.interruptible = was_interruptible;
3151                 return;
3152         }
3153
3154         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3155         intel_ring_emit(ring, MI_SET_CONTEXT);
3156         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3157                         MI_MM_SPACE_GTT |
3158                         MI_SAVE_EXT_STATE_EN |
3159                         MI_RESTORE_EXT_STATE_EN |
3160                         MI_RESTORE_INHIBIT);
3161         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3162         intel_ring_emit(ring, MI_NOOP);
3163         intel_ring_emit(ring, MI_FLUSH);
3164         intel_ring_advance(ring);
3165
3166         /*
3167          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3168          * does an implicit flush, combined with MI_FLUSH above, it should be
3169          * safe to assume that renderctx is valid
3170          */
3171         ret = intel_ring_idle(ring);
3172         dev_priv->mm.interruptible = was_interruptible;
3173         if (ret) {
3174                 DRM_ERROR("failed to enable ironlake power savings\n");
3175                 ironlake_teardown_rc6(dev);
3176                 return;
3177         }
3178
3179         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3180         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3181 }
3182
3183 static unsigned long intel_pxfreq(u32 vidfreq)
3184 {
3185         unsigned long freq;
3186         int div = (vidfreq & 0x3f0000) >> 16;
3187         int post = (vidfreq & 0x3000) >> 12;
3188         int pre = (vidfreq & 0x7);
3189
3190         if (!pre)
3191                 return 0;
3192
3193         freq = ((div * 133333) / ((1<<post) * pre));
3194
3195         return freq;
3196 }
3197
3198 static const struct cparams {
3199         u16 i;
3200         u16 t;
3201         u16 m;
3202         u16 c;
3203 } cparams[] = {
3204         { 1, 1333, 301, 28664 },
3205         { 1, 1066, 294, 24460 },
3206         { 1, 800, 294, 25192 },
3207         { 0, 1333, 276, 27605 },
3208         { 0, 1066, 276, 27605 },
3209         { 0, 800, 231, 23784 },
3210 };
3211
3212 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3213 {
3214         u64 total_count, diff, ret;
3215         u32 count1, count2, count3, m = 0, c = 0;
3216         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3217         int i;
3218
3219         assert_spin_locked(&mchdev_lock);
3220
3221         diff1 = now - dev_priv->ips.last_time1;
3222
3223         /* Prevent division-by-zero if we are asking too fast.
3224          * Also, we don't get interesting results if we are polling
3225          * faster than once in 10ms, so just return the saved value
3226          * in such cases.
3227          */
3228         if (diff1 <= 10)
3229                 return dev_priv->ips.chipset_power;
3230
3231         count1 = I915_READ(DMIEC);
3232         count2 = I915_READ(DDREC);
3233         count3 = I915_READ(CSIEC);
3234
3235         total_count = count1 + count2 + count3;
3236
3237         /* FIXME: handle per-counter overflow */
3238         if (total_count < dev_priv->ips.last_count1) {
3239                 diff = ~0UL - dev_priv->ips.last_count1;
3240                 diff += total_count;
3241         } else {
3242                 diff = total_count - dev_priv->ips.last_count1;
3243         }
3244
3245         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3246                 if (cparams[i].i == dev_priv->ips.c_m &&
3247                     cparams[i].t == dev_priv->ips.r_t) {
3248                         m = cparams[i].m;
3249                         c = cparams[i].c;
3250                         break;
3251                 }
3252         }
3253
3254         diff = div_u64(diff, diff1);
3255         ret = ((m * diff) + c);
3256         ret = div_u64(ret, 10);
3257
3258         dev_priv->ips.last_count1 = total_count;
3259         dev_priv->ips.last_time1 = now;
3260
3261         dev_priv->ips.chipset_power = ret;
3262
3263         return ret;
3264 }
3265
3266 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3267 {
3268         unsigned long val;
3269
3270         if (dev_priv->info->gen != 5)
3271                 return 0;
3272
3273         spin_lock_irq(&mchdev_lock);
3274
3275         val = __i915_chipset_val(dev_priv);
3276
3277         spin_unlock_irq(&mchdev_lock);
3278
3279         return val;
3280 }
3281
3282 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3283 {
3284         unsigned long m, x, b;
3285         u32 tsfs;
3286
3287         tsfs = I915_READ(TSFS);
3288
3289         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3290         x = I915_READ8(TR1);
3291
3292         b = tsfs & TSFS_INTR_MASK;
3293
3294         return ((m * x) / 127) - b;
3295 }
3296
3297 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3298 {
3299         static const struct v_table {
3300                 u16 vd; /* in .1 mil */
3301                 u16 vm; /* in .1 mil */
3302         } v_table[] = {
3303                 { 0, 0, },
3304                 { 375, 0, },
3305                 { 500, 0, },
3306                 { 625, 0, },
3307                 { 750, 0, },
3308                 { 875, 0, },
3309                 { 1000, 0, },
3310                 { 1125, 0, },
3311                 { 4125, 3000, },
3312                 { 4125, 3000, },
3313                 { 4125, 3000, },
3314                 { 4125, 3000, },
3315                 { 4125, 3000, },
3316                 { 4125, 3000, },
3317                 { 4125, 3000, },
3318                 { 4125, 3000, },
3319                 { 4125, 3000, },
3320                 { 4125, 3000, },
3321                 { 4125, 3000, },
3322                 { 4125, 3000, },
3323                 { 4125, 3000, },
3324                 { 4125, 3000, },
3325                 { 4125, 3000, },
3326                 { 4125, 3000, },
3327                 { 4125, 3000, },
3328                 { 4125, 3000, },
3329                 { 4125, 3000, },
3330                 { 4125, 3000, },
3331                 { 4125, 3000, },
3332                 { 4125, 3000, },
3333                 { 4125, 3000, },
3334                 { 4125, 3000, },
3335                 { 4250, 3125, },
3336                 { 4375, 3250, },
3337                 { 4500, 3375, },
3338                 { 4625, 3500, },
3339                 { 4750, 3625, },
3340                 { 4875, 3750, },
3341                 { 5000, 3875, },
3342                 { 5125, 4000, },
3343                 { 5250, 4125, },
3344                 { 5375, 4250, },
3345                 { 5500, 4375, },
3346                 { 5625, 4500, },
3347                 { 5750, 4625, },
3348                 { 5875, 4750, },
3349                 { 6000, 4875, },
3350                 { 6125, 5000, },
3351                 { 6250, 5125, },
3352                 { 6375, 5250, },
3353                 { 6500, 5375, },
3354                 { 6625, 5500, },
3355                 { 6750, 5625, },
3356                 { 6875, 5750, },
3357                 { 7000, 5875, },
3358                 { 7125, 6000, },
3359                 { 7250, 6125, },
3360                 { 7375, 6250, },
3361                 { 7500, 6375, },
3362                 { 7625, 6500, },
3363                 { 7750, 6625, },
3364                 { 7875, 6750, },
3365                 { 8000, 6875, },
3366                 { 8125, 7000, },
3367                 { 8250, 7125, },
3368                 { 8375, 7250, },
3369                 { 8500, 7375, },
3370                 { 8625, 7500, },
3371                 { 8750, 7625, },
3372                 { 8875, 7750, },
3373                 { 9000, 7875, },
3374                 { 9125, 8000, },
3375                 { 9250, 8125, },
3376                 { 9375, 8250, },
3377                 { 9500, 8375, },
3378                 { 9625, 8500, },
3379                 { 9750, 8625, },
3380                 { 9875, 8750, },
3381                 { 10000, 8875, },
3382                 { 10125, 9000, },
3383                 { 10250, 9125, },
3384                 { 10375, 9250, },
3385                 { 10500, 9375, },
3386                 { 10625, 9500, },
3387                 { 10750, 9625, },
3388                 { 10875, 9750, },
3389                 { 11000, 9875, },
3390                 { 11125, 10000, },
3391                 { 11250, 10125, },
3392                 { 11375, 10250, },
3393                 { 11500, 10375, },
3394                 { 11625, 10500, },
3395                 { 11750, 10625, },
3396                 { 11875, 10750, },
3397                 { 12000, 10875, },
3398                 { 12125, 11000, },
3399                 { 12250, 11125, },
3400                 { 12375, 11250, },
3401                 { 12500, 11375, },
3402                 { 12625, 11500, },
3403                 { 12750, 11625, },
3404                 { 12875, 11750, },
3405                 { 13000, 11875, },
3406                 { 13125, 12000, },
3407                 { 13250, 12125, },
3408                 { 13375, 12250, },
3409                 { 13500, 12375, },
3410                 { 13625, 12500, },
3411                 { 13750, 12625, },
3412                 { 13875, 12750, },
3413                 { 14000, 12875, },
3414                 { 14125, 13000, },
3415                 { 14250, 13125, },
3416                 { 14375, 13250, },
3417                 { 14500, 13375, },
3418                 { 14625, 13500, },
3419                 { 14750, 13625, },
3420                 { 14875, 13750, },
3421                 { 15000, 13875, },
3422                 { 15125, 14000, },
3423                 { 15250, 14125, },
3424                 { 15375, 14250, },
3425                 { 15500, 14375, },
3426                 { 15625, 14500, },
3427                 { 15750, 14625, },
3428                 { 15875, 14750, },
3429                 { 16000, 14875, },
3430                 { 16125, 15000, },
3431         };
3432         if (dev_priv->info->is_mobile)
3433                 return v_table[pxvid].vm;
3434         else
3435                 return v_table[pxvid].vd;
3436 }
3437
3438 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3439 {
3440         struct timespec now, diff1;
3441         u64 diff;
3442         unsigned long diffms;
3443         u32 count;
3444
3445         assert_spin_locked(&mchdev_lock);
3446
3447         getrawmonotonic(&now);
3448         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3449
3450         /* Don't divide by 0 */
3451         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3452         if (!diffms)
3453                 return;
3454
3455         count = I915_READ(GFXEC);
3456
3457         if (count < dev_priv->ips.last_count2) {
3458                 diff = ~0UL - dev_priv->ips.last_count2;
3459                 diff += count;
3460         } else {
3461                 diff = count - dev_priv->ips.last_count2;
3462         }
3463
3464         dev_priv->ips.last_count2 = count;
3465         dev_priv->ips.last_time2 = now;
3466
3467         /* More magic constants... */
3468         diff = diff * 1181;
3469         diff = div_u64(diff, diffms * 10);
3470         dev_priv->ips.gfx_power = diff;
3471 }
3472
3473 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3474 {
3475         if (dev_priv->info->gen != 5)
3476                 return;
3477
3478         spin_lock_irq(&mchdev_lock);
3479
3480         __i915_update_gfx_val(dev_priv);
3481
3482         spin_unlock_irq(&mchdev_lock);
3483 }
3484
3485 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3486 {
3487         unsigned long t, corr, state1, corr2, state2;
3488         u32 pxvid, ext_v;
3489
3490         assert_spin_locked(&mchdev_lock);
3491
3492         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3493         pxvid = (pxvid >> 24) & 0x7f;
3494         ext_v = pvid_to_extvid(dev_priv, pxvid);
3495
3496         state1 = ext_v;
3497
3498         t = i915_mch_val(dev_priv);
3499
3500         /* Revel in the empirically derived constants */
3501
3502         /* Correction factor in 1/100000 units */
3503         if (t > 80)
3504                 corr = ((t * 2349) + 135940);
3505         else if (t >= 50)
3506                 corr = ((t * 964) + 29317);
3507         else /* < 50 */
3508                 corr = ((t * 301) + 1004);
3509
3510         corr = corr * ((150142 * state1) / 10000 - 78642);
3511         corr /= 100000;
3512         corr2 = (corr * dev_priv->ips.corr);
3513
3514         state2 = (corr2 * state1) / 10000;
3515         state2 /= 100; /* convert to mW */
3516
3517         __i915_update_gfx_val(dev_priv);
3518
3519         return dev_priv->ips.gfx_power + state2;
3520 }
3521
3522 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3523 {
3524         unsigned long val;
3525
3526         if (dev_priv->info->gen != 5)
3527                 return 0;
3528
3529         spin_lock_irq(&mchdev_lock);
3530
3531         val = __i915_gfx_val(dev_priv);
3532
3533         spin_unlock_irq(&mchdev_lock);
3534
3535         return val;
3536 }
3537
3538 /**
3539  * i915_read_mch_val - return value for IPS use
3540  *
3541  * Calculate and return a value for the IPS driver to use when deciding whether
3542  * we have thermal and power headroom to increase CPU or GPU power budget.
3543  */
3544 unsigned long i915_read_mch_val(void)
3545 {
3546         struct drm_i915_private *dev_priv;
3547         unsigned long chipset_val, graphics_val, ret = 0;
3548
3549         spin_lock_irq(&mchdev_lock);
3550         if (!i915_mch_dev)
3551                 goto out_unlock;
3552         dev_priv = i915_mch_dev;
3553
3554         chipset_val = __i915_chipset_val(dev_priv);
3555         graphics_val = __i915_gfx_val(dev_priv);
3556
3557         ret = chipset_val + graphics_val;
3558
3559 out_unlock:
3560         spin_unlock_irq(&mchdev_lock);
3561
3562         return ret;
3563 }
3564 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3565
3566 /**
3567  * i915_gpu_raise - raise GPU frequency limit
3568  *
3569  * Raise the limit; IPS indicates we have thermal headroom.
3570  */
3571 bool i915_gpu_raise(void)
3572 {
3573         struct drm_i915_private *dev_priv;
3574         bool ret = true;
3575
3576         spin_lock_irq(&mchdev_lock);
3577         if (!i915_mch_dev) {
3578                 ret = false;
3579                 goto out_unlock;
3580         }
3581         dev_priv = i915_mch_dev;
3582
3583         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3584                 dev_priv->ips.max_delay--;
3585
3586 out_unlock:
3587         spin_unlock_irq(&mchdev_lock);
3588
3589         return ret;
3590 }
3591 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3592
3593 /**
3594  * i915_gpu_lower - lower GPU frequency limit
3595  *
3596  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3597  * frequency maximum.
3598  */
3599 bool i915_gpu_lower(void)
3600 {
3601         struct drm_i915_private *dev_priv;
3602         bool ret = true;
3603
3604         spin_lock_irq(&mchdev_lock);
3605         if (!i915_mch_dev) {
3606                 ret = false;
3607                 goto out_unlock;
3608         }
3609         dev_priv = i915_mch_dev;
3610
3611         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3612                 dev_priv->ips.max_delay++;
3613
3614 out_unlock:
3615         spin_unlock_irq(&mchdev_lock);
3616
3617         return ret;
3618 }
3619 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3620
3621 /**
3622  * i915_gpu_busy - indicate GPU business to IPS
3623  *
3624  * Tell the IPS driver whether or not the GPU is busy.
3625  */
3626 bool i915_gpu_busy(void)
3627 {
3628         struct drm_i915_private *dev_priv;
3629         struct intel_ring_buffer *ring;
3630         bool ret = false;
3631         int i;
3632
3633         spin_lock_irq(&mchdev_lock);
3634         if (!i915_mch_dev)
3635                 goto out_unlock;
3636         dev_priv = i915_mch_dev;
3637
3638         for_each_ring(ring, dev_priv, i)
3639                 ret |= !list_empty(&ring->request_list);
3640
3641 out_unlock:
3642         spin_unlock_irq(&mchdev_lock);
3643
3644         return ret;
3645 }
3646 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3647
3648 /**
3649  * i915_gpu_turbo_disable - disable graphics turbo
3650  *
3651  * Disable graphics turbo by resetting the max frequency and setting the
3652  * current frequency to the default.
3653  */
3654 bool i915_gpu_turbo_disable(void)
3655 {
3656         struct drm_i915_private *dev_priv;
3657         bool ret = true;
3658
3659         spin_lock_irq(&mchdev_lock);
3660         if (!i915_mch_dev) {
3661                 ret = false;
3662                 goto out_unlock;
3663         }
3664         dev_priv = i915_mch_dev;
3665
3666         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3667
3668         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3669                 ret = false;
3670
3671 out_unlock:
3672         spin_unlock_irq(&mchdev_lock);
3673
3674         return ret;
3675 }
3676 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3677
3678 /**
3679  * Tells the intel_ips driver that the i915 driver is now loaded, if
3680  * IPS got loaded first.
3681  *
3682  * This awkward dance is so that neither module has to depend on the
3683  * other in order for IPS to do the appropriate communication of
3684  * GPU turbo limits to i915.
3685  */
3686 static void
3687 ips_ping_for_i915_load(void)
3688 {
3689         void (*link)(void);
3690
3691         link = symbol_get(ips_link_to_i915_driver);
3692         if (link) {
3693                 link();
3694                 symbol_put(ips_link_to_i915_driver);
3695         }
3696 }
3697
3698 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3699 {
3700         /* We only register the i915 ips part with intel-ips once everything is
3701          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3702         spin_lock_irq(&mchdev_lock);
3703         i915_mch_dev = dev_priv;
3704         spin_unlock_irq(&mchdev_lock);
3705
3706         ips_ping_for_i915_load();
3707 }
3708
3709 void intel_gpu_ips_teardown(void)
3710 {
3711         spin_lock_irq(&mchdev_lock);
3712         i915_mch_dev = NULL;
3713         spin_unlock_irq(&mchdev_lock);
3714 }
3715 static void intel_init_emon(struct drm_device *dev)
3716 {
3717         struct drm_i915_private *dev_priv = dev->dev_private;
3718         u32 lcfuse;
3719         u8 pxw[16];
3720         int i;
3721
3722         /* Disable to program */
3723         I915_WRITE(ECR, 0);
3724         POSTING_READ(ECR);
3725
3726         /* Program energy weights for various events */
3727         I915_WRITE(SDEW, 0x15040d00);
3728         I915_WRITE(CSIEW0, 0x007f0000);
3729         I915_WRITE(CSIEW1, 0x1e220004);
3730         I915_WRITE(CSIEW2, 0x04000004);
3731
3732         for (i = 0; i < 5; i++)
3733                 I915_WRITE(PEW + (i * 4), 0);
3734         for (i = 0; i < 3; i++)
3735                 I915_WRITE(DEW + (i * 4), 0);
3736
3737         /* Program P-state weights to account for frequency power adjustment */
3738         for (i = 0; i < 16; i++) {
3739                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3740                 unsigned long freq = intel_pxfreq(pxvidfreq);
3741                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3742                         PXVFREQ_PX_SHIFT;
3743                 unsigned long val;
3744
3745                 val = vid * vid;
3746                 val *= (freq / 1000);
3747                 val *= 255;
3748                 val /= (127*127*900);
3749                 if (val > 0xff)
3750                         DRM_ERROR("bad pxval: %ld\n", val);
3751                 pxw[i] = val;
3752         }
3753         /* Render standby states get 0 weight */
3754         pxw[14] = 0;
3755         pxw[15] = 0;
3756
3757         for (i = 0; i < 4; i++) {
3758                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3759                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3760                 I915_WRITE(PXW + (i * 4), val);
3761         }
3762
3763         /* Adjust magic regs to magic values (more experimental results) */
3764         I915_WRITE(OGW0, 0);
3765         I915_WRITE(OGW1, 0);
3766         I915_WRITE(EG0, 0x00007f00);
3767         I915_WRITE(EG1, 0x0000000e);
3768         I915_WRITE(EG2, 0x000e0000);
3769         I915_WRITE(EG3, 0x68000300);
3770         I915_WRITE(EG4, 0x42000000);
3771         I915_WRITE(EG5, 0x00140031);
3772         I915_WRITE(EG6, 0);
3773         I915_WRITE(EG7, 0);
3774
3775         for (i = 0; i < 8; i++)
3776                 I915_WRITE(PXWL + (i * 4), 0);
3777
3778         /* Enable PMON + select events */
3779         I915_WRITE(ECR, 0x80000019);
3780
3781         lcfuse = I915_READ(LCFUSE02);
3782
3783         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3784 }
3785
3786 void intel_disable_gt_powersave(struct drm_device *dev)
3787 {
3788         struct drm_i915_private *dev_priv = dev->dev_private;
3789
3790         /* Interrupts should be disabled already to avoid re-arming. */
3791         WARN_ON(dev->irq_enabled);
3792
3793         if (IS_IRONLAKE_M(dev)) {
3794                 ironlake_disable_drps(dev);
3795                 ironlake_disable_rc6(dev);
3796         } else if (INTEL_INFO(dev)->gen >= 6) {
3797                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3798                 cancel_work_sync(&dev_priv->rps.work);
3799                 if (IS_VALLEYVIEW(dev))
3800                         cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
3801                 mutex_lock(&dev_priv->rps.hw_lock);
3802                 if (IS_VALLEYVIEW(dev))
3803                         valleyview_disable_rps(dev);
3804                 else
3805                         gen6_disable_rps(dev);
3806                 mutex_unlock(&dev_priv->rps.hw_lock);
3807         }
3808 }
3809
3810 static void intel_gen6_powersave_work(struct work_struct *work)
3811 {
3812         struct drm_i915_private *dev_priv =
3813                 container_of(work, struct drm_i915_private,
3814                              rps.delayed_resume_work.work);
3815         struct drm_device *dev = dev_priv->dev;
3816
3817         mutex_lock(&dev_priv->rps.hw_lock);
3818
3819         if (IS_VALLEYVIEW(dev)) {
3820                 valleyview_enable_rps(dev);
3821         } else {
3822                 gen6_enable_rps(dev);
3823                 gen6_update_ring_freq(dev);
3824         }
3825         mutex_unlock(&dev_priv->rps.hw_lock);
3826 }
3827
3828 void intel_enable_gt_powersave(struct drm_device *dev)
3829 {
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831
3832         if (IS_IRONLAKE_M(dev)) {
3833                 ironlake_enable_drps(dev);
3834                 ironlake_enable_rc6(dev);
3835                 intel_init_emon(dev);
3836         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3837                 /*
3838                  * PCU communication is slow and this doesn't need to be
3839                  * done at any specific time, so do this out of our fast path
3840                  * to make resume and init faster.
3841                  */
3842                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3843                                       round_jiffies_up_relative(HZ));
3844         }
3845 }
3846
3847 static void ibx_init_clock_gating(struct drm_device *dev)
3848 {
3849         struct drm_i915_private *dev_priv = dev->dev_private;
3850
3851         /*
3852          * On Ibex Peak and Cougar Point, we need to disable clock
3853          * gating for the panel power sequencer or it will fail to
3854          * start up when no ports are active.
3855          */
3856         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3857 }
3858
3859 static void ironlake_init_clock_gating(struct drm_device *dev)
3860 {
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3863
3864         /* Required for FBC */
3865         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3866                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3867                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3868
3869         I915_WRITE(PCH_3DCGDIS0,
3870                    MARIUNIT_CLOCK_GATE_DISABLE |
3871                    SVSMUNIT_CLOCK_GATE_DISABLE);
3872         I915_WRITE(PCH_3DCGDIS1,
3873                    VFMUNIT_CLOCK_GATE_DISABLE);
3874
3875         /*
3876          * According to the spec the following bits should be set in
3877          * order to enable memory self-refresh
3878          * The bit 22/21 of 0x42004
3879          * The bit 5 of 0x42020
3880          * The bit 15 of 0x45000
3881          */
3882         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3883                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3884                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3885         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3886         I915_WRITE(DISP_ARB_CTL,
3887                    (I915_READ(DISP_ARB_CTL) |
3888                     DISP_FBC_WM_DIS));
3889         I915_WRITE(WM3_LP_ILK, 0);
3890         I915_WRITE(WM2_LP_ILK, 0);
3891         I915_WRITE(WM1_LP_ILK, 0);
3892
3893         /*
3894          * Based on the document from hardware guys the following bits
3895          * should be set unconditionally in order to enable FBC.
3896          * The bit 22 of 0x42000
3897          * The bit 22 of 0x42004
3898          * The bit 7,8,9 of 0x42020.
3899          */
3900         if (IS_IRONLAKE_M(dev)) {
3901                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3902                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3903                            ILK_FBCQ_DIS);
3904                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3905                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3906                            ILK_DPARB_GATE);
3907         }
3908
3909         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3910
3911         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3912                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3913                    ILK_ELPIN_409_SELECT);
3914         I915_WRITE(_3D_CHICKEN2,
3915                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3916                    _3D_CHICKEN2_WM_READ_PIPELINED);
3917
3918         /* WaDisableRenderCachePipelinedFlush:ilk */
3919         I915_WRITE(CACHE_MODE_0,
3920                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3921
3922         ibx_init_clock_gating(dev);
3923 }
3924
3925 static void cpt_init_clock_gating(struct drm_device *dev)
3926 {
3927         struct drm_i915_private *dev_priv = dev->dev_private;
3928         int pipe;
3929         uint32_t val;
3930
3931         /*
3932          * On Ibex Peak and Cougar Point, we need to disable clock
3933          * gating for the panel power sequencer or it will fail to
3934          * start up when no ports are active.
3935          */
3936         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3937         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3938                    DPLS_EDP_PPS_FIX_DIS);
3939         /* The below fixes the weird display corruption, a few pixels shifted
3940          * downward, on (only) LVDS of some HP laptops with IVY.
3941          */
3942         for_each_pipe(pipe) {
3943                 val = I915_READ(TRANS_CHICKEN2(pipe));
3944                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3945                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3946                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3947                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3948                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3949                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3950                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3951                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3952         }
3953         /* WADP0ClockGatingDisable */
3954         for_each_pipe(pipe) {
3955                 I915_WRITE(TRANS_CHICKEN1(pipe),
3956                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3957         }
3958 }
3959
3960 static void gen6_check_mch_setup(struct drm_device *dev)
3961 {
3962         struct drm_i915_private *dev_priv = dev->dev_private;
3963         uint32_t tmp;
3964
3965         tmp = I915_READ(MCH_SSKPD);
3966         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3967                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3968                 DRM_INFO("This can cause pipe underruns and display issues.\n");
3969                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3970         }
3971 }
3972
3973 static void gen6_init_clock_gating(struct drm_device *dev)
3974 {
3975         struct drm_i915_private *dev_priv = dev->dev_private;
3976         int pipe;
3977         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3978
3979         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3980
3981         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3982                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3983                    ILK_ELPIN_409_SELECT);
3984
3985         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
3986         I915_WRITE(_3D_CHICKEN,
3987                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3988
3989         /* WaSetupGtModeTdRowDispatch:snb */
3990         if (IS_SNB_GT1(dev))
3991                 I915_WRITE(GEN6_GT_MODE,
3992                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3993
3994         I915_WRITE(WM3_LP_ILK, 0);
3995         I915_WRITE(WM2_LP_ILK, 0);
3996         I915_WRITE(WM1_LP_ILK, 0);
3997
3998         I915_WRITE(CACHE_MODE_0,
3999                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4000
4001         I915_WRITE(GEN6_UCGCTL1,
4002                    I915_READ(GEN6_UCGCTL1) |
4003                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4004                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4005
4006         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4007          * gating disable must be set.  Failure to set it results in
4008          * flickering pixels due to Z write ordering failures after
4009          * some amount of runtime in the Mesa "fire" demo, and Unigine
4010          * Sanctuary and Tropics, and apparently anything else with
4011          * alpha test or pixel discard.
4012          *
4013          * According to the spec, bit 11 (RCCUNIT) must also be set,
4014          * but we didn't debug actual testcases to find it out.
4015          *
4016          * Also apply WaDisableVDSUnitClockGating:snb and
4017          * WaDisableRCPBUnitClockGating:snb.
4018          */
4019         I915_WRITE(GEN6_UCGCTL2,
4020                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4021                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4022                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4023
4024         /* Bspec says we need to always set all mask bits. */
4025         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4026                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4027
4028         /*
4029          * According to the spec the following bits should be
4030          * set in order to enable memory self-refresh and fbc:
4031          * The bit21 and bit22 of 0x42000
4032          * The bit21 and bit22 of 0x42004
4033          * The bit5 and bit7 of 0x42020
4034          * The bit14 of 0x70180
4035          * The bit14 of 0x71180
4036          */
4037         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4038                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4039                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4040         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4041                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4042                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4043         I915_WRITE(ILK_DSPCLK_GATE_D,
4044                    I915_READ(ILK_DSPCLK_GATE_D) |
4045                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4046                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4047
4048         /* WaMbcDriverBootEnable:snb */
4049         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4050                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4051
4052         for_each_pipe(pipe) {
4053                 I915_WRITE(DSPCNTR(pipe),
4054                            I915_READ(DSPCNTR(pipe)) |
4055                            DISPPLANE_TRICKLE_FEED_DISABLE);
4056                 intel_flush_display_plane(dev_priv, pipe);
4057         }
4058
4059         /* The default value should be 0x200 according to docs, but the two
4060          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4061         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4062         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4063
4064         cpt_init_clock_gating(dev);
4065
4066         gen6_check_mch_setup(dev);
4067 }
4068
4069 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4070 {
4071         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4072
4073         reg &= ~GEN7_FF_SCHED_MASK;
4074         reg |= GEN7_FF_TS_SCHED_HW;
4075         reg |= GEN7_FF_VS_SCHED_HW;
4076         reg |= GEN7_FF_DS_SCHED_HW;
4077
4078         if (IS_HASWELL(dev_priv->dev))
4079                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4080
4081         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4082 }
4083
4084 static void lpt_init_clock_gating(struct drm_device *dev)
4085 {
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087
4088         /*
4089          * TODO: this bit should only be enabled when really needed, then
4090          * disabled when not needed anymore in order to save power.
4091          */
4092         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4093                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4094                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4095                            PCH_LP_PARTITION_LEVEL_DISABLE);
4096
4097         /* WADPOClockGatingDisable:hsw */
4098         I915_WRITE(_TRANSA_CHICKEN1,
4099                    I915_READ(_TRANSA_CHICKEN1) |
4100                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4101 }
4102
4103 static void lpt_suspend_hw(struct drm_device *dev)
4104 {
4105         struct drm_i915_private *dev_priv = dev->dev_private;
4106
4107         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4108                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4109
4110                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4111                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4112         }
4113 }
4114
4115 static void haswell_init_clock_gating(struct drm_device *dev)
4116 {
4117         struct drm_i915_private *dev_priv = dev->dev_private;
4118         int pipe;
4119
4120         I915_WRITE(WM3_LP_ILK, 0);
4121         I915_WRITE(WM2_LP_ILK, 0);
4122         I915_WRITE(WM1_LP_ILK, 0);
4123
4124         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4125          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4126          */
4127         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4128
4129         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4130         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4131                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4132
4133         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4134         I915_WRITE(GEN7_L3CNTLREG1,
4135                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4136         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4137                         GEN7_WA_L3_CHICKEN_MODE);
4138
4139         /* This is required by WaCatErrorRejectionIssue:hsw */
4140         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4141                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4142                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4143
4144         for_each_pipe(pipe) {
4145                 I915_WRITE(DSPCNTR(pipe),
4146                            I915_READ(DSPCNTR(pipe)) |
4147                            DISPPLANE_TRICKLE_FEED_DISABLE);
4148                 intel_flush_display_plane(dev_priv, pipe);
4149         }
4150
4151         /* WaVSRefCountFullforceMissDisable:hsw */
4152         gen7_setup_fixed_func_scheduler(dev_priv);
4153
4154         /* WaDisable4x2SubspanOptimization:hsw */
4155         I915_WRITE(CACHE_MODE_1,
4156                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4157
4158         /* WaMbcDriverBootEnable:hsw */
4159         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4160                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4161
4162         /* WaSwitchSolVfFArbitrationPriority:hsw */
4163         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4164
4165         /* XXX: This is a workaround for early silicon revisions and should be
4166          * removed later.
4167          */
4168         I915_WRITE(WM_DBG,
4169                         I915_READ(WM_DBG) |
4170                         WM_DBG_DISALLOW_MULTIPLE_LP |
4171                         WM_DBG_DISALLOW_SPRITE |
4172                         WM_DBG_DISALLOW_MAXFIFO);
4173
4174         lpt_init_clock_gating(dev);
4175 }
4176
4177 static void ivybridge_init_clock_gating(struct drm_device *dev)
4178 {
4179         struct drm_i915_private *dev_priv = dev->dev_private;
4180         int pipe;
4181         uint32_t snpcr;
4182
4183         I915_WRITE(WM3_LP_ILK, 0);
4184         I915_WRITE(WM2_LP_ILK, 0);
4185         I915_WRITE(WM1_LP_ILK, 0);
4186
4187         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4188
4189         /* WaDisableEarlyCull:ivb */
4190         I915_WRITE(_3D_CHICKEN3,
4191                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4192
4193         /* WaDisableBackToBackFlipFix:ivb */
4194         I915_WRITE(IVB_CHICKEN3,
4195                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4196                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4197
4198         /* WaDisablePSDDualDispatchEnable:ivb */
4199         if (IS_IVB_GT1(dev))
4200                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4201                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4202         else
4203                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4204                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4205
4206         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
4207         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4208                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4209
4210         /* WaApplyL3ControlAndL3ChickenMode:ivb */
4211         I915_WRITE(GEN7_L3CNTLREG1,
4212                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4213         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4214                    GEN7_WA_L3_CHICKEN_MODE);
4215         if (IS_IVB_GT1(dev))
4216                 I915_WRITE(GEN7_ROW_CHICKEN2,
4217                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4218         else
4219                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4220                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4221
4222
4223         /* WaForceL3Serialization:ivb */
4224         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4225                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4226
4227         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4228          * gating disable must be set.  Failure to set it results in
4229          * flickering pixels due to Z write ordering failures after
4230          * some amount of runtime in the Mesa "fire" demo, and Unigine
4231          * Sanctuary and Tropics, and apparently anything else with
4232          * alpha test or pixel discard.
4233          *
4234          * According to the spec, bit 11 (RCCUNIT) must also be set,
4235          * but we didn't debug actual testcases to find it out.
4236          *
4237          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4238          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
4239          */
4240         I915_WRITE(GEN6_UCGCTL2,
4241                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4242                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4243
4244         /* This is required by WaCatErrorRejectionIssue:ivb */
4245         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4246                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4247                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4248
4249         for_each_pipe(pipe) {
4250                 I915_WRITE(DSPCNTR(pipe),
4251                            I915_READ(DSPCNTR(pipe)) |
4252                            DISPPLANE_TRICKLE_FEED_DISABLE);
4253                 intel_flush_display_plane(dev_priv, pipe);
4254         }
4255
4256         /* WaMbcDriverBootEnable:ivb */
4257         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4258                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4259
4260         /* WaVSRefCountFullforceMissDisable:ivb */
4261         gen7_setup_fixed_func_scheduler(dev_priv);
4262
4263         /* WaDisable4x2SubspanOptimization:ivb */
4264         I915_WRITE(CACHE_MODE_1,
4265                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4266
4267         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4268         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4269         snpcr |= GEN6_MBC_SNPCR_MED;
4270         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4271
4272         if (!HAS_PCH_NOP(dev))
4273                 cpt_init_clock_gating(dev);
4274
4275         gen6_check_mch_setup(dev);
4276 }
4277
4278 static void valleyview_init_clock_gating(struct drm_device *dev)
4279 {
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         int pipe;
4282
4283         I915_WRITE(WM3_LP_ILK, 0);
4284         I915_WRITE(WM2_LP_ILK, 0);
4285         I915_WRITE(WM1_LP_ILK, 0);
4286
4287         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4288
4289         /* WaDisableEarlyCull:vlv */
4290         I915_WRITE(_3D_CHICKEN3,
4291                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4292
4293         /* WaDisableBackToBackFlipFix:vlv */
4294         I915_WRITE(IVB_CHICKEN3,
4295                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4296                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4297
4298         /* WaDisablePSDDualDispatchEnable:vlv */
4299         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4300                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4301                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4302
4303         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
4304         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4305                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4306
4307         /* WaApplyL3ControlAndL3ChickenMode:vlv */
4308         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4309         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4310
4311         /* WaForceL3Serialization:vlv */
4312         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4313                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4314
4315         /* WaDisableDopClockGating:vlv */
4316         I915_WRITE(GEN7_ROW_CHICKEN2,
4317                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4318
4319         /* WaForceL3Serialization:vlv */
4320         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4321                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4322
4323         /* This is required by WaCatErrorRejectionIssue:vlv */
4324         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4325                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4326                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4327
4328         /* WaMbcDriverBootEnable:vlv */
4329         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4330                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4331
4332
4333         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4334          * gating disable must be set.  Failure to set it results in
4335          * flickering pixels due to Z write ordering failures after
4336          * some amount of runtime in the Mesa "fire" demo, and Unigine
4337          * Sanctuary and Tropics, and apparently anything else with
4338          * alpha test or pixel discard.
4339          *
4340          * According to the spec, bit 11 (RCCUNIT) must also be set,
4341          * but we didn't debug actual testcases to find it out.
4342          *
4343          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4344          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
4345          *
4346          * Also apply WaDisableVDSUnitClockGating:vlv and
4347          * WaDisableRCPBUnitClockGating:vlv.
4348          */
4349         I915_WRITE(GEN6_UCGCTL2,
4350                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4351                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4352                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4353                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4354                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4355
4356         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4357
4358         for_each_pipe(pipe) {
4359                 I915_WRITE(DSPCNTR(pipe),
4360                            I915_READ(DSPCNTR(pipe)) |
4361                            DISPPLANE_TRICKLE_FEED_DISABLE);
4362                 intel_flush_display_plane(dev_priv, pipe);
4363         }
4364
4365         I915_WRITE(CACHE_MODE_1,
4366                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4367
4368         /*
4369          * WaDisableVLVClockGating_VBIIssue:vlv
4370          * Disable clock gating on th GCFG unit to prevent a delay
4371          * in the reporting of vblank events.
4372          */
4373         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4374
4375         /* Conservative clock gating settings for now */
4376         I915_WRITE(0x9400, 0xffffffff);
4377         I915_WRITE(0x9404, 0xffffffff);
4378         I915_WRITE(0x9408, 0xffffffff);
4379         I915_WRITE(0x940c, 0xffffffff);
4380         I915_WRITE(0x9410, 0xffffffff);
4381         I915_WRITE(0x9414, 0xffffffff);
4382         I915_WRITE(0x9418, 0xffffffff);
4383 }
4384
4385 static void g4x_init_clock_gating(struct drm_device *dev)
4386 {
4387         struct drm_i915_private *dev_priv = dev->dev_private;
4388         uint32_t dspclk_gate;
4389
4390         I915_WRITE(RENCLK_GATE_D1, 0);
4391         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4392                    GS_UNIT_CLOCK_GATE_DISABLE |
4393                    CL_UNIT_CLOCK_GATE_DISABLE);
4394         I915_WRITE(RAMCLK_GATE_D, 0);
4395         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4396                 OVRUNIT_CLOCK_GATE_DISABLE |
4397                 OVCUNIT_CLOCK_GATE_DISABLE;
4398         if (IS_GM45(dev))
4399                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4400         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4401
4402         /* WaDisableRenderCachePipelinedFlush */
4403         I915_WRITE(CACHE_MODE_0,
4404                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4405 }
4406
4407 static void crestline_init_clock_gating(struct drm_device *dev)
4408 {
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410
4411         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4412         I915_WRITE(RENCLK_GATE_D2, 0);
4413         I915_WRITE(DSPCLK_GATE_D, 0);
4414         I915_WRITE(RAMCLK_GATE_D, 0);
4415         I915_WRITE16(DEUC, 0);
4416 }
4417
4418 static void broadwater_init_clock_gating(struct drm_device *dev)
4419 {
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421
4422         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4423                    I965_RCC_CLOCK_GATE_DISABLE |
4424                    I965_RCPB_CLOCK_GATE_DISABLE |
4425                    I965_ISC_CLOCK_GATE_DISABLE |
4426                    I965_FBC_CLOCK_GATE_DISABLE);
4427         I915_WRITE(RENCLK_GATE_D2, 0);
4428 }
4429
4430 static void gen3_init_clock_gating(struct drm_device *dev)
4431 {
4432         struct drm_i915_private *dev_priv = dev->dev_private;
4433         u32 dstate = I915_READ(D_STATE);
4434
4435         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4436                 DSTATE_DOT_CLOCK_GATING;
4437         I915_WRITE(D_STATE, dstate);
4438
4439         if (IS_PINEVIEW(dev))
4440                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4441
4442         /* IIR "flip pending" means done if this bit is set */
4443         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4444 }
4445
4446 static void i85x_init_clock_gating(struct drm_device *dev)
4447 {
4448         struct drm_i915_private *dev_priv = dev->dev_private;
4449
4450         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4451 }
4452
4453 static void i830_init_clock_gating(struct drm_device *dev)
4454 {
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4458 }
4459
4460 void intel_init_clock_gating(struct drm_device *dev)
4461 {
4462         struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464         dev_priv->display.init_clock_gating(dev);
4465 }
4466
4467 void intel_suspend_hw(struct drm_device *dev)
4468 {
4469         if (HAS_PCH_LPT(dev))
4470                 lpt_suspend_hw(dev);
4471 }
4472
4473 /**
4474  * We should only use the power well if we explicitly asked the hardware to
4475  * enable it, so check if it's enabled and also check if we've requested it to
4476  * be enabled.
4477  */
4478 bool intel_display_power_enabled(struct drm_device *dev,
4479                                  enum intel_display_power_domain domain)
4480 {
4481         struct drm_i915_private *dev_priv = dev->dev_private;
4482
4483         if (!HAS_POWER_WELL(dev))
4484                 return true;
4485
4486         switch (domain) {
4487         case POWER_DOMAIN_PIPE_A:
4488         case POWER_DOMAIN_TRANSCODER_EDP:
4489                 return true;
4490         case POWER_DOMAIN_PIPE_B:
4491         case POWER_DOMAIN_PIPE_C:
4492         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
4493         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
4494         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
4495         case POWER_DOMAIN_TRANSCODER_A:
4496         case POWER_DOMAIN_TRANSCODER_B:
4497         case POWER_DOMAIN_TRANSCODER_C:
4498                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4499                        (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4500         default:
4501                 BUG();
4502         }
4503 }
4504
4505 void intel_set_power_well(struct drm_device *dev, bool enable)
4506 {
4507         struct drm_i915_private *dev_priv = dev->dev_private;
4508         bool is_enabled, enable_requested;
4509         uint32_t tmp;
4510
4511         if (!HAS_POWER_WELL(dev))
4512                 return;
4513
4514         if (!i915_disable_power_well && !enable)
4515                 return;
4516
4517         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4518         is_enabled = tmp & HSW_PWR_WELL_STATE;
4519         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4520
4521         if (enable) {
4522                 if (!enable_requested)
4523                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4524
4525                 if (!is_enabled) {
4526                         DRM_DEBUG_KMS("Enabling power well\n");
4527                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4528                                       HSW_PWR_WELL_STATE), 20))
4529                                 DRM_ERROR("Timeout enabling power well\n");
4530                 }
4531         } else {
4532                 if (enable_requested) {
4533                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4534                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
4535                 }
4536         }
4537 }
4538
4539 /*
4540  * Starting with Haswell, we have a "Power Down Well" that can be turned off
4541  * when not needed anymore. We have 4 registers that can request the power well
4542  * to be enabled, and it will only be disabled if none of the registers is
4543  * requesting it to be enabled.
4544  */
4545 void intel_init_power_well(struct drm_device *dev)
4546 {
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548
4549         if (!HAS_POWER_WELL(dev))
4550                 return;
4551
4552         /* For now, we need the power well to be always enabled. */
4553         intel_set_power_well(dev, true);
4554
4555         /* We're taking over the BIOS, so clear any requests made by it since
4556          * the driver is in charge now. */
4557         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4558                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4559 }
4560
4561 /* Set up chip specific power management-related functions */
4562 void intel_init_pm(struct drm_device *dev)
4563 {
4564         struct drm_i915_private *dev_priv = dev->dev_private;
4565
4566         if (I915_HAS_FBC(dev)) {
4567                 if (HAS_PCH_SPLIT(dev)) {
4568                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4569                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4570                                 dev_priv->display.enable_fbc =
4571                                         gen7_enable_fbc;
4572                         else
4573                                 dev_priv->display.enable_fbc =
4574                                         ironlake_enable_fbc;
4575                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4576                 } else if (IS_GM45(dev)) {
4577                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4578                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4579                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4580                 } else if (IS_CRESTLINE(dev)) {
4581                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4582                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4583                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4584                 }
4585                 /* 855GM needs testing */
4586         }
4587
4588         /* For cxsr */
4589         if (IS_PINEVIEW(dev))
4590                 i915_pineview_get_mem_freq(dev);
4591         else if (IS_GEN5(dev))
4592                 i915_ironlake_get_mem_freq(dev);
4593
4594         /* For FIFO watermark updates */
4595         if (HAS_PCH_SPLIT(dev)) {
4596                 if (IS_GEN5(dev)) {
4597                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4598                                 dev_priv->display.update_wm = ironlake_update_wm;
4599                         else {
4600                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4601                                               "Disable CxSR\n");
4602                                 dev_priv->display.update_wm = NULL;
4603                         }
4604                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4605                 } else if (IS_GEN6(dev)) {
4606                         if (SNB_READ_WM0_LATENCY()) {
4607                                 dev_priv->display.update_wm = sandybridge_update_wm;
4608                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4609                         } else {
4610                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4611                                               "Disable CxSR\n");
4612                                 dev_priv->display.update_wm = NULL;
4613                         }
4614                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4615                 } else if (IS_IVYBRIDGE(dev)) {
4616                         if (SNB_READ_WM0_LATENCY()) {
4617                                 dev_priv->display.update_wm = ivybridge_update_wm;
4618                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4619                         } else {
4620                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4621                                               "Disable CxSR\n");
4622                                 dev_priv->display.update_wm = NULL;
4623                         }
4624                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4625                 } else if (IS_HASWELL(dev)) {
4626                         if (SNB_READ_WM0_LATENCY()) {
4627                                 dev_priv->display.update_wm = sandybridge_update_wm;
4628                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4629                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4630                         } else {
4631                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4632                                               "Disable CxSR\n");
4633                                 dev_priv->display.update_wm = NULL;
4634                         }
4635                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4636                 } else
4637                         dev_priv->display.update_wm = NULL;
4638         } else if (IS_VALLEYVIEW(dev)) {
4639                 dev_priv->display.update_wm = valleyview_update_wm;
4640                 dev_priv->display.init_clock_gating =
4641                         valleyview_init_clock_gating;
4642         } else if (IS_PINEVIEW(dev)) {
4643                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4644                                             dev_priv->is_ddr3,
4645                                             dev_priv->fsb_freq,
4646                                             dev_priv->mem_freq)) {
4647                         DRM_INFO("failed to find known CxSR latency "
4648                                  "(found ddr%s fsb freq %d, mem freq %d), "
4649                                  "disabling CxSR\n",
4650                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4651                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4652                         /* Disable CxSR and never update its watermark again */
4653                         pineview_disable_cxsr(dev);
4654                         dev_priv->display.update_wm = NULL;
4655                 } else
4656                         dev_priv->display.update_wm = pineview_update_wm;
4657                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4658         } else if (IS_G4X(dev)) {
4659                 dev_priv->display.update_wm = g4x_update_wm;
4660                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4661         } else if (IS_GEN4(dev)) {
4662                 dev_priv->display.update_wm = i965_update_wm;
4663                 if (IS_CRESTLINE(dev))
4664                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4665                 else if (IS_BROADWATER(dev))
4666                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4667         } else if (IS_GEN3(dev)) {
4668                 dev_priv->display.update_wm = i9xx_update_wm;
4669                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4670                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4671         } else if (IS_I865G(dev)) {
4672                 dev_priv->display.update_wm = i830_update_wm;
4673                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4674                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4675         } else if (IS_I85X(dev)) {
4676                 dev_priv->display.update_wm = i9xx_update_wm;
4677                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4678                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4679         } else {
4680                 dev_priv->display.update_wm = i830_update_wm;
4681                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4682                 if (IS_845G(dev))
4683                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4684                 else
4685                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4686         }
4687 }
4688
4689 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4690 {
4691         u32 gt_thread_status_mask;
4692
4693         if (IS_HASWELL(dev_priv->dev))
4694                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4695         else
4696                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4697
4698         /* w/a for a sporadic read returning 0 by waiting for the GT
4699          * thread to wake up.
4700          */
4701         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4702                 DRM_ERROR("GT thread status wait timed out\n");
4703 }
4704
4705 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4706 {
4707         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4708         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4709 }
4710
4711 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4712 {
4713         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4714                             FORCEWAKE_ACK_TIMEOUT_MS))
4715                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4716
4717         I915_WRITE_NOTRACE(FORCEWAKE, 1);
4718         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4719
4720         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4721                             FORCEWAKE_ACK_TIMEOUT_MS))
4722                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4723
4724         /* WaRsForcewakeWaitTC0:snb */
4725         __gen6_gt_wait_for_thread_c0(dev_priv);
4726 }
4727
4728 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4729 {
4730         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4731         /* something from same cacheline, but !FORCEWAKE_MT */
4732         POSTING_READ(ECOBUS);
4733 }
4734
4735 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4736 {
4737         u32 forcewake_ack;
4738
4739         if (IS_HASWELL(dev_priv->dev))
4740                 forcewake_ack = FORCEWAKE_ACK_HSW;
4741         else
4742                 forcewake_ack = FORCEWAKE_MT_ACK;
4743
4744         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4745                             FORCEWAKE_ACK_TIMEOUT_MS))
4746                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4747
4748         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4749         /* something from same cacheline, but !FORCEWAKE_MT */
4750         POSTING_READ(ECOBUS);
4751
4752         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4753                             FORCEWAKE_ACK_TIMEOUT_MS))
4754                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4755
4756         /* WaRsForcewakeWaitTC0:ivb,hsw */
4757         __gen6_gt_wait_for_thread_c0(dev_priv);
4758 }
4759
4760 /*
4761  * Generally this is called implicitly by the register read function. However,
4762  * if some sequence requires the GT to not power down then this function should
4763  * be called at the beginning of the sequence followed by a call to
4764  * gen6_gt_force_wake_put() at the end of the sequence.
4765  */
4766 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4767 {
4768         unsigned long irqflags;
4769
4770         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4771         if (dev_priv->forcewake_count++ == 0)
4772                 dev_priv->gt.force_wake_get(dev_priv);
4773         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4774 }
4775
4776 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4777 {
4778         u32 gtfifodbg;
4779         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4780         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4781              "MMIO read or write has been dropped %x\n", gtfifodbg))
4782                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4783 }
4784
4785 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4786 {
4787         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4788         /* something from same cacheline, but !FORCEWAKE */
4789         POSTING_READ(ECOBUS);
4790         gen6_gt_check_fifodbg(dev_priv);
4791 }
4792
4793 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4794 {
4795         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4796         /* something from same cacheline, but !FORCEWAKE_MT */
4797         POSTING_READ(ECOBUS);
4798         gen6_gt_check_fifodbg(dev_priv);
4799 }
4800
4801 /*
4802  * see gen6_gt_force_wake_get()
4803  */
4804 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4805 {
4806         unsigned long irqflags;
4807
4808         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4809         if (--dev_priv->forcewake_count == 0)
4810                 dev_priv->gt.force_wake_put(dev_priv);
4811         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4812 }
4813
4814 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4815 {
4816         int ret = 0;
4817
4818         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4819                 int loop = 500;
4820                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4821                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4822                         udelay(10);
4823                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4824                 }
4825                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4826                         ++ret;
4827                 dev_priv->gt_fifo_count = fifo;
4828         }
4829         dev_priv->gt_fifo_count--;
4830
4831         return ret;
4832 }
4833
4834 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4835 {
4836         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4837         /* something from same cacheline, but !FORCEWAKE_VLV */
4838         POSTING_READ(FORCEWAKE_ACK_VLV);
4839 }
4840
4841 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4842 {
4843         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4844                             FORCEWAKE_ACK_TIMEOUT_MS))
4845                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4846
4847         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4848         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4849                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4850
4851         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4852                             FORCEWAKE_ACK_TIMEOUT_MS))
4853                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4854
4855         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4856                              FORCEWAKE_KERNEL),
4857                             FORCEWAKE_ACK_TIMEOUT_MS))
4858                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4859
4860         /* WaRsForcewakeWaitTC0:vlv */
4861         __gen6_gt_wait_for_thread_c0(dev_priv);
4862 }
4863
4864 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4865 {
4866         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4867         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4868                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4869         /* The below doubles as a POSTING_READ */
4870         gen6_gt_check_fifodbg(dev_priv);
4871 }
4872
4873 void intel_gt_reset(struct drm_device *dev)
4874 {
4875         struct drm_i915_private *dev_priv = dev->dev_private;
4876
4877         if (IS_VALLEYVIEW(dev)) {
4878                 vlv_force_wake_reset(dev_priv);
4879         } else if (INTEL_INFO(dev)->gen >= 6) {
4880                 __gen6_gt_force_wake_reset(dev_priv);
4881                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4882                         __gen6_gt_force_wake_mt_reset(dev_priv);
4883         }
4884 }
4885
4886 void intel_gt_init(struct drm_device *dev)
4887 {
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889
4890         spin_lock_init(&dev_priv->gt_lock);
4891
4892         intel_gt_reset(dev);
4893
4894         if (IS_VALLEYVIEW(dev)) {
4895                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4896                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4897         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4898                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4899                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4900         } else if (IS_GEN6(dev)) {
4901                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4902                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4903         }
4904         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4905                           intel_gen6_powersave_work);
4906 }
4907
4908 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4909 {
4910         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4911
4912         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4913                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4914                 return -EAGAIN;
4915         }
4916
4917         I915_WRITE(GEN6_PCODE_DATA, *val);
4918         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4919
4920         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4921                      500)) {
4922                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4923                 return -ETIMEDOUT;
4924         }
4925
4926         *val = I915_READ(GEN6_PCODE_DATA);
4927         I915_WRITE(GEN6_PCODE_DATA, 0);
4928
4929         return 0;
4930 }
4931
4932 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4933 {
4934         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4935
4936         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4937                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4938                 return -EAGAIN;
4939         }
4940
4941         I915_WRITE(GEN6_PCODE_DATA, val);
4942         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4943
4944         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4945                      500)) {
4946                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4947                 return -ETIMEDOUT;
4948         }
4949
4950         I915_WRITE(GEN6_PCODE_DATA, 0);
4951
4952         return 0;
4953 }
4954
4955 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4956                         u8 addr, u32 *val)
4957 {
4958         u32 cmd, devfn, be, bar;
4959
4960         bar = 0;
4961         be = 0xf;
4962         devfn = PCI_DEVFN(2, 0);
4963
4964         cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4965                 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4966                 (bar << IOSF_BAR_SHIFT);
4967
4968         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4969
4970         if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4971                 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4972                                  opcode == PUNIT_OPCODE_REG_READ ?
4973                                  "read" : "write");
4974                 return -EAGAIN;
4975         }
4976
4977         I915_WRITE(VLV_IOSF_ADDR, addr);
4978         if (opcode == PUNIT_OPCODE_REG_WRITE)
4979                 I915_WRITE(VLV_IOSF_DATA, *val);
4980         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4981
4982         if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4983                      5)) {
4984                 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4985                           opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4986                           addr);
4987                 return -ETIMEDOUT;
4988         }
4989
4990         if (opcode == PUNIT_OPCODE_REG_READ)
4991                 *val = I915_READ(VLV_IOSF_DATA);
4992         I915_WRITE(VLV_IOSF_DATA, 0);
4993
4994         return 0;
4995 }
4996
4997 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4998 {
4999         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
5000                             addr, val);
5001 }
5002
5003 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
5004 {
5005         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
5006                             addr, &val);
5007 }
5008
5009 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
5010 {
5011         return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
5012                             addr, val);
5013 }
5014
5015 int vlv_gpu_freq(int ddr_freq, int val)
5016 {
5017         int mult, base;
5018
5019         switch (ddr_freq) {
5020         case 800:
5021                 mult = 20;
5022                 base = 120;
5023                 break;
5024         case 1066:
5025                 mult = 22;
5026                 base = 133;
5027                 break;
5028         case 1333:
5029                 mult = 21;
5030                 base = 125;
5031                 break;
5032         default:
5033                 return -1;
5034         }
5035
5036         return ((val - 0xbd) * mult) + base;
5037 }
5038
5039 int vlv_freq_opcode(int ddr_freq, int val)
5040 {
5041         int mult, base;
5042
5043         switch (ddr_freq) {
5044         case 800:
5045                 mult = 20;
5046                 base = 120;
5047                 break;
5048         case 1066:
5049                 mult = 22;
5050                 base = 133;
5051                 break;
5052         case 1333:
5053                 mult = 21;
5054                 base = 125;
5055                 break;
5056         default:
5057                 return -1;
5058         }
5059
5060         val /= mult;
5061         val -= base / mult;
5062         val += 0xbd;
5063
5064         if (val > 0xea)
5065                 val = 0xea;
5066
5067         return val;
5068 }
5069