Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         case HDMI_INFOFRAME_TYPE_VENDOR:
  78                 return VIDEO_DIP_SELECT_VENDOR;
  79         default:
  80                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  81                 return 0;
  82         }
  83 }
  84
  85 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  86 {
  87         switch (type) {
  88         case HDMI_INFOFRAME_TYPE_AVI:
  89                 return VIDEO_DIP_ENABLE_AVI;
  90         case HDMI_INFOFRAME_TYPE_SPD:
  91                 return VIDEO_DIP_ENABLE_SPD;
  92         case HDMI_INFOFRAME_TYPE_VENDOR:
  93                 return VIDEO_DIP_ENABLE_VENDOR;
  94         default:
  95                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  96                 return 0;
  97         }
  98 }
  99
 100 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 101 {
 102         switch (type) {
 103         case HDMI_INFOFRAME_TYPE_AVI:
 104                 return VIDEO_DIP_ENABLE_AVI_HSW;
 105         case HDMI_INFOFRAME_TYPE_SPD:
 106                 return VIDEO_DIP_ENABLE_SPD_HSW;
 107         case HDMI_INFOFRAME_TYPE_VENDOR:
 108                 return VIDEO_DIP_ENABLE_VS_HSW;
 109         default:
 110                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 111                 return 0;
 112         }
 113 }
 114
 115 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 116                                   enum transcoder cpu_transcoder)
 117 {
 118         switch (type) {
 119         case HDMI_INFOFRAME_TYPE_AVI:
 120                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 121         case HDMI_INFOFRAME_TYPE_SPD:
 122                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 123         case HDMI_INFOFRAME_TYPE_VENDOR:
 124                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
 125         default:
 126                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 127                 return 0;
 128         }
 129 }
 130
 131 static void g4x_write_infoframe(struct drm_encoder *encoder,
 132                                 enum hdmi_infoframe_type type,
 133                                 const uint8_t *frame, ssize_t len)
 134 {
 135         uint32_t *data = (uint32_t *)frame;
 136         struct drm_device *dev = encoder->dev;
 137         struct drm_i915_private *dev_priv = dev->dev_private;
 138         u32 val = I915_READ(VIDEO_DIP_CTL);
 139         int i;
 140
 141         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 142
 143         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 144         val |= g4x_infoframe_index(type);
 145
 146         val &= ~g4x_infoframe_enable(type);
 147
 148         I915_WRITE(VIDEO_DIP_CTL, val);
 149
 150         mmiowb();
 151         for (i = 0; i < len; i += 4) {
 152                 I915_WRITE(VIDEO_DIP_DATA, *data);
 153                 data++;
 154         }
 155         /* Write every possible data byte to force correct ECC calculation. */
 156         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 157                 I915_WRITE(VIDEO_DIP_DATA, 0);
 158         mmiowb();
 159
 160         val |= g4x_infoframe_enable(type);
 161         val &= ~VIDEO_DIP_FREQ_MASK;
 162         val |= VIDEO_DIP_FREQ_VSYNC;
 163
 164         I915_WRITE(VIDEO_DIP_CTL, val);
 165         POSTING_READ(VIDEO_DIP_CTL);
 166 }
 167
 168 static void ibx_write_infoframe(struct drm_encoder *encoder,
 169                                 enum hdmi_infoframe_type type,
 170                                 const uint8_t *frame, ssize_t len)
 171 {
 172         uint32_t *data = (uint32_t *)frame;
 173         struct drm_device *dev = encoder->dev;
 174         struct drm_i915_private *dev_priv = dev->dev_private;
 175         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 176         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 177         u32 val = I915_READ(reg);
 178
 179         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 180
 181         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 182         val |= g4x_infoframe_index(type);
 183
 184         val &= ~g4x_infoframe_enable(type);
 185
 186         I915_WRITE(reg, val);
 187
 188         mmiowb();
 189         for (i = 0; i < len; i += 4) {
 190                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 191                 data++;
 192         }
 193         /* Write every possible data byte to force correct ECC calculation. */
 194         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 196         mmiowb();
 197
 198         val |= g4x_infoframe_enable(type);
 199         val &= ~VIDEO_DIP_FREQ_MASK;
 200         val |= VIDEO_DIP_FREQ_VSYNC;
 201
 202         I915_WRITE(reg, val);
 203         POSTING_READ(reg);
 204 }
 205
 206 static void cpt_write_infoframe(struct drm_encoder *encoder,
 207                                 enum hdmi_infoframe_type type,
 208                                 const uint8_t *frame, ssize_t len)
 209 {
 210         uint32_t *data = (uint32_t *)frame;
 211         struct drm_device *dev = encoder->dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 214         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 215         u32 val = I915_READ(reg);
 216
 217         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 218
 219         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 220         val |= g4x_infoframe_index(type);
 221
 222         /* The DIP control register spec says that we need to update the AVI
 223          * infoframe without clearing its enable bit */
 224         if (type != HDMI_INFOFRAME_TYPE_AVI)
 225                 val &= ~g4x_infoframe_enable(type);
 226
 227         I915_WRITE(reg, val);
 228
 229         mmiowb();
 230         for (i = 0; i < len; i += 4) {
 231                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 232                 data++;
 233         }
 234         /* Write every possible data byte to force correct ECC calculation. */
 235         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 236                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 237         mmiowb();
 238
 239         val |= g4x_infoframe_enable(type);
 240         val &= ~VIDEO_DIP_FREQ_MASK;
 241         val |= VIDEO_DIP_FREQ_VSYNC;
 242
 243         I915_WRITE(reg, val);
 244         POSTING_READ(reg);
 245 }
 246
 247 static void vlv_write_infoframe(struct drm_encoder *encoder,
 248                                 enum hdmi_infoframe_type type,
 249                                 const uint8_t *frame, ssize_t len)
 250 {
 251         uint32_t *data = (uint32_t *)frame;
 252         struct drm_device *dev = encoder->dev;
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 255         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 256         u32 val = I915_READ(reg);
 257
 258         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 259
 260         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 261         val |= g4x_infoframe_index(type);
 262
 263         val &= ~g4x_infoframe_enable(type);
 264
 265         I915_WRITE(reg, val);
 266
 267         mmiowb();
 268         for (i = 0; i < len; i += 4) {
 269                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 270                 data++;
 271         }
 272         /* Write every possible data byte to force correct ECC calculation. */
 273         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 274                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 275         mmiowb();
 276
 277         val |= g4x_infoframe_enable(type);
 278         val &= ~VIDEO_DIP_FREQ_MASK;
 279         val |= VIDEO_DIP_FREQ_VSYNC;
 280
 281         I915_WRITE(reg, val);
 282         POSTING_READ(reg);
 283 }
 284
 285 static void hsw_write_infoframe(struct drm_encoder *encoder,
 286                                 enum hdmi_infoframe_type type,
 287                                 const uint8_t *frame, ssize_t len)
 288 {
 289         uint32_t *data = (uint32_t *)frame;
 290         struct drm_device *dev = encoder->dev;
 291         struct drm_i915_private *dev_priv = dev->dev_private;
 292         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 293         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 294         u32 data_reg;
 295         int i;
 296         u32 val = I915_READ(ctl_reg);
 297
 298         data_reg = hsw_infoframe_data_reg(type,
 299                                           intel_crtc->config.cpu_transcoder);
 300         if (data_reg == 0)
 301                 return;
 302
 303         val &= ~hsw_infoframe_enable(type);
 304         I915_WRITE(ctl_reg, val);
 305
 306         mmiowb();
 307         for (i = 0; i < len; i += 4) {
 308                 I915_WRITE(data_reg + i, *data);
 309                 data++;
 310         }
 311         /* Write every possible data byte to force correct ECC calculation. */
 312         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 313                 I915_WRITE(data_reg + i, 0);
 314         mmiowb();
 315
 316         val |= hsw_infoframe_enable(type);
 317         I915_WRITE(ctl_reg, val);
 318         POSTING_READ(ctl_reg);
 319 }
 320
 321 /*
 322  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 323  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 324  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 325  * used for both technologies.
 326  *
 327  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 328  * DW1:       DB3       | DB2 | DB1 | DB0
 329  * DW2:       DB7       | DB6 | DB5 | DB4
 330  * DW3: ...
 331  *
 332  * (HB is Header Byte, DB is Data Byte)
 333  *
 334  * The hdmi pack() functions don't know about that hardware specific hole so we
 335  * trick them by giving an offset into the buffer and moving back the header
 336  * bytes by one.
 337  */
 338 static void intel_write_infoframe(struct drm_encoder *encoder,
 339                                   union hdmi_infoframe *frame)
 340 {
 341         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 342         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 343         ssize_t len;
 344
 345         /* see comment above for the reason for this offset */
 346         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 347         if (len < 0)
 348                 return;
 349
 350         /* Insert the 'hole' (see big comment above) at position 3 */
 351         buffer[0] = buffer[1];
 352         buffer[1] = buffer[2];
 353         buffer[2] = buffer[3];
 354         buffer[3] = 0;
 355         len++;
 356
 357         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 358 }
 359
 360 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 361                                          struct drm_display_mode *adjusted_mode)
 362 {
 363         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 364         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 365         union hdmi_infoframe frame;
 366         int ret;
 367
 368         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 369                                                        adjusted_mode);
 370         if (ret < 0) {
 371                 DRM_ERROR("couldn't fill AVI infoframe\n");
 372                 return;
 373         }
 374
 375         if (intel_hdmi->rgb_quant_range_selectable) {
 376                 if (intel_crtc->config.limited_color_range)
 377                         frame.avi.quantization_range =
 378                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 379                 else
 380                         frame.avi.quantization_range =
 381                                 HDMI_QUANTIZATION_RANGE_FULL;
 382         }
 383
 384         intel_write_infoframe(encoder, &frame);
 385 }
 386
 387 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 388 {
 389         union hdmi_infoframe frame;
 390         int ret;
 391
 392         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 393         if (ret < 0) {
 394                 DRM_ERROR("couldn't fill SPD infoframe\n");
 395                 return;
 396         }
 397
 398         frame.spd.sdi = HDMI_SPD_SDI_PC;
 399
 400         intel_write_infoframe(encoder, &frame);
 401 }
 402
 403 static void
 404 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
 405                               struct drm_display_mode *adjusted_mode)
 406 {
 407         union hdmi_infoframe frame;
 408         int ret;
 409
 410         ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 411                                                           adjusted_mode);
 412         if (ret < 0)
 413                 return;
 414
 415         intel_write_infoframe(encoder, &frame);
 416 }
 417
 418 static void g4x_set_infoframes(struct drm_encoder *encoder,
 419                                struct drm_display_mode *adjusted_mode)
 420 {
 421         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 422         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 423         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 424         u32 reg = VIDEO_DIP_CTL;
 425         u32 val = I915_READ(reg);
 426         u32 port;
 427
 428         assert_hdmi_port_disabled(intel_hdmi);
 429
 430         /* If the registers were not initialized yet, they might be zeroes,
 431          * which means we're selecting the AVI DIP and we're setting its
 432          * frequency to once. This seems to really confuse the HW and make
 433          * things stop working (the register spec says the AVI always needs to
 434          * be sent every VSync). So here we avoid writing to the register more
 435          * than we need and also explicitly select the AVI DIP and explicitly
 436          * set its frequency to every VSync. Avoiding to write it twice seems to
 437          * be enough to solve the problem, but being defensive shouldn't hurt us
 438          * either. */
 439         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 440
 441         if (!intel_hdmi->has_hdmi_sink) {
 442                 if (!(val & VIDEO_DIP_ENABLE))
 443                         return;
 444                 val &= ~VIDEO_DIP_ENABLE;
 445                 I915_WRITE(reg, val);
 446                 POSTING_READ(reg);
 447                 return;
 448         }
 449
 450         switch (intel_dig_port->port) {
 451         case PORT_B:
 452                 port = VIDEO_DIP_PORT_B;
 453                 break;
 454         case PORT_C:
 455                 port = VIDEO_DIP_PORT_C;
 456                 break;
 457         default:
 458                 BUG();
 459                 return;
 460         }
 461
 462         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 463                 if (val & VIDEO_DIP_ENABLE) {
 464                         val &= ~VIDEO_DIP_ENABLE;
 465                         I915_WRITE(reg, val);
 466                         POSTING_READ(reg);
 467                 }
 468                 val &= ~VIDEO_DIP_PORT_MASK;
 469                 val |= port;
 470         }
 471
 472         val |= VIDEO_DIP_ENABLE;
 473         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 474
 475         I915_WRITE(reg, val);
 476         POSTING_READ(reg);
 477
 478         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 479         intel_hdmi_set_spd_infoframe(encoder);
 480         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 481 }
 482
 483 static void ibx_set_infoframes(struct drm_encoder *encoder,
 484                                struct drm_display_mode *adjusted_mode)
 485 {
 486         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 487         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 488         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 489         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 490         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 491         u32 val = I915_READ(reg);
 492         u32 port;
 493
 494         assert_hdmi_port_disabled(intel_hdmi);
 495
 496         /* See the big comment in g4x_set_infoframes() */
 497         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 498
 499         if (!intel_hdmi->has_hdmi_sink) {
 500                 if (!(val & VIDEO_DIP_ENABLE))
 501                         return;
 502                 val &= ~VIDEO_DIP_ENABLE;
 503                 I915_WRITE(reg, val);
 504                 POSTING_READ(reg);
 505                 return;
 506         }
 507
 508         switch (intel_dig_port->port) {
 509         case PORT_B:
 510                 port = VIDEO_DIP_PORT_B;
 511                 break;
 512         case PORT_C:
 513                 port = VIDEO_DIP_PORT_C;
 514                 break;
 515         case PORT_D:
 516                 port = VIDEO_DIP_PORT_D;
 517                 break;
 518         default:
 519                 BUG();
 520                 return;
 521         }
 522
 523         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 524                 if (val & VIDEO_DIP_ENABLE) {
 525                         val &= ~VIDEO_DIP_ENABLE;
 526                         I915_WRITE(reg, val);
 527                         POSTING_READ(reg);
 528                 }
 529                 val &= ~VIDEO_DIP_PORT_MASK;
 530                 val |= port;
 531         }
 532
 533         val |= VIDEO_DIP_ENABLE;
 534         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 535                  VIDEO_DIP_ENABLE_GCP);
 536
 537         I915_WRITE(reg, val);
 538         POSTING_READ(reg);
 539
 540         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 541         intel_hdmi_set_spd_infoframe(encoder);
 542         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 543 }
 544
 545 static void cpt_set_infoframes(struct drm_encoder *encoder,
 546                                struct drm_display_mode *adjusted_mode)
 547 {
 548         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 549         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 550         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 551         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 552         u32 val = I915_READ(reg);
 553
 554         assert_hdmi_port_disabled(intel_hdmi);
 555
 556         /* See the big comment in g4x_set_infoframes() */
 557         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 558
 559         if (!intel_hdmi->has_hdmi_sink) {
 560                 if (!(val & VIDEO_DIP_ENABLE))
 561                         return;
 562                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 563                 I915_WRITE(reg, val);
 564                 POSTING_READ(reg);
 565                 return;
 566         }
 567
 568         /* Set both together, unset both together: see the spec. */
 569         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 570         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 571                  VIDEO_DIP_ENABLE_GCP);
 572
 573         I915_WRITE(reg, val);
 574         POSTING_READ(reg);
 575
 576         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 577         intel_hdmi_set_spd_infoframe(encoder);
 578         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 579 }
 580
 581 static void vlv_set_infoframes(struct drm_encoder *encoder,
 582                                struct drm_display_mode *adjusted_mode)
 583 {
 584         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 585         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 586         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 587         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 588         u32 val = I915_READ(reg);
 589
 590         assert_hdmi_port_disabled(intel_hdmi);
 591
 592         /* See the big comment in g4x_set_infoframes() */
 593         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 594
 595         if (!intel_hdmi->has_hdmi_sink) {
 596                 if (!(val & VIDEO_DIP_ENABLE))
 597                         return;
 598                 val &= ~VIDEO_DIP_ENABLE;
 599                 I915_WRITE(reg, val);
 600                 POSTING_READ(reg);
 601                 return;
 602         }
 603
 604         val |= VIDEO_DIP_ENABLE;
 605         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 606                  VIDEO_DIP_ENABLE_GCP);
 607
 608         I915_WRITE(reg, val);
 609         POSTING_READ(reg);
 610
 611         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 612         intel_hdmi_set_spd_infoframe(encoder);
 613         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 614 }
 615
 616 static void hsw_set_infoframes(struct drm_encoder *encoder,
 617                                struct drm_display_mode *adjusted_mode)
 618 {
 619         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 620         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 621         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 622         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 623         u32 val = I915_READ(reg);
 624
 625         assert_hdmi_port_disabled(intel_hdmi);
 626
 627         if (!intel_hdmi->has_hdmi_sink) {
 628                 I915_WRITE(reg, 0);
 629                 POSTING_READ(reg);
 630                 return;
 631         }
 632
 633         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 634                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 635
 636         I915_WRITE(reg, val);
 637         POSTING_READ(reg);
 638
 639         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 640         intel_hdmi_set_spd_infoframe(encoder);
 641         intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
 642 }
 643
 644 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 645 {
 646         struct drm_device *dev = encoder->base.dev;
 647         struct drm_i915_private *dev_priv = dev->dev_private;
 648         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 649         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 650         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 651         u32 hdmi_val;
 652
 653         hdmi_val = SDVO_ENCODING_HDMI;
 654         if (!HAS_PCH_SPLIT(dev))
 655                 hdmi_val |= intel_hdmi->color_range;
 656         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 657                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 658         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 659                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 660
 661         if (crtc->config.pipe_bpp > 24)
 662                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 663         else
 664                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 665
 666         /* Required on CPT */
 667         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 668                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 669
 670         if (intel_hdmi->has_audio) {
 671                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 672                                  pipe_name(crtc->pipe));
 673                 hdmi_val |= SDVO_AUDIO_ENABLE;
 674                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 675                 intel_write_eld(&encoder->base, adjusted_mode);
 676         }
 677
 678         if (HAS_PCH_CPT(dev))
 679                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 680         else
 681                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 682
 683         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 684         POSTING_READ(intel_hdmi->hdmi_reg);
 685
 686         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
 687 }
 688
 689 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 690                                     enum pipe *pipe)
 691 {
 692         struct drm_device *dev = encoder->base.dev;
 693         struct drm_i915_private *dev_priv = dev->dev_private;
 694         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 695         u32 tmp;
 696
 697         tmp = I915_READ(intel_hdmi->hdmi_reg);
 698
 699         if (!(tmp & SDVO_ENABLE))
 700                 return false;
 701
 702         if (HAS_PCH_CPT(dev))
 703                 *pipe = PORT_TO_PIPE_CPT(tmp);
 704         else
 705                 *pipe = PORT_TO_PIPE(tmp);
 706
 707         return true;
 708 }
 709
 710 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 711                                   struct intel_crtc_config *pipe_config)
 712 {
 713         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 714         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 715         u32 tmp, flags = 0;
 716         int dotclock;
 717
 718         tmp = I915_READ(intel_hdmi->hdmi_reg);
 719
 720         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 721                 flags |= DRM_MODE_FLAG_PHSYNC;
 722         else
 723                 flags |= DRM_MODE_FLAG_NHSYNC;
 724
 725         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 726                 flags |= DRM_MODE_FLAG_PVSYNC;
 727         else
 728                 flags |= DRM_MODE_FLAG_NVSYNC;
 729
 730         pipe_config->adjusted_mode.flags |= flags;
 731
 732         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
 733                 dotclock = pipe_config->port_clock * 2 / 3;
 734         else
 735                 dotclock = pipe_config->port_clock;
 736
 737         if (HAS_PCH_SPLIT(dev_priv->dev))
 738                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
 739
 740         pipe_config->adjusted_mode.crtc_clock = dotclock;
 741 }
 742
 743 static void intel_enable_hdmi(struct intel_encoder *encoder)
 744 {
 745         struct drm_device *dev = encoder->base.dev;
 746         struct drm_i915_private *dev_priv = dev->dev_private;
 747         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 748         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 749         u32 temp;
 750         u32 enable_bits = SDVO_ENABLE;
 751
 752         if (intel_hdmi->has_audio)
 753                 enable_bits |= SDVO_AUDIO_ENABLE;
 754
 755         temp = I915_READ(intel_hdmi->hdmi_reg);
 756
 757         /* HW workaround for IBX, we need to move the port to transcoder A
 758          * before disabling it, so restore the transcoder select bit here. */
 759         if (HAS_PCH_IBX(dev))
 760                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 761
 762         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 763          * we do this anyway which shows more stable in testing.
 764          */
 765         if (HAS_PCH_SPLIT(dev)) {
 766                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 767                 POSTING_READ(intel_hdmi->hdmi_reg);
 768         }
 769
 770         temp |= enable_bits;
 771
 772         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 773         POSTING_READ(intel_hdmi->hdmi_reg);
 774
 775         /* HW workaround, need to write this twice for issue that may result
 776          * in first write getting masked.
 777          */
 778         if (HAS_PCH_SPLIT(dev)) {
 779                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 780                 POSTING_READ(intel_hdmi->hdmi_reg);
 781         }
 782 }
 783
 784 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 785 {
 786 }
 787
 788 static void intel_disable_hdmi(struct intel_encoder *encoder)
 789 {
 790         struct drm_device *dev = encoder->base.dev;
 791         struct drm_i915_private *dev_priv = dev->dev_private;
 792         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 793         u32 temp;
 794         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 795
 796         temp = I915_READ(intel_hdmi->hdmi_reg);
 797
 798         /* HW workaround for IBX, we need to move the port to transcoder A
 799          * before disabling it. */
 800         if (HAS_PCH_IBX(dev)) {
 801                 struct drm_crtc *crtc = encoder->base.crtc;
 802                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 803
 804                 if (temp & SDVO_PIPE_B_SELECT) {
 805                         temp &= ~SDVO_PIPE_B_SELECT;
 806                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 807                         POSTING_READ(intel_hdmi->hdmi_reg);
 808
 809                         /* Again we need to write this twice. */
 810                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 811                         POSTING_READ(intel_hdmi->hdmi_reg);
 812
 813                         /* Transcoder selection bits only update
 814                          * effectively on vblank. */
 815                         if (crtc)
 816                                 intel_wait_for_vblank(dev, pipe);
 817                         else
 818                                 msleep(50);
 819                 }
 820         }
 821
 822         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 823          * we do this anyway which shows more stable in testing.
 824          */
 825         if (HAS_PCH_SPLIT(dev)) {
 826                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 827                 POSTING_READ(intel_hdmi->hdmi_reg);
 828         }
 829
 830         temp &= ~enable_bits;
 831
 832         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 833         POSTING_READ(intel_hdmi->hdmi_reg);
 834
 835         /* HW workaround, need to write this twice for issue that may result
 836          * in first write getting masked.
 837          */
 838         if (HAS_PCH_SPLIT(dev)) {
 839                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 840                 POSTING_READ(intel_hdmi->hdmi_reg);
 841         }
 842 }
 843
 844 static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
 845 {
 846         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
 847
 848         if (IS_G4X(dev))
 849                 return 165000;
 850         else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
 851                 return 300000;
 852         else
 853                 return 225000;
 854 }
 855
 856 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 857                                  struct drm_display_mode *mode)
 858 {
 859         if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
 860                 return MODE_CLOCK_HIGH;
 861         if (mode->clock < 20000)
 862                 return MODE_CLOCK_LOW;
 863
 864         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 865                 return MODE_NO_DBLESCAN;
 866
 867         return MODE_OK;
 868 }
 869
 870 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 871                                struct intel_crtc_config *pipe_config)
 872 {
 873         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 874         struct drm_device *dev = encoder->base.dev;
 875         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 876         int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
 877         int portclock_limit = hdmi_portclock_limit(intel_hdmi);
 878         int desired_bpp;
 879
 880         if (intel_hdmi->color_range_auto) {
 881                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 882                 if (intel_hdmi->has_hdmi_sink &&
 883                     drm_match_cea_mode(adjusted_mode) > 1)
 884                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 885                 else
 886                         intel_hdmi->color_range = 0;
 887         }
 888
 889         if (intel_hdmi->color_range)
 890                 pipe_config->limited_color_range = true;
 891
 892         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 893                 pipe_config->has_pch_encoder = true;
 894
 895         /*
 896          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 897          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 898          * outputs. We also need to check that the higher clock still fits
 899          * within limits.
 900          */
 901         if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
 902             && HAS_PCH_SPLIT(dev)) {
 903                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 904                 desired_bpp = 12*3;
 905
 906                 /* Need to adjust the port link by 1.5x for 12bpc. */
 907                 pipe_config->port_clock = clock_12bpc;
 908         } else {
 909                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 910                 desired_bpp = 8*3;
 911         }
 912
 913         if (!pipe_config->bw_constrained) {
 914                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 915                 pipe_config->pipe_bpp = desired_bpp;
 916         }
 917
 918         if (adjusted_mode->crtc_clock > portclock_limit) {
 919                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 920                 return false;
 921         }
 922
 923         return true;
 924 }
 925
 926 static enum drm_connector_status
 927 intel_hdmi_detect(struct drm_connector *connector, bool force)
 928 {
 929         struct drm_device *dev = connector->dev;
 930         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 931         struct intel_digital_port *intel_dig_port =
 932                 hdmi_to_dig_port(intel_hdmi);
 933         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         struct edid *edid;
 936         enum drm_connector_status status = connector_status_disconnected;
 937
 938         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 939                       connector->base.id, drm_get_connector_name(connector));
 940
 941         intel_hdmi->has_hdmi_sink = false;
 942         intel_hdmi->has_audio = false;
 943         intel_hdmi->rgb_quant_range_selectable = false;
 944         edid = drm_get_edid(connector,
 945                             intel_gmbus_get_adapter(dev_priv,
 946                                                     intel_hdmi->ddc_bus));
 947
 948         if (edid) {
 949                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 950                         status = connector_status_connected;
 951                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 952                                 intel_hdmi->has_hdmi_sink =
 953                                                 drm_detect_hdmi_monitor(edid);
 954                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 955                         intel_hdmi->rgb_quant_range_selectable =
 956                                 drm_rgb_quant_range_selectable(edid);
 957                 }
 958                 kfree(edid);
 959         }
 960
 961         if (status == connector_status_connected) {
 962                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 963                         intel_hdmi->has_audio =
 964                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 965                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 966         }
 967
 968         return status;
 969 }
 970
 971 static int intel_hdmi_get_modes(struct drm_connector *connector)
 972 {
 973         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 974         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 975
 976         /* We should parse the EDID data and find out if it's an HDMI sink so
 977          * we can send audio to it.
 978          */
 979
 980         return intel_ddc_get_modes(connector,
 981                                    intel_gmbus_get_adapter(dev_priv,
 982                                                            intel_hdmi->ddc_bus));
 983 }
 984
 985 static bool
 986 intel_hdmi_detect_audio(struct drm_connector *connector)
 987 {
 988         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 989         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 990         struct edid *edid;
 991         bool has_audio = false;
 992
 993         edid = drm_get_edid(connector,
 994                             intel_gmbus_get_adapter(dev_priv,
 995                                                     intel_hdmi->ddc_bus));
 996         if (edid) {
 997                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 998                         has_audio = drm_detect_monitor_audio(edid);
 999                 kfree(edid);
1000         }
1001
1002         return has_audio;
1003 }
1004
1005 static int
1006 intel_hdmi_set_property(struct drm_connector *connector,
1007                         struct drm_property *property,
1008                         uint64_t val)
1009 {
1010         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1011         struct intel_digital_port *intel_dig_port =
1012                 hdmi_to_dig_port(intel_hdmi);
1013         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1014         int ret;
1015
1016         ret = drm_object_property_set_value(&connector->base, property, val);
1017         if (ret)
1018                 return ret;
1019
1020         if (property == dev_priv->force_audio_property) {
1021                 enum hdmi_force_audio i = val;
1022                 bool has_audio;
1023
1024                 if (i == intel_hdmi->force_audio)
1025                         return 0;
1026
1027                 intel_hdmi->force_audio = i;
1028
1029                 if (i == HDMI_AUDIO_AUTO)
1030                         has_audio = intel_hdmi_detect_audio(connector);
1031                 else
1032                         has_audio = (i == HDMI_AUDIO_ON);
1033
1034                 if (i == HDMI_AUDIO_OFF_DVI)
1035                         intel_hdmi->has_hdmi_sink = 0;
1036
1037                 intel_hdmi->has_audio = has_audio;
1038                 goto done;
1039         }
1040
1041         if (property == dev_priv->broadcast_rgb_property) {
1042                 bool old_auto = intel_hdmi->color_range_auto;
1043                 uint32_t old_range = intel_hdmi->color_range;
1044
1045                 switch (val) {
1046                 case INTEL_BROADCAST_RGB_AUTO:
1047                         intel_hdmi->color_range_auto = true;
1048                         break;
1049                 case INTEL_BROADCAST_RGB_FULL:
1050                         intel_hdmi->color_range_auto = false;
1051                         intel_hdmi->color_range = 0;
1052                         break;
1053                 case INTEL_BROADCAST_RGB_LIMITED:
1054                         intel_hdmi->color_range_auto = false;
1055                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1056                         break;
1057                 default:
1058                         return -EINVAL;
1059                 }
1060
1061                 if (old_auto == intel_hdmi->color_range_auto &&
1062                     old_range == intel_hdmi->color_range)
1063                         return 0;
1064
1065                 goto done;
1066         }
1067
1068         return -EINVAL;
1069
1070 done:
1071         if (intel_dig_port->base.base.crtc)
1072                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1073
1074         return 0;
1075 }
1076
1077 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1078 {
1079         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1080         struct drm_device *dev = encoder->base.dev;
1081         struct drm_i915_private *dev_priv = dev->dev_private;
1082         struct intel_crtc *intel_crtc =
1083                 to_intel_crtc(encoder->base.crtc);
1084         int port = vlv_dport_to_channel(dport);
1085         int pipe = intel_crtc->pipe;
1086         u32 val;
1087
1088         if (!IS_VALLEYVIEW(dev))
1089                 return;
1090
1091         /* Enable clock channels for this port */
1092         mutex_lock(&dev_priv->dpio_lock);
1093         val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
1094         val = 0;
1095         if (pipe)
1096                 val |= (1<<21);
1097         else
1098                 val &= ~(1<<21);
1099         val |= 0x001000c4;
1100         vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1101
1102         /* HDMI 1.0V-2dB */
1103         vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0);
1104         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port),
1105                          0x2b245f5f);
1106         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
1107                          0x5578b83a);
1108         vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port),
1109                          0x0c782040);
1110         vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port),
1111                          0x2b247878);
1112         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
1113         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
1114                          0x00002000);
1115         vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
1116                          DPIO_TX_OCALINIT_EN);
1117
1118         /* Program lane clock */
1119         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port),
1120                          0x00760018);
1121         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
1122                          0x00400888);
1123         mutex_unlock(&dev_priv->dpio_lock);
1124
1125         intel_enable_hdmi(encoder);
1126
1127         vlv_wait_port_ready(dev_priv, port);
1128 }
1129
1130 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1131 {
1132         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1133         struct drm_device *dev = encoder->base.dev;
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         struct intel_crtc *intel_crtc =
1136                 to_intel_crtc(encoder->base.crtc);
1137         int port = vlv_dport_to_channel(dport);
1138         int pipe = intel_crtc->pipe;
1139
1140         if (!IS_VALLEYVIEW(dev))
1141                 return;
1142
1143         /* Program Tx lane resets to default */
1144         mutex_lock(&dev_priv->dpio_lock);
1145         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
1146                          DPIO_PCS_TX_LANE2_RESET |
1147                          DPIO_PCS_TX_LANE1_RESET);
1148         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
1149                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1150                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1151                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1152                          DPIO_PCS_CLK_SOFT_RESET);
1153
1154         /* Fix up inter-pair skew failure */
1155         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1156         vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1157         vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
1158
1159         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
1160                          0x00002000);
1161         vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
1162                          DPIO_TX_OCALINIT_EN);
1163         mutex_unlock(&dev_priv->dpio_lock);
1164 }
1165
1166 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1167 {
1168         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1169         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1170         struct intel_crtc *intel_crtc =
1171                 to_intel_crtc(encoder->base.crtc);
1172         int port = vlv_dport_to_channel(dport);
1173         int pipe = intel_crtc->pipe;
1174
1175         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1176         mutex_lock(&dev_priv->dpio_lock);
1177         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000);
1178         vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060);
1179         mutex_unlock(&dev_priv->dpio_lock);
1180 }
1181
1182 static void intel_hdmi_destroy(struct drm_connector *connector)
1183 {
1184         drm_connector_cleanup(connector);
1185         kfree(connector);
1186 }
1187
1188 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1189         .dpms = intel_connector_dpms,
1190         .detect = intel_hdmi_detect,
1191         .fill_modes = drm_helper_probe_single_connector_modes,
1192         .set_property = intel_hdmi_set_property,
1193         .destroy = intel_hdmi_destroy,
1194 };
1195
1196 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1197         .get_modes = intel_hdmi_get_modes,
1198         .mode_valid = intel_hdmi_mode_valid,
1199         .best_encoder = intel_best_encoder,
1200 };
1201
1202 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1203         .destroy = intel_encoder_destroy,
1204 };
1205
1206 static void
1207 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1208 {
1209         intel_attach_force_audio_property(connector);
1210         intel_attach_broadcast_rgb_property(connector);
1211         intel_hdmi->color_range_auto = true;
1212 }
1213
1214 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1215                                struct intel_connector *intel_connector)
1216 {
1217         struct drm_connector *connector = &intel_connector->base;
1218         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1219         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1220         struct drm_device *dev = intel_encoder->base.dev;
1221         struct drm_i915_private *dev_priv = dev->dev_private;
1222         enum port port = intel_dig_port->port;
1223
1224         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1225                            DRM_MODE_CONNECTOR_HDMIA);
1226         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1227
1228         connector->interlace_allowed = 1;
1229         connector->doublescan_allowed = 0;
1230         connector->stereo_allowed = 1;
1231
1232         switch (port) {
1233         case PORT_B:
1234                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1235                 intel_encoder->hpd_pin = HPD_PORT_B;
1236                 break;
1237         case PORT_C:
1238                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1239                 intel_encoder->hpd_pin = HPD_PORT_C;
1240                 break;
1241         case PORT_D:
1242                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1243                 intel_encoder->hpd_pin = HPD_PORT_D;
1244                 break;
1245         case PORT_A:
1246                 intel_encoder->hpd_pin = HPD_PORT_A;
1247                 /* Internal port only for eDP. */
1248         default:
1249                 BUG();
1250         }
1251
1252         if (IS_VALLEYVIEW(dev)) {
1253                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1254                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1255         } else if (!HAS_PCH_SPLIT(dev)) {
1256                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1257                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1258         } else if (HAS_DDI(dev)) {
1259                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1260                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1261         } else if (HAS_PCH_IBX(dev)) {
1262                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1263                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1264         } else {
1265                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1266                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1267         }
1268
1269         if (HAS_DDI(dev))
1270                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1271         else
1272                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1273
1274         intel_hdmi_add_properties(intel_hdmi, connector);
1275
1276         intel_connector_attach_encoder(intel_connector, intel_encoder);
1277         drm_sysfs_connector_add(connector);
1278
1279         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1280          * 0xd.  Failure to do so will result in spurious interrupts being
1281          * generated on the port when a cable is not attached.
1282          */
1283         if (IS_G4X(dev) && !IS_GM45(dev)) {
1284                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1285                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1286         }
1287 }
1288
1289 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1290 {
1291         struct intel_digital_port *intel_dig_port;
1292         struct intel_encoder *intel_encoder;
1293         struct intel_connector *intel_connector;
1294
1295         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1296         if (!intel_dig_port)
1297                 return;
1298
1299         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1300         if (!intel_connector) {
1301                 kfree(intel_dig_port);
1302                 return;
1303         }
1304
1305         intel_encoder = &intel_dig_port->base;
1306
1307         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1308                          DRM_MODE_ENCODER_TMDS);
1309
1310         intel_encoder->compute_config = intel_hdmi_compute_config;
1311         intel_encoder->mode_set = intel_hdmi_mode_set;
1312         intel_encoder->disable = intel_disable_hdmi;
1313         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1314         intel_encoder->get_config = intel_hdmi_get_config;
1315         if (IS_VALLEYVIEW(dev)) {
1316                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
1317                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1318                 intel_encoder->enable = vlv_enable_hdmi;
1319                 intel_encoder->post_disable = vlv_hdmi_post_disable;
1320         } else {
1321                 intel_encoder->enable = intel_enable_hdmi;
1322         }
1323
1324         intel_encoder->type = INTEL_OUTPUT_HDMI;
1325         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1326         intel_encoder->cloneable = false;
1327
1328         intel_dig_port->port = port;
1329         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1330         intel_dig_port->dp.output_reg = 0;
1331
1332         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1333 }