Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 static void intel_increase_pllclock(struct drm_crtc *crtc);
  45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  46
  47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  48                                 struct intel_crtc_config *pipe_config);
  49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  50                                    struct intel_crtc_config *pipe_config);
  51
  52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
  53                           int x, int y, struct drm_framebuffer *old_fb);
  54
  55
  56 typedef struct {
  57         int     min, max;
  58 } intel_range_t;
  59
  60 typedef struct {
  61         int     dot_limit;
  62         int     p2_slow, p2_fast;
  63 } intel_p2_t;
  64
  65 typedef struct intel_limit intel_limit_t;
  66 struct intel_limit {
  67         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  68         intel_p2_t          p2;
  69 };
  70
  71 int
  72 intel_pch_rawclk(struct drm_device *dev)
  73 {
  74         struct drm_i915_private *dev_priv = dev->dev_private;
  75
  76         WARN_ON(!HAS_PCH_SPLIT(dev));
  77
  78         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79 }
  80
  81 static inline u32 /* units of 100MHz */
  82 intel_fdi_link_freq(struct drm_device *dev)
  83 {
  84         if (IS_GEN5(dev)) {
  85                 struct drm_i915_private *dev_priv = dev->dev_private;
  86                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  87         } else
  88                 return 27;
  89 }
  90
  91 static const intel_limit_t intel_limits_i8xx_dac = {
  92         .dot = { .min = 25000, .max = 350000 },
  93         .vco = { .min = 930000, .max = 1400000 },
  94         .n = { .min = 3, .max = 16 },
  95         .m = { .min = 96, .max = 140 },
  96         .m1 = { .min = 18, .max = 26 },
  97         .m2 = { .min = 6, .max = 16 },
  98         .p = { .min = 4, .max = 128 },
  99         .p1 = { .min = 2, .max = 33 },
 100         .p2 = { .dot_limit = 165000,
 101                 .p2_slow = 4, .p2_fast = 2 },
 102 };
 103
 104 static const intel_limit_t intel_limits_i8xx_dvo = {
 105         .dot = { .min = 25000, .max = 350000 },
 106         .vco = { .min = 930000, .max = 1400000 },
 107         .n = { .min = 3, .max = 16 },
 108         .m = { .min = 96, .max = 140 },
 109         .m1 = { .min = 18, .max = 26 },
 110         .m2 = { .min = 6, .max = 16 },
 111         .p = { .min = 4, .max = 128 },
 112         .p1 = { .min = 2, .max = 33 },
 113         .p2 = { .dot_limit = 165000,
 114                 .p2_slow = 4, .p2_fast = 4 },
 115 };
 116
 117 static const intel_limit_t intel_limits_i8xx_lvds = {
 118         .dot = { .min = 25000, .max = 350000 },
 119         .vco = { .min = 930000, .max = 1400000 },
 120         .n = { .min = 3, .max = 16 },
 121         .m = { .min = 96, .max = 140 },
 122         .m1 = { .min = 18, .max = 26 },
 123         .m2 = { .min = 6, .max = 16 },
 124         .p = { .min = 4, .max = 128 },
 125         .p1 = { .min = 1, .max = 6 },
 126         .p2 = { .dot_limit = 165000,
 127                 .p2_slow = 14, .p2_fast = 7 },
 128 };
 129
 130 static const intel_limit_t intel_limits_i9xx_sdvo = {
 131         .dot = { .min = 20000, .max = 400000 },
 132         .vco = { .min = 1400000, .max = 2800000 },
 133         .n = { .min = 1, .max = 6 },
 134         .m = { .min = 70, .max = 120 },
 135         .m1 = { .min = 8, .max = 18 },
 136         .m2 = { .min = 3, .max = 7 },
 137         .p = { .min = 5, .max = 80 },
 138         .p1 = { .min = 1, .max = 8 },
 139         .p2 = { .dot_limit = 200000,
 140                 .p2_slow = 10, .p2_fast = 5 },
 141 };
 142
 143 static const intel_limit_t intel_limits_i9xx_lvds = {
 144         .dot = { .min = 20000, .max = 400000 },
 145         .vco = { .min = 1400000, .max = 2800000 },
 146         .n = { .min = 1, .max = 6 },
 147         .m = { .min = 70, .max = 120 },
 148         .m1 = { .min = 8, .max = 18 },
 149         .m2 = { .min = 3, .max = 7 },
 150         .p = { .min = 7, .max = 98 },
 151         .p1 = { .min = 1, .max = 8 },
 152         .p2 = { .dot_limit = 112000,
 153                 .p2_slow = 14, .p2_fast = 7 },
 154 };
 155
 156
 157 static const intel_limit_t intel_limits_g4x_sdvo = {
 158         .dot = { .min = 25000, .max = 270000 },
 159         .vco = { .min = 1750000, .max = 3500000},
 160         .n = { .min = 1, .max = 4 },
 161         .m = { .min = 104, .max = 138 },
 162         .m1 = { .min = 17, .max = 23 },
 163         .m2 = { .min = 5, .max = 11 },
 164         .p = { .min = 10, .max = 30 },
 165         .p1 = { .min = 1, .max = 3},
 166         .p2 = { .dot_limit = 270000,
 167                 .p2_slow = 10,
 168                 .p2_fast = 10
 169         },
 170 };
 171
 172 static const intel_limit_t intel_limits_g4x_hdmi = {
 173         .dot = { .min = 22000, .max = 400000 },
 174         .vco = { .min = 1750000, .max = 3500000},
 175         .n = { .min = 1, .max = 4 },
 176         .m = { .min = 104, .max = 138 },
 177         .m1 = { .min = 16, .max = 23 },
 178         .m2 = { .min = 5, .max = 11 },
 179         .p = { .min = 5, .max = 80 },
 180         .p1 = { .min = 1, .max = 8},
 181         .p2 = { .dot_limit = 165000,
 182                 .p2_slow = 10, .p2_fast = 5 },
 183 };
 184
 185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 186         .dot = { .min = 20000, .max = 115000 },
 187         .vco = { .min = 1750000, .max = 3500000 },
 188         .n = { .min = 1, .max = 3 },
 189         .m = { .min = 104, .max = 138 },
 190         .m1 = { .min = 17, .max = 23 },
 191         .m2 = { .min = 5, .max = 11 },
 192         .p = { .min = 28, .max = 112 },
 193         .p1 = { .min = 2, .max = 8 },
 194         .p2 = { .dot_limit = 0,
 195                 .p2_slow = 14, .p2_fast = 14
 196         },
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 200         .dot = { .min = 80000, .max = 224000 },
 201         .vco = { .min = 1750000, .max = 3500000 },
 202         .n = { .min = 1, .max = 3 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 17, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 14, .max = 42 },
 207         .p1 = { .min = 2, .max = 6 },
 208         .p2 = { .dot_limit = 0,
 209                 .p2_slow = 7, .p2_fast = 7
 210         },
 211 };
 212
 213 static const intel_limit_t intel_limits_pineview_sdvo = {
 214         .dot = { .min = 20000, .max = 400000},
 215         .vco = { .min = 1700000, .max = 3500000 },
 216         /* Pineview's Ncounter is a ring counter */
 217         .n = { .min = 3, .max = 6 },
 218         .m = { .min = 2, .max = 256 },
 219         /* Pineview only has one combined m divider, which we treat as m2. */
 220         .m1 = { .min = 0, .max = 0 },
 221         .m2 = { .min = 0, .max = 254 },
 222         .p = { .min = 5, .max = 80 },
 223         .p1 = { .min = 1, .max = 8 },
 224         .p2 = { .dot_limit = 200000,
 225                 .p2_slow = 10, .p2_fast = 5 },
 226 };
 227
 228 static const intel_limit_t intel_limits_pineview_lvds = {
 229         .dot = { .min = 20000, .max = 400000 },
 230         .vco = { .min = 1700000, .max = 3500000 },
 231         .n = { .min = 3, .max = 6 },
 232         .m = { .min = 2, .max = 256 },
 233         .m1 = { .min = 0, .max = 0 },
 234         .m2 = { .min = 0, .max = 254 },
 235         .p = { .min = 7, .max = 112 },
 236         .p1 = { .min = 1, .max = 8 },
 237         .p2 = { .dot_limit = 112000,
 238                 .p2_slow = 14, .p2_fast = 14 },
 239 };
 240
 241 /* Ironlake / Sandybridge
 242  *
 243  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 244  * the range value for them is (actual_value - 2).
 245  */
 246 static const intel_limit_t intel_limits_ironlake_dac = {
 247         .dot = { .min = 25000, .max = 350000 },
 248         .vco = { .min = 1760000, .max = 3510000 },
 249         .n = { .min = 1, .max = 5 },
 250         .m = { .min = 79, .max = 127 },
 251         .m1 = { .min = 12, .max = 22 },
 252         .m2 = { .min = 5, .max = 9 },
 253         .p = { .min = 5, .max = 80 },
 254         .p1 = { .min = 1, .max = 8 },
 255         .p2 = { .dot_limit = 225000,
 256                 .p2_slow = 10, .p2_fast = 5 },
 257 };
 258
 259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 260         .dot = { .min = 25000, .max = 350000 },
 261         .vco = { .min = 1760000, .max = 3510000 },
 262         .n = { .min = 1, .max = 3 },
 263         .m = { .min = 79, .max = 118 },
 264         .m1 = { .min = 12, .max = 22 },
 265         .m2 = { .min = 5, .max = 9 },
 266         .p = { .min = 28, .max = 112 },
 267         .p1 = { .min = 2, .max = 8 },
 268         .p2 = { .dot_limit = 225000,
 269                 .p2_slow = 14, .p2_fast = 14 },
 270 };
 271
 272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 273         .dot = { .min = 25000, .max = 350000 },
 274         .vco = { .min = 1760000, .max = 3510000 },
 275         .n = { .min = 1, .max = 3 },
 276         .m = { .min = 79, .max = 127 },
 277         .m1 = { .min = 12, .max = 22 },
 278         .m2 = { .min = 5, .max = 9 },
 279         .p = { .min = 14, .max = 56 },
 280         .p1 = { .min = 2, .max = 8 },
 281         .p2 = { .dot_limit = 225000,
 282                 .p2_slow = 7, .p2_fast = 7 },
 283 };
 284
 285 /* LVDS 100mhz refclk limits. */
 286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 287         .dot = { .min = 25000, .max = 350000 },
 288         .vco = { .min = 1760000, .max = 3510000 },
 289         .n = { .min = 1, .max = 2 },
 290         .m = { .min = 79, .max = 126 },
 291         .m1 = { .min = 12, .max = 22 },
 292         .m2 = { .min = 5, .max = 9 },
 293         .p = { .min = 28, .max = 112 },
 294         .p1 = { .min = 2, .max = 8 },
 295         .p2 = { .dot_limit = 225000,
 296                 .p2_slow = 14, .p2_fast = 14 },
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 126 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 42 },
 307         .p1 = { .min = 2, .max = 6 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310 };
 311
 312 static const intel_limit_t intel_limits_vlv = {
 313          /*
 314           * These are the data rate limits (measured in fast clocks)
 315           * since those are the strictest limits we have. The fast
 316           * clock and actual rate limits are more relaxed, so checking
 317           * them would make no difference.
 318           */
 319         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 320         .vco = { .min = 4000000, .max = 6000000 },
 321         .n = { .min = 1, .max = 7 },
 322         .m1 = { .min = 2, .max = 3 },
 323         .m2 = { .min = 11, .max = 156 },
 324         .p1 = { .min = 2, .max = 3 },
 325         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 326 };
 327
 328 static void vlv_clock(int refclk, intel_clock_t *clock)
 329 {
 330         clock->m = clock->m1 * clock->m2;
 331         clock->p = clock->p1 * clock->p2;
 332         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 333         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 334 }
 335
 336 /**
 337  * Returns whether any output on the specified pipe is of the specified type
 338  */
 339 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 340 {
 341         struct drm_device *dev = crtc->dev;
 342         struct intel_encoder *encoder;
 343
 344         for_each_encoder_on_crtc(dev, crtc, encoder)
 345                 if (encoder->type == type)
 346                         return true;
 347
 348         return false;
 349 }
 350
 351 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 352                                                 int refclk)
 353 {
 354         struct drm_device *dev = crtc->dev;
 355         const intel_limit_t *limit;
 356
 357         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 358                 if (intel_is_dual_link_lvds(dev)) {
 359                         if (refclk == 100000)
 360                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 361                         else
 362                                 limit = &intel_limits_ironlake_dual_lvds;
 363                 } else {
 364                         if (refclk == 100000)
 365                                 limit = &intel_limits_ironlake_single_lvds_100m;
 366                         else
 367                                 limit = &intel_limits_ironlake_single_lvds;
 368                 }
 369         } else
 370                 limit = &intel_limits_ironlake_dac;
 371
 372         return limit;
 373 }
 374
 375 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 376 {
 377         struct drm_device *dev = crtc->dev;
 378         const intel_limit_t *limit;
 379
 380         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 381                 if (intel_is_dual_link_lvds(dev))
 382                         limit = &intel_limits_g4x_dual_channel_lvds;
 383                 else
 384                         limit = &intel_limits_g4x_single_channel_lvds;
 385         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 386                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 387                 limit = &intel_limits_g4x_hdmi;
 388         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 389                 limit = &intel_limits_g4x_sdvo;
 390         } else /* The option is for other outputs */
 391                 limit = &intel_limits_i9xx_sdvo;
 392
 393         return limit;
 394 }
 395
 396 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 397 {
 398         struct drm_device *dev = crtc->dev;
 399         const intel_limit_t *limit;
 400
 401         if (HAS_PCH_SPLIT(dev))
 402                 limit = intel_ironlake_limit(crtc, refclk);
 403         else if (IS_G4X(dev)) {
 404                 limit = intel_g4x_limit(crtc);
 405         } else if (IS_PINEVIEW(dev)) {
 406                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 407                         limit = &intel_limits_pineview_lvds;
 408                 else
 409                         limit = &intel_limits_pineview_sdvo;
 410         } else if (IS_VALLEYVIEW(dev)) {
 411                 limit = &intel_limits_vlv;
 412         } else if (!IS_GEN2(dev)) {
 413                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 414                         limit = &intel_limits_i9xx_lvds;
 415                 else
 416                         limit = &intel_limits_i9xx_sdvo;
 417         } else {
 418                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 419                         limit = &intel_limits_i8xx_lvds;
 420                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
 421                         limit = &intel_limits_i8xx_dvo;
 422                 else
 423                         limit = &intel_limits_i8xx_dac;
 424         }
 425         return limit;
 426 }
 427
 428 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 429 static void pineview_clock(int refclk, intel_clock_t *clock)
 430 {
 431         clock->m = clock->m2 + 2;
 432         clock->p = clock->p1 * clock->p2;
 433         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 434         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 435 }
 436
 437 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 438 {
 439         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 440 }
 441
 442 static void i9xx_clock(int refclk, intel_clock_t *clock)
 443 {
 444         clock->m = i9xx_dpll_compute_m(clock);
 445         clock->p = clock->p1 * clock->p2;
 446         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 447         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 448 }
 449
 450 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 451 /**
 452  * Returns whether the given set of divisors are valid for a given refclk with
 453  * the given connectors.
 454  */
 455
 456 static bool intel_PLL_is_valid(struct drm_device *dev,
 457                                const intel_limit_t *limit,
 458                                const intel_clock_t *clock)
 459 {
 460         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 461                 INTELPllInvalid("n out of range\n");
 462         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 463                 INTELPllInvalid("p1 out of range\n");
 464         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 465                 INTELPllInvalid("m2 out of range\n");
 466         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 467                 INTELPllInvalid("m1 out of range\n");
 468
 469         if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
 470                 if (clock->m1 <= clock->m2)
 471                         INTELPllInvalid("m1 <= m2\n");
 472
 473         if (!IS_VALLEYVIEW(dev)) {
 474                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 475                         INTELPllInvalid("p out of range\n");
 476                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 477                         INTELPllInvalid("m out of range\n");
 478         }
 479
 480         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 481                 INTELPllInvalid("vco out of range\n");
 482         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 483          * connector, etc., rather than just a single range.
 484          */
 485         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 486                 INTELPllInvalid("dot out of range\n");
 487
 488         return true;
 489 }
 490
 491 static bool
 492 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 493                     int target, int refclk, intel_clock_t *match_clock,
 494                     intel_clock_t *best_clock)
 495 {
 496         struct drm_device *dev = crtc->dev;
 497         intel_clock_t clock;
 498         int err = target;
 499
 500         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 501                 /*
 502                  * For LVDS just rely on its current settings for dual-channel.
 503                  * We haven't figured out how to reliably set up different
 504                  * single/dual channel state, if we even can.
 505                  */
 506                 if (intel_is_dual_link_lvds(dev))
 507                         clock.p2 = limit->p2.p2_fast;
 508                 else
 509                         clock.p2 = limit->p2.p2_slow;
 510         } else {
 511                 if (target < limit->p2.dot_limit)
 512                         clock.p2 = limit->p2.p2_slow;
 513                 else
 514                         clock.p2 = limit->p2.p2_fast;
 515         }
 516
 517         memset(best_clock, 0, sizeof(*best_clock));
 518
 519         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 520              clock.m1++) {
 521                 for (clock.m2 = limit->m2.min;
 522                      clock.m2 <= limit->m2.max; clock.m2++) {
 523                         if (clock.m2 >= clock.m1)
 524                                 break;
 525                         for (clock.n = limit->n.min;
 526                              clock.n <= limit->n.max; clock.n++) {
 527                                 for (clock.p1 = limit->p1.min;
 528                                         clock.p1 <= limit->p1.max; clock.p1++) {
 529                                         int this_err;
 530
 531                                         i9xx_clock(refclk, &clock);
 532                                         if (!intel_PLL_is_valid(dev, limit,
 533                                                                 &clock))
 534                                                 continue;
 535                                         if (match_clock &&
 536                                             clock.p != match_clock->p)
 537                                                 continue;
 538
 539                                         this_err = abs(clock.dot - target);
 540                                         if (this_err < err) {
 541                                                 *best_clock = clock;
 542                                                 err = this_err;
 543                                         }
 544                                 }
 545                         }
 546                 }
 547         }
 548
 549         return (err != target);
 550 }
 551
 552 static bool
 553 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 554                    int target, int refclk, intel_clock_t *match_clock,
 555                    intel_clock_t *best_clock)
 556 {
 557         struct drm_device *dev = crtc->dev;
 558         intel_clock_t clock;
 559         int err = target;
 560
 561         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 562                 /*
 563                  * For LVDS just rely on its current settings for dual-channel.
 564                  * We haven't figured out how to reliably set up different
 565                  * single/dual channel state, if we even can.
 566                  */
 567                 if (intel_is_dual_link_lvds(dev))
 568                         clock.p2 = limit->p2.p2_fast;
 569                 else
 570                         clock.p2 = limit->p2.p2_slow;
 571         } else {
 572                 if (target < limit->p2.dot_limit)
 573                         clock.p2 = limit->p2.p2_slow;
 574                 else
 575                         clock.p2 = limit->p2.p2_fast;
 576         }
 577
 578         memset(best_clock, 0, sizeof(*best_clock));
 579
 580         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 581              clock.m1++) {
 582                 for (clock.m2 = limit->m2.min;
 583                      clock.m2 <= limit->m2.max; clock.m2++) {
 584                         for (clock.n = limit->n.min;
 585                              clock.n <= limit->n.max; clock.n++) {
 586                                 for (clock.p1 = limit->p1.min;
 587                                         clock.p1 <= limit->p1.max; clock.p1++) {
 588                                         int this_err;
 589
 590                                         pineview_clock(refclk, &clock);
 591                                         if (!intel_PLL_is_valid(dev, limit,
 592                                                                 &clock))
 593                                                 continue;
 594                                         if (match_clock &&
 595                                             clock.p != match_clock->p)
 596                                                 continue;
 597
 598                                         this_err = abs(clock.dot - target);
 599                                         if (this_err < err) {
 600                                                 *best_clock = clock;
 601                                                 err = this_err;
 602                                         }
 603                                 }
 604                         }
 605                 }
 606         }
 607
 608         return (err != target);
 609 }
 610
 611 static bool
 612 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 613                    int target, int refclk, intel_clock_t *match_clock,
 614                    intel_clock_t *best_clock)
 615 {
 616         struct drm_device *dev = crtc->dev;
 617         intel_clock_t clock;
 618         int max_n;
 619         bool found;
 620         /* approximately equals target * 0.00585 */
 621         int err_most = (target >> 8) + (target >> 9);
 622         found = false;
 623
 624         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 625                 if (intel_is_dual_link_lvds(dev))
 626                         clock.p2 = limit->p2.p2_fast;
 627                 else
 628                         clock.p2 = limit->p2.p2_slow;
 629         } else {
 630                 if (target < limit->p2.dot_limit)
 631                         clock.p2 = limit->p2.p2_slow;
 632                 else
 633                         clock.p2 = limit->p2.p2_fast;
 634         }
 635
 636         memset(best_clock, 0, sizeof(*best_clock));
 637         max_n = limit->n.max;
 638         /* based on hardware requirement, prefer smaller n to precision */
 639         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 640                 /* based on hardware requirement, prefere larger m1,m2 */
 641                 for (clock.m1 = limit->m1.max;
 642                      clock.m1 >= limit->m1.min; clock.m1--) {
 643                         for (clock.m2 = limit->m2.max;
 644                              clock.m2 >= limit->m2.min; clock.m2--) {
 645                                 for (clock.p1 = limit->p1.max;
 646                                      clock.p1 >= limit->p1.min; clock.p1--) {
 647                                         int this_err;
 648
 649                                         i9xx_clock(refclk, &clock);
 650                                         if (!intel_PLL_is_valid(dev, limit,
 651                                                                 &clock))
 652                                                 continue;
 653
 654                                         this_err = abs(clock.dot - target);
 655                                         if (this_err < err_most) {
 656                                                 *best_clock = clock;
 657                                                 err_most = this_err;
 658                                                 max_n = clock.n;
 659                                                 found = true;
 660                                         }
 661                                 }
 662                         }
 663                 }
 664         }
 665         return found;
 666 }
 667
 668 static bool
 669 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
 670                    int target, int refclk, intel_clock_t *match_clock,
 671                    intel_clock_t *best_clock)
 672 {
 673         struct drm_device *dev = crtc->dev;
 674         intel_clock_t clock;
 675         unsigned int bestppm = 1000000;
 676         /* min update 19.2 MHz */
 677         int max_n = min(limit->n.max, refclk / 19200);
 678         bool found = false;
 679
 680         target *= 5; /* fast clock */
 681
 682         memset(best_clock, 0, sizeof(*best_clock));
 683
 684         /* based on hardware requirement, prefer smaller n to precision */
 685         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 686                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 687                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 688                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 689                                 clock.p = clock.p1 * clock.p2;
 690                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 691                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 692                                         unsigned int ppm, diff;
 693
 694                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 695                                                                      refclk * clock.m1);
 696
 697                                         vlv_clock(refclk, &clock);
 698
 699                                         if (!intel_PLL_is_valid(dev, limit,
 700                                                                 &clock))
 701                                                 continue;
 702
 703                                         diff = abs(clock.dot - target);
 704                                         ppm = div_u64(1000000ULL * diff, target);
 705
 706                                         if (ppm < 100 && clock.p > best_clock->p) {
 707                                                 bestppm = 0;
 708                                                 *best_clock = clock;
 709                                                 found = true;
 710                                         }
 711
 712                                         if (bestppm >= 10 && ppm < bestppm - 10) {
 713                                                 bestppm = ppm;
 714                                                 *best_clock = clock;
 715                                                 found = true;
 716                                         }
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return found;
 723 }
 724
 725 bool intel_crtc_active(struct drm_crtc *crtc)
 726 {
 727         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 728
 729         /* Be paranoid as we can arrive here with only partial
 730          * state retrieved from the hardware during setup.
 731          *
 732          * We can ditch the adjusted_mode.crtc_clock check as soon
 733          * as Haswell has gained clock readout/fastboot support.
 734          *
 735          * We can ditch the crtc->fb check as soon as we can
 736          * properly reconstruct framebuffers.
 737          */
 738         return intel_crtc->active && crtc->fb &&
 739                 intel_crtc->config.adjusted_mode.crtc_clock;
 740 }
 741
 742 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 743                                              enum pipe pipe)
 744 {
 745         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 746         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 747
 748         return intel_crtc->config.cpu_transcoder;
 749 }
 750
 751 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 752 {
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         u32 frame, frame_reg = PIPEFRAME(pipe);
 755
 756         frame = I915_READ(frame_reg);
 757
 758         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 759                 DRM_DEBUG_KMS("vblank wait timed out\n");
 760 }
 761
 762 /**
 763  * intel_wait_for_vblank - wait for vblank on a given pipe
 764  * @dev: drm device
 765  * @pipe: pipe to wait for
 766  *
 767  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 768  * mode setting code.
 769  */
 770 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = dev->dev_private;
 773         int pipestat_reg = PIPESTAT(pipe);
 774
 775         if (INTEL_INFO(dev)->gen >= 5) {
 776                 ironlake_wait_for_vblank(dev, pipe);
 777                 return;
 778         }
 779
 780         /* Clear existing vblank status. Note this will clear any other
 781          * sticky status fields as well.
 782          *
 783          * This races with i915_driver_irq_handler() with the result
 784          * that either function could miss a vblank event.  Here it is not
 785          * fatal, as we will either wait upon the next vblank interrupt or
 786          * timeout.  Generally speaking intel_wait_for_vblank() is only
 787          * called during modeset at which time the GPU should be idle and
 788          * should *not* be performing page flips and thus not waiting on
 789          * vblanks...
 790          * Currently, the result of us stealing a vblank from the irq
 791          * handler is that a single frame will be skipped during swapbuffers.
 792          */
 793         I915_WRITE(pipestat_reg,
 794                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 795
 796         /* Wait for vblank interrupt bit to set */
 797         if (wait_for(I915_READ(pipestat_reg) &
 798                      PIPE_VBLANK_INTERRUPT_STATUS,
 799                      50))
 800                 DRM_DEBUG_KMS("vblank wait timed out\n");
 801 }
 802
 803 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
 804 {
 805         struct drm_i915_private *dev_priv = dev->dev_private;
 806         u32 reg = PIPEDSL(pipe);
 807         u32 line1, line2;
 808         u32 line_mask;
 809
 810         if (IS_GEN2(dev))
 811                 line_mask = DSL_LINEMASK_GEN2;
 812         else
 813                 line_mask = DSL_LINEMASK_GEN3;
 814
 815         line1 = I915_READ(reg) & line_mask;
 816         mdelay(5);
 817         line2 = I915_READ(reg) & line_mask;
 818
 819         return line1 == line2;
 820 }
 821
 822 /*
 823  * intel_wait_for_pipe_off - wait for pipe to turn off
 824  * @dev: drm device
 825  * @pipe: pipe to wait for
 826  *
 827  * After disabling a pipe, we can't wait for vblank in the usual way,
 828  * spinning on the vblank interrupt status bit, since we won't actually
 829  * see an interrupt when the pipe is disabled.
 830  *
 831  * On Gen4 and above:
 832  *   wait for the pipe register state bit to turn off
 833  *
 834  * Otherwise:
 835  *   wait for the display line value to settle (it usually
 836  *   ends up stopping at the start of the next frame).
 837  *
 838  */
 839 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 840 {
 841         struct drm_i915_private *dev_priv = dev->dev_private;
 842         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 843                                                                       pipe);
 844
 845         if (INTEL_INFO(dev)->gen >= 4) {
 846                 int reg = PIPECONF(cpu_transcoder);
 847
 848                 /* Wait for the Pipe State to go off */
 849                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 850                              100))
 851                         WARN(1, "pipe_off wait timed out\n");
 852         } else {
 853                 /* Wait for the display line to settle */
 854                 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
 855                         WARN(1, "pipe_off wait timed out\n");
 856         }
 857 }
 858
 859 /*
 860  * ibx_digital_port_connected - is the specified port connected?
 861  * @dev_priv: i915 private structure
 862  * @port: the port to test
 863  *
 864  * Returns true if @port is connected, false otherwise.
 865  */
 866 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 867                                 struct intel_digital_port *port)
 868 {
 869         u32 bit;
 870
 871         if (HAS_PCH_IBX(dev_priv->dev)) {
 872                 switch(port->port) {
 873                 case PORT_B:
 874                         bit = SDE_PORTB_HOTPLUG;
 875                         break;
 876                 case PORT_C:
 877                         bit = SDE_PORTC_HOTPLUG;
 878                         break;
 879                 case PORT_D:
 880                         bit = SDE_PORTD_HOTPLUG;
 881                         break;
 882                 default:
 883                         return true;
 884                 }
 885         } else {
 886                 switch(port->port) {
 887                 case PORT_B:
 888                         bit = SDE_PORTB_HOTPLUG_CPT;
 889                         break;
 890                 case PORT_C:
 891                         bit = SDE_PORTC_HOTPLUG_CPT;
 892                         break;
 893                 case PORT_D:
 894                         bit = SDE_PORTD_HOTPLUG_CPT;
 895                         break;
 896                 default:
 897                         return true;
 898                 }
 899         }
 900
 901         return I915_READ(SDEISR) & bit;
 902 }
 903
 904 static const char *state_string(bool enabled)
 905 {
 906         return enabled ? "on" : "off";
 907 }
 908
 909 /* Only for pre-ILK configs */
 910 void assert_pll(struct drm_i915_private *dev_priv,
 911                 enum pipe pipe, bool state)
 912 {
 913         int reg;
 914         u32 val;
 915         bool cur_state;
 916
 917         reg = DPLL(pipe);
 918         val = I915_READ(reg);
 919         cur_state = !!(val & DPLL_VCO_ENABLE);
 920         WARN(cur_state != state,
 921              "PLL state assertion failure (expected %s, current %s)\n",
 922              state_string(state), state_string(cur_state));
 923 }
 924
 925 /* XXX: the dsi pll is shared between MIPI DSI ports */
 926 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
 927 {
 928         u32 val;
 929         bool cur_state;
 930
 931         mutex_lock(&dev_priv->dpio_lock);
 932         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 933         mutex_unlock(&dev_priv->dpio_lock);
 934
 935         cur_state = val & DSI_PLL_VCO_EN;
 936         WARN(cur_state != state,
 937              "DSI PLL state assertion failure (expected %s, current %s)\n",
 938              state_string(state), state_string(cur_state));
 939 }
 940 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
 941 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
 942
 943 struct intel_shared_dpll *
 944 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
 945 {
 946         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 947
 948         if (crtc->config.shared_dpll < 0)
 949                 return NULL;
 950
 951         return &dev_priv->shared_dplls[crtc->config.shared_dpll];
 952 }
 953
 954 /* For ILK+ */
 955 void assert_shared_dpll(struct drm_i915_private *dev_priv,
 956                         struct intel_shared_dpll *pll,
 957                         bool state)
 958 {
 959         bool cur_state;
 960         struct intel_dpll_hw_state hw_state;
 961
 962         if (HAS_PCH_LPT(dev_priv->dev)) {
 963                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 964                 return;
 965         }
 966
 967         if (WARN (!pll,
 968                   "asserting DPLL %s with no DPLL\n", state_string(state)))
 969                 return;
 970
 971         cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
 972         WARN(cur_state != state,
 973              "%s assertion failure (expected %s, current %s)\n",
 974              pll->name, state_string(state), state_string(cur_state));
 975 }
 976
 977 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 978                           enum pipe pipe, bool state)
 979 {
 980         int reg;
 981         u32 val;
 982         bool cur_state;
 983         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 984                                                                       pipe);
 985
 986         if (HAS_DDI(dev_priv->dev)) {
 987                 /* DDI does not have a specific FDI_TX register */
 988                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 989                 val = I915_READ(reg);
 990                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 991         } else {
 992                 reg = FDI_TX_CTL(pipe);
 993                 val = I915_READ(reg);
 994                 cur_state = !!(val & FDI_TX_ENABLE);
 995         }
 996         WARN(cur_state != state,
 997              "FDI TX state assertion failure (expected %s, current %s)\n",
 998              state_string(state), state_string(cur_state));
 999 }
1000 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004                           enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = FDI_RX_CTL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & FDI_RX_ENABLE);
1013         WARN(cur_state != state,
1014              "FDI RX state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021                                       enum pipe pipe)
1022 {
1023         int reg;
1024         u32 val;
1025
1026         /* ILK FDI PLL is always enabled */
1027         if (dev_priv->info->gen == 5)
1028                 return;
1029
1030         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1031         if (HAS_DDI(dev_priv->dev))
1032                 return;
1033
1034         reg = FDI_TX_CTL(pipe);
1035         val = I915_READ(reg);
1036         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037 }
1038
1039 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040                        enum pipe pipe, bool state)
1041 {
1042         int reg;
1043         u32 val;
1044         bool cur_state;
1045
1046         reg = FDI_RX_CTL(pipe);
1047         val = I915_READ(reg);
1048         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049         WARN(cur_state != state,
1050              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051              state_string(state), state_string(cur_state));
1052 }
1053
1054 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055                                   enum pipe pipe)
1056 {
1057         int pp_reg, lvds_reg;
1058         u32 val;
1059         enum pipe panel_pipe = PIPE_A;
1060         bool locked = true;
1061
1062         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063                 pp_reg = PCH_PP_CONTROL;
1064                 lvds_reg = PCH_LVDS;
1065         } else {
1066                 pp_reg = PP_CONTROL;
1067                 lvds_reg = LVDS;
1068         }
1069
1070         val = I915_READ(pp_reg);
1071         if (!(val & PANEL_POWER_ON) ||
1072             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073                 locked = false;
1074
1075         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076                 panel_pipe = PIPE_B;
1077
1078         WARN(panel_pipe == pipe && locked,
1079              "panel assertion failure, pipe %c regs locked\n",
1080              pipe_name(pipe));
1081 }
1082
1083 static void assert_cursor(struct drm_i915_private *dev_priv,
1084                           enum pipe pipe, bool state)
1085 {
1086         struct drm_device *dev = dev_priv->dev;
1087         bool cur_state;
1088
1089         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090                 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091         else if (IS_845G(dev) || IS_I865G(dev))
1092                 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093         else
1094                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096         WARN(cur_state != state,
1097              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098              pipe_name(pipe), state_string(state), state_string(cur_state));
1099 }
1100 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
1103 void assert_pipe(struct drm_i915_private *dev_priv,
1104                  enum pipe pipe, bool state)
1105 {
1106         int reg;
1107         u32 val;
1108         bool cur_state;
1109         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110                                                                       pipe);
1111
1112         /* if we need the pipe A quirk it must be always on */
1113         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114                 state = true;
1115
1116         if (!intel_display_power_enabled(dev_priv->dev,
1117                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1118                 cur_state = false;
1119         } else {
1120                 reg = PIPECONF(cpu_transcoder);
1121                 val = I915_READ(reg);
1122                 cur_state = !!(val & PIPECONF_ENABLE);
1123         }
1124
1125         WARN(cur_state != state,
1126              "pipe %c assertion failure (expected %s, current %s)\n",
1127              pipe_name(pipe), state_string(state), state_string(cur_state));
1128 }
1129
1130 static void assert_plane(struct drm_i915_private *dev_priv,
1131                          enum plane plane, bool state)
1132 {
1133         int reg;
1134         u32 val;
1135         bool cur_state;
1136
1137         reg = DSPCNTR(plane);
1138         val = I915_READ(reg);
1139         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140         WARN(cur_state != state,
1141              "plane %c assertion failure (expected %s, current %s)\n",
1142              plane_name(plane), state_string(state), state_string(cur_state));
1143 }
1144
1145 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
1148 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149                                    enum pipe pipe)
1150 {
1151         struct drm_device *dev = dev_priv->dev;
1152         int reg, i;
1153         u32 val;
1154         int cur_pipe;
1155
1156         /* Primary planes are fixed to pipes on gen4+ */
1157         if (INTEL_INFO(dev)->gen >= 4) {
1158                 reg = DSPCNTR(pipe);
1159                 val = I915_READ(reg);
1160                 WARN((val & DISPLAY_PLANE_ENABLE),
1161                      "plane %c assertion failure, should be disabled but not\n",
1162                      plane_name(pipe));
1163                 return;
1164         }
1165
1166         /* Need to check both planes against the pipe */
1167         for_each_pipe(i) {
1168                 reg = DSPCNTR(i);
1169                 val = I915_READ(reg);
1170                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171                         DISPPLANE_SEL_PIPE_SHIFT;
1172                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1173                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174                      plane_name(i), pipe_name(pipe));
1175         }
1176 }
1177
1178 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179                                     enum pipe pipe)
1180 {
1181         struct drm_device *dev = dev_priv->dev;
1182         int reg, i;
1183         u32 val;
1184
1185         if (IS_VALLEYVIEW(dev)) {
1186                 for (i = 0; i < dev_priv->num_plane; i++) {
1187                         reg = SPCNTR(pipe, i);
1188                         val = I915_READ(reg);
1189                         WARN((val & SP_ENABLE),
1190                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191                              sprite_name(pipe, i), pipe_name(pipe));
1192                 }
1193         } else if (INTEL_INFO(dev)->gen >= 7) {
1194                 reg = SPRCTL(pipe);
1195                 val = I915_READ(reg);
1196                 WARN((val & SPRITE_ENABLE),
1197                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198                      plane_name(pipe), pipe_name(pipe));
1199         } else if (INTEL_INFO(dev)->gen >= 5) {
1200                 reg = DVSCNTR(pipe);
1201                 val = I915_READ(reg);
1202                 WARN((val & DVS_ENABLE),
1203                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204                      plane_name(pipe), pipe_name(pipe));
1205         }
1206 }
1207
1208 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209 {
1210         u32 val;
1211         bool enabled;
1212
1213         if (HAS_PCH_LPT(dev_priv->dev)) {
1214                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215                 return;
1216         }
1217
1218         val = I915_READ(PCH_DREF_CONTROL);
1219         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220                             DREF_SUPERSPREAD_SOURCE_MASK));
1221         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222 }
1223
1224 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225                                            enum pipe pipe)
1226 {
1227         int reg;
1228         u32 val;
1229         bool enabled;
1230
1231         reg = PCH_TRANSCONF(pipe);
1232         val = I915_READ(reg);
1233         enabled = !!(val & TRANS_ENABLE);
1234         WARN(enabled,
1235              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236              pipe_name(pipe));
1237 }
1238
1239 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240                             enum pipe pipe, u32 port_sel, u32 val)
1241 {
1242         if ((val & DP_PORT_EN) == 0)
1243                 return false;
1244
1245         if (HAS_PCH_CPT(dev_priv->dev)) {
1246                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249                         return false;
1250         } else {
1251                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252                         return false;
1253         }
1254         return true;
1255 }
1256
1257 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258                               enum pipe pipe, u32 val)
1259 {
1260         if ((val & SDVO_ENABLE) == 0)
1261                 return false;
1262
1263         if (HAS_PCH_CPT(dev_priv->dev)) {
1264                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1265                         return false;
1266         } else {
1267                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1268                         return false;
1269         }
1270         return true;
1271 }
1272
1273 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274                               enum pipe pipe, u32 val)
1275 {
1276         if ((val & LVDS_PORT_EN) == 0)
1277                 return false;
1278
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290                               enum pipe pipe, u32 val)
1291 {
1292         if ((val & ADPA_DAC_ENABLE) == 0)
1293                 return false;
1294         if (HAS_PCH_CPT(dev_priv->dev)) {
1295                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296                         return false;
1297         } else {
1298                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299                         return false;
1300         }
1301         return true;
1302 }
1303
1304 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1305                                    enum pipe pipe, int reg, u32 port_sel)
1306 {
1307         u32 val = I915_READ(reg);
1308         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1309              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1310              reg, pipe_name(pipe));
1311
1312         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313              && (val & DP_PIPEB_SELECT),
1314              "IBX PCH dp port still using transcoder B\n");
1315 }
1316
1317 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318                                      enum pipe pipe, int reg)
1319 {
1320         u32 val = I915_READ(reg);
1321         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1322              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1323              reg, pipe_name(pipe));
1324
1325         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1326              && (val & SDVO_PIPE_B_SELECT),
1327              "IBX PCH hdmi port still using transcoder B\n");
1328 }
1329
1330 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331                                       enum pipe pipe)
1332 {
1333         int reg;
1334         u32 val;
1335
1336         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1339
1340         reg = PCH_ADPA;
1341         val = I915_READ(reg);
1342         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1343              "PCH VGA enabled on transcoder %c, should be disabled\n",
1344              pipe_name(pipe));
1345
1346         reg = PCH_LVDS;
1347         val = I915_READ(reg);
1348         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1349              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1350              pipe_name(pipe));
1351
1352         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1355 }
1356
1357 static void intel_init_dpio(struct drm_device *dev)
1358 {
1359         struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361         if (!IS_VALLEYVIEW(dev))
1362                 return;
1363
1364         /*
1365          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1367          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368          *   b. The other bits such as sfr settings / modesel may all be set
1369          *      to 0.
1370          *
1371          * This should only be done on init and resume from S3 with both
1372          * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373          */
1374         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375 }
1376
1377 static void vlv_enable_pll(struct intel_crtc *crtc)
1378 {
1379         struct drm_device *dev = crtc->base.dev;
1380         struct drm_i915_private *dev_priv = dev->dev_private;
1381         int reg = DPLL(crtc->pipe);
1382         u32 dpll = crtc->config.dpll_hw_state.dpll;
1383
1384         assert_pipe_disabled(dev_priv, crtc->pipe);
1385
1386         /* No really, not for ILK+ */
1387         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389         /* PLL is protected by panel, make sure we can write it */
1390         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1391                 assert_panel_unlocked(dev_priv, crtc->pipe);
1392
1393         I915_WRITE(reg, dpll);
1394         POSTING_READ(reg);
1395         udelay(150);
1396
1397         if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398                 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400         I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401         POSTING_READ(DPLL_MD(crtc->pipe));
1402
1403         /* We do this three times for luck */
1404         I915_WRITE(reg, dpll);
1405         POSTING_READ(reg);
1406         udelay(150); /* wait for warmup */
1407         I915_WRITE(reg, dpll);
1408         POSTING_READ(reg);
1409         udelay(150); /* wait for warmup */
1410         I915_WRITE(reg, dpll);
1411         POSTING_READ(reg);
1412         udelay(150); /* wait for warmup */
1413 }
1414
1415 static void i9xx_enable_pll(struct intel_crtc *crtc)
1416 {
1417         struct drm_device *dev = crtc->base.dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         int reg = DPLL(crtc->pipe);
1420         u32 dpll = crtc->config.dpll_hw_state.dpll;
1421
1422         assert_pipe_disabled(dev_priv, crtc->pipe);
1423
1424         /* No really, not for ILK+ */
1425         BUG_ON(dev_priv->info->gen >= 5);
1426
1427         /* PLL is protected by panel, make sure we can write it */
1428         if (IS_MOBILE(dev) && !IS_I830(dev))
1429                 assert_panel_unlocked(dev_priv, crtc->pipe);
1430
1431         I915_WRITE(reg, dpll);
1432
1433         /* Wait for the clocks to stabilize. */
1434         POSTING_READ(reg);
1435         udelay(150);
1436
1437         if (INTEL_INFO(dev)->gen >= 4) {
1438                 I915_WRITE(DPLL_MD(crtc->pipe),
1439                            crtc->config.dpll_hw_state.dpll_md);
1440         } else {
1441                 /* The pixel multiplier can only be updated once the
1442                  * DPLL is enabled and the clocks are stable.
1443                  *
1444                  * So write it again.
1445                  */
1446                 I915_WRITE(reg, dpll);
1447         }
1448
1449         /* We do this three times for luck */
1450         I915_WRITE(reg, dpll);
1451         POSTING_READ(reg);
1452         udelay(150); /* wait for warmup */
1453         I915_WRITE(reg, dpll);
1454         POSTING_READ(reg);
1455         udelay(150); /* wait for warmup */
1456         I915_WRITE(reg, dpll);
1457         POSTING_READ(reg);
1458         udelay(150); /* wait for warmup */
1459 }
1460
1461 /**
1462  * i9xx_disable_pll - disable a PLL
1463  * @dev_priv: i915 private structure
1464  * @pipe: pipe PLL to disable
1465  *
1466  * Disable the PLL for @pipe, making sure the pipe is off first.
1467  *
1468  * Note!  This is for pre-ILK only.
1469  */
1470 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471 {
1472         /* Don't disable pipe A or pipe A PLLs if needed */
1473         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474                 return;
1475
1476         /* Make sure the pipe isn't still relying on us */
1477         assert_pipe_disabled(dev_priv, pipe);
1478
1479         I915_WRITE(DPLL(pipe), 0);
1480         POSTING_READ(DPLL(pipe));
1481 }
1482
1483 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484 {
1485         u32 val = 0;
1486
1487         /* Make sure the pipe isn't still relying on us */
1488         assert_pipe_disabled(dev_priv, pipe);
1489
1490         /* Leave integrated clock source enabled */
1491         if (pipe == PIPE_B)
1492                 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493         I915_WRITE(DPLL(pipe), val);
1494         POSTING_READ(DPLL(pipe));
1495 }
1496
1497 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498 {
1499         u32 port_mask;
1500
1501         if (!port)
1502                 port_mask = DPLL_PORTB_READY_MASK;
1503         else
1504                 port_mask = DPLL_PORTC_READY_MASK;
1505
1506         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508                      'B' + port, I915_READ(DPLL(0)));
1509 }
1510
1511 /**
1512  * ironlake_enable_shared_dpll - enable PCH PLL
1513  * @dev_priv: i915 private structure
1514  * @pipe: pipe PLL to enable
1515  *
1516  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517  * drives the transcoder clock.
1518  */
1519 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1520 {
1521         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1523
1524         /* PCH PLLs only available on ILK, SNB and IVB */
1525         BUG_ON(dev_priv->info->gen < 5);
1526         if (WARN_ON(pll == NULL))
1527                 return;
1528
1529         if (WARN_ON(pll->refcount == 0))
1530                 return;
1531
1532         DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533                       pll->name, pll->active, pll->on,
1534                       crtc->base.base.id);
1535
1536         if (pll->active++) {
1537                 WARN_ON(!pll->on);
1538                 assert_shared_dpll_enabled(dev_priv, pll);
1539                 return;
1540         }
1541         WARN_ON(pll->on);
1542
1543         DRM_DEBUG_KMS("enabling %s\n", pll->name);
1544         pll->enable(dev_priv, pll);
1545         pll->on = true;
1546 }
1547
1548 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1549 {
1550         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1552
1553         /* PCH only available on ILK+ */
1554         BUG_ON(dev_priv->info->gen < 5);
1555         if (WARN_ON(pll == NULL))
1556                return;
1557
1558         if (WARN_ON(pll->refcount == 0))
1559                 return;
1560
1561         DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562                       pll->name, pll->active, pll->on,
1563                       crtc->base.base.id);
1564
1565         if (WARN_ON(pll->active == 0)) {
1566                 assert_shared_dpll_disabled(dev_priv, pll);
1567                 return;
1568         }
1569
1570         assert_shared_dpll_enabled(dev_priv, pll);
1571         WARN_ON(!pll->on);
1572         if (--pll->active)
1573                 return;
1574
1575         DRM_DEBUG_KMS("disabling %s\n", pll->name);
1576         pll->disable(dev_priv, pll);
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1586         uint32_t reg, val, pipeconf_val;
1587
1588         /* PCH only available on ILK+ */
1589         BUG_ON(dev_priv->info->gen < 5);
1590
1591         /* Make sure PCH DPLL is enabled */
1592         assert_shared_dpll_enabled(dev_priv,
1593                                    intel_crtc_to_shared_dpll(intel_crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port, bool dsi)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_cursor_disabled(dev_priv, pipe);
1739         assert_sprites_disabled(dev_priv, pipe);
1740
1741         if (HAS_PCH_LPT(dev_priv->dev))
1742                 pch_transcoder = TRANSCODER_A;
1743         else
1744                 pch_transcoder = pipe;
1745
1746         /*
1747          * A pipe without a PLL won't actually be able to drive bits from
1748          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1749          * need the check.
1750          */
1751         if (!HAS_PCH_SPLIT(dev_priv->dev))
1752                 if (dsi)
1753                         assert_dsi_pll_enabled(dev_priv);
1754                 else
1755                         assert_pll_enabled(dev_priv, pipe);
1756         else {
1757                 if (pch_port) {
1758                         /* if driving the PCH, we need FDI enabled */
1759                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1760                         assert_fdi_tx_pll_enabled(dev_priv,
1761                                                   (enum pipe) cpu_transcoder);
1762                 }
1763                 /* FIXME: assert CPU port conditions for SNB+ */
1764         }
1765
1766         reg = PIPECONF(cpu_transcoder);
1767         val = I915_READ(reg);
1768         if (val & PIPECONF_ENABLE)
1769                 return;
1770
1771         I915_WRITE(reg, val | PIPECONF_ENABLE);
1772         intel_wait_for_vblank(dev_priv->dev, pipe);
1773 }
1774
1775 /**
1776  * intel_disable_pipe - disable a pipe, asserting requirements
1777  * @dev_priv: i915 private structure
1778  * @pipe: pipe to disable
1779  *
1780  * Disable @pipe, making sure that various hardware specific requirements
1781  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782  *
1783  * @pipe should be %PIPE_A or %PIPE_B.
1784  *
1785  * Will wait until the pipe has shut down before returning.
1786  */
1787 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788                                enum pipe pipe)
1789 {
1790         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791                                                                       pipe);
1792         int reg;
1793         u32 val;
1794
1795         /*
1796          * Make sure planes won't keep trying to pump pixels to us,
1797          * or we might hang the display.
1798          */
1799         assert_planes_disabled(dev_priv, pipe);
1800         assert_cursor_disabled(dev_priv, pipe);
1801         assert_sprites_disabled(dev_priv, pipe);
1802
1803         /* Don't disable pipe A or pipe A PLLs if needed */
1804         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805                 return;
1806
1807         reg = PIPECONF(cpu_transcoder);
1808         val = I915_READ(reg);
1809         if ((val & PIPECONF_ENABLE) == 0)
1810                 return;
1811
1812         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1813         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814 }
1815
1816 /*
1817  * Plane regs are double buffered, going from enabled->disabled needs a
1818  * trigger in order to latch.  The display address reg provides this.
1819  */
1820 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821                                enum plane plane)
1822 {
1823         u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825         I915_WRITE(reg, I915_READ(reg));
1826         POSTING_READ(reg);
1827 }
1828
1829 /**
1830  * intel_enable_primary_plane - enable the primary plane on a given pipe
1831  * @dev_priv: i915 private structure
1832  * @plane: plane to enable
1833  * @pipe: pipe being fed
1834  *
1835  * Enable @plane on @pipe, making sure that @pipe is running first.
1836  */
1837 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838                                        enum plane plane, enum pipe pipe)
1839 {
1840         struct intel_crtc *intel_crtc =
1841                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1842         int reg;
1843         u32 val;
1844
1845         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846         assert_pipe_enabled(dev_priv, pipe);
1847
1848         WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1849
1850         intel_crtc->primary_enabled = true;
1851
1852         reg = DSPCNTR(plane);
1853         val = I915_READ(reg);
1854         if (val & DISPLAY_PLANE_ENABLE)
1855                 return;
1856
1857         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1858         intel_flush_primary_plane(dev_priv, plane);
1859         intel_wait_for_vblank(dev_priv->dev, pipe);
1860 }
1861
1862 /**
1863  * intel_disable_primary_plane - disable the primary plane
1864  * @dev_priv: i915 private structure
1865  * @plane: plane to disable
1866  * @pipe: pipe consuming the data
1867  *
1868  * Disable @plane; should be an independent operation.
1869  */
1870 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871                                         enum plane plane, enum pipe pipe)
1872 {
1873         struct intel_crtc *intel_crtc =
1874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1875         int reg;
1876         u32 val;
1877
1878         WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1879
1880         intel_crtc->primary_enabled = false;
1881
1882         reg = DSPCNTR(plane);
1883         val = I915_READ(reg);
1884         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885                 return;
1886
1887         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1888         intel_flush_primary_plane(dev_priv, plane);
1889         intel_wait_for_vblank(dev_priv->dev, pipe);
1890 }
1891
1892 static bool need_vtd_wa(struct drm_device *dev)
1893 {
1894 #ifdef CONFIG_INTEL_IOMMU
1895         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896                 return true;
1897 #endif
1898         return false;
1899 }
1900
1901 int
1902 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1903                            struct drm_i915_gem_object *obj,
1904                            struct intel_ring_buffer *pipelined)
1905 {
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         u32 alignment;
1908         int ret;
1909
1910         switch (obj->tiling_mode) {
1911         case I915_TILING_NONE:
1912                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913                         alignment = 128 * 1024;
1914                 else if (INTEL_INFO(dev)->gen >= 4)
1915                         alignment = 4 * 1024;
1916                 else
1917                         alignment = 64 * 1024;
1918                 break;
1919         case I915_TILING_X:
1920                 /* pin() will align the object as required by fence */
1921                 alignment = 0;
1922                 break;
1923         case I915_TILING_Y:
1924                 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1925                 return -EINVAL;
1926         default:
1927                 BUG();
1928         }
1929
1930         /* Note that the w/a also requires 64 PTE of padding following the
1931          * bo. We currently fill all unused PTE with the shadow page and so
1932          * we should always have valid PTE following the scanout preventing
1933          * the VT-d warning.
1934          */
1935         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936                 alignment = 256 * 1024;
1937
1938         dev_priv->mm.interruptible = false;
1939         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1940         if (ret)
1941                 goto err_interruptible;
1942
1943         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944          * fence, whereas 965+ only requires a fence if using
1945          * framebuffer compression.  For simplicity, we always install
1946          * a fence as the cost is not that onerous.
1947          */
1948         ret = i915_gem_object_get_fence(obj);
1949         if (ret)
1950                 goto err_unpin;
1951
1952         i915_gem_object_pin_fence(obj);
1953
1954         dev_priv->mm.interruptible = true;
1955         return 0;
1956
1957 err_unpin:
1958         i915_gem_object_unpin_from_display_plane(obj);
1959 err_interruptible:
1960         dev_priv->mm.interruptible = true;
1961         return ret;
1962 }
1963
1964 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965 {
1966         i915_gem_object_unpin_fence(obj);
1967         i915_gem_object_unpin_from_display_plane(obj);
1968 }
1969
1970 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971  * is assumed to be a power-of-two. */
1972 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973                                              unsigned int tiling_mode,
1974                                              unsigned int cpp,
1975                                              unsigned int pitch)
1976 {
1977         if (tiling_mode != I915_TILING_NONE) {
1978                 unsigned int tile_rows, tiles;
1979
1980                 tile_rows = *y / 8;
1981                 *y %= 8;
1982
1983                 tiles = *x / (512/cpp);
1984                 *x %= 512/cpp;
1985
1986                 return tile_rows * pitch * 8 + tiles * 4096;
1987         } else {
1988                 unsigned int offset;
1989
1990                 offset = *y * pitch + *x * cpp;
1991                 *y = 0;
1992                 *x = (offset & 4095) / cpp;
1993                 return offset & -4096;
1994         }
1995 }
1996
1997 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998                              int x, int y)
1999 {
2000         struct drm_device *dev = crtc->dev;
2001         struct drm_i915_private *dev_priv = dev->dev_private;
2002         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003         struct intel_framebuffer *intel_fb;
2004         struct drm_i915_gem_object *obj;
2005         int plane = intel_crtc->plane;
2006         unsigned long linear_offset;
2007         u32 dspcntr;
2008         u32 reg;
2009
2010         switch (plane) {
2011         case 0:
2012         case 1:
2013                 break;
2014         default:
2015                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2016                 return -EINVAL;
2017         }
2018
2019         intel_fb = to_intel_framebuffer(fb);
2020         obj = intel_fb->obj;
2021
2022         reg = DSPCNTR(plane);
2023         dspcntr = I915_READ(reg);
2024         /* Mask out pixel format bits in case we change it */
2025         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2026         switch (fb->pixel_format) {
2027         case DRM_FORMAT_C8:
2028                 dspcntr |= DISPPLANE_8BPP;
2029                 break;
2030         case DRM_FORMAT_XRGB1555:
2031         case DRM_FORMAT_ARGB1555:
2032                 dspcntr |= DISPPLANE_BGRX555;
2033                 break;
2034         case DRM_FORMAT_RGB565:
2035                 dspcntr |= DISPPLANE_BGRX565;
2036                 break;
2037         case DRM_FORMAT_XRGB8888:
2038         case DRM_FORMAT_ARGB8888:
2039                 dspcntr |= DISPPLANE_BGRX888;
2040                 break;
2041         case DRM_FORMAT_XBGR8888:
2042         case DRM_FORMAT_ABGR8888:
2043                 dspcntr |= DISPPLANE_RGBX888;
2044                 break;
2045         case DRM_FORMAT_XRGB2101010:
2046         case DRM_FORMAT_ARGB2101010:
2047                 dspcntr |= DISPPLANE_BGRX101010;
2048                 break;
2049         case DRM_FORMAT_XBGR2101010:
2050         case DRM_FORMAT_ABGR2101010:
2051                 dspcntr |= DISPPLANE_RGBX101010;
2052                 break;
2053         default:
2054                 BUG();
2055         }
2056
2057         if (INTEL_INFO(dev)->gen >= 4) {
2058                 if (obj->tiling_mode != I915_TILING_NONE)
2059                         dspcntr |= DISPPLANE_TILED;
2060                 else
2061                         dspcntr &= ~DISPPLANE_TILED;
2062         }
2063
2064         if (IS_G4X(dev))
2065                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
2067         I915_WRITE(reg, dspcntr);
2068
2069         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2070
2071         if (INTEL_INFO(dev)->gen >= 4) {
2072                 intel_crtc->dspaddr_offset =
2073                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074                                                        fb->bits_per_pixel / 8,
2075                                                        fb->pitches[0]);
2076                 linear_offset -= intel_crtc->dspaddr_offset;
2077         } else {
2078                 intel_crtc->dspaddr_offset = linear_offset;
2079         }
2080
2081         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083                       fb->pitches[0]);
2084         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2085         if (INTEL_INFO(dev)->gen >= 4) {
2086                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2087                                      i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2088                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2089                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2090         } else
2091                 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2092         POSTING_READ(reg);
2093
2094         return 0;
2095 }
2096
2097 static int ironlake_update_plane(struct drm_crtc *crtc,
2098                                  struct drm_framebuffer *fb, int x, int y)
2099 {
2100         struct drm_device *dev = crtc->dev;
2101         struct drm_i915_private *dev_priv = dev->dev_private;
2102         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103         struct intel_framebuffer *intel_fb;
2104         struct drm_i915_gem_object *obj;
2105         int plane = intel_crtc->plane;
2106         unsigned long linear_offset;
2107         u32 dspcntr;
2108         u32 reg;
2109
2110         switch (plane) {
2111         case 0:
2112         case 1:
2113         case 2:
2114                 break;
2115         default:
2116                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2117                 return -EINVAL;
2118         }
2119
2120         intel_fb = to_intel_framebuffer(fb);
2121         obj = intel_fb->obj;
2122
2123         reg = DSPCNTR(plane);
2124         dspcntr = I915_READ(reg);
2125         /* Mask out pixel format bits in case we change it */
2126         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2127         switch (fb->pixel_format) {
2128         case DRM_FORMAT_C8:
2129                 dspcntr |= DISPPLANE_8BPP;
2130                 break;
2131         case DRM_FORMAT_RGB565:
2132                 dspcntr |= DISPPLANE_BGRX565;
2133                 break;
2134         case DRM_FORMAT_XRGB8888:
2135         case DRM_FORMAT_ARGB8888:
2136                 dspcntr |= DISPPLANE_BGRX888;
2137                 break;
2138         case DRM_FORMAT_XBGR8888:
2139         case DRM_FORMAT_ABGR8888:
2140                 dspcntr |= DISPPLANE_RGBX888;
2141                 break;
2142         case DRM_FORMAT_XRGB2101010:
2143         case DRM_FORMAT_ARGB2101010:
2144                 dspcntr |= DISPPLANE_BGRX101010;
2145                 break;
2146         case DRM_FORMAT_XBGR2101010:
2147         case DRM_FORMAT_ABGR2101010:
2148                 dspcntr |= DISPPLANE_RGBX101010;
2149                 break;
2150         default:
2151                 BUG();
2152         }
2153
2154         if (obj->tiling_mode != I915_TILING_NONE)
2155                 dspcntr |= DISPPLANE_TILED;
2156         else
2157                 dspcntr &= ~DISPPLANE_TILED;
2158
2159         if (IS_HASWELL(dev))
2160                 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161         else
2162                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2163
2164         I915_WRITE(reg, dspcntr);
2165
2166         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2167         intel_crtc->dspaddr_offset =
2168                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169                                                fb->bits_per_pixel / 8,
2170                                                fb->pitches[0]);
2171         linear_offset -= intel_crtc->dspaddr_offset;
2172
2173         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174                       i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175                       fb->pitches[0]);
2176         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2177         I915_MODIFY_DISPBASE(DSPSURF(plane),
2178                              i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2179         if (IS_HASWELL(dev)) {
2180                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181         } else {
2182                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184         }
2185         POSTING_READ(reg);
2186
2187         return 0;
2188 }
2189
2190 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2191 static int
2192 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193                            int x, int y, enum mode_set_atomic state)
2194 {
2195         struct drm_device *dev = crtc->dev;
2196         struct drm_i915_private *dev_priv = dev->dev_private;
2197
2198         if (dev_priv->display.disable_fbc)
2199                 dev_priv->display.disable_fbc(dev);
2200         intel_increase_pllclock(crtc);
2201
2202         return dev_priv->display.update_plane(crtc, fb, x, y);
2203 }
2204
2205 void intel_display_handle_reset(struct drm_device *dev)
2206 {
2207         struct drm_i915_private *dev_priv = dev->dev_private;
2208         struct drm_crtc *crtc;
2209
2210         /*
2211          * Flips in the rings have been nuked by the reset,
2212          * so complete all pending flips so that user space
2213          * will get its events and not get stuck.
2214          *
2215          * Also update the base address of all primary
2216          * planes to the the last fb to make sure we're
2217          * showing the correct fb after a reset.
2218          *
2219          * Need to make two loops over the crtcs so that we
2220          * don't try to grab a crtc mutex before the
2221          * pending_flip_queue really got woken up.
2222          */
2223
2224         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226                 enum plane plane = intel_crtc->plane;
2227
2228                 intel_prepare_page_flip(dev, plane);
2229                 intel_finish_page_flip_plane(dev, plane);
2230         }
2231
2232         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235                 mutex_lock(&crtc->mutex);
2236                 if (intel_crtc->active)
2237                         dev_priv->display.update_plane(crtc, crtc->fb,
2238                                                        crtc->x, crtc->y);
2239                 mutex_unlock(&crtc->mutex);
2240         }
2241 }
2242
2243 static int
2244 intel_finish_fb(struct drm_framebuffer *old_fb)
2245 {
2246         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248         bool was_interruptible = dev_priv->mm.interruptible;
2249         int ret;
2250
2251         /* Big Hammer, we also need to ensure that any pending
2252          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253          * current scanout is retired before unpinning the old
2254          * framebuffer.
2255          *
2256          * This should only fail upon a hung GPU, in which case we
2257          * can safely continue.
2258          */
2259         dev_priv->mm.interruptible = false;
2260         ret = i915_gem_object_finish_gpu(obj);
2261         dev_priv->mm.interruptible = was_interruptible;
2262
2263         return ret;
2264 }
2265
2266 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267 {
2268         struct drm_device *dev = crtc->dev;
2269         struct drm_i915_master_private *master_priv;
2270         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272         if (!dev->primary->master)
2273                 return;
2274
2275         master_priv = dev->primary->master->driver_priv;
2276         if (!master_priv->sarea_priv)
2277                 return;
2278
2279         switch (intel_crtc->pipe) {
2280         case 0:
2281                 master_priv->sarea_priv->pipeA_x = x;
2282                 master_priv->sarea_priv->pipeA_y = y;
2283                 break;
2284         case 1:
2285                 master_priv->sarea_priv->pipeB_x = x;
2286                 master_priv->sarea_priv->pipeB_y = y;
2287                 break;
2288         default:
2289                 break;
2290         }
2291 }
2292
2293 static int
2294 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2295                     struct drm_framebuffer *fb)
2296 {
2297         struct drm_device *dev = crtc->dev;
2298         struct drm_i915_private *dev_priv = dev->dev_private;
2299         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2300         struct drm_framebuffer *old_fb;
2301         int ret;
2302
2303         /* no fb bound */
2304         if (!fb) {
2305                 DRM_ERROR("No FB bound\n");
2306                 return 0;
2307         }
2308
2309         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2310                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311                           plane_name(intel_crtc->plane),
2312                           INTEL_INFO(dev)->num_pipes);
2313                 return -EINVAL;
2314         }
2315
2316         mutex_lock(&dev->struct_mutex);
2317         ret = intel_pin_and_fence_fb_obj(dev,
2318                                          to_intel_framebuffer(fb)->obj,
2319                                          NULL);
2320         if (ret != 0) {
2321                 mutex_unlock(&dev->struct_mutex);
2322                 DRM_ERROR("pin & fence failed\n");
2323                 return ret;
2324         }
2325
2326         /*
2327          * Update pipe size and adjust fitter if needed: the reason for this is
2328          * that in compute_mode_changes we check the native mode (not the pfit
2329          * mode) to see if we can flip rather than do a full mode set. In the
2330          * fastboot case, we'll flip, but if we don't update the pipesrc and
2331          * pfit state, we'll end up with a big fb scanned out into the wrong
2332          * sized surface.
2333          *
2334          * To fix this properly, we need to hoist the checks up into
2335          * compute_mode_changes (or above), check the actual pfit state and
2336          * whether the platform allows pfit disable with pipe active, and only
2337          * then update the pipesrc and pfit state, even on the flip path.
2338          */
2339         if (i915_fastboot) {
2340                 const struct drm_display_mode *adjusted_mode =
2341                         &intel_crtc->config.adjusted_mode;
2342
2343                 I915_WRITE(PIPESRC(intel_crtc->pipe),
2344                            ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345                            (adjusted_mode->crtc_vdisplay - 1));
2346                 if (!intel_crtc->config.pch_pfit.enabled &&
2347                     (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348                      intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349                         I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350                         I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351                         I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352                 }
2353         }
2354
2355         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2356         if (ret) {
2357                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2358                 mutex_unlock(&dev->struct_mutex);
2359                 DRM_ERROR("failed to update base address\n");
2360                 return ret;
2361         }
2362
2363         old_fb = crtc->fb;
2364         crtc->fb = fb;
2365         crtc->x = x;
2366         crtc->y = y;
2367
2368         if (old_fb) {
2369                 if (intel_crtc->active && old_fb != fb)
2370                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2371                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2372         }
2373
2374         intel_update_fbc(dev);
2375         intel_edp_psr_update(dev);
2376         mutex_unlock(&dev->struct_mutex);
2377
2378         intel_crtc_update_sarea_pos(crtc, x, y);
2379
2380         return 0;
2381 }
2382
2383 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384 {
2385         struct drm_device *dev = crtc->dev;
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388         int pipe = intel_crtc->pipe;
2389         u32 reg, temp;
2390
2391         /* enable normal train */
2392         reg = FDI_TX_CTL(pipe);
2393         temp = I915_READ(reg);
2394         if (IS_IVYBRIDGE(dev)) {
2395                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2397         } else {
2398                 temp &= ~FDI_LINK_TRAIN_NONE;
2399                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2400         }
2401         I915_WRITE(reg, temp);
2402
2403         reg = FDI_RX_CTL(pipe);
2404         temp = I915_READ(reg);
2405         if (HAS_PCH_CPT(dev)) {
2406                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408         } else {
2409                 temp &= ~FDI_LINK_TRAIN_NONE;
2410                 temp |= FDI_LINK_TRAIN_NONE;
2411         }
2412         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414         /* wait one idle pattern time */
2415         POSTING_READ(reg);
2416         udelay(1000);
2417
2418         /* IVB wants error correction enabled */
2419         if (IS_IVYBRIDGE(dev))
2420                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421                            FDI_FE_ERRC_ENABLE);
2422 }
2423
2424 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2425 {
2426         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2427 }
2428
2429 static void ivb_modeset_global_resources(struct drm_device *dev)
2430 {
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         struct intel_crtc *pipe_B_crtc =
2433                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2434         struct intel_crtc *pipe_C_crtc =
2435                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2436         uint32_t temp;
2437
2438         /*
2439          * When everything is off disable fdi C so that we could enable fdi B
2440          * with all lanes. Note that we don't care about enabled pipes without
2441          * an enabled pch encoder.
2442          */
2443         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2444             !pipe_has_enabled_pch(pipe_C_crtc)) {
2445                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447
2448                 temp = I915_READ(SOUTH_CHICKEN1);
2449                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451                 I915_WRITE(SOUTH_CHICKEN1, temp);
2452         }
2453 }
2454
2455 /* The FDI link training functions for ILK/Ibexpeak. */
2456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457 {
2458         struct drm_device *dev = crtc->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461         int pipe = intel_crtc->pipe;
2462         int plane = intel_crtc->plane;
2463         u32 reg, temp, tries;
2464
2465         /* FDI needs bits from pipe & plane first */
2466         assert_pipe_enabled(dev_priv, pipe);
2467         assert_plane_enabled(dev_priv, plane);
2468
2469         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470            for train result */
2471         reg = FDI_RX_IMR(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_RX_SYMBOL_LOCK;
2474         temp &= ~FDI_RX_BIT_LOCK;
2475         I915_WRITE(reg, temp);
2476         I915_READ(reg);
2477         udelay(150);
2478
2479         /* enable CPU FDI TX and PCH FDI RX */
2480         reg = FDI_TX_CTL(pipe);
2481         temp = I915_READ(reg);
2482         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2484         temp &= ~FDI_LINK_TRAIN_NONE;
2485         temp |= FDI_LINK_TRAIN_PATTERN_1;
2486         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2487
2488         reg = FDI_RX_CTL(pipe);
2489         temp = I915_READ(reg);
2490         temp &= ~FDI_LINK_TRAIN_NONE;
2491         temp |= FDI_LINK_TRAIN_PATTERN_1;
2492         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494         POSTING_READ(reg);
2495         udelay(150);
2496
2497         /* Ironlake workaround, enable clock pointer after FDI enable*/
2498         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2500                    FDI_RX_PHASE_SYNC_POINTER_EN);
2501
2502         reg = FDI_RX_IIR(pipe);
2503         for (tries = 0; tries < 5; tries++) {
2504                 temp = I915_READ(reg);
2505                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506
2507                 if ((temp & FDI_RX_BIT_LOCK)) {
2508                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2509                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2510                         break;
2511                 }
2512         }
2513         if (tries == 5)
2514                 DRM_ERROR("FDI train 1 fail!\n");
2515
2516         /* Train 2 */
2517         reg = FDI_TX_CTL(pipe);
2518         temp = I915_READ(reg);
2519         temp &= ~FDI_LINK_TRAIN_NONE;
2520         temp |= FDI_LINK_TRAIN_PATTERN_2;
2521         I915_WRITE(reg, temp);
2522
2523         reg = FDI_RX_CTL(pipe);
2524         temp = I915_READ(reg);
2525         temp &= ~FDI_LINK_TRAIN_NONE;
2526         temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         I915_WRITE(reg, temp);
2528
2529         POSTING_READ(reg);
2530         udelay(150);
2531
2532         reg = FDI_RX_IIR(pipe);
2533         for (tries = 0; tries < 5; tries++) {
2534                 temp = I915_READ(reg);
2535                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536
2537                 if (temp & FDI_RX_SYMBOL_LOCK) {
2538                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2539                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2540                         break;
2541                 }
2542         }
2543         if (tries == 5)
2544                 DRM_ERROR("FDI train 2 fail!\n");
2545
2546         DRM_DEBUG_KMS("FDI train done\n");
2547
2548 }
2549
2550 static const int snb_b_fdi_train_param[] = {
2551         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2552         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2553         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2554         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555 };
2556
2557 /* The FDI link training functions for SNB/Cougarpoint. */
2558 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2559 {
2560         struct drm_device *dev = crtc->dev;
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563         int pipe = intel_crtc->pipe;
2564         u32 reg, temp, i, retry;
2565
2566         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567            for train result */
2568         reg = FDI_RX_IMR(pipe);
2569         temp = I915_READ(reg);
2570         temp &= ~FDI_RX_SYMBOL_LOCK;
2571         temp &= ~FDI_RX_BIT_LOCK;
2572         I915_WRITE(reg, temp);
2573
2574         POSTING_READ(reg);
2575         udelay(150);
2576
2577         /* enable CPU FDI TX and PCH FDI RX */
2578         reg = FDI_TX_CTL(pipe);
2579         temp = I915_READ(reg);
2580         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2581         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2582         temp &= ~FDI_LINK_TRAIN_NONE;
2583         temp |= FDI_LINK_TRAIN_PATTERN_1;
2584         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585         /* SNB-B */
2586         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2587         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2588
2589         I915_WRITE(FDI_RX_MISC(pipe),
2590                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591
2592         reg = FDI_RX_CTL(pipe);
2593         temp = I915_READ(reg);
2594         if (HAS_PCH_CPT(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597         } else {
2598                 temp &= ~FDI_LINK_TRAIN_NONE;
2599                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600         }
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         for (i = 0; i < 4; i++) {
2607                 reg = FDI_TX_CTL(pipe);
2608                 temp = I915_READ(reg);
2609                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610                 temp |= snb_b_fdi_train_param[i];
2611                 I915_WRITE(reg, temp);
2612
2613                 POSTING_READ(reg);
2614                 udelay(500);
2615
2616                 for (retry = 0; retry < 5; retry++) {
2617                         reg = FDI_RX_IIR(pipe);
2618                         temp = I915_READ(reg);
2619                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620                         if (temp & FDI_RX_BIT_LOCK) {
2621                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623                                 break;
2624                         }
2625                         udelay(50);
2626                 }
2627                 if (retry < 5)
2628                         break;
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2;
2638         if (IS_GEN6(dev)) {
2639                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640                 /* SNB-B */
2641                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642         }
2643         I915_WRITE(reg, temp);
2644
2645         reg = FDI_RX_CTL(pipe);
2646         temp = I915_READ(reg);
2647         if (HAS_PCH_CPT(dev)) {
2648                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650         } else {
2651                 temp &= ~FDI_LINK_TRAIN_NONE;
2652                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653         }
2654         I915_WRITE(reg, temp);
2655
2656         POSTING_READ(reg);
2657         udelay(150);
2658
2659         for (i = 0; i < 4; i++) {
2660                 reg = FDI_TX_CTL(pipe);
2661                 temp = I915_READ(reg);
2662                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663                 temp |= snb_b_fdi_train_param[i];
2664                 I915_WRITE(reg, temp);
2665
2666                 POSTING_READ(reg);
2667                 udelay(500);
2668
2669                 for (retry = 0; retry < 5; retry++) {
2670                         reg = FDI_RX_IIR(pipe);
2671                         temp = I915_READ(reg);
2672                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673                         if (temp & FDI_RX_SYMBOL_LOCK) {
2674                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676                                 break;
2677                         }
2678                         udelay(50);
2679                 }
2680                 if (retry < 5)
2681                         break;
2682         }
2683         if (i == 4)
2684                 DRM_ERROR("FDI train 2 fail!\n");
2685
2686         DRM_DEBUG_KMS("FDI train done.\n");
2687 }
2688
2689 /* Manual link training for Ivy Bridge A0 parts */
2690 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691 {
2692         struct drm_device *dev = crtc->dev;
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695         int pipe = intel_crtc->pipe;
2696         u32 reg, temp, i, j;
2697
2698         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699            for train result */
2700         reg = FDI_RX_IMR(pipe);
2701         temp = I915_READ(reg);
2702         temp &= ~FDI_RX_SYMBOL_LOCK;
2703         temp &= ~FDI_RX_BIT_LOCK;
2704         I915_WRITE(reg, temp);
2705
2706         POSTING_READ(reg);
2707         udelay(150);
2708
2709         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710                       I915_READ(FDI_RX_IIR(pipe)));
2711
2712         /* Try each vswing and preemphasis setting twice before moving on */
2713         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2714                 /* disable first in case we need to retry */
2715                 reg = FDI_TX_CTL(pipe);
2716                 temp = I915_READ(reg);
2717                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718                 temp &= ~FDI_TX_ENABLE;
2719                 I915_WRITE(reg, temp);
2720
2721                 reg = FDI_RX_CTL(pipe);
2722                 temp = I915_READ(reg);
2723                 temp &= ~FDI_LINK_TRAIN_AUTO;
2724                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725                 temp &= ~FDI_RX_ENABLE;
2726                 I915_WRITE(reg, temp);
2727
2728                 /* enable CPU FDI TX and PCH FDI RX */
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2732                 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2733                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2734                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2735                 temp |= snb_b_fdi_train_param[j/2];
2736                 temp |= FDI_COMPOSITE_SYNC;
2737                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2738
2739                 I915_WRITE(FDI_RX_MISC(pipe),
2740                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2741
2742                 reg = FDI_RX_CTL(pipe);
2743                 temp = I915_READ(reg);
2744                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745                 temp |= FDI_COMPOSITE_SYNC;
2746                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2747
2748                 POSTING_READ(reg);
2749                 udelay(1); /* should be 0.5us */
2750
2751                 for (i = 0; i < 4; i++) {
2752                         reg = FDI_RX_IIR(pipe);
2753                         temp = I915_READ(reg);
2754                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2755
2756                         if (temp & FDI_RX_BIT_LOCK ||
2757                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2758                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2759                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2760                                               i);
2761                                 break;
2762                         }
2763                         udelay(1); /* should be 0.5us */
2764                 }
2765                 if (i == 4) {
2766                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2767                         continue;
2768                 }
2769
2770                 /* Train 2 */
2771                 reg = FDI_TX_CTL(pipe);
2772                 temp = I915_READ(reg);
2773                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775                 I915_WRITE(reg, temp);
2776
2777                 reg = FDI_RX_CTL(pipe);
2778                 temp = I915_READ(reg);
2779                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2780                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2781                 I915_WRITE(reg, temp);
2782
2783                 POSTING_READ(reg);
2784                 udelay(2); /* should be 1.5us */
2785
2786                 for (i = 0; i < 4; i++) {
2787                         reg = FDI_RX_IIR(pipe);
2788                         temp = I915_READ(reg);
2789                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2790
2791                         if (temp & FDI_RX_SYMBOL_LOCK ||
2792                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2793                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2794                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2795                                               i);
2796                                 goto train_done;
2797                         }
2798                         udelay(2); /* should be 1.5us */
2799                 }
2800                 if (i == 4)
2801                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2802         }
2803
2804 train_done:
2805         DRM_DEBUG_KMS("FDI train done.\n");
2806 }
2807
2808 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2809 {
2810         struct drm_device *dev = intel_crtc->base.dev;
2811         struct drm_i915_private *dev_priv = dev->dev_private;
2812         int pipe = intel_crtc->pipe;
2813         u32 reg, temp;
2814
2815
2816         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2817         reg = FDI_RX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2820         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2821         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2822         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2823
2824         POSTING_READ(reg);
2825         udelay(200);
2826
2827         /* Switch from Rawclk to PCDclk */
2828         temp = I915_READ(reg);
2829         I915_WRITE(reg, temp | FDI_PCDCLK);
2830
2831         POSTING_READ(reg);
2832         udelay(200);
2833
2834         /* Enable CPU FDI TX PLL, always on for Ironlake */
2835         reg = FDI_TX_CTL(pipe);
2836         temp = I915_READ(reg);
2837         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2839
2840                 POSTING_READ(reg);
2841                 udelay(100);
2842         }
2843 }
2844
2845 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2846 {
2847         struct drm_device *dev = intel_crtc->base.dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         int pipe = intel_crtc->pipe;
2850         u32 reg, temp;
2851
2852         /* Switch from PCDclk to Rawclk */
2853         reg = FDI_RX_CTL(pipe);
2854         temp = I915_READ(reg);
2855         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2856
2857         /* Disable CPU FDI TX PLL */
2858         reg = FDI_TX_CTL(pipe);
2859         temp = I915_READ(reg);
2860         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2861
2862         POSTING_READ(reg);
2863         udelay(100);
2864
2865         reg = FDI_RX_CTL(pipe);
2866         temp = I915_READ(reg);
2867         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2868
2869         /* Wait for the clocks to turn off. */
2870         POSTING_READ(reg);
2871         udelay(100);
2872 }
2873
2874 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct drm_i915_private *dev_priv = dev->dev_private;
2878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879         int pipe = intel_crtc->pipe;
2880         u32 reg, temp;
2881
2882         /* disable CPU FDI tx and PCH FDI rx */
2883         reg = FDI_TX_CTL(pipe);
2884         temp = I915_READ(reg);
2885         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2886         POSTING_READ(reg);
2887
2888         reg = FDI_RX_CTL(pipe);
2889         temp = I915_READ(reg);
2890         temp &= ~(0x7 << 16);
2891         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2892         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2893
2894         POSTING_READ(reg);
2895         udelay(100);
2896
2897         /* Ironlake workaround, disable clock pointer after downing FDI */
2898         if (HAS_PCH_IBX(dev)) {
2899                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2900         }
2901
2902         /* still set train pattern 1 */
2903         reg = FDI_TX_CTL(pipe);
2904         temp = I915_READ(reg);
2905         temp &= ~FDI_LINK_TRAIN_NONE;
2906         temp |= FDI_LINK_TRAIN_PATTERN_1;
2907         I915_WRITE(reg, temp);
2908
2909         reg = FDI_RX_CTL(pipe);
2910         temp = I915_READ(reg);
2911         if (HAS_PCH_CPT(dev)) {
2912                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914         } else {
2915                 temp &= ~FDI_LINK_TRAIN_NONE;
2916                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2917         }
2918         /* BPC in FDI rx is consistent with that in PIPECONF */
2919         temp &= ~(0x07 << 16);
2920         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2921         I915_WRITE(reg, temp);
2922
2923         POSTING_READ(reg);
2924         udelay(100);
2925 }
2926
2927 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2928 {
2929         struct drm_device *dev = crtc->dev;
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932         unsigned long flags;
2933         bool pending;
2934
2935         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2936             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2937                 return false;
2938
2939         spin_lock_irqsave(&dev->event_lock, flags);
2940         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2941         spin_unlock_irqrestore(&dev->event_lock, flags);
2942
2943         return pending;
2944 }
2945
2946 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2947 {
2948         struct drm_device *dev = crtc->dev;
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951         if (crtc->fb == NULL)
2952                 return;
2953
2954         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2955
2956         wait_event(dev_priv->pending_flip_queue,
2957                    !intel_crtc_has_pending_flip(crtc));
2958
2959         mutex_lock(&dev->struct_mutex);
2960         intel_finish_fb(crtc->fb);
2961         mutex_unlock(&dev->struct_mutex);
2962 }
2963
2964 /* Program iCLKIP clock to the desired frequency */
2965 static void lpt_program_iclkip(struct drm_crtc *crtc)
2966 {
2967         struct drm_device *dev = crtc->dev;
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
2970         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971         u32 temp;
2972
2973         mutex_lock(&dev_priv->dpio_lock);
2974
2975         /* It is necessary to ungate the pixclk gate prior to programming
2976          * the divisors, and gate it back when it is done.
2977          */
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980         /* Disable SSCCTL */
2981         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2982                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983                                 SBI_SSCCTL_DISABLE,
2984                         SBI_ICLK);
2985
2986         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2987         if (clock == 20000) {
2988                 auxdiv = 1;
2989                 divsel = 0x41;
2990                 phaseinc = 0x20;
2991         } else {
2992                 /* The iCLK virtual clock root frequency is in MHz,
2993                  * but the adjusted_mode->crtc_clock in in KHz. To get the
2994                  * divisors, it is necessary to divide one by another, so we
2995                  * convert the virtual clock precision to KHz here for higher
2996                  * precision.
2997                  */
2998                 u32 iclk_virtual_root_freq = 172800 * 1000;
2999                 u32 iclk_pi_range = 64;
3000                 u32 desired_divisor, msb_divisor_value, pi_value;
3001
3002                 desired_divisor = (iclk_virtual_root_freq / clock);
3003                 msb_divisor_value = desired_divisor / iclk_pi_range;
3004                 pi_value = desired_divisor % iclk_pi_range;
3005
3006                 auxdiv = 0;
3007                 divsel = msb_divisor_value - 2;
3008                 phaseinc = pi_value;
3009         }
3010
3011         /* This should not happen with any sane values */
3012         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3018                         clock,
3019                         auxdiv,
3020                         divsel,
3021                         phasedir,
3022                         phaseinc);
3023
3024         /* Program SSCDIVINTPHASE6 */
3025         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3026         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3032         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3033
3034         /* Program SSCAUXDIV */
3035         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3036         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3038         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3039
3040         /* Enable modulator and associated divider */
3041         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3042         temp &= ~SBI_SSCCTL_DISABLE;
3043         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3044
3045         /* Wait for initialization time */
3046         udelay(24);
3047
3048         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3049
3050         mutex_unlock(&dev_priv->dpio_lock);
3051 }
3052
3053 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3054                                                 enum pipe pch_transcoder)
3055 {
3056         struct drm_device *dev = crtc->base.dev;
3057         struct drm_i915_private *dev_priv = dev->dev_private;
3058         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3059
3060         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3061                    I915_READ(HTOTAL(cpu_transcoder)));
3062         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3063                    I915_READ(HBLANK(cpu_transcoder)));
3064         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3065                    I915_READ(HSYNC(cpu_transcoder)));
3066
3067         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3068                    I915_READ(VTOTAL(cpu_transcoder)));
3069         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3070                    I915_READ(VBLANK(cpu_transcoder)));
3071         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3072                    I915_READ(VSYNC(cpu_transcoder)));
3073         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3074                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3075 }
3076
3077 /*
3078  * Enable PCH resources required for PCH ports:
3079  *   - PCH PLLs
3080  *   - FDI training & RX/TX
3081  *   - update transcoder timings
3082  *   - DP transcoding bits
3083  *   - transcoder
3084  */
3085 static void ironlake_pch_enable(struct drm_crtc *crtc)
3086 {
3087         struct drm_device *dev = crtc->dev;
3088         struct drm_i915_private *dev_priv = dev->dev_private;
3089         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3090         int pipe = intel_crtc->pipe;
3091         u32 reg, temp;
3092
3093         assert_pch_transcoder_disabled(dev_priv, pipe);
3094
3095         /* Write the TU size bits before fdi link training, so that error
3096          * detection works. */
3097         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3098                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3099
3100         /* For PCH output, training FDI link */
3101         dev_priv->display.fdi_link_train(crtc);
3102
3103         /* We need to program the right clock selection before writing the pixel
3104          * mutliplier into the DPLL. */
3105         if (HAS_PCH_CPT(dev)) {
3106                 u32 sel;
3107
3108                 temp = I915_READ(PCH_DPLL_SEL);
3109                 temp |= TRANS_DPLL_ENABLE(pipe);
3110                 sel = TRANS_DPLLB_SEL(pipe);
3111                 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3112                         temp |= sel;
3113                 else
3114                         temp &= ~sel;
3115                 I915_WRITE(PCH_DPLL_SEL, temp);
3116         }
3117
3118         /* XXX: pch pll's can be enabled any time before we enable the PCH
3119          * transcoder, and we actually should do this to not upset any PCH
3120          * transcoder that already use the clock when we share it.
3121          *
3122          * Note that enable_shared_dpll tries to do the right thing, but
3123          * get_shared_dpll unconditionally resets the pll - we need that to have
3124          * the right LVDS enable sequence. */
3125         ironlake_enable_shared_dpll(intel_crtc);
3126
3127         /* set transcoder timing, panel must allow it */
3128         assert_panel_unlocked(dev_priv, pipe);
3129         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3130
3131         intel_fdi_normal_train(crtc);
3132
3133         /* For PCH DP, enable TRANS_DP_CTL */
3134         if (HAS_PCH_CPT(dev) &&
3135             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3136              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3137                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3138                 reg = TRANS_DP_CTL(pipe);
3139                 temp = I915_READ(reg);
3140                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3141                           TRANS_DP_SYNC_MASK |
3142                           TRANS_DP_BPC_MASK);
3143                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3144                          TRANS_DP_ENH_FRAMING);
3145                 temp |= bpc << 9; /* same format but at 11:9 */
3146
3147                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3148                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3149                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3150                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3151
3152                 switch (intel_trans_dp_port_sel(crtc)) {
3153                 case PCH_DP_B:
3154                         temp |= TRANS_DP_PORT_SEL_B;
3155                         break;
3156                 case PCH_DP_C:
3157                         temp |= TRANS_DP_PORT_SEL_C;
3158                         break;
3159                 case PCH_DP_D:
3160                         temp |= TRANS_DP_PORT_SEL_D;
3161                         break;
3162                 default:
3163                         BUG();
3164                 }
3165
3166                 I915_WRITE(reg, temp);
3167         }
3168
3169         ironlake_enable_pch_transcoder(dev_priv, pipe);
3170 }
3171
3172 static void lpt_pch_enable(struct drm_crtc *crtc)
3173 {
3174         struct drm_device *dev = crtc->dev;
3175         struct drm_i915_private *dev_priv = dev->dev_private;
3176         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3178
3179         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3180
3181         lpt_program_iclkip(crtc);
3182
3183         /* Set transcoder timing. */
3184         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3185
3186         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3187 }
3188
3189 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3190 {
3191         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3192
3193         if (pll == NULL)
3194                 return;
3195
3196         if (pll->refcount == 0) {
3197                 WARN(1, "bad %s refcount\n", pll->name);
3198                 return;
3199         }
3200
3201         if (--pll->refcount == 0) {
3202                 WARN_ON(pll->on);
3203                 WARN_ON(pll->active);
3204         }
3205
3206         crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3207 }
3208
3209 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3210 {
3211         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3212         struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3213         enum intel_dpll_id i;
3214
3215         if (pll) {
3216                 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3217                               crtc->base.base.id, pll->name);
3218                 intel_put_shared_dpll(crtc);
3219         }
3220
3221         if (HAS_PCH_IBX(dev_priv->dev)) {
3222                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3223                 i = (enum intel_dpll_id) crtc->pipe;
3224                 pll = &dev_priv->shared_dplls[i];
3225
3226                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3227                               crtc->base.base.id, pll->name);
3228
3229                 goto found;
3230         }
3231
3232         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3233                 pll = &dev_priv->shared_dplls[i];
3234
3235                 /* Only want to check enabled timings first */
3236                 if (pll->refcount == 0)
3237                         continue;
3238
3239                 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3240                            sizeof(pll->hw_state)) == 0) {
3241                         DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3242                                       crtc->base.base.id,
3243                                       pll->name, pll->refcount, pll->active);
3244
3245                         goto found;
3246                 }
3247         }
3248
3249         /* Ok no matching timings, maybe there's a free one? */
3250         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3251                 pll = &dev_priv->shared_dplls[i];
3252                 if (pll->refcount == 0) {
3253                         DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3254                                       crtc->base.base.id, pll->name);
3255                         goto found;
3256                 }
3257         }
3258
3259         return NULL;
3260
3261 found:
3262         crtc->config.shared_dpll = i;
3263         DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3264                          pipe_name(crtc->pipe));
3265
3266         if (pll->active == 0) {
3267                 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3268                        sizeof(pll->hw_state));
3269
3270                 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3271                 WARN_ON(pll->on);
3272                 assert_shared_dpll_disabled(dev_priv, pll);
3273
3274                 pll->mode_set(dev_priv, pll);
3275         }
3276         pll->refcount++;
3277
3278         return pll;
3279 }
3280
3281 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3282 {
3283         struct drm_i915_private *dev_priv = dev->dev_private;
3284         int dslreg = PIPEDSL(pipe);
3285         u32 temp;
3286
3287         temp = I915_READ(dslreg);
3288         udelay(500);
3289         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3290                 if (wait_for(I915_READ(dslreg) != temp, 5))
3291                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3292         }
3293 }
3294
3295 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3296 {
3297         struct drm_device *dev = crtc->base.dev;
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         int pipe = crtc->pipe;
3300
3301         if (crtc->config.pch_pfit.enabled) {
3302                 /* Force use of hard-coded filter coefficients
3303                  * as some pre-programmed values are broken,
3304                  * e.g. x201.
3305                  */
3306                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3307                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3308                                                  PF_PIPE_SEL_IVB(pipe));
3309                 else
3310                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3311                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3312                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3313         }
3314 }
3315
3316 static void intel_enable_planes(struct drm_crtc *crtc)
3317 {
3318         struct drm_device *dev = crtc->dev;
3319         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3320         struct intel_plane *intel_plane;
3321
3322         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3323                 if (intel_plane->pipe == pipe)
3324                         intel_plane_restore(&intel_plane->base);
3325 }
3326
3327 static void intel_disable_planes(struct drm_crtc *crtc)
3328 {
3329         struct drm_device *dev = crtc->dev;
3330         enum pipe pipe = to_intel_crtc(crtc)->pipe;
3331         struct intel_plane *intel_plane;
3332
3333         list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3334                 if (intel_plane->pipe == pipe)
3335                         intel_plane_disable(&intel_plane->base);
3336 }
3337
3338 void hsw_enable_ips(struct intel_crtc *crtc)
3339 {
3340         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3341
3342         if (!crtc->config.ips_enabled)
3343                 return;
3344
3345         /* We can only enable IPS after we enable a plane and wait for a vblank.
3346          * We guarantee that the plane is enabled by calling intel_enable_ips
3347          * only after intel_enable_plane. And intel_enable_plane already waits
3348          * for a vblank, so all we need to do here is to enable the IPS bit. */
3349         assert_plane_enabled(dev_priv, crtc->plane);
3350         I915_WRITE(IPS_CTL, IPS_ENABLE);
3351
3352         /* The bit only becomes 1 in the next vblank, so this wait here is
3353          * essentially intel_wait_for_vblank. If we don't have this and don't
3354          * wait for vblanks until the end of crtc_enable, then the HW state
3355          * readout code will complain that the expected IPS_CTL value is not the
3356          * one we read. */
3357         if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3358                 DRM_ERROR("Timed out waiting for IPS enable\n");
3359 }
3360
3361 void hsw_disable_ips(struct intel_crtc *crtc)
3362 {
3363         struct drm_device *dev = crtc->base.dev;
3364         struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366         if (!crtc->config.ips_enabled)
3367                 return;
3368
3369         assert_plane_enabled(dev_priv, crtc->plane);
3370         I915_WRITE(IPS_CTL, 0);
3371         POSTING_READ(IPS_CTL);
3372
3373         /* We need to wait for a vblank before we can disable the plane. */
3374         intel_wait_for_vblank(dev, crtc->pipe);
3375 }
3376
3377 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3378 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3379 {
3380         struct drm_device *dev = crtc->dev;
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383         enum pipe pipe = intel_crtc->pipe;
3384         int palreg = PALETTE(pipe);
3385         int i;
3386         bool reenable_ips = false;
3387
3388         /* The clocks have to be on to load the palette. */
3389         if (!crtc->enabled || !intel_crtc->active)
3390                 return;
3391
3392         if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3393                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3394                         assert_dsi_pll_enabled(dev_priv);
3395                 else
3396                         assert_pll_enabled(dev_priv, pipe);
3397         }
3398
3399         /* use legacy palette for Ironlake */
3400         if (HAS_PCH_SPLIT(dev))
3401                 palreg = LGC_PALETTE(pipe);
3402
3403         /* Workaround : Do not read or write the pipe palette/gamma data while
3404          * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3405          */
3406         if (intel_crtc->config.ips_enabled &&
3407             ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3408              GAMMA_MODE_MODE_SPLIT)) {
3409                 hsw_disable_ips(intel_crtc);
3410                 reenable_ips = true;
3411         }
3412
3413         for (i = 0; i < 256; i++) {
3414                 I915_WRITE(palreg + 4 * i,
3415                            (intel_crtc->lut_r[i] << 16) |
3416                            (intel_crtc->lut_g[i] << 8) |
3417                            intel_crtc->lut_b[i]);
3418         }
3419
3420         if (reenable_ips)
3421                 hsw_enable_ips(intel_crtc);
3422 }
3423
3424 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3425 {
3426         struct drm_device *dev = crtc->dev;
3427         struct drm_i915_private *dev_priv = dev->dev_private;
3428         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3429         struct intel_encoder *encoder;
3430         int pipe = intel_crtc->pipe;
3431         int plane = intel_crtc->plane;
3432
3433         WARN_ON(!crtc->enabled);
3434
3435         if (intel_crtc->active)
3436                 return;
3437
3438         intel_crtc->active = true;
3439
3440         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3441         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3442
3443         for_each_encoder_on_crtc(dev, crtc, encoder)
3444                 if (encoder->pre_enable)
3445                         encoder->pre_enable(encoder);
3446
3447         if (intel_crtc->config.has_pch_encoder) {
3448                 /* Note: FDI PLL enabling _must_ be done before we enable the
3449                  * cpu pipes, hence this is separate from all the other fdi/pch
3450                  * enabling. */
3451                 ironlake_fdi_pll_enable(intel_crtc);
3452         } else {
3453                 assert_fdi_tx_disabled(dev_priv, pipe);
3454                 assert_fdi_rx_disabled(dev_priv, pipe);
3455         }
3456
3457         ironlake_pfit_enable(intel_crtc);
3458
3459         /*
3460          * On ILK+ LUT must be loaded before the pipe is running but with
3461          * clocks enabled
3462          */
3463         intel_crtc_load_lut(crtc);
3464
3465         intel_update_watermarks(crtc);
3466         intel_enable_pipe(dev_priv, pipe,
3467                           intel_crtc->config.has_pch_encoder, false);
3468         intel_enable_primary_plane(dev_priv, plane, pipe);
3469         intel_enable_planes(crtc);
3470         intel_crtc_update_cursor(crtc, true);
3471
3472         if (intel_crtc->config.has_pch_encoder)
3473                 ironlake_pch_enable(crtc);
3474
3475         mutex_lock(&dev->struct_mutex);
3476         intel_update_fbc(dev);
3477         mutex_unlock(&dev->struct_mutex);
3478
3479         for_each_encoder_on_crtc(dev, crtc, encoder)
3480                 encoder->enable(encoder);
3481
3482         if (HAS_PCH_CPT(dev))
3483                 cpt_verify_modeset(dev, intel_crtc->pipe);
3484
3485         /*
3486          * There seems to be a race in PCH platform hw (at least on some
3487          * outputs) where an enabled pipe still completes any pageflip right
3488          * away (as if the pipe is off) instead of waiting for vblank. As soon
3489          * as the first vblank happend, everything works as expected. Hence just
3490          * wait for one vblank before returning to avoid strange things
3491          * happening.
3492          */
3493         intel_wait_for_vblank(dev, intel_crtc->pipe);
3494 }
3495
3496 /* IPS only exists on ULT machines and is tied to pipe A. */
3497 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3498 {
3499         return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3500 }
3501
3502 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         int pipe = intel_crtc->pipe;
3508         int plane = intel_crtc->plane;
3509
3510         intel_enable_primary_plane(dev_priv, plane, pipe);
3511         intel_enable_planes(crtc);
3512         intel_crtc_update_cursor(crtc, true);
3513
3514         hsw_enable_ips(intel_crtc);
3515
3516         mutex_lock(&dev->struct_mutex);
3517         intel_update_fbc(dev);
3518         mutex_unlock(&dev->struct_mutex);
3519 }
3520
3521 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3522 {
3523         struct drm_device *dev = crtc->dev;
3524         struct drm_i915_private *dev_priv = dev->dev_private;
3525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526         int pipe = intel_crtc->pipe;
3527         int plane = intel_crtc->plane;
3528
3529         intel_crtc_wait_for_pending_flips(crtc);
3530         drm_vblank_off(dev, pipe);
3531
3532         /* FBC must be disabled before disabling the plane on HSW. */
3533         if (dev_priv->fbc.plane == plane)
3534                 intel_disable_fbc(dev);
3535
3536         hsw_disable_ips(intel_crtc);
3537
3538         intel_crtc_update_cursor(crtc, false);
3539         intel_disable_planes(crtc);
3540         intel_disable_primary_plane(dev_priv, plane, pipe);
3541 }
3542
3543 /*
3544  * This implements the workaround described in the "notes" section of the mode
3545  * set sequence documentation. When going from no pipes or single pipe to
3546  * multiple pipes, and planes are enabled after the pipe, we need to wait at
3547  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3548  */
3549 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3550 {
3551         struct drm_device *dev = crtc->base.dev;
3552         struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3553
3554         /* We want to get the other_active_crtc only if there's only 1 other
3555          * active crtc. */
3556         list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3557                 if (!crtc_it->active || crtc_it == crtc)
3558                         continue;
3559
3560                 if (other_active_crtc)
3561                         return;
3562
3563                 other_active_crtc = crtc_it;
3564         }
3565         if (!other_active_crtc)
3566                 return;
3567
3568         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3569         intel_wait_for_vblank(dev, other_active_crtc->pipe);
3570 }
3571
3572 static void haswell_crtc_enable(struct drm_crtc *crtc)
3573 {
3574         struct drm_device *dev = crtc->dev;
3575         struct drm_i915_private *dev_priv = dev->dev_private;
3576         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3577         struct intel_encoder *encoder;
3578         int pipe = intel_crtc->pipe;
3579
3580         WARN_ON(!crtc->enabled);
3581
3582         if (intel_crtc->active)
3583                 return;
3584
3585         intel_crtc->active = true;
3586
3587         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3588         if (intel_crtc->config.has_pch_encoder)
3589                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3590
3591         if (intel_crtc->config.has_pch_encoder)
3592                 dev_priv->display.fdi_link_train(crtc);
3593
3594         for_each_encoder_on_crtc(dev, crtc, encoder)
3595                 if (encoder->pre_enable)
3596                         encoder->pre_enable(encoder);
3597
3598         intel_ddi_enable_pipe_clock(intel_crtc);
3599
3600         ironlake_pfit_enable(intel_crtc);
3601
3602         /*
3603          * On ILK+ LUT must be loaded before the pipe is running but with
3604          * clocks enabled
3605          */
3606         intel_crtc_load_lut(crtc);
3607
3608         intel_ddi_set_pipe_settings(crtc);
3609         intel_ddi_enable_transcoder_func(crtc);
3610
3611         intel_update_watermarks(crtc);
3612         intel_enable_pipe(dev_priv, pipe,
3613                           intel_crtc->config.has_pch_encoder, false);
3614
3615         if (intel_crtc->config.has_pch_encoder)
3616                 lpt_pch_enable(crtc);
3617
3618         for_each_encoder_on_crtc(dev, crtc, encoder) {
3619                 encoder->enable(encoder);
3620                 intel_opregion_notify_encoder(encoder, true);
3621         }
3622
3623         /* If we change the relative order between pipe/planes enabling, we need
3624          * to change the workaround. */
3625         haswell_mode_set_planes_workaround(intel_crtc);
3626         haswell_crtc_enable_planes(crtc);
3627
3628         /*
3629          * There seems to be a race in PCH platform hw (at least on some
3630          * outputs) where an enabled pipe still completes any pageflip right
3631          * away (as if the pipe is off) instead of waiting for vblank. As soon
3632          * as the first vblank happend, everything works as expected. Hence just
3633          * wait for one vblank before returning to avoid strange things
3634          * happening.
3635          */
3636         intel_wait_for_vblank(dev, intel_crtc->pipe);
3637 }
3638
3639 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3640 {
3641         struct drm_device *dev = crtc->base.dev;
3642         struct drm_i915_private *dev_priv = dev->dev_private;
3643         int pipe = crtc->pipe;
3644
3645         /* To avoid upsetting the power well on haswell only disable the pfit if
3646          * it's in use. The hw state code will make sure we get this right. */
3647         if (crtc->config.pch_pfit.enabled) {
3648                 I915_WRITE(PF_CTL(pipe), 0);
3649                 I915_WRITE(PF_WIN_POS(pipe), 0);
3650                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3651         }
3652 }
3653
3654 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3655 {
3656         struct drm_device *dev = crtc->dev;
3657         struct drm_i915_private *dev_priv = dev->dev_private;
3658         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659         struct intel_encoder *encoder;
3660         int pipe = intel_crtc->pipe;
3661         int plane = intel_crtc->plane;
3662         u32 reg, temp;
3663
3664
3665         if (!intel_crtc->active)
3666                 return;
3667
3668         for_each_encoder_on_crtc(dev, crtc, encoder)
3669                 encoder->disable(encoder);
3670
3671         intel_crtc_wait_for_pending_flips(crtc);
3672         drm_vblank_off(dev, pipe);
3673
3674         if (dev_priv->fbc.plane == plane)
3675                 intel_disable_fbc(dev);
3676
3677         intel_crtc_update_cursor(crtc, false);
3678         intel_disable_planes(crtc);
3679         intel_disable_primary_plane(dev_priv, plane, pipe);
3680
3681         if (intel_crtc->config.has_pch_encoder)
3682                 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3683
3684         intel_disable_pipe(dev_priv, pipe);
3685
3686         ironlake_pfit_disable(intel_crtc);
3687
3688         for_each_encoder_on_crtc(dev, crtc, encoder)
3689                 if (encoder->post_disable)
3690                         encoder->post_disable(encoder);
3691
3692         if (intel_crtc->config.has_pch_encoder) {
3693                 ironlake_fdi_disable(crtc);
3694
3695                 ironlake_disable_pch_transcoder(dev_priv, pipe);
3696                 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3697
3698                 if (HAS_PCH_CPT(dev)) {
3699                         /* disable TRANS_DP_CTL */
3700                         reg = TRANS_DP_CTL(pipe);
3701                         temp = I915_READ(reg);
3702                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3703                                   TRANS_DP_PORT_SEL_MASK);
3704                         temp |= TRANS_DP_PORT_SEL_NONE;
3705                         I915_WRITE(reg, temp);
3706
3707                         /* disable DPLL_SEL */
3708                         temp = I915_READ(PCH_DPLL_SEL);
3709                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3710                         I915_WRITE(PCH_DPLL_SEL, temp);
3711                 }
3712
3713                 /* disable PCH DPLL */
3714                 intel_disable_shared_dpll(intel_crtc);
3715
3716                 ironlake_fdi_pll_disable(intel_crtc);
3717         }
3718
3719         intel_crtc->active = false;
3720         intel_update_watermarks(crtc);
3721
3722         mutex_lock(&dev->struct_mutex);
3723         intel_update_fbc(dev);
3724         mutex_unlock(&dev->struct_mutex);
3725 }
3726
3727 static void haswell_crtc_disable(struct drm_crtc *crtc)
3728 {
3729         struct drm_device *dev = crtc->dev;
3730         struct drm_i915_private *dev_priv = dev->dev_private;
3731         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3732         struct intel_encoder *encoder;
3733         int pipe = intel_crtc->pipe;
3734         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3735
3736         if (!intel_crtc->active)
3737                 return;
3738
3739         haswell_crtc_disable_planes(crtc);
3740
3741         for_each_encoder_on_crtc(dev, crtc, encoder) {
3742                 intel_opregion_notify_encoder(encoder, false);
3743                 encoder->disable(encoder);
3744         }
3745
3746         if (intel_crtc->config.has_pch_encoder)
3747                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3748         intel_disable_pipe(dev_priv, pipe);
3749
3750         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3751
3752         ironlake_pfit_disable(intel_crtc);
3753
3754         intel_ddi_disable_pipe_clock(intel_crtc);
3755
3756         for_each_encoder_on_crtc(dev, crtc, encoder)
3757                 if (encoder->post_disable)
3758                         encoder->post_disable(encoder);
3759
3760         if (intel_crtc->config.has_pch_encoder) {
3761                 lpt_disable_pch_transcoder(dev_priv);
3762                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3763                 intel_ddi_fdi_disable(crtc);
3764         }
3765
3766         intel_crtc->active = false;
3767         intel_update_watermarks(crtc);
3768
3769         mutex_lock(&dev->struct_mutex);
3770         intel_update_fbc(dev);
3771         mutex_unlock(&dev->struct_mutex);
3772 }
3773
3774 static void ironlake_crtc_off(struct drm_crtc *crtc)
3775 {
3776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777         intel_put_shared_dpll(intel_crtc);
3778 }
3779
3780 static void haswell_crtc_off(struct drm_crtc *crtc)
3781 {
3782         intel_ddi_put_crtc_pll(crtc);
3783 }
3784
3785 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3786 {
3787         if (!enable && intel_crtc->overlay) {
3788                 struct drm_device *dev = intel_crtc->base.dev;
3789                 struct drm_i915_private *dev_priv = dev->dev_private;
3790
3791                 mutex_lock(&dev->struct_mutex);
3792                 dev_priv->mm.interruptible = false;
3793                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3794                 dev_priv->mm.interruptible = true;
3795                 mutex_unlock(&dev->struct_mutex);
3796         }
3797
3798         /* Let userspace switch the overlay on again. In most cases userspace
3799          * has to recompute where to put it anyway.
3800          */
3801 }
3802
3803 /**
3804  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3805  * cursor plane briefly if not already running after enabling the display
3806  * plane.
3807  * This workaround avoids occasional blank screens when self refresh is
3808  * enabled.
3809  */
3810 static void
3811 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3812 {
3813         u32 cntl = I915_READ(CURCNTR(pipe));
3814
3815         if ((cntl & CURSOR_MODE) == 0) {
3816                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3817
3818                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3819                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3820                 intel_wait_for_vblank(dev_priv->dev, pipe);
3821                 I915_WRITE(CURCNTR(pipe), cntl);
3822                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3823                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3824         }
3825 }
3826
3827 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3828 {
3829         struct drm_device *dev = crtc->base.dev;
3830         struct drm_i915_private *dev_priv = dev->dev_private;
3831         struct intel_crtc_config *pipe_config = &crtc->config;
3832
3833         if (!crtc->config.gmch_pfit.control)
3834                 return;
3835
3836         /*
3837          * The panel fitter should only be adjusted whilst the pipe is disabled,
3838          * according to register description and PRM.
3839          */
3840         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3841         assert_pipe_disabled(dev_priv, crtc->pipe);
3842
3843         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3844         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3845
3846         /* Border color in case we don't scale up to the full screen. Black by
3847          * default, change to something else for debugging. */
3848         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3849 }
3850
3851 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3852 {
3853         struct drm_device *dev = crtc->dev;
3854         struct drm_i915_private *dev_priv = dev->dev_private;
3855         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856         struct intel_encoder *encoder;
3857         int pipe = intel_crtc->pipe;
3858         int plane = intel_crtc->plane;
3859         bool is_dsi;
3860
3861         WARN_ON(!crtc->enabled);
3862
3863         if (intel_crtc->active)
3864                 return;
3865
3866         intel_crtc->active = true;
3867
3868         for_each_encoder_on_crtc(dev, crtc, encoder)
3869                 if (encoder->pre_pll_enable)
3870                         encoder->pre_pll_enable(encoder);
3871
3872         is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3873
3874         if (!is_dsi)
3875                 vlv_enable_pll(intel_crtc);
3876
3877         for_each_encoder_on_crtc(dev, crtc, encoder)
3878                 if (encoder->pre_enable)
3879                         encoder->pre_enable(encoder);
3880
3881         i9xx_pfit_enable(intel_crtc);
3882
3883         intel_crtc_load_lut(crtc);
3884
3885         intel_update_watermarks(crtc);
3886         intel_enable_pipe(dev_priv, pipe, false, is_dsi);
3887         intel_enable_primary_plane(dev_priv, plane, pipe);
3888         intel_enable_planes(crtc);
3889         intel_crtc_update_cursor(crtc, true);
3890
3891         intel_update_fbc(dev);
3892
3893         for_each_encoder_on_crtc(dev, crtc, encoder)
3894                 encoder->enable(encoder);
3895 }
3896
3897 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3898 {
3899         struct drm_device *dev = crtc->dev;
3900         struct drm_i915_private *dev_priv = dev->dev_private;
3901         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3902         struct intel_encoder *encoder;
3903         int pipe = intel_crtc->pipe;
3904         int plane = intel_crtc->plane;
3905
3906         WARN_ON(!crtc->enabled);
3907
3908         if (intel_crtc->active)
3909                 return;
3910
3911         intel_crtc->active = true;
3912
3913         for_each_encoder_on_crtc(dev, crtc, encoder)
3914                 if (encoder->pre_enable)
3915                         encoder->pre_enable(encoder);
3916
3917         i9xx_enable_pll(intel_crtc);
3918
3919         i9xx_pfit_enable(intel_crtc);
3920
3921         intel_crtc_load_lut(crtc);
3922
3923         intel_update_watermarks(crtc);
3924         intel_enable_pipe(dev_priv, pipe, false, false);
3925         intel_enable_primary_plane(dev_priv, plane, pipe);
3926         intel_enable_planes(crtc);
3927         /* The fixup needs to happen before cursor is enabled */
3928         if (IS_G4X(dev))
3929                 g4x_fixup_plane(dev_priv, pipe);
3930         intel_crtc_update_cursor(crtc, true);
3931
3932         /* Give the overlay scaler a chance to enable if it's on this pipe */
3933         intel_crtc_dpms_overlay(intel_crtc, true);
3934
3935         intel_update_fbc(dev);
3936
3937         for_each_encoder_on_crtc(dev, crtc, encoder)
3938                 encoder->enable(encoder);
3939 }
3940
3941 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3942 {
3943         struct drm_device *dev = crtc->base.dev;
3944         struct drm_i915_private *dev_priv = dev->dev_private;
3945
3946         if (!crtc->config.gmch_pfit.control)
3947                 return;
3948
3949         assert_pipe_disabled(dev_priv, crtc->pipe);
3950
3951         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3952                          I915_READ(PFIT_CONTROL));
3953         I915_WRITE(PFIT_CONTROL, 0);
3954 }
3955
3956 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3957 {
3958         struct drm_device *dev = crtc->dev;
3959         struct drm_i915_private *dev_priv = dev->dev_private;
3960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3961         struct intel_encoder *encoder;
3962         int pipe = intel_crtc->pipe;
3963         int plane = intel_crtc->plane;
3964
3965         if (!intel_crtc->active)
3966                 return;
3967
3968         for_each_encoder_on_crtc(dev, crtc, encoder)
3969                 encoder->disable(encoder);
3970
3971         /* Give the overlay scaler a chance to disable if it's on this pipe */
3972         intel_crtc_wait_for_pending_flips(crtc);
3973         drm_vblank_off(dev, pipe);
3974
3975         if (dev_priv->fbc.plane == plane)
3976                 intel_disable_fbc(dev);
3977
3978         intel_crtc_dpms_overlay(intel_crtc, false);
3979         intel_crtc_update_cursor(crtc, false);
3980         intel_disable_planes(crtc);
3981         intel_disable_primary_plane(dev_priv, plane, pipe);
3982
3983         intel_disable_pipe(dev_priv, pipe);
3984
3985         i9xx_pfit_disable(intel_crtc);
3986
3987         for_each_encoder_on_crtc(dev, crtc, encoder)
3988                 if (encoder->post_disable)
3989                         encoder->post_disable(encoder);
3990
3991         if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3992                 vlv_disable_pll(dev_priv, pipe);
3993         else if (!IS_VALLEYVIEW(dev))
3994                 i9xx_disable_pll(dev_priv, pipe);
3995
3996         intel_crtc->active = false;
3997         intel_update_watermarks(crtc);
3998
3999         intel_update_fbc(dev);
4000 }
4001
4002 static void i9xx_crtc_off(struct drm_crtc *crtc)
4003 {
4004 }
4005
4006 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4007                                     bool enabled)
4008 {
4009         struct drm_device *dev = crtc->dev;
4010         struct drm_i915_master_private *master_priv;
4011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4012         int pipe = intel_crtc->pipe;
4013
4014         if (!dev->primary->master)
4015                 return;
4016
4017         master_priv = dev->primary->master->driver_priv;
4018         if (!master_priv->sarea_priv)
4019                 return;
4020
4021         switch (pipe) {
4022         case 0:
4023                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4024                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4025                 break;
4026         case 1:
4027                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4028                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4029                 break;
4030         default:
4031                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4032                 break;
4033         }
4034 }
4035
4036 /**
4037  * Sets the power management mode of the pipe and plane.
4038  */
4039 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4040 {
4041         struct drm_device *dev = crtc->dev;
4042         struct drm_i915_private *dev_priv = dev->dev_private;
4043         struct intel_encoder *intel_encoder;
4044         bool enable = false;
4045
4046         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4047                 enable |= intel_encoder->connectors_active;
4048
4049         if (enable)
4050                 dev_priv->display.crtc_enable(crtc);
4051         else
4052                 dev_priv->display.crtc_disable(crtc);
4053
4054         intel_crtc_update_sarea(crtc, enable);
4055 }
4056
4057 static void intel_crtc_disable(struct drm_crtc *crtc)
4058 {
4059         struct drm_device *dev = crtc->dev;
4060         struct drm_connector *connector;
4061         struct drm_i915_private *dev_priv = dev->dev_private;
4062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063
4064         /* crtc should still be enabled when we disable it. */
4065         WARN_ON(!crtc->enabled);
4066
4067         dev_priv->display.crtc_disable(crtc);
4068         intel_crtc->eld_vld = false;
4069         intel_crtc_update_sarea(crtc, false);
4070         dev_priv->display.off(crtc);
4071
4072         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4073         assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4074         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4075
4076         if (crtc->fb) {
4077                 mutex_lock(&dev->struct_mutex);
4078                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4079                 mutex_unlock(&dev->struct_mutex);
4080                 crtc->fb = NULL;
4081         }
4082
4083         /* Update computed state. */
4084         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4085                 if (!connector->encoder || !connector->encoder->crtc)
4086                         continue;
4087
4088                 if (connector->encoder->crtc != crtc)
4089                         continue;
4090
4091                 connector->dpms = DRM_MODE_DPMS_OFF;
4092                 to_intel_encoder(connector->encoder)->connectors_active = false;
4093         }
4094 }
4095
4096 void intel_encoder_destroy(struct drm_encoder *encoder)
4097 {
4098         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4099
4100         drm_encoder_cleanup(encoder);
4101         kfree(intel_encoder);
4102 }
4103
4104 /* Simple dpms helper for encoders with just one connector, no cloning and only
4105  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4106  * state of the entire output pipe. */
4107 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4108 {
4109         if (mode == DRM_MODE_DPMS_ON) {
4110                 encoder->connectors_active = true;
4111
4112                 intel_crtc_update_dpms(encoder->base.crtc);
4113         } else {
4114                 encoder->connectors_active = false;
4115
4116                 intel_crtc_update_dpms(encoder->base.crtc);
4117         }
4118 }
4119
4120 /* Cross check the actual hw state with our own modeset state tracking (and it's
4121  * internal consistency). */
4122 static void intel_connector_check_state(struct intel_connector *connector)
4123 {
4124         if (connector->get_hw_state(connector)) {
4125                 struct intel_encoder *encoder = connector->encoder;
4126                 struct drm_crtc *crtc;
4127                 bool encoder_enabled;
4128                 enum pipe pipe;
4129
4130                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4131                               connector->base.base.id,
4132                               drm_get_connector_name(&connector->base));
4133
4134                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4135                      "wrong connector dpms state\n");
4136                 WARN(connector->base.encoder != &encoder->base,
4137                      "active connector not linked to encoder\n");
4138                 WARN(!encoder->connectors_active,
4139                      "encoder->connectors_active not set\n");
4140
4141                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4142                 WARN(!encoder_enabled, "encoder not enabled\n");
4143                 if (WARN_ON(!encoder->base.crtc))
4144                         return;
4145
4146                 crtc = encoder->base.crtc;
4147
4148                 WARN(!crtc->enabled, "crtc not enabled\n");
4149                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4150                 WARN(pipe != to_intel_crtc(crtc)->pipe,
4151                      "encoder active on the wrong pipe\n");
4152         }
4153 }
4154
4155 /* Even simpler default implementation, if there's really no special case to
4156  * consider. */
4157 void intel_connector_dpms(struct drm_connector *connector, int mode)
4158 {
4159         struct intel_encoder *encoder = intel_attached_encoder(connector);
4160
4161         /* All the simple cases only support two dpms states. */
4162         if (mode != DRM_MODE_DPMS_ON)
4163                 mode = DRM_MODE_DPMS_OFF;
4164
4165         if (mode == connector->dpms)
4166                 return;
4167
4168         connector->dpms = mode;
4169
4170         /* Only need to change hw state when actually enabled */
4171         if (encoder->base.crtc)
4172                 intel_encoder_dpms(encoder, mode);
4173         else
4174                 WARN_ON(encoder->connectors_active != false);
4175
4176         intel_modeset_check_state(connector->dev);
4177 }
4178
4179 /* Simple connector->get_hw_state implementation for encoders that support only
4180  * one connector and no cloning and hence the encoder state determines the state
4181  * of the connector. */
4182 bool intel_connector_get_hw_state(struct intel_connector *connector)
4183 {
4184         enum pipe pipe = 0;
4185         struct intel_encoder *encoder = connector->encoder;
4186
4187         return encoder->get_hw_state(encoder, &pipe);
4188 }
4189
4190 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4191                                      struct intel_crtc_config *pipe_config)
4192 {
4193         struct drm_i915_private *dev_priv = dev->dev_private;
4194         struct intel_crtc *pipe_B_crtc =
4195                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4196
4197         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4198                       pipe_name(pipe), pipe_config->fdi_lanes);
4199         if (pipe_config->fdi_lanes > 4) {
4200                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4201                               pipe_name(pipe), pipe_config->fdi_lanes);
4202                 return false;
4203         }
4204
4205         if (IS_HASWELL(dev)) {
4206                 if (pipe_config->fdi_lanes > 2) {
4207                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4208                                       pipe_config->fdi_lanes);
4209                         return false;
4210                 } else {
4211                         return true;
4212                 }
4213         }
4214
4215         if (INTEL_INFO(dev)->num_pipes == 2)
4216                 return true;
4217
4218         /* Ivybridge 3 pipe is really complicated */
4219         switch (pipe) {
4220         case PIPE_A:
4221                 return true;
4222         case PIPE_B:
4223                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4224                     pipe_config->fdi_lanes > 2) {
4225                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4226                                       pipe_name(pipe), pipe_config->fdi_lanes);
4227                         return false;
4228                 }
4229                 return true;
4230         case PIPE_C:
4231                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4232                     pipe_B_crtc->config.fdi_lanes <= 2) {
4233                         if (pipe_config->fdi_lanes > 2) {
4234                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4235                                               pipe_name(pipe), pipe_config->fdi_lanes);
4236                                 return false;
4237                         }
4238                 } else {
4239                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4240                         return false;
4241                 }
4242                 return true;
4243         default:
4244                 BUG();
4245         }
4246 }
4247
4248 #define RETRY 1
4249 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4250                                        struct intel_crtc_config *pipe_config)
4251 {
4252         struct drm_device *dev = intel_crtc->base.dev;
4253         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4254         int lane, link_bw, fdi_dotclock;
4255         bool setup_ok, needs_recompute = false;
4256
4257 retry:
4258         /* FDI is a binary signal running at ~2.7GHz, encoding
4259          * each output octet as 10 bits. The actual frequency
4260          * is stored as a divider into a 100MHz clock, and the
4261          * mode pixel clock is stored in units of 1KHz.
4262          * Hence the bw of each lane in terms of the mode signal
4263          * is:
4264          */
4265         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4266
4267         fdi_dotclock = adjusted_mode->crtc_clock;
4268
4269         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4270                                            pipe_config->pipe_bpp);
4271
4272         pipe_config->fdi_lanes = lane;
4273
4274         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4275                                link_bw, &pipe_config->fdi_m_n);
4276
4277         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4278                                             intel_crtc->pipe, pipe_config);
4279         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4280                 pipe_config->pipe_bpp -= 2*3;
4281                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4282                               pipe_config->pipe_bpp);
4283                 needs_recompute = true;
4284                 pipe_config->bw_constrained = true;
4285
4286                 goto retry;
4287         }
4288
4289         if (needs_recompute)
4290                 return RETRY;
4291
4292         return setup_ok ? 0 : -EINVAL;
4293 }
4294
4295 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4296                                    struct intel_crtc_config *pipe_config)
4297 {
4298         pipe_config->ips_enabled = i915_enable_ips &&
4299                                    hsw_crtc_supports_ips(crtc) &&
4300                                    pipe_config->pipe_bpp <= 24;
4301 }
4302
4303 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4304                                      struct intel_crtc_config *pipe_config)
4305 {
4306         struct drm_device *dev = crtc->base.dev;
4307         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4308
4309         /* FIXME should check pixel clock limits on all platforms */
4310         if (INTEL_INFO(dev)->gen < 4) {
4311                 struct drm_i915_private *dev_priv = dev->dev_private;
4312                 int clock_limit =
4313                         dev_priv->display.get_display_clock_speed(dev);
4314
4315                 /*
4316                  * Enable pixel doubling when the dot clock
4317                  * is > 90% of the (display) core speed.
4318                  *
4319                  * GDG double wide on either pipe,
4320                  * otherwise pipe A only.
4321                  */
4322                 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4323                     adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4324                         clock_limit *= 2;
4325                         pipe_config->double_wide = true;
4326                 }
4327
4328                 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4329                         return -EINVAL;
4330         }
4331
4332         /*
4333          * Pipe horizontal size must be even in:
4334          * - DVO ganged mode
4335          * - LVDS dual channel mode
4336          * - Double wide pipe
4337          */
4338         if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4339              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4340                 pipe_config->pipe_src_w &= ~1;
4341
4342         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4343          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4344          */
4345         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4346                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4347                 return -EINVAL;
4348
4349         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4350                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4351         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4352                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4353                  * for lvds. */
4354                 pipe_config->pipe_bpp = 8*3;
4355         }
4356
4357         if (HAS_IPS(dev))
4358                 hsw_compute_ips_config(crtc, pipe_config);
4359
4360         /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4361          * clock survives for now. */
4362         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4363                 pipe_config->shared_dpll = crtc->config.shared_dpll;
4364
4365         if (pipe_config->has_pch_encoder)
4366                 return ironlake_fdi_compute_config(crtc, pipe_config);
4367
4368         return 0;
4369 }
4370
4371 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4372 {
4373         return 400000; /* FIXME */
4374 }
4375
4376 static int i945_get_display_clock_speed(struct drm_device *dev)
4377 {
4378         return 400000;
4379 }
4380
4381 static int i915_get_display_clock_speed(struct drm_device *dev)
4382 {
4383         return 333000;
4384 }
4385
4386 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4387 {
4388         return 200000;
4389 }
4390
4391 static int pnv_get_display_clock_speed(struct drm_device *dev)
4392 {
4393         u16 gcfgc = 0;
4394
4395         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4396
4397         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4398         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4399                 return 267000;
4400         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4401                 return 333000;
4402         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4403                 return 444000;
4404         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4405                 return 200000;
4406         default:
4407                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4408         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4409                 return 133000;
4410         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4411                 return 167000;
4412         }
4413 }
4414
4415 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4416 {
4417         u16 gcfgc = 0;
4418
4419         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4420
4421         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4422                 return 133000;
4423         else {
4424                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4425                 case GC_DISPLAY_CLOCK_333_MHZ:
4426                         return 333000;
4427                 default:
4428                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4429                         return 190000;
4430                 }
4431         }
4432 }
4433
4434 static int i865_get_display_clock_speed(struct drm_device *dev)
4435 {
4436         return 266000;
4437 }
4438
4439 static int i855_get_display_clock_speed(struct drm_device *dev)
4440 {
4441         u16 hpllcc = 0;
4442         /* Assume that the hardware is in the high speed state.  This
4443          * should be the default.
4444          */
4445         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4446         case GC_CLOCK_133_200:
4447         case GC_CLOCK_100_200:
4448                 return 200000;
4449         case GC_CLOCK_166_250:
4450                 return 250000;
4451         case GC_CLOCK_100_133:
4452                 return 133000;
4453         }
4454
4455         /* Shouldn't happen */
4456         return 0;
4457 }
4458
4459 static int i830_get_display_clock_speed(struct drm_device *dev)
4460 {
4461         return 133000;
4462 }
4463
4464 static void
4465 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4466 {
4467         while (*num > DATA_LINK_M_N_MASK ||
4468                *den > DATA_LINK_M_N_MASK) {
4469                 *num >>= 1;
4470                 *den >>= 1;
4471         }
4472 }
4473
4474 static void compute_m_n(unsigned int m, unsigned int n,
4475                         uint32_t *ret_m, uint32_t *ret_n)
4476 {
4477         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4478         *ret_m = div_u64((uint64_t) m * *ret_n, n);
4479         intel_reduce_m_n_ratio(ret_m, ret_n);
4480 }
4481
4482 void
4483 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4484                        int pixel_clock, int link_clock,
4485                        struct intel_link_m_n *m_n)
4486 {
4487         m_n->tu = 64;
4488
4489         compute_m_n(bits_per_pixel * pixel_clock,
4490                     link_clock * nlanes * 8,
4491                     &m_n->gmch_m, &m_n->gmch_n);
4492
4493         compute_m_n(pixel_clock, link_clock,
4494                     &m_n->link_m, &m_n->link_n);
4495 }
4496
4497 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4498 {
4499         if (i915_panel_use_ssc >= 0)
4500                 return i915_panel_use_ssc != 0;
4501         return dev_priv->vbt.lvds_use_ssc
4502                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4503 }
4504
4505 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4506 {
4507         struct drm_device *dev = crtc->dev;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         int refclk;
4510
4511         if (IS_VALLEYVIEW(dev)) {
4512                 refclk = 100000;
4513         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4514             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4515                 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4516                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4517                               refclk / 1000);
4518         } else if (!IS_GEN2(dev)) {
4519                 refclk = 96000;
4520         } else {
4521                 refclk = 48000;
4522         }
4523
4524         return refclk;
4525 }
4526
4527 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4528 {
4529         return (1 << dpll->n) << 16 | dpll->m2;
4530 }
4531
4532 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4533 {
4534         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4535 }
4536
4537 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4538                                      intel_clock_t *reduced_clock)
4539 {
4540         struct drm_device *dev = crtc->base.dev;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         int pipe = crtc->pipe;
4543         u32 fp, fp2 = 0;
4544
4545         if (IS_PINEVIEW(dev)) {
4546                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4547                 if (reduced_clock)
4548                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4549         } else {
4550                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4551                 if (reduced_clock)
4552                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4553         }
4554
4555         I915_WRITE(FP0(pipe), fp);
4556         crtc->config.dpll_hw_state.fp0 = fp;
4557
4558         crtc->lowfreq_avail = false;
4559         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4560             reduced_clock && i915_powersave) {
4561                 I915_WRITE(FP1(pipe), fp2);
4562                 crtc->config.dpll_hw_state.fp1 = fp2;
4563                 crtc->lowfreq_avail = true;
4564         } else {
4565                 I915_WRITE(FP1(pipe), fp);
4566                 crtc->config.dpll_hw_state.fp1 = fp;
4567         }
4568 }
4569
4570 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4571                 pipe)
4572 {
4573         u32 reg_val;
4574
4575         /*
4576          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4577          * and set it to a reasonable value instead.
4578          */
4579         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4580         reg_val &= 0xffffff00;
4581         reg_val |= 0x00000030;
4582         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4583
4584         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4585         reg_val &= 0x8cffffff;
4586         reg_val = 0x8c000000;
4587         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4588
4589         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
4590         reg_val &= 0xffffff00;
4591         vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
4592
4593         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
4594         reg_val &= 0x00ffffff;
4595         reg_val |= 0xb0000000;
4596         vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
4597 }
4598
4599 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4600                                          struct intel_link_m_n *m_n)
4601 {
4602         struct drm_device *dev = crtc->base.dev;
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         int pipe = crtc->pipe;
4605
4606         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4607         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4608         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4609         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4610 }
4611
4612 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4613                                          struct intel_link_m_n *m_n)
4614 {
4615         struct drm_device *dev = crtc->base.dev;
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617         int pipe = crtc->pipe;
4618         enum transcoder transcoder = crtc->config.cpu_transcoder;
4619
4620         if (INTEL_INFO(dev)->gen >= 5) {
4621                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4622                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4623                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4624                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4625         } else {
4626                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4627                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4628                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4629                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4630         }
4631 }
4632
4633 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4634 {
4635         if (crtc->config.has_pch_encoder)
4636                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4637         else
4638                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4639 }
4640
4641 static void vlv_update_pll(struct intel_crtc *crtc)
4642 {
4643         struct drm_device *dev = crtc->base.dev;
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         int pipe = crtc->pipe;
4646         u32 dpll, mdiv;
4647         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4648         u32 coreclk, reg_val, dpll_md;
4649
4650         mutex_lock(&dev_priv->dpio_lock);
4651
4652         bestn = crtc->config.dpll.n;
4653         bestm1 = crtc->config.dpll.m1;
4654         bestm2 = crtc->config.dpll.m2;
4655         bestp1 = crtc->config.dpll.p1;
4656         bestp2 = crtc->config.dpll.p2;
4657
4658         /* See eDP HDMI DPIO driver vbios notes doc */
4659
4660         /* PLL B needs special handling */
4661         if (pipe)
4662                 vlv_pllb_recal_opamp(dev_priv, pipe);
4663
4664         /* Set up Tx target for periodic Rcomp update */
4665         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
4666
4667         /* Disable target IRef on PLL */
4668         reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
4669         reg_val &= 0x00ffffff;
4670         vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
4671
4672         /* Disable fast lock */
4673         vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
4674
4675         /* Set idtafcrecal before PLL is enabled */
4676         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4677         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4678         mdiv |= ((bestn << DPIO_N_SHIFT));
4679         mdiv |= (1 << DPIO_K_SHIFT);
4680
4681         /*
4682          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4683          * but we don't support that).
4684          * Note: don't use the DAC post divider as it seems unstable.
4685          */
4686         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4687         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4688
4689         mdiv |= DPIO_ENABLE_CALIBRATION;
4690         vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
4691
4692         /* Set HBR and RBR LPF coefficients */
4693         if (crtc->config.port_clock == 162000 ||
4694             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4695             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4696                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4697                                  0x009f0003);
4698         else
4699                 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
4700                                  0x00d0000f);
4701
4702         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4703             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4704                 /* Use SSC source */
4705                 if (!pipe)
4706                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4707                                          0x0df40000);
4708                 else
4709                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4710                                          0x0df70000);
4711         } else { /* HDMI or VGA */
4712                 /* Use bend source */
4713                 if (!pipe)
4714                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4715                                          0x0df70000);
4716                 else
4717                         vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
4718                                          0x0df40000);
4719         }
4720
4721         coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
4722         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4723         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4724             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4725                 coreclk |= 0x01000000;
4726         vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
4727
4728         vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
4729
4730         /* Enable DPIO clock input */
4731         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4732                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4733         /* We should never disable this, set it here for state tracking */
4734         if (pipe == PIPE_B)
4735                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4736         dpll |= DPLL_VCO_ENABLE;
4737         crtc->config.dpll_hw_state.dpll = dpll;
4738
4739         dpll_md = (crtc->config.pixel_multiplier - 1)
4740                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4741         crtc->config.dpll_hw_state.dpll_md = dpll_md;
4742
4743         if (crtc->config.has_dp_encoder)
4744                 intel_dp_set_m_n(crtc);
4745
4746         mutex_unlock(&dev_priv->dpio_lock);
4747 }
4748
4749 static void i9xx_update_pll(struct intel_crtc *crtc,
4750                             intel_clock_t *reduced_clock,
4751                             int num_connectors)
4752 {
4753         struct drm_device *dev = crtc->base.dev;
4754         struct drm_i915_private *dev_priv = dev->dev_private;
4755         u32 dpll;
4756         bool is_sdvo;
4757         struct dpll *clock = &crtc->config.dpll;
4758
4759         i9xx_update_pll_dividers(crtc, reduced_clock);
4760
4761         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4762                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4763
4764         dpll = DPLL_VGA_MODE_DIS;
4765
4766         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4767                 dpll |= DPLLB_MODE_LVDS;
4768         else
4769                 dpll |= DPLLB_MODE_DAC_SERIAL;
4770
4771         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4772                 dpll |= (crtc->config.pixel_multiplier - 1)
4773                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4774         }
4775
4776         if (is_sdvo)
4777                 dpll |= DPLL_SDVO_HIGH_SPEED;
4778
4779         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4780                 dpll |= DPLL_SDVO_HIGH_SPEED;
4781
4782         /* compute bitmask from p1 value */
4783         if (IS_PINEVIEW(dev))
4784                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4785         else {
4786                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4787                 if (IS_G4X(dev) && reduced_clock)
4788                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4789         }
4790         switch (clock->p2) {
4791         case 5:
4792                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4793                 break;
4794         case 7:
4795                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4796                 break;
4797         case 10:
4798                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4799                 break;
4800         case 14:
4801                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4802                 break;
4803         }
4804         if (INTEL_INFO(dev)->gen >= 4)
4805                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4806
4807         if (crtc->config.sdvo_tv_clock)
4808                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4809         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4810                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4811                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4812         else
4813                 dpll |= PLL_REF_INPUT_DREFCLK;
4814
4815         dpll |= DPLL_VCO_ENABLE;
4816         crtc->config.dpll_hw_state.dpll = dpll;
4817
4818         if (INTEL_INFO(dev)->gen >= 4) {
4819                 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4820                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4821                 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4822         }
4823
4824         if (crtc->config.has_dp_encoder)
4825                 intel_dp_set_m_n(crtc);
4826 }
4827
4828 static void i8xx_update_pll(struct intel_crtc *crtc,
4829                             intel_clock_t *reduced_clock,
4830                             int num_connectors)
4831 {
4832         struct drm_device *dev = crtc->base.dev;
4833         struct drm_i915_private *dev_priv = dev->dev_private;
4834         u32 dpll;
4835         struct dpll *clock = &crtc->config.dpll;
4836
4837         i9xx_update_pll_dividers(crtc, reduced_clock);
4838
4839         dpll = DPLL_VGA_MODE_DIS;
4840
4841         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4842                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4843         } else {
4844                 if (clock->p1 == 2)
4845                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4846                 else
4847                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4848                 if (clock->p2 == 4)
4849                         dpll |= PLL_P2_DIVIDE_BY_4;
4850         }
4851
4852         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4853                 dpll |= DPLL_DVO_2X_MODE;
4854
4855         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4856                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4857                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4858         else
4859                 dpll |= PLL_REF_INPUT_DREFCLK;
4860
4861         dpll |= DPLL_VCO_ENABLE;
4862         crtc->config.dpll_hw_state.dpll = dpll;
4863 }
4864
4865 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4866 {
4867         struct drm_device *dev = intel_crtc->base.dev;
4868         struct drm_i915_private *dev_priv = dev->dev_private;
4869         enum pipe pipe = intel_crtc->pipe;
4870         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4871         struct drm_display_mode *adjusted_mode =
4872                 &intel_crtc->config.adjusted_mode;
4873         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4874
4875         /* We need to be careful not to changed the adjusted mode, for otherwise
4876          * the hw state checker will get angry at the mismatch. */
4877         crtc_vtotal = adjusted_mode->crtc_vtotal;
4878         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4879
4880         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4881                 /* the chip adds 2 halflines automatically */
4882                 crtc_vtotal -= 1;
4883                 crtc_vblank_end -= 1;
4884                 vsyncshift = adjusted_mode->crtc_hsync_start
4885                              - adjusted_mode->crtc_htotal / 2;
4886         } else {
4887                 vsyncshift = 0;
4888         }
4889
4890         if (INTEL_INFO(dev)->gen > 3)
4891                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4892
4893         I915_WRITE(HTOTAL(cpu_transcoder),
4894                    (adjusted_mode->crtc_hdisplay - 1) |
4895                    ((adjusted_mode->crtc_htotal - 1) << 16));
4896         I915_WRITE(HBLANK(cpu_transcoder),
4897                    (adjusted_mode->crtc_hblank_start - 1) |
4898                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4899         I915_WRITE(HSYNC(cpu_transcoder),
4900                    (adjusted_mode->crtc_hsync_start - 1) |
4901                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4902
4903         I915_WRITE(VTOTAL(cpu_transcoder),
4904                    (adjusted_mode->crtc_vdisplay - 1) |
4905                    ((crtc_vtotal - 1) << 16));
4906         I915_WRITE(VBLANK(cpu_transcoder),
4907                    (adjusted_mode->crtc_vblank_start - 1) |
4908                    ((crtc_vblank_end - 1) << 16));
4909         I915_WRITE(VSYNC(cpu_transcoder),
4910                    (adjusted_mode->crtc_vsync_start - 1) |
4911                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4912
4913         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4914          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4915          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4916          * bits. */
4917         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4918             (pipe == PIPE_B || pipe == PIPE_C))
4919                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4920
4921         /* pipesrc controls the size that is scaled from, which should
4922          * always be the user's requested size.
4923          */
4924         I915_WRITE(PIPESRC(pipe),
4925                    ((intel_crtc->config.pipe_src_w - 1) << 16) |
4926                    (intel_crtc->config.pipe_src_h - 1));
4927 }
4928
4929 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4930                                    struct intel_crtc_config *pipe_config)
4931 {
4932         struct drm_device *dev = crtc->base.dev;
4933         struct drm_i915_private *dev_priv = dev->dev_private;
4934         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4935         uint32_t tmp;
4936
4937         tmp = I915_READ(HTOTAL(cpu_transcoder));
4938         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4939         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4940         tmp = I915_READ(HBLANK(cpu_transcoder));
4941         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4942         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4943         tmp = I915_READ(HSYNC(cpu_transcoder));
4944         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4945         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4946
4947         tmp = I915_READ(VTOTAL(cpu_transcoder));
4948         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4949         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4950         tmp = I915_READ(VBLANK(cpu_transcoder));
4951         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4952         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4953         tmp = I915_READ(VSYNC(cpu_transcoder));
4954         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4955         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4956
4957         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4958                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4959                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4960                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4961         }
4962
4963         tmp = I915_READ(PIPESRC(crtc->pipe));
4964         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4965         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4966
4967         pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4968         pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
4969 }
4970
4971 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4972                                              struct intel_crtc_config *pipe_config)
4973 {
4974         struct drm_crtc *crtc = &intel_crtc->base;
4975
4976         crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4977         crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4978         crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4979         crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4980
4981         crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4982         crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4983         crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4984         crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4985
4986         crtc->mode.flags = pipe_config->adjusted_mode.flags;
4987
4988         crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
4989         crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4990 }
4991
4992 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4993 {
4994         struct drm_device *dev = intel_crtc->base.dev;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         uint32_t pipeconf;
4997
4998         pipeconf = 0;
4999
5000         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5001             I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5002                 pipeconf |= PIPECONF_ENABLE;
5003
5004         if (intel_crtc->config.double_wide)
5005                 pipeconf |= PIPECONF_DOUBLE_WIDE;
5006
5007         /* only g4x and later have fancy bpc/dither controls */
5008         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5009                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5010                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5011                         pipeconf |= PIPECONF_DITHER_EN |
5012                                     PIPECONF_DITHER_TYPE_SP;
5013
5014                 switch (intel_crtc->config.pipe_bpp) {
5015                 case 18:
5016                         pipeconf |= PIPECONF_6BPC;
5017                         break;
5018                 case 24:
5019                         pipeconf |= PIPECONF_8BPC;
5020                         break;
5021                 case 30:
5022                         pipeconf |= PIPECONF_10BPC;
5023                         break;
5024                 default:
5025                         /* Case prevented by intel_choose_pipe_bpp_dither. */
5026                         BUG();
5027                 }
5028         }
5029
5030         if (HAS_PIPE_CXSR(dev)) {
5031                 if (intel_crtc->lowfreq_avail) {
5032                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5033                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5034                 } else {
5035                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5036                 }
5037         }
5038
5039         if (!IS_GEN2(dev) &&
5040             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5041                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5042         else
5043                 pipeconf |= PIPECONF_PROGRESSIVE;
5044
5045         if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5046                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5047
5048         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5049         POSTING_READ(PIPECONF(intel_crtc->pipe));
5050 }
5051
5052 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5053                               int x, int y,
5054                               struct drm_framebuffer *fb)
5055 {
5056         struct drm_device *dev = crtc->dev;
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059         int pipe = intel_crtc->pipe;
5060         int plane = intel_crtc->plane;
5061         int refclk, num_connectors = 0;
5062         intel_clock_t clock, reduced_clock;
5063         u32 dspcntr;
5064         bool ok, has_reduced_clock = false;
5065         bool is_lvds = false, is_dsi = false;
5066         struct intel_encoder *encoder;
5067         const intel_limit_t *limit;
5068         int ret;
5069
5070         for_each_encoder_on_crtc(dev, crtc, encoder) {
5071                 switch (encoder->type) {
5072                 case INTEL_OUTPUT_LVDS:
5073                         is_lvds = true;
5074                         break;
5075                 case INTEL_OUTPUT_DSI:
5076                         is_dsi = true;
5077                         break;
5078                 }
5079
5080                 num_connectors++;
5081         }
5082
5083         if (is_dsi)
5084                 goto skip_dpll;
5085
5086         if (!intel_crtc->config.clock_set) {
5087                 refclk = i9xx_get_refclk(crtc, num_connectors);
5088
5089                 /*
5090                  * Returns a set of divisors for the desired target clock with
5091                  * the given refclk, or FALSE.  The returned values represent
5092                  * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5093                  * 2) / p1 / p2.
5094                  */
5095                 limit = intel_limit(crtc, refclk);
5096                 ok = dev_priv->display.find_dpll(limit, crtc,
5097                                                  intel_crtc->config.port_clock,
5098                                                  refclk, NULL, &clock);
5099                 if (!ok) {
5100                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5101                         return -EINVAL;
5102                 }
5103
5104                 if (is_lvds && dev_priv->lvds_downclock_avail) {
5105                         /*
5106                          * Ensure we match the reduced clock's P to the target
5107                          * clock.  If the clocks don't match, we can't switch
5108                          * the display clock by using the FP0/FP1. In such case
5109                          * we will disable the LVDS downclock feature.
5110                          */
5111                         has_reduced_clock =
5112                                 dev_priv->display.find_dpll(limit, crtc,
5113                                                             dev_priv->lvds_downclock,
5114                                                             refclk, &clock,
5115                                                             &reduced_clock);
5116                 }
5117                 /* Compat-code for transition, will disappear. */
5118                 intel_crtc->config.dpll.n = clock.n;
5119                 intel_crtc->config.dpll.m1 = clock.m1;
5120                 intel_crtc->config.dpll.m2 = clock.m2;
5121                 intel_crtc->config.dpll.p1 = clock.p1;
5122                 intel_crtc->config.dpll.p2 = clock.p2;
5123         }
5124
5125         if (IS_GEN2(dev)) {
5126                 i8xx_update_pll(intel_crtc,
5127                                 has_reduced_clock ? &reduced_clock : NULL,
5128                                 num_connectors);
5129         } else if (IS_VALLEYVIEW(dev)) {
5130                 vlv_update_pll(intel_crtc);
5131         } else {
5132                 i9xx_update_pll(intel_crtc,
5133                                 has_reduced_clock ? &reduced_clock : NULL,
5134                                 num_connectors);
5135         }
5136
5137 skip_dpll:
5138         /* Set up the display plane register */
5139         dspcntr = DISPPLANE_GAMMA_ENABLE;
5140
5141         if (!IS_VALLEYVIEW(dev)) {
5142                 if (pipe == 0)
5143                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5144                 else
5145                         dspcntr |= DISPPLANE_SEL_PIPE_B;
5146         }
5147
5148         intel_set_pipe_timings(intel_crtc);
5149
5150         /* pipesrc and dspsize control the size that is scaled from,
5151          * which should always be the user's requested size.
5152          */
5153         I915_WRITE(DSPSIZE(plane),
5154                    ((intel_crtc->config.pipe_src_h - 1) << 16) |
5155                    (intel_crtc->config.pipe_src_w - 1));
5156         I915_WRITE(DSPPOS(plane), 0);
5157
5158         i9xx_set_pipeconf(intel_crtc);
5159
5160         I915_WRITE(DSPCNTR(plane), dspcntr);
5161         POSTING_READ(DSPCNTR(plane));
5162
5163         ret = intel_pipe_set_base(crtc, x, y, fb);
5164
5165         return ret;
5166 }
5167
5168 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5169                                  struct intel_crtc_config *pipe_config)
5170 {
5171         struct drm_device *dev = crtc->base.dev;
5172         struct drm_i915_private *dev_priv = dev->dev_private;
5173         uint32_t tmp;
5174
5175         tmp = I915_READ(PFIT_CONTROL);
5176         if (!(tmp & PFIT_ENABLE))
5177                 return;
5178
5179         /* Check whether the pfit is attached to our pipe. */
5180         if (INTEL_INFO(dev)->gen < 4) {
5181                 if (crtc->pipe != PIPE_B)
5182                         return;
5183         } else {
5184                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5185                         return;
5186         }
5187
5188         pipe_config->gmch_pfit.control = tmp;
5189         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5190         if (INTEL_INFO(dev)->gen < 5)
5191                 pipe_config->gmch_pfit.lvds_border_bits =
5192                         I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5193 }
5194
5195 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5196                                struct intel_crtc_config *pipe_config)
5197 {
5198         struct drm_device *dev = crtc->base.dev;
5199         struct drm_i915_private *dev_priv = dev->dev_private;
5200         int pipe = pipe_config->cpu_transcoder;
5201         intel_clock_t clock;
5202         u32 mdiv;
5203         int refclk = 100000;
5204
5205         mutex_lock(&dev_priv->dpio_lock);
5206         mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5207         mutex_unlock(&dev_priv->dpio_lock);
5208
5209         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5210         clock.m2 = mdiv & DPIO_M2DIV_MASK;
5211         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5212         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5213         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5214
5215         vlv_clock(refclk, &clock);
5216
5217         /* clock.dot is the fast clock */
5218         pipe_config->port_clock = clock.dot / 5;
5219 }
5220
5221 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5222                                  struct intel_crtc_config *pipe_config)
5223 {
5224         struct drm_device *dev = crtc->base.dev;
5225         struct drm_i915_private *dev_priv = dev->dev_private;
5226         uint32_t tmp;
5227
5228         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5229         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5230
5231         tmp = I915_READ(PIPECONF(crtc->pipe));
5232         if (!(tmp & PIPECONF_ENABLE))
5233                 return false;
5234
5235         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5236                 switch (tmp & PIPECONF_BPC_MASK) {
5237                 case PIPECONF_6BPC:
5238                         pipe_config->pipe_bpp = 18;
5239                         break;
5240                 case PIPECONF_8BPC:
5241                         pipe_config->pipe_bpp = 24;
5242                         break;
5243                 case PIPECONF_10BPC:
5244                         pipe_config->pipe_bpp = 30;
5245                         break;
5246                 default:
5247                         break;
5248                 }
5249         }
5250
5251         if (INTEL_INFO(dev)->gen < 4)
5252                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5253
5254         intel_get_pipe_timings(crtc, pipe_config);
5255
5256         i9xx_get_pfit_config(crtc, pipe_config);
5257
5258         if (INTEL_INFO(dev)->gen >= 4) {
5259                 tmp = I915_READ(DPLL_MD(crtc->pipe));
5260                 pipe_config->pixel_multiplier =
5261                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5262                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5263                 pipe_config->dpll_hw_state.dpll_md = tmp;
5264         } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5265                 tmp = I915_READ(DPLL(crtc->pipe));
5266                 pipe_config->pixel_multiplier =
5267                         ((tmp & SDVO_MULTIPLIER_MASK)
5268                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5269         } else {
5270                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5271                  * port and will be fixed up in the encoder->get_config
5272                  * function. */
5273                 pipe_config->pixel_multiplier = 1;
5274         }
5275         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5276         if (!IS_VALLEYVIEW(dev)) {
5277                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5278                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5279         } else {
5280                 /* Mask out read-only status bits. */
5281                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5282                                                      DPLL_PORTC_READY_MASK |
5283                                                      DPLL_PORTB_READY_MASK);
5284         }
5285
5286         if (IS_VALLEYVIEW(dev))
5287                 vlv_crtc_clock_get(crtc, pipe_config);
5288         else
5289                 i9xx_crtc_clock_get(crtc, pipe_config);
5290
5291         return true;
5292 }
5293
5294 static void ironlake_init_pch_refclk(struct drm_device *dev)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         struct drm_mode_config *mode_config = &dev->mode_config;
5298         struct intel_encoder *encoder;
5299         u32 val, final;
5300         bool has_lvds = false;
5301         bool has_cpu_edp = false;
5302         bool has_panel = false;
5303         bool has_ck505 = false;
5304         bool can_ssc = false;
5305
5306         /* We need to take the global config into account */
5307         list_for_each_entry(encoder, &mode_config->encoder_list,
5308                             base.head) {
5309                 switch (encoder->type) {
5310                 case INTEL_OUTPUT_LVDS:
5311                         has_panel = true;
5312                         has_lvds = true;
5313                         break;
5314                 case INTEL_OUTPUT_EDP:
5315                         has_panel = true;
5316                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5317                                 has_cpu_edp = true;
5318                         break;
5319                 }
5320         }
5321
5322         if (HAS_PCH_IBX(dev)) {
5323                 has_ck505 = dev_priv->vbt.display_clock_mode;
5324                 can_ssc = has_ck505;
5325         } else {
5326                 has_ck505 = false;
5327                 can_ssc = true;
5328         }
5329
5330         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5331                       has_panel, has_lvds, has_ck505);
5332
5333         /* Ironlake: try to setup display ref clock before DPLL
5334          * enabling. This is only under driver's control after
5335          * PCH B stepping, previous chipset stepping should be
5336          * ignoring this setting.
5337          */
5338         val = I915_READ(PCH_DREF_CONTROL);
5339
5340         /* As we must carefully and slowly disable/enable each source in turn,
5341          * compute the final state we want first and check if we need to
5342          * make any changes at all.
5343          */
5344         final = val;
5345         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5346         if (has_ck505)
5347                 final |= DREF_NONSPREAD_CK505_ENABLE;
5348         else
5349                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5350
5351         final &= ~DREF_SSC_SOURCE_MASK;
5352         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5353         final &= ~DREF_SSC1_ENABLE;
5354
5355         if (has_panel) {
5356                 final |= DREF_SSC_SOURCE_ENABLE;
5357
5358                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5359                         final |= DREF_SSC1_ENABLE;
5360
5361                 if (has_cpu_edp) {
5362                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5363                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5364                         else
5365                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5366                 } else
5367                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5368         } else {
5369                 final |= DREF_SSC_SOURCE_DISABLE;
5370                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5371         }
5372
5373         if (final == val)
5374                 return;
5375
5376         /* Always enable nonspread source */
5377         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5378
5379         if (has_ck505)
5380                 val |= DREF_NONSPREAD_CK505_ENABLE;
5381         else
5382                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5383
5384         if (has_panel) {
5385                 val &= ~DREF_SSC_SOURCE_MASK;
5386                 val |= DREF_SSC_SOURCE_ENABLE;
5387
5388                 /* SSC must be turned on before enabling the CPU output  */
5389                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5390                         DRM_DEBUG_KMS("Using SSC on panel\n");
5391                         val |= DREF_SSC1_ENABLE;
5392                 } else
5393                         val &= ~DREF_SSC1_ENABLE;
5394
5395                 /* Get SSC going before enabling the outputs */
5396                 I915_WRITE(PCH_DREF_CONTROL, val);
5397                 POSTING_READ(PCH_DREF_CONTROL);
5398                 udelay(200);
5399
5400                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5401
5402                 /* Enable CPU source on CPU attached eDP */
5403                 if (has_cpu_edp) {
5404                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5405                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5406                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5407                         }
5408                         else
5409                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5410                 } else
5411                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5412
5413                 I915_WRITE(PCH_DREF_CONTROL, val);
5414                 POSTING_READ(PCH_DREF_CONTROL);
5415                 udelay(200);
5416         } else {
5417                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5418
5419                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5420
5421                 /* Turn off CPU output */
5422                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5423
5424                 I915_WRITE(PCH_DREF_CONTROL, val);
5425                 POSTING_READ(PCH_DREF_CONTROL);
5426                 udelay(200);
5427
5428                 /* Turn off the SSC source */
5429                 val &= ~DREF_SSC_SOURCE_MASK;
5430                 val |= DREF_SSC_SOURCE_DISABLE;
5431
5432                 /* Turn off SSC1 */
5433                 val &= ~DREF_SSC1_ENABLE;
5434
5435                 I915_WRITE(PCH_DREF_CONTROL, val);
5436                 POSTING_READ(PCH_DREF_CONTROL);
5437                 udelay(200);
5438         }
5439
5440         BUG_ON(val != final);
5441 }
5442
5443 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5444 {
5445         uint32_t tmp;
5446
5447         tmp = I915_READ(SOUTH_CHICKEN2);
5448         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5449         I915_WRITE(SOUTH_CHICKEN2, tmp);
5450
5451         if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5452                                FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5453                 DRM_ERROR("FDI mPHY reset assert timeout\n");
5454
5455         tmp = I915_READ(SOUTH_CHICKEN2);
5456         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5457         I915_WRITE(SOUTH_CHICKEN2, tmp);
5458
5459         if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5460                                 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5461                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5462 }
5463
5464 /* WaMPhyProgramming:hsw */
5465 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5466 {
5467         uint32_t tmp;
5468
5469         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5470         tmp &= ~(0xFF << 24);
5471         tmp |= (0x12 << 24);
5472         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5473
5474         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5475         tmp |= (1 << 11);
5476         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5477
5478         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5479         tmp |= (1 << 11);
5480         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5481
5482         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5483         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5484         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5485
5486         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5487         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5488         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5489
5490         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5491         tmp &= ~(7 << 13);
5492         tmp |= (5 << 13);
5493         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5494
5495         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5496         tmp &= ~(7 << 13);
5497         tmp |= (5 << 13);
5498         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5499
5500         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5501         tmp &= ~0xFF;
5502         tmp |= 0x1C;
5503         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5504
5505         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5506         tmp &= ~0xFF;
5507         tmp |= 0x1C;
5508         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5509
5510         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5511         tmp &= ~(0xFF << 16);
5512         tmp |= (0x1C << 16);
5513         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5514
5515         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5516         tmp &= ~(0xFF << 16);
5517         tmp |= (0x1C << 16);
5518         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5519
5520         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5521         tmp |= (1 << 27);
5522         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5523
5524         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5525         tmp |= (1 << 27);
5526         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5527
5528         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5529         tmp &= ~(0xF << 28);
5530         tmp |= (4 << 28);
5531         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5532
5533         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5534         tmp &= ~(0xF << 28);
5535         tmp |= (4 << 28);
5536         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5537 }
5538
5539 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5540  * Programming" based on the parameters passed:
5541  * - Sequence to enable CLKOUT_DP
5542  * - Sequence to enable CLKOUT_DP without spread
5543  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5544  */
5545 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5546                                  bool with_fdi)
5547 {
5548         struct drm_i915_private *dev_priv = dev->dev_private;
5549         uint32_t reg, tmp;
5550
5551         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5552                 with_spread = true;
5553         if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5554                  with_fdi, "LP PCH doesn't have FDI\n"))
5555                 with_fdi = false;
5556
5557         mutex_lock(&dev_priv->dpio_lock);
5558
5559         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5560         tmp &= ~SBI_SSCCTL_DISABLE;
5561         tmp |= SBI_SSCCTL_PATHALT;
5562         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5563
5564         udelay(24);
5565
5566         if (with_spread) {
5567                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5568                 tmp &= ~SBI_SSCCTL_PATHALT;
5569                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5570
5571                 if (with_fdi) {
5572                         lpt_reset_fdi_mphy(dev_priv);
5573                         lpt_program_fdi_mphy(dev_priv);
5574                 }
5575         }
5576
5577         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5578                SBI_GEN0 : SBI_DBUFF0;
5579         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5580         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5581         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5582
5583         mutex_unlock(&dev_priv->dpio_lock);
5584 }
5585
5586 /* Sequence to disable CLKOUT_DP */
5587 static void lpt_disable_clkout_dp(struct drm_device *dev)
5588 {
5589         struct drm_i915_private *dev_priv = dev->dev_private;
5590         uint32_t reg, tmp;
5591
5592         mutex_lock(&dev_priv->dpio_lock);
5593
5594         reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5595                SBI_GEN0 : SBI_DBUFF0;
5596         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5597         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5598         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5599
5600         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5601         if (!(tmp & SBI_SSCCTL_DISABLE)) {
5602                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5603                         tmp |= SBI_SSCCTL_PATHALT;
5604                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605                         udelay(32);
5606                 }
5607                 tmp |= SBI_SSCCTL_DISABLE;
5608                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5609         }
5610
5611         mutex_unlock(&dev_priv->dpio_lock);
5612 }
5613
5614 static void lpt_init_pch_refclk(struct drm_device *dev)
5615 {
5616         struct drm_mode_config *mode_config = &dev->mode_config;
5617         struct intel_encoder *encoder;
5618         bool has_vga = false;
5619
5620         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5621                 switch (encoder->type) {
5622                 case INTEL_OUTPUT_ANALOG:
5623                         has_vga = true;
5624                         break;
5625                 }
5626         }
5627
5628         if (has_vga)
5629                 lpt_enable_clkout_dp(dev, true, true);
5630         else
5631                 lpt_disable_clkout_dp(dev);
5632 }
5633
5634 /*
5635  * Initialize reference clocks when the driver loads
5636  */
5637 void intel_init_pch_refclk(struct drm_device *dev)
5638 {
5639         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5640                 ironlake_init_pch_refclk(dev);
5641         else if (HAS_PCH_LPT(dev))
5642                 lpt_init_pch_refclk(dev);
5643 }
5644
5645 static int ironlake_get_refclk(struct drm_crtc *crtc)
5646 {
5647         struct drm_device *dev = crtc->dev;
5648         struct drm_i915_private *dev_priv = dev->dev_private;
5649         struct intel_encoder *encoder;
5650         int num_connectors = 0;
5651         bool is_lvds = false;
5652
5653         for_each_encoder_on_crtc(dev, crtc, encoder) {
5654                 switch (encoder->type) {
5655                 case INTEL_OUTPUT_LVDS:
5656                         is_lvds = true;
5657                         break;
5658                 }
5659                 num_connectors++;
5660         }
5661
5662         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5663                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5664                               dev_priv->vbt.lvds_ssc_freq);
5665                 return dev_priv->vbt.lvds_ssc_freq * 1000;
5666         }
5667
5668         return 120000;
5669 }
5670
5671 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5672 {
5673         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5675         int pipe = intel_crtc->pipe;
5676         uint32_t val;
5677
5678         val = 0;
5679
5680         switch (intel_crtc->config.pipe_bpp) {
5681         case 18:
5682                 val |= PIPECONF_6BPC;
5683                 break;
5684         case 24:
5685                 val |= PIPECONF_8BPC;
5686                 break;
5687         case 30:
5688                 val |= PIPECONF_10BPC;
5689                 break;
5690         case 36:
5691                 val |= PIPECONF_12BPC;
5692                 break;
5693         default:
5694                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5695                 BUG();
5696         }
5697
5698         if (intel_crtc->config.dither)
5699                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5700
5701         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5702                 val |= PIPECONF_INTERLACED_ILK;
5703         else
5704                 val |= PIPECONF_PROGRESSIVE;
5705
5706         if (intel_crtc->config.limited_color_range)
5707                 val |= PIPECONF_COLOR_RANGE_SELECT;
5708
5709         I915_WRITE(PIPECONF(pipe), val);
5710         POSTING_READ(PIPECONF(pipe));
5711 }
5712
5713 /*
5714  * Set up the pipe CSC unit.
5715  *
5716  * Currently only full range RGB to limited range RGB conversion
5717  * is supported, but eventually this should handle various
5718  * RGB<->YCbCr scenarios as well.
5719  */
5720 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5721 {
5722         struct drm_device *dev = crtc->dev;
5723         struct drm_i915_private *dev_priv = dev->dev_private;
5724         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725         int pipe = intel_crtc->pipe;
5726         uint16_t coeff = 0x7800; /* 1.0 */
5727
5728         /*
5729          * TODO: Check what kind of values actually come out of the pipe
5730          * with these coeff/postoff values and adjust to get the best
5731          * accuracy. Perhaps we even need to take the bpc value into
5732          * consideration.
5733          */
5734
5735         if (intel_crtc->config.limited_color_range)
5736                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5737
5738         /*
5739          * GY/GU and RY/RU should be the other way around according
5740          * to BSpec, but reality doesn't agree. Just set them up in
5741          * a way that results in the correct picture.
5742          */
5743         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5744         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5745
5746         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5747         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5748
5749         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5750         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5751
5752         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5753         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5754         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5755
5756         if (INTEL_INFO(dev)->gen > 6) {
5757                 uint16_t postoff = 0;
5758
5759                 if (intel_crtc->config.limited_color_range)
5760                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5761
5762                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5763                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5764                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5765
5766                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5767         } else {
5768                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5769
5770                 if (intel_crtc->config.limited_color_range)
5771                         mode |= CSC_BLACK_SCREEN_OFFSET;
5772
5773                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5774         }
5775 }
5776
5777 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5778 {
5779         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5781         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5782         uint32_t val;
5783
5784         val = 0;
5785
5786         if (intel_crtc->config.dither)
5787                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5788
5789         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5790                 val |= PIPECONF_INTERLACED_ILK;
5791         else
5792                 val |= PIPECONF_PROGRESSIVE;
5793
5794         I915_WRITE(PIPECONF(cpu_transcoder), val);
5795         POSTING_READ(PIPECONF(cpu_transcoder));
5796
5797         I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5798         POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5799 }
5800
5801 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5802                                     intel_clock_t *clock,
5803                                     bool *has_reduced_clock,
5804                                     intel_clock_t *reduced_clock)
5805 {
5806         struct drm_device *dev = crtc->dev;
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         struct intel_encoder *intel_encoder;
5809         int refclk;
5810         const intel_limit_t *limit;
5811         bool ret, is_lvds = false;
5812
5813         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5814                 switch (intel_encoder->type) {
5815                 case INTEL_OUTPUT_LVDS:
5816                         is_lvds = true;
5817                         break;
5818                 }
5819         }
5820
5821         refclk = ironlake_get_refclk(crtc);
5822
5823         /*
5824          * Returns a set of divisors for the desired target clock with the given
5825          * refclk, or FALSE.  The returned values represent the clock equation:
5826          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5827          */
5828         limit = intel_limit(crtc, refclk);
5829         ret = dev_priv->display.find_dpll(limit, crtc,
5830                                           to_intel_crtc(crtc)->config.port_clock,
5831                                           refclk, NULL, clock);
5832         if (!ret)
5833                 return false;
5834
5835         if (is_lvds && dev_priv->lvds_downclock_avail) {
5836                 /*
5837                  * Ensure we match the reduced clock's P to the target clock.
5838                  * If the clocks don't match, we can't switch the display clock
5839                  * by using the FP0/FP1. In such case we will disable the LVDS
5840                  * downclock feature.
5841                 */
5842                 *has_reduced_clock =
5843                         dev_priv->display.find_dpll(limit, crtc,
5844                                                     dev_priv->lvds_downclock,
5845                                                     refclk, clock,
5846                                                     reduced_clock);
5847         }
5848
5849         return true;
5850 }
5851
5852 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5853 {
5854         struct drm_i915_private *dev_priv = dev->dev_private;
5855         uint32_t temp;
5856
5857         temp = I915_READ(SOUTH_CHICKEN1);
5858         if (temp & FDI_BC_BIFURCATION_SELECT)
5859                 return;
5860
5861         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5862         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5863
5864         temp |= FDI_BC_BIFURCATION_SELECT;
5865         DRM_DEBUG_KMS("enabling fdi C rx\n");
5866         I915_WRITE(SOUTH_CHICKEN1, temp);
5867         POSTING_READ(SOUTH_CHICKEN1);
5868 }
5869
5870 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5871 {
5872         struct drm_device *dev = intel_crtc->base.dev;
5873         struct drm_i915_private *dev_priv = dev->dev_private;
5874
5875         switch (intel_crtc->pipe) {
5876         case PIPE_A:
5877                 break;
5878         case PIPE_B:
5879                 if (intel_crtc->config.fdi_lanes > 2)
5880                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5881                 else
5882                         cpt_enable_fdi_bc_bifurcation(dev);
5883
5884                 break;
5885         case PIPE_C:
5886                 cpt_enable_fdi_bc_bifurcation(dev);
5887
5888                 break;
5889         default:
5890                 BUG();
5891         }
5892 }
5893
5894 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5895 {
5896         /*
5897          * Account for spread spectrum to avoid
5898          * oversubscribing the link. Max center spread
5899          * is 2.5%; use 5% for safety's sake.
5900          */
5901         u32 bps = target_clock * bpp * 21 / 20;
5902         return bps / (link_bw * 8) + 1;
5903 }
5904
5905 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5906 {
5907         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5908 }
5909
5910 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5911                                       u32 *fp,
5912                                       intel_clock_t *reduced_clock, u32 *fp2)
5913 {
5914         struct drm_crtc *crtc = &intel_crtc->base;
5915         struct drm_device *dev = crtc->dev;
5916         struct drm_i915_private *dev_priv = dev->dev_private;
5917         struct intel_encoder *intel_encoder;
5918         uint32_t dpll;
5919         int factor, num_connectors = 0;
5920         bool is_lvds = false, is_sdvo = false;
5921
5922         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5923                 switch (intel_encoder->type) {
5924                 case INTEL_OUTPUT_LVDS:
5925                         is_lvds = true;
5926                         break;
5927                 case INTEL_OUTPUT_SDVO:
5928                 case INTEL_OUTPUT_HDMI:
5929                         is_sdvo = true;
5930                         break;
5931                 }
5932
5933                 num_connectors++;
5934         }
5935
5936         /* Enable autotuning of the PLL clock (if permissible) */
5937         factor = 21;
5938         if (is_lvds) {
5939                 if ((intel_panel_use_ssc(dev_priv) &&
5940                      dev_priv->vbt.lvds_ssc_freq == 100) ||
5941                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5942                         factor = 25;
5943         } else if (intel_crtc->config.sdvo_tv_clock)
5944                 factor = 20;
5945
5946         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5947                 *fp |= FP_CB_TUNE;
5948
5949         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5950                 *fp2 |= FP_CB_TUNE;
5951
5952         dpll = 0;
5953
5954         if (is_lvds)
5955                 dpll |= DPLLB_MODE_LVDS;
5956         else
5957                 dpll |= DPLLB_MODE_DAC_SERIAL;
5958
5959         dpll |= (intel_crtc->config.pixel_multiplier - 1)
5960                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5961
5962         if (is_sdvo)
5963                 dpll |= DPLL_SDVO_HIGH_SPEED;
5964         if (intel_crtc->config.has_dp_encoder)
5965                 dpll |= DPLL_SDVO_HIGH_SPEED;
5966
5967         /* compute bitmask from p1 value */
5968         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5969         /* also FPA1 */
5970         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5971
5972         switch (intel_crtc->config.dpll.p2) {
5973         case 5:
5974                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5975                 break;
5976         case 7:
5977                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5978                 break;
5979         case 10:
5980                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5981                 break;
5982         case 14:
5983                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5984                 break;
5985         }
5986
5987         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5988                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5989         else
5990                 dpll |= PLL_REF_INPUT_DREFCLK;
5991
5992         return dpll | DPLL_VCO_ENABLE;
5993 }
5994
5995 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5996                                   int x, int y,
5997                                   struct drm_framebuffer *fb)
5998 {
5999         struct drm_device *dev = crtc->dev;
6000         struct drm_i915_private *dev_priv = dev->dev_private;
6001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002         int pipe = intel_crtc->pipe;
6003         int plane = intel_crtc->plane;
6004         int num_connectors = 0;
6005         intel_clock_t clock, reduced_clock;
6006         u32 dpll = 0, fp = 0, fp2 = 0;
6007         bool ok, has_reduced_clock = false;
6008         bool is_lvds = false;
6009         struct intel_encoder *encoder;
6010         struct intel_shared_dpll *pll;
6011         int ret;
6012
6013         for_each_encoder_on_crtc(dev, crtc, encoder) {
6014                 switch (encoder->type) {
6015                 case INTEL_OUTPUT_LVDS:
6016                         is_lvds = true;
6017                         break;
6018                 }
6019
6020                 num_connectors++;
6021         }
6022
6023         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6024              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6025
6026         ok = ironlake_compute_clocks(crtc, &clock,
6027                                      &has_reduced_clock, &reduced_clock);
6028         if (!ok && !intel_crtc->config.clock_set) {
6029                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6030                 return -EINVAL;
6031         }
6032         /* Compat-code for transition, will disappear. */
6033         if (!intel_crtc->config.clock_set) {
6034                 intel_crtc->config.dpll.n = clock.n;
6035                 intel_crtc->config.dpll.m1 = clock.m1;
6036                 intel_crtc->config.dpll.m2 = clock.m2;
6037                 intel_crtc->config.dpll.p1 = clock.p1;
6038                 intel_crtc->config.dpll.p2 = clock.p2;
6039         }
6040
6041         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6042         if (intel_crtc->config.has_pch_encoder) {
6043                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6044                 if (has_reduced_clock)
6045                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6046
6047                 dpll = ironlake_compute_dpll(intel_crtc,
6048                                              &fp, &reduced_clock,
6049                                              has_reduced_clock ? &fp2 : NULL);
6050
6051                 intel_crtc->config.dpll_hw_state.dpll = dpll;
6052                 intel_crtc->config.dpll_hw_state.fp0 = fp;
6053                 if (has_reduced_clock)
6054                         intel_crtc->config.dpll_hw_state.fp1 = fp2;
6055                 else
6056                         intel_crtc->config.dpll_hw_state.fp1 = fp;
6057
6058                 pll = intel_get_shared_dpll(intel_crtc);
6059                 if (pll == NULL) {
6060                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6061                                          pipe_name(pipe));
6062                         return -EINVAL;
6063                 }
6064         } else
6065                 intel_put_shared_dpll(intel_crtc);
6066
6067         if (intel_crtc->config.has_dp_encoder)
6068                 intel_dp_set_m_n(intel_crtc);
6069
6070         if (is_lvds && has_reduced_clock && i915_powersave)
6071                 intel_crtc->lowfreq_avail = true;
6072         else
6073                 intel_crtc->lowfreq_avail = false;
6074
6075         intel_set_pipe_timings(intel_crtc);
6076
6077         if (intel_crtc->config.has_pch_encoder) {
6078                 intel_cpu_transcoder_set_m_n(intel_crtc,
6079                                              &intel_crtc->config.fdi_m_n);
6080         }
6081
6082         if (IS_IVYBRIDGE(dev))
6083                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
6084
6085         ironlake_set_pipeconf(crtc);
6086
6087         /* Set up the display plane register */
6088         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6089         POSTING_READ(DSPCNTR(plane));
6090
6091         ret = intel_pipe_set_base(crtc, x, y, fb);
6092
6093         return ret;
6094 }
6095
6096 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6097                                          struct intel_link_m_n *m_n)
6098 {
6099         struct drm_device *dev = crtc->base.dev;
6100         struct drm_i915_private *dev_priv = dev->dev_private;
6101         enum pipe pipe = crtc->pipe;
6102
6103         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6104         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6105         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6106                 & ~TU_SIZE_MASK;
6107         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6108         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6109                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6110 }
6111
6112 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6113                                          enum transcoder transcoder,
6114                                          struct intel_link_m_n *m_n)
6115 {
6116         struct drm_device *dev = crtc->base.dev;
6117         struct drm_i915_private *dev_priv = dev->dev_private;
6118         enum pipe pipe = crtc->pipe;
6119
6120         if (INTEL_INFO(dev)->gen >= 5) {
6121                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6122                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6123                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6124                         & ~TU_SIZE_MASK;
6125                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6126                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6127                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6128         } else {
6129                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6130                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6131                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6132                         & ~TU_SIZE_MASK;
6133                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6134                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6135                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6136         }
6137 }
6138
6139 void intel_dp_get_m_n(struct intel_crtc *crtc,
6140                       struct intel_crtc_config *pipe_config)
6141 {
6142         if (crtc->config.has_pch_encoder)
6143                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6144         else
6145                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6146                                              &pipe_config->dp_m_n);
6147 }
6148
6149 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6150                                         struct intel_crtc_config *pipe_config)
6151 {
6152         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6153                                      &pipe_config->fdi_m_n);
6154 }
6155
6156 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6157                                      struct intel_crtc_config *pipe_config)
6158 {
6159         struct drm_device *dev = crtc->base.dev;
6160         struct drm_i915_private *dev_priv = dev->dev_private;
6161         uint32_t tmp;
6162
6163         tmp = I915_READ(PF_CTL(crtc->pipe));
6164
6165         if (tmp & PF_ENABLE) {
6166                 pipe_config->pch_pfit.enabled = true;
6167                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6168                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6169
6170                 /* We currently do not free assignements of panel fitters on
6171                  * ivb/hsw (since we don't use the higher upscaling modes which
6172                  * differentiates them) so just WARN about this case for now. */
6173                 if (IS_GEN7(dev)) {
6174                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6175                                 PF_PIPE_SEL_IVB(crtc->pipe));
6176                 }
6177         }
6178 }
6179
6180 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6181                                      struct intel_crtc_config *pipe_config)
6182 {
6183         struct drm_device *dev = crtc->base.dev;
6184         struct drm_i915_private *dev_priv = dev->dev_private;
6185         uint32_t tmp;
6186
6187         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6188         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6189
6190         tmp = I915_READ(PIPECONF(crtc->pipe));
6191         if (!(tmp & PIPECONF_ENABLE))
6192                 return false;
6193
6194         switch (tmp & PIPECONF_BPC_MASK) {
6195         case PIPECONF_6BPC:
6196                 pipe_config->pipe_bpp = 18;
6197                 break;
6198         case PIPECONF_8BPC:
6199                 pipe_config->pipe_bpp = 24;
6200                 break;
6201         case PIPECONF_10BPC:
6202                 pipe_config->pipe_bpp = 30;
6203                 break;
6204         case PIPECONF_12BPC:
6205                 pipe_config->pipe_bpp = 36;
6206                 break;
6207         default:
6208                 break;
6209         }
6210
6211         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6212                 struct intel_shared_dpll *pll;
6213
6214                 pipe_config->has_pch_encoder = true;
6215
6216                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6217                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6218                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6219
6220                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6221
6222                 if (HAS_PCH_IBX(dev_priv->dev)) {
6223                         pipe_config->shared_dpll =
6224                                 (enum intel_dpll_id) crtc->pipe;
6225                 } else {
6226                         tmp = I915_READ(PCH_DPLL_SEL);
6227                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6228                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6229                         else
6230                                 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6231                 }
6232
6233                 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6234
6235                 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6236                                            &pipe_config->dpll_hw_state));
6237
6238                 tmp = pipe_config->dpll_hw_state.dpll;
6239                 pipe_config->pixel_multiplier =
6240                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6241                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6242
6243                 ironlake_pch_clock_get(crtc, pipe_config);
6244         } else {
6245                 pipe_config->pixel_multiplier = 1;
6246         }
6247
6248         intel_get_pipe_timings(crtc, pipe_config);
6249
6250         ironlake_get_pfit_config(crtc, pipe_config);
6251
6252         return true;
6253 }
6254
6255 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6256 {
6257         struct drm_device *dev = dev_priv->dev;
6258         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6259         struct intel_crtc *crtc;
6260         unsigned long irqflags;
6261         uint32_t val;
6262
6263         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6264                 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6265                      pipe_name(crtc->pipe));
6266
6267         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6268         WARN(plls->spll_refcount, "SPLL enabled\n");
6269         WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6270         WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6271         WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6272         WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6273              "CPU PWM1 enabled\n");
6274         WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6275              "CPU PWM2 enabled\n");
6276         WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6277              "PCH PWM1 enabled\n");
6278         WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6279              "Utility pin enabled\n");
6280         WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6281
6282         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6283         val = I915_READ(DEIMR);
6284         WARN((val & ~DE_PCH_EVENT_IVB) != val,
6285              "Unexpected DEIMR bits enabled: 0x%x\n", val);
6286         val = I915_READ(SDEIMR);
6287         WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6288              "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6289         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6290 }
6291
6292 /*
6293  * This function implements pieces of two sequences from BSpec:
6294  * - Sequence for display software to disable LCPLL
6295  * - Sequence for display software to allow package C8+
6296  * The steps implemented here are just the steps that actually touch the LCPLL
6297  * register. Callers should take care of disabling all the display engine
6298  * functions, doing the mode unset, fixing interrupts, etc.
6299  */
6300 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6301                               bool switch_to_fclk, bool allow_power_down)
6302 {
6303         uint32_t val;
6304
6305         assert_can_disable_lcpll(dev_priv);
6306
6307         val = I915_READ(LCPLL_CTL);
6308
6309         if (switch_to_fclk) {
6310                 val |= LCPLL_CD_SOURCE_FCLK;
6311                 I915_WRITE(LCPLL_CTL, val);
6312
6313                 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6314                                        LCPLL_CD_SOURCE_FCLK_DONE, 1))
6315                         DRM_ERROR("Switching to FCLK failed\n");
6316
6317                 val = I915_READ(LCPLL_CTL);
6318         }
6319
6320         val |= LCPLL_PLL_DISABLE;
6321         I915_WRITE(LCPLL_CTL, val);
6322         POSTING_READ(LCPLL_CTL);
6323
6324         if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6325                 DRM_ERROR("LCPLL still locked\n");
6326
6327         val = I915_READ(D_COMP);
6328         val |= D_COMP_COMP_DISABLE;
6329         mutex_lock(&dev_priv->rps.hw_lock);
6330         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6331                 DRM_ERROR("Failed to disable D_COMP\n");
6332         mutex_unlock(&dev_priv->rps.hw_lock);
6333         POSTING_READ(D_COMP);
6334         ndelay(100);
6335
6336         if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6337                 DRM_ERROR("D_COMP RCOMP still in progress\n");
6338
6339         if (allow_power_down) {
6340                 val = I915_READ(LCPLL_CTL);
6341                 val |= LCPLL_POWER_DOWN_ALLOW;
6342                 I915_WRITE(LCPLL_CTL, val);
6343                 POSTING_READ(LCPLL_CTL);
6344         }
6345 }
6346
6347 /*
6348  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6349  * source.
6350  */
6351 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6352 {
6353         uint32_t val;
6354
6355         val = I915_READ(LCPLL_CTL);
6356
6357         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6358                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6359                 return;
6360
6361         /* Make sure we're not on PC8 state before disabling PC8, otherwise
6362          * we'll hang the machine! */
6363         dev_priv->uncore.funcs.force_wake_get(dev_priv);
6364
6365         if (val & LCPLL_POWER_DOWN_ALLOW) {
6366                 val &= ~LCPLL_POWER_DOWN_ALLOW;
6367                 I915_WRITE(LCPLL_CTL, val);
6368                 POSTING_READ(LCPLL_CTL);
6369         }
6370
6371         val = I915_READ(D_COMP);
6372         val |= D_COMP_COMP_FORCE;
6373         val &= ~D_COMP_COMP_DISABLE;
6374         mutex_lock(&dev_priv->rps.hw_lock);
6375         if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6376                 DRM_ERROR("Failed to enable D_COMP\n");
6377         mutex_unlock(&dev_priv->rps.hw_lock);
6378         POSTING_READ(D_COMP);
6379
6380         val = I915_READ(LCPLL_CTL);
6381         val &= ~LCPLL_PLL_DISABLE;
6382         I915_WRITE(LCPLL_CTL, val);
6383
6384         if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6385                 DRM_ERROR("LCPLL not locked yet\n");
6386
6387         if (val & LCPLL_CD_SOURCE_FCLK) {
6388                 val = I915_READ(LCPLL_CTL);
6389                 val &= ~LCPLL_CD_SOURCE_FCLK;
6390                 I915_WRITE(LCPLL_CTL, val);
6391
6392                 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6393                                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6394                         DRM_ERROR("Switching back to LCPLL failed\n");
6395         }
6396
6397         dev_priv->uncore.funcs.force_wake_put(dev_priv);
6398 }
6399
6400 void hsw_enable_pc8_work(struct work_struct *__work)
6401 {
6402         struct drm_i915_private *dev_priv =
6403                 container_of(to_delayed_work(__work), struct drm_i915_private,
6404                              pc8.enable_work);
6405         struct drm_device *dev = dev_priv->dev;
6406         uint32_t val;
6407
6408         if (dev_priv->pc8.enabled)
6409                 return;
6410
6411         DRM_DEBUG_KMS("Enabling package C8+\n");
6412
6413         dev_priv->pc8.enabled = true;
6414
6415         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6416                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6417                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6418                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6419         }
6420
6421         lpt_disable_clkout_dp(dev);
6422         hsw_pc8_disable_interrupts(dev);
6423         hsw_disable_lcpll(dev_priv, true, true);
6424 }
6425
6426 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6427 {
6428         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6429         WARN(dev_priv->pc8.disable_count < 1,
6430              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6431
6432         dev_priv->pc8.disable_count--;
6433         if (dev_priv->pc8.disable_count != 0)
6434                 return;
6435
6436         schedule_delayed_work(&dev_priv->pc8.enable_work,
6437                               msecs_to_jiffies(i915_pc8_timeout));
6438 }
6439
6440 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6441 {
6442         struct drm_device *dev = dev_priv->dev;
6443         uint32_t val;
6444
6445         WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6446         WARN(dev_priv->pc8.disable_count < 0,
6447              "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6448
6449         dev_priv->pc8.disable_count++;
6450         if (dev_priv->pc8.disable_count != 1)
6451                 return;
6452
6453         cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6454         if (!dev_priv->pc8.enabled)
6455                 return;
6456
6457         DRM_DEBUG_KMS("Disabling package C8+\n");
6458
6459         hsw_restore_lcpll(dev_priv);
6460         hsw_pc8_restore_interrupts(dev);
6461         lpt_init_pch_refclk(dev);
6462
6463         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6464                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6465                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6466                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6467         }
6468
6469         intel_prepare_ddi(dev);
6470         i915_gem_init_swizzling(dev);
6471         mutex_lock(&dev_priv->rps.hw_lock);
6472         gen6_update_ring_freq(dev);
6473         mutex_unlock(&dev_priv->rps.hw_lock);
6474         dev_priv->pc8.enabled = false;
6475 }
6476
6477 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6478 {
6479         mutex_lock(&dev_priv->pc8.lock);
6480         __hsw_enable_package_c8(dev_priv);
6481         mutex_unlock(&dev_priv->pc8.lock);
6482 }
6483
6484 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6485 {
6486         mutex_lock(&dev_priv->pc8.lock);
6487         __hsw_disable_package_c8(dev_priv);
6488         mutex_unlock(&dev_priv->pc8.lock);
6489 }
6490
6491 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6492 {
6493         struct drm_device *dev = dev_priv->dev;
6494         struct intel_crtc *crtc;
6495         uint32_t val;
6496
6497         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6498                 if (crtc->base.enabled)
6499                         return false;
6500
6501         /* This case is still possible since we have the i915.disable_power_well
6502          * parameter and also the KVMr or something else might be requesting the
6503          * power well. */
6504         val = I915_READ(HSW_PWR_WELL_DRIVER);
6505         if (val != 0) {
6506                 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6507                 return false;
6508         }
6509
6510         return true;
6511 }
6512
6513 /* Since we're called from modeset_global_resources there's no way to
6514  * symmetrically increase and decrease the refcount, so we use
6515  * dev_priv->pc8.requirements_met to track whether we already have the refcount
6516  * or not.
6517  */
6518 static void hsw_update_package_c8(struct drm_device *dev)
6519 {
6520         struct drm_i915_private *dev_priv = dev->dev_private;
6521         bool allow;
6522
6523         if (!i915_enable_pc8)
6524                 return;
6525
6526         mutex_lock(&dev_priv->pc8.lock);
6527
6528         allow = hsw_can_enable_package_c8(dev_priv);
6529
6530         if (allow == dev_priv->pc8.requirements_met)
6531                 goto done;
6532
6533         dev_priv->pc8.requirements_met = allow;
6534
6535         if (allow)
6536                 __hsw_enable_package_c8(dev_priv);
6537         else
6538                 __hsw_disable_package_c8(dev_priv);
6539
6540 done:
6541         mutex_unlock(&dev_priv->pc8.lock);
6542 }
6543
6544 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6545 {
6546         if (!dev_priv->pc8.gpu_idle) {
6547                 dev_priv->pc8.gpu_idle = true;
6548                 hsw_enable_package_c8(dev_priv);
6549         }
6550 }
6551
6552 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6553 {
6554         if (dev_priv->pc8.gpu_idle) {
6555                 dev_priv->pc8.gpu_idle = false;
6556                 hsw_disable_package_c8(dev_priv);
6557         }
6558 }
6559
6560 #define for_each_power_domain(domain, mask)                             \
6561         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
6562                 if ((1 << (domain)) & (mask))
6563
6564 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6565                                             enum pipe pipe, bool pfit_enabled)
6566 {
6567         unsigned long mask;
6568         enum transcoder transcoder;
6569
6570         transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6571
6572         mask = BIT(POWER_DOMAIN_PIPE(pipe));
6573         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6574         if (pfit_enabled)
6575                 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6576
6577         return mask;
6578 }
6579
6580 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6581 {
6582         struct drm_i915_private *dev_priv = dev->dev_private;
6583
6584         if (dev_priv->power_domains.init_power_on == enable)
6585                 return;
6586
6587         if (enable)
6588                 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6589         else
6590                 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6591
6592         dev_priv->power_domains.init_power_on = enable;
6593 }
6594
6595 static void modeset_update_power_wells(struct drm_device *dev)
6596 {
6597         unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6598         struct intel_crtc *crtc;
6599
6600         /*
6601          * First get all needed power domains, then put all unneeded, to avoid
6602          * any unnecessary toggling of the power wells.
6603          */
6604         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6605                 enum intel_display_power_domain domain;
6606
6607                 if (!crtc->base.enabled)
6608                         continue;
6609
6610                 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6611                                                 crtc->pipe,
6612                                                 crtc->config.pch_pfit.enabled);
6613
6614                 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6615                         intel_display_power_get(dev, domain);
6616         }
6617
6618         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6619                 enum intel_display_power_domain domain;
6620
6621                 for_each_power_domain(domain, crtc->enabled_power_domains)
6622                         intel_display_power_put(dev, domain);
6623
6624                 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6625         }
6626
6627         intel_display_set_init_power(dev, false);
6628 }
6629
6630 static void haswell_modeset_global_resources(struct drm_device *dev)
6631 {
6632         modeset_update_power_wells(dev);
6633         hsw_update_package_c8(dev);
6634 }
6635
6636 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6637                                  int x, int y,
6638                                  struct drm_framebuffer *fb)
6639 {
6640         struct drm_device *dev = crtc->dev;
6641         struct drm_i915_private *dev_priv = dev->dev_private;
6642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6643         int plane = intel_crtc->plane;
6644         int ret;
6645
6646         if (!intel_ddi_pll_mode_set(crtc))
6647                 return -EINVAL;
6648
6649         if (intel_crtc->config.has_dp_encoder)
6650                 intel_dp_set_m_n(intel_crtc);
6651
6652         intel_crtc->lowfreq_avail = false;
6653
6654         intel_set_pipe_timings(intel_crtc);
6655
6656         if (intel_crtc->config.has_pch_encoder) {
6657                 intel_cpu_transcoder_set_m_n(intel_crtc,
6658                                              &intel_crtc->config.fdi_m_n);
6659         }
6660
6661         haswell_set_pipeconf(crtc);
6662
6663         intel_set_pipe_csc(crtc);
6664
6665         /* Set up the display plane register */
6666         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6667         POSTING_READ(DSPCNTR(plane));
6668
6669         ret = intel_pipe_set_base(crtc, x, y, fb);
6670
6671         return ret;
6672 }
6673
6674 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6675                                     struct intel_crtc_config *pipe_config)
6676 {
6677         struct drm_device *dev = crtc->base.dev;
6678         struct drm_i915_private *dev_priv = dev->dev_private;
6679         enum intel_display_power_domain pfit_domain;
6680         uint32_t tmp;
6681
6682         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6683         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6684
6685         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6686         if (tmp & TRANS_DDI_FUNC_ENABLE) {
6687                 enum pipe trans_edp_pipe;
6688                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6689                 default:
6690                         WARN(1, "unknown pipe linked to edp transcoder\n");
6691                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6692                 case TRANS_DDI_EDP_INPUT_A_ON:
6693                         trans_edp_pipe = PIPE_A;
6694                         break;
6695                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6696                         trans_edp_pipe = PIPE_B;
6697                         break;
6698                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6699                         trans_edp_pipe = PIPE_C;
6700                         break;
6701                 }
6702
6703                 if (trans_edp_pipe == crtc->pipe)
6704                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
6705         }
6706
6707         if (!intel_display_power_enabled(dev,
6708                         POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6709                 return false;
6710
6711         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6712         if (!(tmp & PIPECONF_ENABLE))
6713                 return false;
6714
6715         /*
6716          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6717          * DDI E. So just check whether this pipe is wired to DDI E and whether
6718          * the PCH transcoder is on.
6719          */
6720         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6721         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6722             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6723                 pipe_config->has_pch_encoder = true;
6724
6725                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6726                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6727                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6728
6729                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6730         }
6731
6732         intel_get_pipe_timings(crtc, pipe_config);
6733
6734         pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6735         if (intel_display_power_enabled(dev, pfit_domain))
6736                 ironlake_get_pfit_config(crtc, pipe_config);
6737
6738         pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6739                                    (I915_READ(IPS_CTL) & IPS_ENABLE);
6740
6741         pipe_config->pixel_multiplier = 1;
6742
6743         return true;
6744 }
6745
6746 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6747                                int x, int y,
6748                                struct drm_framebuffer *fb)
6749 {
6750         struct drm_device *dev = crtc->dev;
6751         struct drm_i915_private *dev_priv = dev->dev_private;
6752         struct intel_encoder *encoder;
6753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6755         int pipe = intel_crtc->pipe;
6756         int ret;
6757
6758         drm_vblank_pre_modeset(dev, pipe);
6759
6760         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6761
6762         drm_vblank_post_modeset(dev, pipe);
6763
6764         if (ret != 0)
6765                 return ret;
6766
6767         for_each_encoder_on_crtc(dev, crtc, encoder) {
6768                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6769                         encoder->base.base.id,
6770                         drm_get_encoder_name(&encoder->base),
6771                         mode->base.id, mode->name);
6772                 encoder->mode_set(encoder);
6773         }
6774
6775         return 0;
6776 }
6777
6778 static struct {
6779         int clock;
6780         u32 config;
6781 } hdmi_audio_clock[] = {
6782         { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
6783         { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
6784         { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
6785         { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
6786         { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
6787         { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
6788         { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
6789         { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
6790         { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
6791         { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
6792 };
6793
6794 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
6795 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
6796 {
6797         int i;
6798
6799         for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
6800                 if (mode->clock == hdmi_audio_clock[i].clock)
6801                         break;
6802         }
6803
6804         if (i == ARRAY_SIZE(hdmi_audio_clock)) {
6805                 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
6806                 i = 1;
6807         }
6808
6809         DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
6810                       hdmi_audio_clock[i].clock,
6811                       hdmi_audio_clock[i].config);
6812
6813         return hdmi_audio_clock[i].config;
6814 }
6815
6816 static bool intel_eld_uptodate(struct drm_connector *connector,
6817                                int reg_eldv, uint32_t bits_eldv,
6818                                int reg_elda, uint32_t bits_elda,
6819                                int reg_edid)
6820 {
6821         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6822         uint8_t *eld = connector->eld;
6823         uint32_t i;
6824
6825         i = I915_READ(reg_eldv);
6826         i &= bits_eldv;
6827
6828         if (!eld[0])
6829                 return !i;
6830
6831         if (!i)
6832                 return false;
6833
6834         i = I915_READ(reg_elda);
6835         i &= ~bits_elda;
6836         I915_WRITE(reg_elda, i);
6837
6838         for (i = 0; i < eld[2]; i++)
6839                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6840                         return false;
6841
6842         return true;
6843 }
6844
6845 static void g4x_write_eld(struct drm_connector *connector,
6846                           struct drm_crtc *crtc,
6847                           struct drm_display_mode *mode)
6848 {
6849         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6850         uint8_t *eld = connector->eld;
6851         uint32_t eldv;
6852         uint32_t len;
6853         uint32_t i;
6854
6855         i = I915_READ(G4X_AUD_VID_DID);
6856
6857         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6858                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6859         else
6860                 eldv = G4X_ELDV_DEVCTG;
6861
6862         if (intel_eld_uptodate(connector,
6863                                G4X_AUD_CNTL_ST, eldv,
6864                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6865                                G4X_HDMIW_HDMIEDID))
6866                 return;
6867
6868         i = I915_READ(G4X_AUD_CNTL_ST);
6869         i &= ~(eldv | G4X_ELD_ADDR);
6870         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6871         I915_WRITE(G4X_AUD_CNTL_ST, i);
6872
6873         if (!eld[0])
6874                 return;
6875
6876         len = min_t(uint8_t, eld[2], len);
6877         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6878         for (i = 0; i < len; i++)
6879                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6880
6881         i = I915_READ(G4X_AUD_CNTL_ST);
6882         i |= eldv;
6883         I915_WRITE(G4X_AUD_CNTL_ST, i);
6884 }
6885
6886 static void haswell_write_eld(struct drm_connector *connector,
6887                               struct drm_crtc *crtc,
6888                               struct drm_display_mode *mode)
6889 {
6890         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6891         uint8_t *eld = connector->eld;
6892         struct drm_device *dev = crtc->dev;
6893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6894         uint32_t eldv;
6895         uint32_t i;
6896         int len;
6897         int pipe = to_intel_crtc(crtc)->pipe;
6898         int tmp;
6899
6900         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6901         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6902         int aud_config = HSW_AUD_CFG(pipe);
6903         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6904
6905
6906         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6907
6908         /* Audio output enable */
6909         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6910         tmp = I915_READ(aud_cntrl_st2);
6911         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6912         I915_WRITE(aud_cntrl_st2, tmp);
6913
6914         /* Wait for 1 vertical blank */
6915         intel_wait_for_vblank(dev, pipe);
6916
6917         /* Set ELD valid state */
6918         tmp = I915_READ(aud_cntrl_st2);
6919         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
6920         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6921         I915_WRITE(aud_cntrl_st2, tmp);
6922         tmp = I915_READ(aud_cntrl_st2);
6923         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
6924
6925         /* Enable HDMI mode */
6926         tmp = I915_READ(aud_config);
6927         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
6928         /* clear N_programing_enable and N_value_index */
6929         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6930         I915_WRITE(aud_config, tmp);
6931
6932         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6933
6934         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6935         intel_crtc->eld_vld = true;
6936
6937         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6938                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6939                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6940                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6941         } else {
6942                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
6943         }
6944
6945         if (intel_eld_uptodate(connector,
6946                                aud_cntrl_st2, eldv,
6947                                aud_cntl_st, IBX_ELD_ADDRESS,
6948                                hdmiw_hdmiedid))
6949                 return;
6950
6951         i = I915_READ(aud_cntrl_st2);
6952         i &= ~eldv;
6953         I915_WRITE(aud_cntrl_st2, i);
6954
6955         if (!eld[0])
6956                 return;
6957
6958         i = I915_READ(aud_cntl_st);
6959         i &= ~IBX_ELD_ADDRESS;
6960         I915_WRITE(aud_cntl_st, i);
6961         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6962         DRM_DEBUG_DRIVER("port num:%d\n", i);
6963
6964         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6965         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6966         for (i = 0; i < len; i++)
6967                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6968
6969         i = I915_READ(aud_cntrl_st2);
6970         i |= eldv;
6971         I915_WRITE(aud_cntrl_st2, i);
6972
6973 }
6974
6975 static void ironlake_write_eld(struct drm_connector *connector,
6976                                struct drm_crtc *crtc,
6977                                struct drm_display_mode *mode)
6978 {
6979         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6980         uint8_t *eld = connector->eld;
6981         uint32_t eldv;
6982         uint32_t i;
6983         int len;
6984         int hdmiw_hdmiedid;
6985         int aud_config;
6986         int aud_cntl_st;
6987         int aud_cntrl_st2;
6988         int pipe = to_intel_crtc(crtc)->pipe;
6989
6990         if (HAS_PCH_IBX(connector->dev)) {
6991                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6992                 aud_config = IBX_AUD_CFG(pipe);
6993                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6994                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6995         } else {
6996                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6997                 aud_config = CPT_AUD_CFG(pipe);
6998                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6999                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7000         }
7001
7002         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7003
7004         i = I915_READ(aud_cntl_st);
7005         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
7006         if (!i) {
7007                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7008                 /* operate blindly on all ports */
7009                 eldv = IBX_ELD_VALIDB;
7010                 eldv |= IBX_ELD_VALIDB << 4;
7011                 eldv |= IBX_ELD_VALIDB << 8;
7012         } else {
7013                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7014                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7015         }
7016
7017         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7018                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7019                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
7020                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7021         } else {
7022                 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7023         }
7024
7025         if (intel_eld_uptodate(connector,
7026                                aud_cntrl_st2, eldv,
7027                                aud_cntl_st, IBX_ELD_ADDRESS,
7028                                hdmiw_hdmiedid))
7029                 return;
7030
7031         i = I915_READ(aud_cntrl_st2);
7032         i &= ~eldv;
7033         I915_WRITE(aud_cntrl_st2, i);
7034
7035         if (!eld[0])
7036                 return;
7037
7038         i = I915_READ(aud_cntl_st);
7039         i &= ~IBX_ELD_ADDRESS;
7040         I915_WRITE(aud_cntl_st, i);
7041
7042         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
7043         DRM_DEBUG_DRIVER("ELD size %d\n", len);
7044         for (i = 0; i < len; i++)
7045                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7046
7047         i = I915_READ(aud_cntrl_st2);
7048         i |= eldv;
7049         I915_WRITE(aud_cntrl_st2, i);
7050 }
7051
7052 void intel_write_eld(struct drm_encoder *encoder,
7053                      struct drm_display_mode *mode)
7054 {
7055         struct drm_crtc *crtc = encoder->crtc;
7056         struct drm_connector *connector;
7057         struct drm_device *dev = encoder->dev;
7058         struct drm_i915_private *dev_priv = dev->dev_private;
7059
7060         connector = drm_select_eld(encoder, mode);
7061         if (!connector)
7062                 return;
7063
7064         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7065                          connector->base.id,
7066                          drm_get_connector_name(connector),
7067                          connector->encoder->base.id,
7068                          drm_get_encoder_name(connector->encoder));
7069
7070         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7071
7072         if (dev_priv->display.write_eld)
7073                 dev_priv->display.write_eld(connector, crtc, mode);
7074 }
7075
7076 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7077 {
7078         struct drm_device *dev = crtc->dev;
7079         struct drm_i915_private *dev_priv = dev->dev_private;
7080         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7081         bool visible = base != 0;
7082         u32 cntl;
7083
7084         if (intel_crtc->cursor_visible == visible)
7085                 return;
7086
7087         cntl = I915_READ(_CURACNTR);
7088         if (visible) {
7089                 /* On these chipsets we can only modify the base whilst
7090                  * the cursor is disabled.
7091                  */
7092                 I915_WRITE(_CURABASE, base);
7093
7094                 cntl &= ~(CURSOR_FORMAT_MASK);
7095                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7096                 cntl |= CURSOR_ENABLE |
7097                         CURSOR_GAMMA_ENABLE |
7098                         CURSOR_FORMAT_ARGB;
7099         } else
7100                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7101         I915_WRITE(_CURACNTR, cntl);
7102
7103         intel_crtc->cursor_visible = visible;
7104 }
7105
7106 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7107 {
7108         struct drm_device *dev = crtc->dev;
7109         struct drm_i915_private *dev_priv = dev->dev_private;
7110         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7111         int pipe = intel_crtc->pipe;
7112         bool visible = base != 0;
7113
7114         if (intel_crtc->cursor_visible != visible) {
7115                 uint32_t cntl = I915_READ(CURCNTR(pipe));
7116                 if (base) {
7117                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7118                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7119                         cntl |= pipe << 28; /* Connect to correct pipe */
7120                 } else {
7121                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7122                         cntl |= CURSOR_MODE_DISABLE;
7123                 }
7124                 I915_WRITE(CURCNTR(pipe), cntl);
7125
7126                 intel_crtc->cursor_visible = visible;
7127         }
7128         /* and commit changes on next vblank */
7129         I915_WRITE(CURBASE(pipe), base);
7130 }
7131
7132 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7133 {
7134         struct drm_device *dev = crtc->dev;
7135         struct drm_i915_private *dev_priv = dev->dev_private;
7136         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137         int pipe = intel_crtc->pipe;
7138         bool visible = base != 0;
7139
7140         if (intel_crtc->cursor_visible != visible) {
7141                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7142                 if (base) {
7143                         cntl &= ~CURSOR_MODE;
7144                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7145                 } else {
7146                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7147                         cntl |= CURSOR_MODE_DISABLE;
7148                 }
7149                 if (IS_HASWELL(dev)) {
7150                         cntl |= CURSOR_PIPE_CSC_ENABLE;
7151                         cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7152                 }
7153                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7154
7155                 intel_crtc->cursor_visible = visible;
7156         }
7157         /* and commit changes on next vblank */
7158         I915_WRITE(CURBASE_IVB(pipe), base);
7159 }
7160
7161 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7162 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7163                                      bool on)
7164 {
7165         struct drm_device *dev = crtc->dev;
7166         struct drm_i915_private *dev_priv = dev->dev_private;
7167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7168         int pipe = intel_crtc->pipe;
7169         int x = intel_crtc->cursor_x;
7170         int y = intel_crtc->cursor_y;
7171         u32 base = 0, pos = 0;
7172         bool visible;
7173
7174         if (on)
7175                 base = intel_crtc->cursor_addr;
7176
7177         if (x >= intel_crtc->config.pipe_src_w)
7178                 base = 0;
7179
7180         if (y >= intel_crtc->config.pipe_src_h)
7181                 base = 0;
7182
7183         if (x < 0) {
7184                 if (x + intel_crtc->cursor_width <= 0)
7185                         base = 0;
7186
7187                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7188                 x = -x;
7189         }
7190         pos |= x << CURSOR_X_SHIFT;
7191
7192         if (y < 0) {
7193                 if (y + intel_crtc->cursor_height <= 0)
7194                         base = 0;
7195
7196                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7197                 y = -y;
7198         }
7199         pos |= y << CURSOR_Y_SHIFT;
7200
7201         visible = base != 0;
7202         if (!visible && !intel_crtc->cursor_visible)
7203                 return;
7204
7205         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7206                 I915_WRITE(CURPOS_IVB(pipe), pos);
7207                 ivb_update_cursor(crtc, base);
7208         } else {
7209                 I915_WRITE(CURPOS(pipe), pos);
7210                 if (IS_845G(dev) || IS_I865G(dev))
7211                         i845_update_cursor(crtc, base);
7212                 else
7213                         i9xx_update_cursor(crtc, base);
7214         }
7215 }
7216
7217 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7218                                  struct drm_file *file,
7219                                  uint32_t handle,
7220                                  uint32_t width, uint32_t height)
7221 {
7222         struct drm_device *dev = crtc->dev;
7223         struct drm_i915_private *dev_priv = dev->dev_private;
7224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7225         struct drm_i915_gem_object *obj;
7226         uint32_t addr;
7227         int ret;
7228
7229         /* if we want to turn off the cursor ignore width and height */
7230         if (!handle) {
7231                 DRM_DEBUG_KMS("cursor off\n");
7232                 addr = 0;
7233                 obj = NULL;
7234                 mutex_lock(&dev->struct_mutex);
7235                 goto finish;
7236         }
7237
7238         /* Currently we only support 64x64 cursors */
7239         if (width != 64 || height != 64) {
7240                 DRM_ERROR("we currently only support 64x64 cursors\n");
7241                 return -EINVAL;
7242         }
7243
7244         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7245         if (&obj->base == NULL)
7246                 return -ENOENT;
7247
7248         if (obj->base.size < width * height * 4) {
7249                 DRM_ERROR("buffer is to small\n");
7250                 ret = -ENOMEM;
7251                 goto fail;
7252         }
7253
7254         /* we only need to pin inside GTT if cursor is non-phy */
7255         mutex_lock(&dev->struct_mutex);
7256         if (!dev_priv->info->cursor_needs_physical) {
7257                 unsigned alignment;
7258
7259                 if (obj->tiling_mode) {
7260                         DRM_ERROR("cursor cannot be tiled\n");
7261                         ret = -EINVAL;
7262                         goto fail_locked;
7263                 }
7264
7265                 /* Note that the w/a also requires 2 PTE of padding following
7266                  * the bo. We currently fill all unused PTE with the shadow
7267                  * page and so we should always have valid PTE following the
7268                  * cursor preventing the VT-d warning.
7269                  */
7270                 alignment = 0;
7271                 if (need_vtd_wa(dev))
7272                         alignment = 64*1024;
7273
7274                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7275                 if (ret) {
7276                         DRM_ERROR("failed to move cursor bo into the GTT\n");
7277                         goto fail_locked;
7278                 }
7279
7280                 ret = i915_gem_object_put_fence(obj);
7281                 if (ret) {
7282                         DRM_ERROR("failed to release fence for cursor");
7283                         goto fail_unpin;
7284                 }
7285
7286                 addr = i915_gem_obj_ggtt_offset(obj);
7287         } else {
7288                 int align = IS_I830(dev) ? 16 * 1024 : 256;
7289                 ret = i915_gem_attach_phys_object(dev, obj,
7290                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7291                                                   align);
7292                 if (ret) {
7293                         DRM_ERROR("failed to attach phys object\n");
7294                         goto fail_locked;
7295                 }
7296                 addr = obj->phys_obj->handle->busaddr;
7297         }
7298
7299         if (IS_GEN2(dev))
7300                 I915_WRITE(CURSIZE, (height << 12) | width);
7301
7302  finish:
7303         if (intel_crtc->cursor_bo) {
7304                 if (dev_priv->info->cursor_needs_physical) {
7305                         if (intel_crtc->cursor_bo != obj)
7306                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7307                 } else
7308                         i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7309                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7310         }
7311
7312         mutex_unlock(&dev->struct_mutex);
7313
7314         intel_crtc->cursor_addr = addr;
7315         intel_crtc->cursor_bo = obj;
7316         intel_crtc->cursor_width = width;
7317         intel_crtc->cursor_height = height;
7318
7319         if (intel_crtc->active)
7320                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7321
7322         return 0;
7323 fail_unpin:
7324         i915_gem_object_unpin_from_display_plane(obj);
7325 fail_locked:
7326         mutex_unlock(&dev->struct_mutex);
7327 fail:
7328         drm_gem_object_unreference_unlocked(&obj->base);
7329         return ret;
7330 }
7331
7332 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7333 {
7334         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7335
7336         intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7337         intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7338
7339         if (intel_crtc->active)
7340                 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7341
7342         return 0;
7343 }
7344
7345 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7346                                  u16 *blue, uint32_t start, uint32_t size)
7347 {
7348         int end = (start + size > 256) ? 256 : start + size, i;
7349         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7350
7351         for (i = start; i < end; i++) {
7352                 intel_crtc->lut_r[i] = red[i] >> 8;
7353                 intel_crtc->lut_g[i] = green[i] >> 8;
7354                 intel_crtc->lut_b[i] = blue[i] >> 8;
7355         }
7356
7357         intel_crtc_load_lut(crtc);
7358 }
7359
7360 /* VESA 640x480x72Hz mode to set on the pipe */
7361 static struct drm_display_mode load_detect_mode = {
7362         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7363                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7364 };
7365
7366 static struct drm_framebuffer *
7367 intel_framebuffer_create(struct drm_device *dev,
7368                          struct drm_mode_fb_cmd2 *mode_cmd,
7369                          struct drm_i915_gem_object *obj)
7370 {
7371         struct intel_framebuffer *intel_fb;
7372         int ret;
7373
7374         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7375         if (!intel_fb) {
7376                 drm_gem_object_unreference_unlocked(&obj->base);
7377                 return ERR_PTR(-ENOMEM);
7378         }
7379
7380         ret = i915_mutex_lock_interruptible(dev);
7381         if (ret)
7382                 goto err;
7383
7384         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7385         mutex_unlock(&dev->struct_mutex);
7386         if (ret)
7387                 goto err;
7388
7389         return &intel_fb->base;
7390 err:
7391         drm_gem_object_unreference_unlocked(&obj->base);
7392         kfree(intel_fb);
7393
7394         return ERR_PTR(ret);
7395 }
7396
7397 static u32
7398 intel_framebuffer_pitch_for_width(int width, int bpp)
7399 {
7400         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7401         return ALIGN(pitch, 64);
7402 }
7403
7404 static u32
7405 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7406 {
7407         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7408         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7409 }
7410
7411 static struct drm_framebuffer *
7412 intel_framebuffer_create_for_mode(struct drm_device *dev,
7413                                   struct drm_display_mode *mode,
7414                                   int depth, int bpp)
7415 {
7416         struct drm_i915_gem_object *obj;
7417         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7418
7419         obj = i915_gem_alloc_object(dev,
7420                                     intel_framebuffer_size_for_mode(mode, bpp));
7421         if (obj == NULL)
7422                 return ERR_PTR(-ENOMEM);
7423
7424         mode_cmd.width = mode->hdisplay;
7425         mode_cmd.height = mode->vdisplay;
7426         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7427                                                                 bpp);
7428         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7429
7430         return intel_framebuffer_create(dev, &mode_cmd, obj);
7431 }
7432
7433 static struct drm_framebuffer *
7434 mode_fits_in_fbdev(struct drm_device *dev,
7435                    struct drm_display_mode *mode)
7436 {
7437 #ifdef CONFIG_DRM_I915_FBDEV
7438         struct drm_i915_private *dev_priv = dev->dev_private;
7439         struct drm_i915_gem_object *obj;
7440         struct drm_framebuffer *fb;
7441
7442         if (dev_priv->fbdev == NULL)
7443                 return NULL;
7444
7445         obj = dev_priv->fbdev->ifb.obj;
7446         if (obj == NULL)
7447                 return NULL;
7448
7449         fb = &dev_priv->fbdev->ifb.base;
7450         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7451                                                                fb->bits_per_pixel))
7452                 return NULL;
7453
7454         if (obj->base.size < mode->vdisplay * fb->pitches[0])
7455                 return NULL;
7456
7457         return fb;
7458 #else
7459         return NULL;
7460 #endif
7461 }
7462
7463 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7464                                 struct drm_display_mode *mode,
7465                                 struct intel_load_detect_pipe *old)
7466 {
7467         struct intel_crtc *intel_crtc;
7468         struct intel_encoder *intel_encoder =
7469                 intel_attached_encoder(connector);
7470         struct drm_crtc *possible_crtc;
7471         struct drm_encoder *encoder = &intel_encoder->base;
7472         struct drm_crtc *crtc = NULL;
7473         struct drm_device *dev = encoder->dev;
7474         struct drm_framebuffer *fb;
7475         int i = -1;
7476
7477         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7478                       connector->base.id, drm_get_connector_name(connector),
7479                       encoder->base.id, drm_get_encoder_name(encoder));
7480
7481         /*
7482          * Algorithm gets a little messy:
7483          *
7484          *   - if the connector already has an assigned crtc, use it (but make
7485          *     sure it's on first)
7486          *
7487          *   - try to find the first unused crtc that can drive this connector,
7488          *     and use that if we find one
7489          */
7490
7491         /* See if we already have a CRTC for this connector */
7492         if (encoder->crtc) {
7493                 crtc = encoder->crtc;
7494
7495                 mutex_lock(&crtc->mutex);
7496
7497                 old->dpms_mode = connector->dpms;
7498                 old->load_detect_temp = false;
7499
7500                 /* Make sure the crtc and connector are running */
7501                 if (connector->dpms != DRM_MODE_DPMS_ON)
7502                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7503
7504                 return true;
7505         }
7506
7507         /* Find an unused one (if possible) */
7508         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7509                 i++;
7510                 if (!(encoder->possible_crtcs & (1 << i)))
7511                         continue;
7512                 if (!possible_crtc->enabled) {
7513                         crtc = possible_crtc;
7514                         break;
7515                 }
7516         }
7517
7518         /*
7519          * If we didn't find an unused CRTC, don't use any.
7520          */
7521         if (!crtc) {
7522                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7523                 return false;
7524         }
7525
7526         mutex_lock(&crtc->mutex);
7527         intel_encoder->new_crtc = to_intel_crtc(crtc);
7528         to_intel_connector(connector)->new_encoder = intel_encoder;
7529
7530         intel_crtc = to_intel_crtc(crtc);
7531         old->dpms_mode = connector->dpms;
7532         old->load_detect_temp = true;
7533         old->release_fb = NULL;
7534
7535         if (!mode)
7536                 mode = &load_detect_mode;
7537
7538         /* We need a framebuffer large enough to accommodate all accesses
7539          * that the plane may generate whilst we perform load detection.
7540          * We can not rely on the fbcon either being present (we get called
7541          * during its initialisation to detect all boot displays, or it may
7542          * not even exist) or that it is large enough to satisfy the
7543          * requested mode.
7544          */
7545         fb = mode_fits_in_fbdev(dev, mode);
7546         if (fb == NULL) {
7547                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7548                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7549                 old->release_fb = fb;
7550         } else
7551                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7552         if (IS_ERR(fb)) {
7553                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7554                 mutex_unlock(&crtc->mutex);
7555                 return false;
7556         }
7557
7558         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7559                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7560                 if (old->release_fb)
7561                         old->release_fb->funcs->destroy(old->release_fb);
7562                 mutex_unlock(&crtc->mutex);
7563                 return false;
7564         }
7565
7566         /* let the connector get through one full cycle before testing */
7567         intel_wait_for_vblank(dev, intel_crtc->pipe);
7568         return true;
7569 }
7570
7571 void intel_release_load_detect_pipe(struct drm_connector *connector,
7572                                     struct intel_load_detect_pipe *old)
7573 {
7574         struct intel_encoder *intel_encoder =
7575                 intel_attached_encoder(connector);
7576         struct drm_encoder *encoder = &intel_encoder->base;
7577         struct drm_crtc *crtc = encoder->crtc;
7578
7579         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7580                       connector->base.id, drm_get_connector_name(connector),
7581                       encoder->base.id, drm_get_encoder_name(encoder));
7582
7583         if (old->load_detect_temp) {
7584                 to_intel_connector(connector)->new_encoder = NULL;
7585                 intel_encoder->new_crtc = NULL;
7586                 intel_set_mode(crtc, NULL, 0, 0, NULL);
7587
7588                 if (old->release_fb) {
7589                         drm_framebuffer_unregister_private(old->release_fb);
7590                         drm_framebuffer_unreference(old->release_fb);
7591                 }
7592
7593                 mutex_unlock(&crtc->mutex);
7594                 return;
7595         }
7596
7597         /* Switch crtc and encoder back off if necessary */
7598         if (old->dpms_mode != DRM_MODE_DPMS_ON)
7599                 connector->funcs->dpms(connector, old->dpms_mode);
7600
7601         mutex_unlock(&crtc->mutex);
7602 }
7603
7604 static int i9xx_pll_refclk(struct drm_device *dev,
7605                            const struct intel_crtc_config *pipe_config)
7606 {
7607         struct drm_i915_private *dev_priv = dev->dev_private;
7608         u32 dpll = pipe_config->dpll_hw_state.dpll;
7609
7610         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7611                 return dev_priv->vbt.lvds_ssc_freq * 1000;
7612         else if (HAS_PCH_SPLIT(dev))
7613                 return 120000;
7614         else if (!IS_GEN2(dev))
7615                 return 96000;
7616         else
7617                 return 48000;
7618 }
7619
7620 /* Returns the clock of the currently programmed mode of the given pipe. */
7621 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7622                                 struct intel_crtc_config *pipe_config)
7623 {
7624         struct drm_device *dev = crtc->base.dev;
7625         struct drm_i915_private *dev_priv = dev->dev_private;
7626         int pipe = pipe_config->cpu_transcoder;
7627         u32 dpll = pipe_config->dpll_hw_state.dpll;
7628         u32 fp;
7629         intel_clock_t clock;
7630         int refclk = i9xx_pll_refclk(dev, pipe_config);
7631
7632         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7633                 fp = pipe_config->dpll_hw_state.fp0;
7634         else
7635                 fp = pipe_config->dpll_hw_state.fp1;
7636
7637         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7638         if (IS_PINEVIEW(dev)) {
7639                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7640                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7641         } else {
7642                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7643                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7644         }
7645
7646         if (!IS_GEN2(dev)) {
7647                 if (IS_PINEVIEW(dev))
7648                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7649                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7650                 else
7651                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7652                                DPLL_FPA01_P1_POST_DIV_SHIFT);
7653
7654                 switch (dpll & DPLL_MODE_MASK) {
7655                 case DPLLB_MODE_DAC_SERIAL:
7656                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7657                                 5 : 10;
7658                         break;
7659                 case DPLLB_MODE_LVDS:
7660                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7661                                 7 : 14;
7662                         break;
7663                 default:
7664                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7665                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
7666                         return;
7667                 }
7668
7669                 if (IS_PINEVIEW(dev))
7670                         pineview_clock(refclk, &clock);
7671                 else
7672                         i9xx_clock(refclk, &clock);
7673         } else {
7674                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7675
7676                 if (is_lvds) {
7677                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7678                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
7679                         clock.p2 = 14;
7680                 } else {
7681                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
7682                                 clock.p1 = 2;
7683                         else {
7684                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7685                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7686                         }
7687                         if (dpll & PLL_P2_DIVIDE_BY_4)
7688                                 clock.p2 = 4;
7689                         else
7690                                 clock.p2 = 2;
7691                 }
7692
7693                 i9xx_clock(refclk, &clock);
7694         }
7695
7696         /*
7697          * This value includes pixel_multiplier. We will use
7698          * port_clock to compute adjusted_mode.crtc_clock in the
7699          * encoder's get_config() function.
7700          */
7701         pipe_config->port_clock = clock.dot;
7702 }
7703
7704 int intel_dotclock_calculate(int link_freq,
7705                              const struct intel_link_m_n *m_n)
7706 {
7707         /*
7708          * The calculation for the data clock is:
7709          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7710          * But we want to avoid losing precison if possible, so:
7711          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7712          *
7713          * and the link clock is simpler:
7714          * link_clock = (m * link_clock) / n
7715          */
7716
7717         if (!m_n->link_n)
7718                 return 0;
7719
7720         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7721 }
7722
7723 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7724                                    struct intel_crtc_config *pipe_config)
7725 {
7726         struct drm_device *dev = crtc->base.dev;
7727
7728         /* read out port_clock from the DPLL */
7729         i9xx_crtc_clock_get(crtc, pipe_config);
7730
7731         /*
7732          * This value does not include pixel_multiplier.
7733          * We will check that port_clock and adjusted_mode.crtc_clock
7734          * agree once we know their relationship in the encoder's
7735          * get_config() function.
7736          */
7737         pipe_config->adjusted_mode.crtc_clock =
7738                 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7739                                          &pipe_config->fdi_m_n);
7740 }
7741
7742 /** Returns the currently programmed mode of the given pipe. */
7743 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7744                                              struct drm_crtc *crtc)
7745 {
7746         struct drm_i915_private *dev_priv = dev->dev_private;
7747         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7748         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7749         struct drm_display_mode *mode;
7750         struct intel_crtc_config pipe_config;
7751         int htot = I915_READ(HTOTAL(cpu_transcoder));
7752         int hsync = I915_READ(HSYNC(cpu_transcoder));
7753         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7754         int vsync = I915_READ(VSYNC(cpu_transcoder));
7755         enum pipe pipe = intel_crtc->pipe;
7756
7757         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7758         if (!mode)
7759                 return NULL;
7760
7761         /*
7762          * Construct a pipe_config sufficient for getting the clock info
7763          * back out of crtc_clock_get.
7764          *
7765          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7766          * to use a real value here instead.
7767          */
7768         pipe_config.cpu_transcoder = (enum transcoder) pipe;
7769         pipe_config.pixel_multiplier = 1;
7770         pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7771         pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7772         pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
7773         i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7774
7775         mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
7776         mode->hdisplay = (htot & 0xffff) + 1;
7777         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7778         mode->hsync_start = (hsync & 0xffff) + 1;
7779         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7780         mode->vdisplay = (vtot & 0xffff) + 1;
7781         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7782         mode->vsync_start = (vsync & 0xffff) + 1;
7783         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7784
7785         drm_mode_set_name(mode);
7786
7787         return mode;
7788 }
7789
7790 static void intel_increase_pllclock(struct drm_crtc *crtc)
7791 {
7792         struct drm_device *dev = crtc->dev;
7793         drm_i915_private_t *dev_priv = dev->dev_private;
7794         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7795         int pipe = intel_crtc->pipe;
7796         int dpll_reg = DPLL(pipe);
7797         int dpll;
7798
7799         if (HAS_PCH_SPLIT(dev))
7800                 return;
7801
7802         if (!dev_priv->lvds_downclock_avail)
7803                 return;
7804
7805         dpll = I915_READ(dpll_reg);
7806         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7807                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7808
7809                 assert_panel_unlocked(dev_priv, pipe);
7810
7811                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7812                 I915_WRITE(dpll_reg, dpll);
7813                 intel_wait_for_vblank(dev, pipe);
7814
7815                 dpll = I915_READ(dpll_reg);
7816                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7817                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7818         }
7819 }
7820
7821 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7822 {
7823         struct drm_device *dev = crtc->dev;
7824         drm_i915_private_t *dev_priv = dev->dev_private;
7825         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7826
7827         if (HAS_PCH_SPLIT(dev))
7828                 return;
7829
7830         if (!dev_priv->lvds_downclock_avail)
7831                 return;
7832
7833         /*
7834          * Since this is called by a timer, we should never get here in
7835          * the manual case.
7836          */
7837         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7838                 int pipe = intel_crtc->pipe;
7839                 int dpll_reg = DPLL(pipe);
7840                 int dpll;
7841
7842                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7843
7844                 assert_panel_unlocked(dev_priv, pipe);
7845
7846                 dpll = I915_READ(dpll_reg);
7847                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7848                 I915_WRITE(dpll_reg, dpll);
7849                 intel_wait_for_vblank(dev, pipe);
7850                 dpll = I915_READ(dpll_reg);
7851                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7852                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7853         }
7854
7855 }
7856
7857 void intel_mark_busy(struct drm_device *dev)
7858 {
7859         struct drm_i915_private *dev_priv = dev->dev_private;
7860
7861         hsw_package_c8_gpu_busy(dev_priv);
7862         i915_update_gfx_val(dev_priv);
7863 }
7864
7865 void intel_mark_idle(struct drm_device *dev)
7866 {
7867         struct drm_i915_private *dev_priv = dev->dev_private;
7868         struct drm_crtc *crtc;
7869
7870         hsw_package_c8_gpu_idle(dev_priv);
7871
7872         if (!i915_powersave)
7873                 return;
7874
7875         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7876                 if (!crtc->fb)
7877                         continue;
7878
7879                 intel_decrease_pllclock(crtc);
7880         }
7881
7882         if (dev_priv->info->gen >= 6)
7883                 gen6_rps_idle(dev->dev_private);
7884 }
7885
7886 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7887                         struct intel_ring_buffer *ring)
7888 {
7889         struct drm_device *dev = obj->base.dev;
7890         struct drm_crtc *crtc;
7891
7892         if (!i915_powersave)
7893                 return;
7894
7895         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7896                 if (!crtc->fb)
7897                         continue;
7898
7899                 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7900                         continue;
7901
7902                 intel_increase_pllclock(crtc);
7903                 if (ring && intel_fbc_enabled(dev))
7904                         ring->fbc_dirty = true;
7905         }
7906 }
7907
7908 static void intel_crtc_destroy(struct drm_crtc *crtc)
7909 {
7910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7911         struct drm_device *dev = crtc->dev;
7912         struct intel_unpin_work *work;
7913         unsigned long flags;
7914
7915         spin_lock_irqsave(&dev->event_lock, flags);
7916         work = intel_crtc->unpin_work;
7917         intel_crtc->unpin_work = NULL;
7918         spin_unlock_irqrestore(&dev->event_lock, flags);
7919
7920         if (work) {
7921                 cancel_work_sync(&work->work);
7922                 kfree(work);
7923         }
7924
7925         intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7926
7927         drm_crtc_cleanup(crtc);
7928
7929         kfree(intel_crtc);
7930 }
7931
7932 static void intel_unpin_work_fn(struct work_struct *__work)
7933 {
7934         struct intel_unpin_work *work =
7935                 container_of(__work, struct intel_unpin_work, work);
7936         struct drm_device *dev = work->crtc->dev;
7937
7938         mutex_lock(&dev->struct_mutex);
7939         intel_unpin_fb_obj(work->old_fb_obj);
7940         drm_gem_object_unreference(&work->pending_flip_obj->base);
7941         drm_gem_object_unreference(&work->old_fb_obj->base);
7942
7943         intel_update_fbc(dev);
7944         mutex_unlock(&dev->struct_mutex);
7945
7946         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7947         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7948
7949         kfree(work);
7950 }
7951
7952 static void do_intel_finish_page_flip(struct drm_device *dev,
7953                                       struct drm_crtc *crtc)
7954 {
7955         drm_i915_private_t *dev_priv = dev->dev_private;
7956         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7957         struct intel_unpin_work *work;
7958         unsigned long flags;
7959
7960         /* Ignore early vblank irqs */
7961         if (intel_crtc == NULL)
7962                 return;
7963
7964         spin_lock_irqsave(&dev->event_lock, flags);
7965         work = intel_crtc->unpin_work;
7966
7967         /* Ensure we don't miss a work->pending update ... */
7968         smp_rmb();
7969
7970         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7971                 spin_unlock_irqrestore(&dev->event_lock, flags);
7972                 return;
7973         }
7974
7975         /* and that the unpin work is consistent wrt ->pending. */
7976         smp_rmb();
7977
7978         intel_crtc->unpin_work = NULL;
7979
7980         if (work->event)
7981                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7982
7983         drm_vblank_put(dev, intel_crtc->pipe);
7984
7985         spin_unlock_irqrestore(&dev->event_lock, flags);
7986
7987         wake_up_all(&dev_priv->pending_flip_queue);
7988
7989         queue_work(dev_priv->wq, &work->work);
7990
7991         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7992 }
7993
7994 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7995 {
7996         drm_i915_private_t *dev_priv = dev->dev_private;
7997         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7998
7999         do_intel_finish_page_flip(dev, crtc);
8000 }
8001
8002 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8003 {
8004         drm_i915_private_t *dev_priv = dev->dev_private;
8005         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8006
8007         do_intel_finish_page_flip(dev, crtc);
8008 }
8009
8010 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8011 {
8012         drm_i915_private_t *dev_priv = dev->dev_private;
8013         struct intel_crtc *intel_crtc =
8014                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8015         unsigned long flags;
8016
8017         /* NB: An MMIO update of the plane base pointer will also
8018          * generate a page-flip completion irq, i.e. every modeset
8019          * is also accompanied by a spurious intel_prepare_page_flip().
8020          */
8021         spin_lock_irqsave(&dev->event_lock, flags);
8022         if (intel_crtc->unpin_work)
8023                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8024         spin_unlock_irqrestore(&dev->event_lock, flags);
8025 }
8026
8027 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8028 {
8029         /* Ensure that the work item is consistent when activating it ... */
8030         smp_wmb();
8031         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8032         /* and that it is marked active as soon as the irq could fire. */
8033         smp_wmb();
8034 }
8035
8036 static int intel_gen2_queue_flip(struct drm_device *dev,
8037                                  struct drm_crtc *crtc,
8038                                  struct drm_framebuffer *fb,
8039                                  struct drm_i915_gem_object *obj,
8040                                  uint32_t flags)
8041 {
8042         struct drm_i915_private *dev_priv = dev->dev_private;
8043         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8044         u32 flip_mask;
8045         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8046         int ret;
8047
8048         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8049         if (ret)
8050                 goto err;
8051
8052         ret = intel_ring_begin(ring, 6);
8053         if (ret)
8054                 goto err_unpin;
8055
8056         /* Can't queue multiple flips, so wait for the previous
8057          * one to finish before executing the next.
8058          */
8059         if (intel_crtc->plane)
8060                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8061         else
8062                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8063         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8064         intel_ring_emit(ring, MI_NOOP);
8065         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8066                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8067         intel_ring_emit(ring, fb->pitches[0]);
8068         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8069         intel_ring_emit(ring, 0); /* aux display base address, unused */
8070
8071         intel_mark_page_flip_active(intel_crtc);
8072         __intel_ring_advance(ring);
8073         return 0;
8074
8075 err_unpin:
8076         intel_unpin_fb_obj(obj);
8077 err:
8078         return ret;
8079 }
8080
8081 static int intel_gen3_queue_flip(struct drm_device *dev,
8082                                  struct drm_crtc *crtc,
8083                                  struct drm_framebuffer *fb,
8084                                  struct drm_i915_gem_object *obj,
8085                                  uint32_t flags)
8086 {
8087         struct drm_i915_private *dev_priv = dev->dev_private;
8088         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8089         u32 flip_mask;
8090         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8091         int ret;
8092
8093         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8094         if (ret)
8095                 goto err;
8096
8097         ret = intel_ring_begin(ring, 6);
8098         if (ret)
8099                 goto err_unpin;
8100
8101         if (intel_crtc->plane)
8102                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8103         else
8104                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8105         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8106         intel_ring_emit(ring, MI_NOOP);
8107         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8108                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8109         intel_ring_emit(ring, fb->pitches[0]);
8110         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8111         intel_ring_emit(ring, MI_NOOP);
8112
8113         intel_mark_page_flip_active(intel_crtc);
8114         __intel_ring_advance(ring);
8115         return 0;
8116
8117 err_unpin:
8118         intel_unpin_fb_obj(obj);
8119 err:
8120         return ret;
8121 }
8122
8123 static int intel_gen4_queue_flip(struct drm_device *dev,
8124                                  struct drm_crtc *crtc,
8125                                  struct drm_framebuffer *fb,
8126                                  struct drm_i915_gem_object *obj,
8127                                  uint32_t flags)
8128 {
8129         struct drm_i915_private *dev_priv = dev->dev_private;
8130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8131         uint32_t pf, pipesrc;
8132         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8133         int ret;
8134
8135         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8136         if (ret)
8137                 goto err;
8138
8139         ret = intel_ring_begin(ring, 4);
8140         if (ret)
8141                 goto err_unpin;
8142
8143         /* i965+ uses the linear or tiled offsets from the
8144          * Display Registers (which do not change across a page-flip)
8145          * so we need only reprogram the base address.
8146          */
8147         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8148                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8149         intel_ring_emit(ring, fb->pitches[0]);
8150         intel_ring_emit(ring,
8151                         (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8152                         obj->tiling_mode);
8153
8154         /* XXX Enabling the panel-fitter across page-flip is so far
8155          * untested on non-native modes, so ignore it for now.
8156          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8157          */
8158         pf = 0;
8159         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8160         intel_ring_emit(ring, pf | pipesrc);
8161
8162         intel_mark_page_flip_active(intel_crtc);
8163         __intel_ring_advance(ring);
8164         return 0;
8165
8166 err_unpin:
8167         intel_unpin_fb_obj(obj);
8168 err:
8169         return ret;
8170 }
8171
8172 static int intel_gen6_queue_flip(struct drm_device *dev,
8173                                  struct drm_crtc *crtc,
8174                                  struct drm_framebuffer *fb,
8175                                  struct drm_i915_gem_object *obj,
8176                                  uint32_t flags)
8177 {
8178         struct drm_i915_private *dev_priv = dev->dev_private;
8179         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8180         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8181         uint32_t pf, pipesrc;
8182         int ret;
8183
8184         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8185         if (ret)
8186                 goto err;
8187
8188         ret = intel_ring_begin(ring, 4);
8189         if (ret)
8190                 goto err_unpin;
8191
8192         intel_ring_emit(ring, MI_DISPLAY_FLIP |
8193                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8194         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8195         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8196
8197         /* Contrary to the suggestions in the documentation,
8198          * "Enable Panel Fitter" does not seem to be required when page
8199          * flipping with a non-native mode, and worse causes a normal
8200          * modeset to fail.
8201          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8202          */
8203         pf = 0;
8204         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8205         intel_ring_emit(ring, pf | pipesrc);
8206
8207         intel_mark_page_flip_active(intel_crtc);
8208         __intel_ring_advance(ring);
8209         return 0;
8210
8211 err_unpin:
8212         intel_unpin_fb_obj(obj);
8213 err:
8214         return ret;
8215 }
8216
8217 static int intel_gen7_queue_flip(struct drm_device *dev,
8218                                  struct drm_crtc *crtc,
8219                                  struct drm_framebuffer *fb,
8220                                  struct drm_i915_gem_object *obj,
8221                                  uint32_t flags)
8222 {
8223         struct drm_i915_private *dev_priv = dev->dev_private;
8224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8225         struct intel_ring_buffer *ring;
8226         uint32_t plane_bit = 0;
8227         int len, ret;
8228
8229         ring = obj->ring;
8230         if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8231                 ring = &dev_priv->ring[BCS];
8232
8233         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8234         if (ret)
8235                 goto err;
8236
8237         switch(intel_crtc->plane) {
8238         case PLANE_A:
8239                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8240                 break;
8241         case PLANE_B:
8242                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8243                 break;
8244         case PLANE_C:
8245                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8246                 break;
8247         default:
8248                 WARN_ONCE(1, "unknown plane in flip command\n");
8249                 ret = -ENODEV;
8250                 goto err_unpin;
8251         }
8252
8253         len = 4;
8254         if (ring->id == RCS)
8255                 len += 6;
8256
8257         ret = intel_ring_begin(ring, len);
8258         if (ret)
8259                 goto err_unpin;
8260
8261         /* Unmask the flip-done completion message. Note that the bspec says that
8262          * we should do this for both the BCS and RCS, and that we must not unmask
8263          * more than one flip event at any time (or ensure that one flip message
8264          * can be sent by waiting for flip-done prior to queueing new flips).
8265          * Experimentation says that BCS works despite DERRMR masking all
8266          * flip-done completion events and that unmasking all planes at once
8267          * for the RCS also doesn't appear to drop events. Setting the DERRMR
8268          * to zero does lead to lockups within MI_DISPLAY_FLIP.
8269          */
8270         if (ring->id == RCS) {
8271                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8272                 intel_ring_emit(ring, DERRMR);
8273                 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8274                                         DERRMR_PIPEB_PRI_FLIP_DONE |
8275                                         DERRMR_PIPEC_PRI_FLIP_DONE));
8276                 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8277                 intel_ring_emit(ring, DERRMR);
8278                 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8279         }
8280
8281         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8282         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8283         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8284         intel_ring_emit(ring, (MI_NOOP));
8285
8286         intel_mark_page_flip_active(intel_crtc);
8287         __intel_ring_advance(ring);
8288         return 0;
8289
8290 err_unpin:
8291         intel_unpin_fb_obj(obj);
8292 err:
8293         return ret;
8294 }
8295
8296 static int intel_default_queue_flip(struct drm_device *dev,
8297                                     struct drm_crtc *crtc,
8298                                     struct drm_framebuffer *fb,
8299                                     struct drm_i915_gem_object *obj,
8300                                     uint32_t flags)
8301 {
8302         return -ENODEV;
8303 }
8304
8305 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8306                                 struct drm_framebuffer *fb,
8307                                 struct drm_pending_vblank_event *event,
8308                                 uint32_t page_flip_flags)
8309 {
8310         struct drm_device *dev = crtc->dev;
8311         struct drm_i915_private *dev_priv = dev->dev_private;
8312         struct drm_framebuffer *old_fb = crtc->fb;
8313         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8314         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8315         struct intel_unpin_work *work;
8316         unsigned long flags;
8317         int ret;
8318
8319         /* Can't change pixel format via MI display flips. */
8320         if (fb->pixel_format != crtc->fb->pixel_format)
8321                 return -EINVAL;
8322
8323         /*
8324          * TILEOFF/LINOFF registers can't be changed via MI display flips.
8325          * Note that pitch changes could also affect these register.
8326          */
8327         if (INTEL_INFO(dev)->gen > 3 &&
8328             (fb->offsets[0] != crtc->fb->offsets[0] ||
8329              fb->pitches[0] != crtc->fb->pitches[0]))
8330                 return -EINVAL;
8331
8332         work = kzalloc(sizeof(*work), GFP_KERNEL);
8333         if (work == NULL)
8334                 return -ENOMEM;
8335
8336         work->event = event;
8337         work->crtc = crtc;
8338         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8339         INIT_WORK(&work->work, intel_unpin_work_fn);
8340
8341         ret = drm_vblank_get(dev, intel_crtc->pipe);
8342         if (ret)
8343                 goto free_work;
8344
8345         /* We borrow the event spin lock for protecting unpin_work */
8346         spin_lock_irqsave(&dev->event_lock, flags);
8347         if (intel_crtc->unpin_work) {
8348                 spin_unlock_irqrestore(&dev->event_lock, flags);
8349                 kfree(work);
8350                 drm_vblank_put(dev, intel_crtc->pipe);
8351
8352                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8353                 return -EBUSY;
8354         }
8355         intel_crtc->unpin_work = work;
8356         spin_unlock_irqrestore(&dev->event_lock, flags);
8357
8358         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8359                 flush_workqueue(dev_priv->wq);
8360
8361         ret = i915_mutex_lock_interruptible(dev);
8362         if (ret)
8363                 goto cleanup;
8364
8365         /* Reference the objects for the scheduled work. */
8366         drm_gem_object_reference(&work->old_fb_obj->base);
8367         drm_gem_object_reference(&obj->base);
8368
8369         crtc->fb = fb;
8370
8371         work->pending_flip_obj = obj;
8372
8373         work->enable_stall_check = true;
8374
8375         atomic_inc(&intel_crtc->unpin_work_count);
8376         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8377
8378         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8379         if (ret)
8380                 goto cleanup_pending;
8381
8382         intel_disable_fbc(dev);
8383         intel_mark_fb_busy(obj, NULL);
8384         mutex_unlock(&dev->struct_mutex);
8385
8386         trace_i915_flip_request(intel_crtc->plane, obj);
8387
8388         return 0;
8389
8390 cleanup_pending:
8391         atomic_dec(&intel_crtc->unpin_work_count);
8392         crtc->fb = old_fb;
8393         drm_gem_object_unreference(&work->old_fb_obj->base);
8394         drm_gem_object_unreference(&obj->base);
8395         mutex_unlock(&dev->struct_mutex);
8396
8397 cleanup:
8398         spin_lock_irqsave(&dev->event_lock, flags);
8399         intel_crtc->unpin_work = NULL;
8400         spin_unlock_irqrestore(&dev->event_lock, flags);
8401
8402         drm_vblank_put(dev, intel_crtc->pipe);
8403 free_work:
8404         kfree(work);
8405
8406         return ret;
8407 }
8408
8409 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8410         .mode_set_base_atomic = intel_pipe_set_base_atomic,
8411         .load_lut = intel_crtc_load_lut,
8412 };
8413
8414 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8415                                   struct drm_crtc *crtc)
8416 {
8417         struct drm_device *dev;
8418         struct drm_crtc *tmp;
8419         int crtc_mask = 1;
8420
8421         WARN(!crtc, "checking null crtc?\n");
8422
8423         dev = crtc->dev;
8424
8425         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8426                 if (tmp == crtc)
8427                         break;
8428                 crtc_mask <<= 1;
8429         }
8430
8431         if (encoder->possible_crtcs & crtc_mask)
8432                 return true;
8433         return false;
8434 }
8435
8436 /**
8437  * intel_modeset_update_staged_output_state
8438  *
8439  * Updates the staged output configuration state, e.g. after we've read out the
8440  * current hw state.
8441  */
8442 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8443 {
8444         struct intel_encoder *encoder;
8445         struct intel_connector *connector;
8446
8447         list_for_each_entry(connector, &dev->mode_config.connector_list,
8448                             base.head) {
8449                 connector->new_encoder =
8450                         to_intel_encoder(connector->base.encoder);
8451         }
8452
8453         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8454                             base.head) {
8455                 encoder->new_crtc =
8456                         to_intel_crtc(encoder->base.crtc);
8457         }
8458 }
8459
8460 /**
8461  * intel_modeset_commit_output_state
8462  *
8463  * This function copies the stage display pipe configuration to the real one.
8464  */
8465 static void intel_modeset_commit_output_state(struct drm_device *dev)
8466 {
8467         struct intel_encoder *encoder;
8468         struct intel_connector *connector;
8469
8470         list_for_each_entry(connector, &dev->mode_config.connector_list,
8471                             base.head) {
8472                 connector->base.encoder = &connector->new_encoder->base;
8473         }
8474
8475         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8476                             base.head) {
8477                 encoder->base.crtc = &encoder->new_crtc->base;
8478         }
8479 }
8480
8481 static void
8482 connected_sink_compute_bpp(struct intel_connector * connector,
8483                            struct intel_crtc_config *pipe_config)
8484 {
8485         int bpp = pipe_config->pipe_bpp;
8486
8487         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8488                 connector->base.base.id,
8489                 drm_get_connector_name(&connector->base));
8490
8491         /* Don't use an invalid EDID bpc value */
8492         if (connector->base.display_info.bpc &&
8493             connector->base.display_info.bpc * 3 < bpp) {
8494                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8495                               bpp, connector->base.display_info.bpc*3);
8496                 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8497         }
8498
8499         /* Clamp bpp to 8 on screens without EDID 1.4 */
8500         if (connector->base.display_info.bpc == 0 && bpp > 24) {
8501                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8502                               bpp);
8503                 pipe_config->pipe_bpp = 24;
8504         }
8505 }
8506
8507 static int
8508 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8509                           struct drm_framebuffer *fb,
8510                           struct intel_crtc_config *pipe_config)
8511 {
8512         struct drm_device *dev = crtc->base.dev;
8513         struct intel_connector *connector;
8514         int bpp;
8515
8516         switch (fb->pixel_format) {
8517         case DRM_FORMAT_C8:
8518                 bpp = 8*3; /* since we go through a colormap */
8519                 break;
8520         case DRM_FORMAT_XRGB1555:
8521         case DRM_FORMAT_ARGB1555:
8522                 /* checked in intel_framebuffer_init already */
8523                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8524                         return -EINVAL;
8525         case DRM_FORMAT_RGB565:
8526                 bpp = 6*3; /* min is 18bpp */
8527                 break;
8528         case DRM_FORMAT_XBGR8888:
8529         case DRM_FORMAT_ABGR8888:
8530                 /* checked in intel_framebuffer_init already */
8531                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8532                         return -EINVAL;
8533         case DRM_FORMAT_XRGB8888:
8534         case DRM_FORMAT_ARGB8888:
8535                 bpp = 8*3;
8536                 break;
8537         case DRM_FORMAT_XRGB2101010:
8538         case DRM_FORMAT_ARGB2101010:
8539         case DRM_FORMAT_XBGR2101010:
8540         case DRM_FORMAT_ABGR2101010:
8541                 /* checked in intel_framebuffer_init already */
8542                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8543                         return -EINVAL;
8544                 bpp = 10*3;
8545                 break;
8546         /* TODO: gen4+ supports 16 bpc floating point, too. */
8547         default:
8548                 DRM_DEBUG_KMS("unsupported depth\n");
8549                 return -EINVAL;
8550         }
8551
8552         pipe_config->pipe_bpp = bpp;
8553
8554         /* Clamp display bpp to EDID value */
8555         list_for_each_entry(connector, &dev->mode_config.connector_list,
8556                             base.head) {
8557                 if (!connector->new_encoder ||
8558                     connector->new_encoder->new_crtc != crtc)
8559                         continue;
8560
8561                 connected_sink_compute_bpp(connector, pipe_config);
8562         }
8563
8564         return bpp;
8565 }
8566
8567 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8568 {
8569         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8570                         "type: 0x%x flags: 0x%x\n",
8571                 mode->crtc_clock,
8572                 mode->crtc_hdisplay, mode->crtc_hsync_start,
8573                 mode->crtc_hsync_end, mode->crtc_htotal,
8574                 mode->crtc_vdisplay, mode->crtc_vsync_start,
8575                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8576 }
8577
8578 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8579                                    struct intel_crtc_config *pipe_config,
8580                                    const char *context)
8581 {
8582         DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8583                       context, pipe_name(crtc->pipe));
8584
8585         DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8586         DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8587                       pipe_config->pipe_bpp, pipe_config->dither);
8588         DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8589                       pipe_config->has_pch_encoder,
8590                       pipe_config->fdi_lanes,
8591                       pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8592                       pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8593                       pipe_config->fdi_m_n.tu);
8594         DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8595                       pipe_config->has_dp_encoder,
8596                       pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8597                       pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8598                       pipe_config->dp_m_n.tu);
8599         DRM_DEBUG_KMS("requested mode:\n");
8600         drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8601         DRM_DEBUG_KMS("adjusted mode:\n");
8602         drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8603         intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8604         DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8605         DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8606                       pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8607         DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8608                       pipe_config->gmch_pfit.control,
8609                       pipe_config->gmch_pfit.pgm_ratios,
8610                       pipe_config->gmch_pfit.lvds_border_bits);
8611         DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8612                       pipe_config->pch_pfit.pos,
8613                       pipe_config->pch_pfit.size,
8614                       pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8615         DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8616         DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8617 }
8618
8619 static bool check_encoder_cloning(struct drm_crtc *crtc)
8620 {
8621         int num_encoders = 0;
8622         bool uncloneable_encoders = false;
8623         struct intel_encoder *encoder;
8624
8625         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8626                             base.head) {
8627                 if (&encoder->new_crtc->base != crtc)
8628                         continue;
8629
8630                 num_encoders++;
8631                 if (!encoder->cloneable)
8632                         uncloneable_encoders = true;
8633         }
8634
8635         return !(num_encoders > 1 && uncloneable_encoders);
8636 }
8637
8638 static struct intel_crtc_config *
8639 intel_modeset_pipe_config(struct drm_crtc *crtc,
8640                           struct drm_framebuffer *fb,
8641                           struct drm_display_mode *mode)
8642 {
8643         struct drm_device *dev = crtc->dev;
8644         struct intel_encoder *encoder;
8645         struct intel_crtc_config *pipe_config;
8646         int plane_bpp, ret = -EINVAL;
8647         bool retry = true;
8648
8649         if (!check_encoder_cloning(crtc)) {
8650                 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8651                 return ERR_PTR(-EINVAL);
8652         }
8653
8654         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8655         if (!pipe_config)
8656                 return ERR_PTR(-ENOMEM);
8657
8658         drm_mode_copy(&pipe_config->adjusted_mode, mode);
8659         drm_mode_copy(&pipe_config->requested_mode, mode);
8660
8661         pipe_config->cpu_transcoder =
8662                 (enum transcoder) to_intel_crtc(crtc)->pipe;
8663         pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8664
8665         /*
8666          * Sanitize sync polarity flags based on requested ones. If neither
8667          * positive or negative polarity is requested, treat this as meaning
8668          * negative polarity.
8669          */
8670         if (!(pipe_config->adjusted_mode.flags &
8671               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8672                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8673
8674         if (!(pipe_config->adjusted_mode.flags &
8675               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8676                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8677
8678         /* Compute a starting value for pipe_config->pipe_bpp taking the source
8679          * plane pixel format and any sink constraints into account. Returns the
8680          * source plane bpp so that dithering can be selected on mismatches
8681          * after encoders and crtc also have had their say. */
8682         plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8683                                               fb, pipe_config);
8684         if (plane_bpp < 0)
8685                 goto fail;
8686
8687         /*
8688          * Determine the real pipe dimensions. Note that stereo modes can
8689          * increase the actual pipe size due to the frame doubling and
8690          * insertion of additional space for blanks between the frame. This
8691          * is stored in the crtc timings. We use the requested mode to do this
8692          * computation to clearly distinguish it from the adjusted mode, which
8693          * can be changed by the connectors in the below retry loop.
8694          */
8695         drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8696         pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8697         pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8698
8699 encoder_retry:
8700         /* Ensure the port clock defaults are reset when retrying. */
8701         pipe_config->port_clock = 0;
8702         pipe_config->pixel_multiplier = 1;
8703
8704         /* Fill in default crtc timings, allow encoders to overwrite them. */
8705         drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
8706
8707         /* Pass our mode to the connectors and the CRTC to give them a chance to
8708          * adjust it according to limitations or connector properties, and also
8709          * a chance to reject the mode entirely.
8710          */
8711         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8712                             base.head) {
8713
8714                 if (&encoder->new_crtc->base != crtc)
8715                         continue;
8716
8717                 if (!(encoder->compute_config(encoder, pipe_config))) {
8718                         DRM_DEBUG_KMS("Encoder config failure\n");
8719                         goto fail;
8720                 }
8721         }
8722
8723         /* Set default port clock if not overwritten by the encoder. Needs to be
8724          * done afterwards in case the encoder adjusts the mode. */
8725         if (!pipe_config->port_clock)
8726                 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8727                         * pipe_config->pixel_multiplier;
8728
8729         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
8730         if (ret < 0) {
8731                 DRM_DEBUG_KMS("CRTC fixup failed\n");
8732                 goto fail;
8733         }
8734
8735         if (ret == RETRY) {
8736                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8737                         ret = -EINVAL;
8738                         goto fail;
8739                 }
8740
8741                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8742                 retry = false;
8743                 goto encoder_retry;
8744         }
8745
8746         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8747         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8748                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8749
8750         return pipe_config;
8751 fail:
8752         kfree(pipe_config);
8753         return ERR_PTR(ret);
8754 }
8755
8756 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8757  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8758 static void
8759 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8760                              unsigned *prepare_pipes, unsigned *disable_pipes)
8761 {
8762         struct intel_crtc *intel_crtc;
8763         struct drm_device *dev = crtc->dev;
8764         struct intel_encoder *encoder;
8765         struct intel_connector *connector;
8766         struct drm_crtc *tmp_crtc;
8767
8768         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
8769
8770         /* Check which crtcs have changed outputs connected to them, these need
8771          * to be part of the prepare_pipes mask. We don't (yet) support global
8772          * modeset across multiple crtcs, so modeset_pipes will only have one
8773          * bit set at most. */
8774         list_for_each_entry(connector, &dev->mode_config.connector_list,
8775                             base.head) {
8776                 if (connector->base.encoder == &connector->new_encoder->base)
8777                         continue;
8778
8779                 if (connector->base.encoder) {
8780                         tmp_crtc = connector->base.encoder->crtc;
8781
8782                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8783                 }
8784
8785                 if (connector->new_encoder)
8786                         *prepare_pipes |=
8787                                 1 << connector->new_encoder->new_crtc->pipe;
8788         }
8789
8790         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8791                             base.head) {
8792                 if (encoder->base.crtc == &encoder->new_crtc->base)
8793                         continue;
8794
8795                 if (encoder->base.crtc) {
8796                         tmp_crtc = encoder->base.crtc;
8797
8798                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8799                 }
8800
8801                 if (encoder->new_crtc)
8802                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
8803         }
8804
8805         /* Check for any pipes that will be fully disabled ... */
8806         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8807                             base.head) {
8808                 bool used = false;
8809
8810                 /* Don't try to disable disabled crtcs. */
8811                 if (!intel_crtc->base.enabled)
8812                         continue;
8813
8814                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8815                                     base.head) {
8816                         if (encoder->new_crtc == intel_crtc)
8817                                 used = true;
8818                 }
8819
8820                 if (!used)
8821                         *disable_pipes |= 1 << intel_crtc->pipe;
8822         }
8823
8824
8825         /* set_mode is also used to update properties on life display pipes. */
8826         intel_crtc = to_intel_crtc(crtc);
8827         if (crtc->enabled)
8828                 *prepare_pipes |= 1 << intel_crtc->pipe;
8829
8830         /*
8831          * For simplicity do a full modeset on any pipe where the output routing
8832          * changed. We could be more clever, but that would require us to be
8833          * more careful with calling the relevant encoder->mode_set functions.
8834          */
8835         if (*prepare_pipes)
8836                 *modeset_pipes = *prepare_pipes;
8837
8838         /* ... and mask these out. */
8839         *modeset_pipes &= ~(*disable_pipes);
8840         *prepare_pipes &= ~(*disable_pipes);
8841
8842         /*
8843          * HACK: We don't (yet) fully support global modesets. intel_set_config
8844          * obies this rule, but the modeset restore mode of
8845          * intel_modeset_setup_hw_state does not.
8846          */
8847         *modeset_pipes &= 1 << intel_crtc->pipe;
8848         *prepare_pipes &= 1 << intel_crtc->pipe;
8849
8850         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8851                       *modeset_pipes, *prepare_pipes, *disable_pipes);
8852 }
8853
8854 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8855 {
8856         struct drm_encoder *encoder;
8857         struct drm_device *dev = crtc->dev;
8858
8859         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8860                 if (encoder->crtc == crtc)
8861                         return true;
8862
8863         return false;
8864 }
8865
8866 static void
8867 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8868 {
8869         struct intel_encoder *intel_encoder;
8870         struct intel_crtc *intel_crtc;
8871         struct drm_connector *connector;
8872
8873         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8874                             base.head) {
8875                 if (!intel_encoder->base.crtc)
8876                         continue;
8877
8878                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8879
8880                 if (prepare_pipes & (1 << intel_crtc->pipe))
8881                         intel_encoder->connectors_active = false;
8882         }
8883
8884         intel_modeset_commit_output_state(dev);
8885
8886         /* Update computed state. */
8887         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8888                             base.head) {
8889                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8890         }
8891
8892         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8893                 if (!connector->encoder || !connector->encoder->crtc)
8894                         continue;
8895
8896                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8897
8898                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8899                         struct drm_property *dpms_property =
8900                                 dev->mode_config.dpms_property;
8901
8902                         connector->dpms = DRM_MODE_DPMS_ON;
8903                         drm_object_property_set_value(&connector->base,
8904                                                          dpms_property,
8905                                                          DRM_MODE_DPMS_ON);
8906
8907                         intel_encoder = to_intel_encoder(connector->encoder);
8908                         intel_encoder->connectors_active = true;
8909                 }
8910         }
8911
8912 }
8913
8914 static bool intel_fuzzy_clock_check(int clock1, int clock2)
8915 {
8916         int diff;
8917
8918         if (clock1 == clock2)
8919                 return true;
8920
8921         if (!clock1 || !clock2)
8922                 return false;
8923
8924         diff = abs(clock1 - clock2);
8925
8926         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8927                 return true;
8928
8929         return false;
8930 }
8931
8932 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8933         list_for_each_entry((intel_crtc), \
8934                             &(dev)->mode_config.crtc_list, \
8935                             base.head) \
8936                 if (mask & (1 <<(intel_crtc)->pipe))
8937
8938 static bool
8939 intel_pipe_config_compare(struct drm_device *dev,
8940                           struct intel_crtc_config *current_config,
8941                           struct intel_crtc_config *pipe_config)
8942 {
8943 #define PIPE_CONF_CHECK_X(name) \
8944         if (current_config->name != pipe_config->name) { \
8945                 DRM_ERROR("mismatch in " #name " " \
8946                           "(expected 0x%08x, found 0x%08x)\n", \
8947                           current_config->name, \
8948                           pipe_config->name); \
8949                 return false; \
8950         }
8951
8952 #define PIPE_CONF_CHECK_I(name) \
8953         if (current_config->name != pipe_config->name) { \
8954                 DRM_ERROR("mismatch in " #name " " \
8955                           "(expected %i, found %i)\n", \
8956                           current_config->name, \
8957                           pipe_config->name); \
8958                 return false; \
8959         }
8960
8961 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8962         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8963                 DRM_ERROR("mismatch in " #name "(" #mask ") "      \
8964                           "(expected %i, found %i)\n", \
8965                           current_config->name & (mask), \
8966                           pipe_config->name & (mask)); \
8967                 return false; \
8968         }
8969
8970 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8971         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8972                 DRM_ERROR("mismatch in " #name " " \
8973                           "(expected %i, found %i)\n", \
8974                           current_config->name, \
8975                           pipe_config->name); \
8976                 return false; \
8977         }
8978
8979 #define PIPE_CONF_QUIRK(quirk)  \
8980         ((current_config->quirks | pipe_config->quirks) & (quirk))
8981
8982         PIPE_CONF_CHECK_I(cpu_transcoder);
8983
8984         PIPE_CONF_CHECK_I(has_pch_encoder);
8985         PIPE_CONF_CHECK_I(fdi_lanes);
8986         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8987         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8988         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8989         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8990         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8991
8992         PIPE_CONF_CHECK_I(has_dp_encoder);
8993         PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8994         PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8995         PIPE_CONF_CHECK_I(dp_m_n.link_m);
8996         PIPE_CONF_CHECK_I(dp_m_n.link_n);
8997         PIPE_CONF_CHECK_I(dp_m_n.tu);
8998
8999         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9000         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9001         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9002         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9003         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9004         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9005
9006         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9007         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9008         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9009         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9010         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9011         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9012
9013         PIPE_CONF_CHECK_I(pixel_multiplier);
9014
9015         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9016                               DRM_MODE_FLAG_INTERLACE);
9017
9018         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9019                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9020                                       DRM_MODE_FLAG_PHSYNC);
9021                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9022                                       DRM_MODE_FLAG_NHSYNC);
9023                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9024                                       DRM_MODE_FLAG_PVSYNC);
9025                 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9026                                       DRM_MODE_FLAG_NVSYNC);
9027         }
9028
9029         PIPE_CONF_CHECK_I(pipe_src_w);
9030         PIPE_CONF_CHECK_I(pipe_src_h);
9031
9032         PIPE_CONF_CHECK_I(gmch_pfit.control);
9033         /* pfit ratios are autocomputed by the hw on gen4+ */
9034         if (INTEL_INFO(dev)->gen < 4)
9035                 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9036         PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9037         PIPE_CONF_CHECK_I(pch_pfit.enabled);
9038         if (current_config->pch_pfit.enabled) {
9039                 PIPE_CONF_CHECK_I(pch_pfit.pos);
9040                 PIPE_CONF_CHECK_I(pch_pfit.size);
9041         }
9042
9043         PIPE_CONF_CHECK_I(ips_enabled);
9044
9045         PIPE_CONF_CHECK_I(double_wide);
9046
9047         PIPE_CONF_CHECK_I(shared_dpll);
9048         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9049         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9050         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9051         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9052
9053         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9054                 PIPE_CONF_CHECK_I(pipe_bpp);
9055
9056         if (!IS_HASWELL(dev)) {
9057                 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9058                 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9059         }
9060
9061 #undef PIPE_CONF_CHECK_X
9062 #undef PIPE_CONF_CHECK_I
9063 #undef PIPE_CONF_CHECK_FLAGS
9064 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9065 #undef PIPE_CONF_QUIRK
9066
9067         return true;
9068 }
9069
9070 static void
9071 check_connector_state(struct drm_device *dev)
9072 {
9073         struct intel_connector *connector;
9074
9075         list_for_each_entry(connector, &dev->mode_config.connector_list,
9076                             base.head) {
9077                 /* This also checks the encoder/connector hw state with the
9078                  * ->get_hw_state callbacks. */
9079                 intel_connector_check_state(connector);
9080
9081                 WARN(&connector->new_encoder->base != connector->base.encoder,
9082                      "connector's staged encoder doesn't match current encoder\n");
9083         }
9084 }
9085
9086 static void
9087 check_encoder_state(struct drm_device *dev)
9088 {
9089         struct intel_encoder *encoder;
9090         struct intel_connector *connector;
9091
9092         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9093                             base.head) {
9094                 bool enabled = false;
9095                 bool active = false;
9096                 enum pipe pipe, tracked_pipe;
9097
9098                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9099                               encoder->base.base.id,
9100                               drm_get_encoder_name(&encoder->base));
9101
9102                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9103                      "encoder's stage crtc doesn't match current crtc\n");
9104                 WARN(encoder->connectors_active && !encoder->base.crtc,
9105                      "encoder's active_connectors set, but no crtc\n");
9106
9107                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9108                                     base.head) {
9109                         if (connector->base.encoder != &encoder->base)
9110                                 continue;
9111                         enabled = true;
9112                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9113                                 active = true;
9114                 }
9115                 WARN(!!encoder->base.crtc != enabled,
9116                      "encoder's enabled state mismatch "
9117                      "(expected %i, found %i)\n",
9118                      !!encoder->base.crtc, enabled);
9119                 WARN(active && !encoder->base.crtc,
9120                      "active encoder with no crtc\n");
9121
9122                 WARN(encoder->connectors_active != active,
9123                      "encoder's computed active state doesn't match tracked active state "
9124                      "(expected %i, found %i)\n", active, encoder->connectors_active);
9125
9126                 active = encoder->get_hw_state(encoder, &pipe);
9127                 WARN(active != encoder->connectors_active,
9128                      "encoder's hw state doesn't match sw tracking "
9129                      "(expected %i, found %i)\n",
9130                      encoder->connectors_active, active);
9131
9132                 if (!encoder->base.crtc)
9133                         continue;
9134
9135                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9136                 WARN(active && pipe != tracked_pipe,
9137                      "active encoder's pipe doesn't match"
9138                      "(expected %i, found %i)\n",
9139                      tracked_pipe, pipe);
9140
9141         }
9142 }
9143
9144 static void
9145 check_crtc_state(struct drm_device *dev)
9146 {
9147         drm_i915_private_t *dev_priv = dev->dev_private;
9148         struct intel_crtc *crtc;
9149         struct intel_encoder *encoder;
9150         struct intel_crtc_config pipe_config;
9151
9152         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9153                             base.head) {
9154                 bool enabled = false;
9155                 bool active = false;
9156
9157                 memset(&pipe_config, 0, sizeof(pipe_config));
9158
9159                 DRM_DEBUG_KMS("[CRTC:%d]\n",
9160                               crtc->base.base.id);
9161
9162                 WARN(crtc->active && !crtc->base.enabled,
9163                      "active crtc, but not enabled in sw tracking\n");
9164
9165                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9166                                     base.head) {
9167                         if (encoder->base.crtc != &crtc->base)
9168                                 continue;
9169                         enabled = true;
9170                         if (encoder->connectors_active)
9171                                 active = true;
9172                 }
9173
9174                 WARN(active != crtc->active,
9175                      "crtc's computed active state doesn't match tracked active state "
9176                      "(expected %i, found %i)\n", active, crtc->active);
9177                 WARN(enabled != crtc->base.enabled,
9178                      "crtc's computed enabled state doesn't match tracked enabled state "
9179                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9180
9181                 active = dev_priv->display.get_pipe_config(crtc,
9182                                                            &pipe_config);
9183
9184                 /* hw state is inconsistent with the pipe A quirk */
9185                 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9186                         active = crtc->active;
9187
9188                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9189                                     base.head) {
9190                         enum pipe pipe;
9191                         if (encoder->base.crtc != &crtc->base)
9192                                 continue;
9193                         if (encoder->get_config &&
9194                             encoder->get_hw_state(encoder, &pipe))
9195                                 encoder->get_config(encoder, &pipe_config);
9196                 }
9197
9198                 WARN(crtc->active != active,
9199                      "crtc active state doesn't match with hw state "
9200                      "(expected %i, found %i)\n", crtc->active, active);
9201
9202                 if (active &&
9203                     !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9204                         WARN(1, "pipe state doesn't match!\n");
9205                         intel_dump_pipe_config(crtc, &pipe_config,
9206                                                "[hw state]");
9207                         intel_dump_pipe_config(crtc, &crtc->config,
9208                                                "[sw state]");
9209                 }
9210         }
9211 }
9212
9213 static void
9214 check_shared_dpll_state(struct drm_device *dev)
9215 {
9216         drm_i915_private_t *dev_priv = dev->dev_private;
9217         struct intel_crtc *crtc;
9218         struct intel_dpll_hw_state dpll_hw_state;
9219         int i;
9220
9221         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9222                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9223                 int enabled_crtcs = 0, active_crtcs = 0;
9224                 bool active;
9225
9226                 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9227
9228                 DRM_DEBUG_KMS("%s\n", pll->name);
9229
9230                 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9231
9232                 WARN(pll->active > pll->refcount,
9233                      "more active pll users than references: %i vs %i\n",
9234                      pll->active, pll->refcount);
9235                 WARN(pll->active && !pll->on,
9236                      "pll in active use but not on in sw tracking\n");
9237                 WARN(pll->on && !pll->active,
9238                      "pll in on but not on in use in sw tracking\n");
9239                 WARN(pll->on != active,
9240                      "pll on state mismatch (expected %i, found %i)\n",
9241                      pll->on, active);
9242
9243                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9244                                     base.head) {
9245                         if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9246                                 enabled_crtcs++;
9247                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9248                                 active_crtcs++;
9249                 }
9250                 WARN(pll->active != active_crtcs,
9251                      "pll active crtcs mismatch (expected %i, found %i)\n",
9252                      pll->active, active_crtcs);
9253                 WARN(pll->refcount != enabled_crtcs,
9254                      "pll enabled crtcs mismatch (expected %i, found %i)\n",
9255                      pll->refcount, enabled_crtcs);
9256
9257                 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9258                                        sizeof(dpll_hw_state)),
9259                      "pll hw state mismatch\n");
9260         }
9261 }
9262
9263 void
9264 intel_modeset_check_state(struct drm_device *dev)
9265 {
9266         check_connector_state(dev);
9267         check_encoder_state(dev);
9268         check_crtc_state(dev);
9269         check_shared_dpll_state(dev);
9270 }
9271
9272 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9273                                      int dotclock)
9274 {
9275         /*
9276          * FDI already provided one idea for the dotclock.
9277          * Yell if the encoder disagrees.
9278          */
9279         WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9280              "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9281              pipe_config->adjusted_mode.crtc_clock, dotclock);
9282 }
9283
9284 static int __intel_set_mode(struct drm_crtc *crtc,
9285                             struct drm_display_mode *mode,
9286                             int x, int y, struct drm_framebuffer *fb)
9287 {
9288         struct drm_device *dev = crtc->dev;
9289         drm_i915_private_t *dev_priv = dev->dev_private;
9290         struct drm_display_mode *saved_mode, *saved_hwmode;
9291         struct intel_crtc_config *pipe_config = NULL;
9292         struct intel_crtc *intel_crtc;
9293         unsigned disable_pipes, prepare_pipes, modeset_pipes;
9294         int ret = 0;
9295
9296         saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9297         if (!saved_mode)
9298                 return -ENOMEM;
9299         saved_hwmode = saved_mode + 1;
9300
9301         intel_modeset_affected_pipes(crtc, &modeset_pipes,
9302                                      &prepare_pipes, &disable_pipes);
9303
9304         *saved_hwmode = crtc->hwmode;
9305         *saved_mode = crtc->mode;
9306
9307         /* Hack: Because we don't (yet) support global modeset on multiple
9308          * crtcs, we don't keep track of the new mode for more than one crtc.
9309          * Hence simply check whether any bit is set in modeset_pipes in all the
9310          * pieces of code that are not yet converted to deal with mutliple crtcs
9311          * changing their mode at the same time. */
9312         if (modeset_pipes) {
9313                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9314                 if (IS_ERR(pipe_config)) {
9315                         ret = PTR_ERR(pipe_config);
9316                         pipe_config = NULL;
9317
9318                         goto out;
9319                 }
9320                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9321                                        "[modeset]");
9322         }
9323
9324         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9325                 intel_crtc_disable(&intel_crtc->base);
9326
9327         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9328                 if (intel_crtc->base.enabled)
9329                         dev_priv->display.crtc_disable(&intel_crtc->base);
9330         }
9331
9332         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9333          * to set it here already despite that we pass it down the callchain.
9334          */
9335         if (modeset_pipes) {
9336                 crtc->mode = *mode;
9337                 /* mode_set/enable/disable functions rely on a correct pipe
9338                  * config. */
9339                 to_intel_crtc(crtc)->config = *pipe_config;
9340         }
9341
9342         /* Only after disabling all output pipelines that will be changed can we
9343          * update the the output configuration. */
9344         intel_modeset_update_state(dev, prepare_pipes);
9345
9346         if (dev_priv->display.modeset_global_resources)
9347                 dev_priv->display.modeset_global_resources(dev);
9348
9349         /* Set up the DPLL and any encoders state that needs to adjust or depend
9350          * on the DPLL.
9351          */
9352         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9353                 ret = intel_crtc_mode_set(&intel_crtc->base,
9354                                           x, y, fb);
9355                 if (ret)
9356                         goto done;
9357         }
9358
9359         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9360         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9361                 dev_priv->display.crtc_enable(&intel_crtc->base);
9362
9363         if (modeset_pipes) {
9364                 /* Store real post-adjustment hardware mode. */
9365                 crtc->hwmode = pipe_config->adjusted_mode;
9366
9367                 /* Calculate and store various constants which
9368                  * are later needed by vblank and swap-completion
9369                  * timestamping. They are derived from true hwmode.
9370                  */
9371                 drm_calc_timestamping_constants(crtc);
9372         }
9373
9374         /* FIXME: add subpixel order */
9375 done:
9376         if (ret && crtc->enabled) {
9377                 crtc->hwmode = *saved_hwmode;
9378                 crtc->mode = *saved_mode;
9379         }
9380
9381 out:
9382         kfree(pipe_config);
9383         kfree(saved_mode);
9384         return ret;
9385 }
9386
9387 static int intel_set_mode(struct drm_crtc *crtc,
9388                           struct drm_display_mode *mode,
9389                           int x, int y, struct drm_framebuffer *fb)
9390 {
9391         int ret;
9392
9393         ret = __intel_set_mode(crtc, mode, x, y, fb);
9394
9395         if (ret == 0)
9396                 intel_modeset_check_state(crtc->dev);
9397
9398         return ret;
9399 }
9400
9401 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9402 {
9403         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9404 }
9405
9406 #undef for_each_intel_crtc_masked
9407
9408 static void intel_set_config_free(struct intel_set_config *config)
9409 {
9410         if (!config)
9411                 return;
9412
9413         kfree(config->save_connector_encoders);
9414         kfree(config->save_encoder_crtcs);
9415         kfree(config);
9416 }
9417
9418 static int intel_set_config_save_state(struct drm_device *dev,
9419                                        struct intel_set_config *config)
9420 {
9421         struct drm_encoder *encoder;
9422         struct drm_connector *connector;
9423         int count;
9424
9425         config->save_encoder_crtcs =
9426                 kcalloc(dev->mode_config.num_encoder,
9427                         sizeof(struct drm_crtc *), GFP_KERNEL);
9428         if (!config->save_encoder_crtcs)
9429                 return -ENOMEM;
9430
9431         config->save_connector_encoders =
9432                 kcalloc(dev->mode_config.num_connector,
9433                         sizeof(struct drm_encoder *), GFP_KERNEL);
9434         if (!config->save_connector_encoders)
9435                 return -ENOMEM;
9436
9437         /* Copy data. Note that driver private data is not affected.
9438          * Should anything bad happen only the expected state is
9439          * restored, not the drivers personal bookkeeping.
9440          */
9441         count = 0;
9442         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9443                 config->save_encoder_crtcs[count++] = encoder->crtc;
9444         }
9445
9446         count = 0;
9447         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9448                 config->save_connector_encoders[count++] = connector->encoder;
9449         }
9450
9451         return 0;
9452 }
9453
9454 static void intel_set_config_restore_state(struct drm_device *dev,
9455                                            struct intel_set_config *config)
9456 {
9457         struct intel_encoder *encoder;
9458         struct intel_connector *connector;
9459         int count;
9460
9461         count = 0;
9462         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9463                 encoder->new_crtc =
9464                         to_intel_crtc(config->save_encoder_crtcs[count++]);
9465         }
9466
9467         count = 0;
9468         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9469                 connector->new_encoder =
9470                         to_intel_encoder(config->save_connector_encoders[count++]);
9471         }
9472 }
9473
9474 static bool
9475 is_crtc_connector_off(struct drm_mode_set *set)
9476 {
9477         int i;
9478
9479         if (set->num_connectors == 0)
9480                 return false;
9481
9482         if (WARN_ON(set->connectors == NULL))
9483                 return false;
9484
9485         for (i = 0; i < set->num_connectors; i++)
9486                 if (set->connectors[i]->encoder &&
9487                     set->connectors[i]->encoder->crtc == set->crtc &&
9488                     set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9489                         return true;
9490
9491         return false;
9492 }
9493
9494 static void
9495 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9496                                       struct intel_set_config *config)
9497 {
9498
9499         /* We should be able to check here if the fb has the same properties
9500          * and then just flip_or_move it */
9501         if (is_crtc_connector_off(set)) {
9502                 config->mode_changed = true;
9503         } else if (set->crtc->fb != set->fb) {
9504                 /* If we have no fb then treat it as a full mode set */
9505                 if (set->crtc->fb == NULL) {
9506                         struct intel_crtc *intel_crtc =
9507                                 to_intel_crtc(set->crtc);
9508
9509                         if (intel_crtc->active && i915_fastboot) {
9510                                 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9511                                 config->fb_changed = true;
9512                         } else {
9513                                 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9514                                 config->mode_changed = true;
9515                         }
9516                 } else if (set->fb == NULL) {
9517                         config->mode_changed = true;
9518                 } else if (set->fb->pixel_format !=
9519                            set->crtc->fb->pixel_format) {
9520                         config->mode_changed = true;
9521                 } else {
9522                         config->fb_changed = true;
9523                 }
9524         }
9525
9526         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9527                 config->fb_changed = true;
9528
9529         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9530                 DRM_DEBUG_KMS("modes are different, full mode set\n");
9531                 drm_mode_debug_printmodeline(&set->crtc->mode);
9532                 drm_mode_debug_printmodeline(set->mode);
9533                 config->mode_changed = true;
9534         }
9535
9536         DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9537                         set->crtc->base.id, config->mode_changed, config->fb_changed);
9538 }
9539
9540 static int
9541 intel_modeset_stage_output_state(struct drm_device *dev,
9542                                  struct drm_mode_set *set,
9543                                  struct intel_set_config *config)
9544 {
9545         struct drm_crtc *new_crtc;
9546         struct intel_connector *connector;
9547         struct intel_encoder *encoder;
9548         int ro;
9549
9550         /* The upper layers ensure that we either disable a crtc or have a list
9551          * of connectors. For paranoia, double-check this. */
9552         WARN_ON(!set->fb && (set->num_connectors != 0));
9553         WARN_ON(set->fb && (set->num_connectors == 0));
9554
9555         list_for_each_entry(connector, &dev->mode_config.connector_list,
9556                             base.head) {
9557                 /* Otherwise traverse passed in connector list and get encoders
9558                  * for them. */
9559                 for (ro = 0; ro < set->num_connectors; ro++) {
9560                         if (set->connectors[ro] == &connector->base) {
9561                                 connector->new_encoder = connector->encoder;
9562                                 break;
9563                         }
9564                 }
9565
9566                 /* If we disable the crtc, disable all its connectors. Also, if
9567                  * the connector is on the changing crtc but not on the new
9568                  * connector list, disable it. */
9569                 if ((!set->fb || ro == set->num_connectors) &&
9570                     connector->base.encoder &&
9571                     connector->base.encoder->crtc == set->crtc) {
9572                         connector->new_encoder = NULL;
9573
9574                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9575                                 connector->base.base.id,
9576                                 drm_get_connector_name(&connector->base));
9577                 }
9578
9579
9580                 if (&connector->new_encoder->base != connector->base.encoder) {
9581                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9582                         config->mode_changed = true;
9583                 }
9584         }
9585         /* connector->new_encoder is now updated for all connectors. */
9586
9587         /* Update crtc of enabled connectors. */
9588         list_for_each_entry(connector, &dev->mode_config.connector_list,
9589                             base.head) {
9590                 if (!connector->new_encoder)
9591                         continue;
9592
9593                 new_crtc = connector->new_encoder->base.crtc;
9594
9595                 for (ro = 0; ro < set->num_connectors; ro++) {
9596                         if (set->connectors[ro] == &connector->base)
9597                                 new_crtc = set->crtc;
9598                 }
9599
9600                 /* Make sure the new CRTC will work with the encoder */
9601                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9602                                            new_crtc)) {
9603                         return -EINVAL;
9604                 }
9605                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9606
9607                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9608                         connector->base.base.id,
9609                         drm_get_connector_name(&connector->base),
9610                         new_crtc->base.id);
9611         }
9612
9613         /* Check for any encoders that needs to be disabled. */
9614         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9615                             base.head) {
9616                 list_for_each_entry(connector,
9617                                     &dev->mode_config.connector_list,
9618                                     base.head) {
9619                         if (connector->new_encoder == encoder) {
9620                                 WARN_ON(!connector->new_encoder->new_crtc);
9621
9622                                 goto next_encoder;
9623                         }
9624                 }
9625                 encoder->new_crtc = NULL;
9626 next_encoder:
9627                 /* Only now check for crtc changes so we don't miss encoders
9628                  * that will be disabled. */
9629                 if (&encoder->new_crtc->base != encoder->base.crtc) {
9630                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9631                         config->mode_changed = true;
9632                 }
9633         }
9634         /* Now we've also updated encoder->new_crtc for all encoders. */
9635
9636         return 0;
9637 }
9638
9639 static int intel_crtc_set_config(struct drm_mode_set *set)
9640 {
9641         struct drm_device *dev;
9642         struct drm_mode_set save_set;
9643         struct intel_set_config *config;
9644         int ret;
9645
9646         BUG_ON(!set);
9647         BUG_ON(!set->crtc);
9648         BUG_ON(!set->crtc->helper_private);
9649
9650         /* Enforce sane interface api - has been abused by the fb helper. */
9651         BUG_ON(!set->mode && set->fb);
9652         BUG_ON(set->fb && set->num_connectors == 0);
9653
9654         if (set->fb) {
9655                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9656                                 set->crtc->base.id, set->fb->base.id,
9657                                 (int)set->num_connectors, set->x, set->y);
9658         } else {
9659                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9660         }
9661
9662         dev = set->crtc->dev;
9663
9664         ret = -ENOMEM;
9665         config = kzalloc(sizeof(*config), GFP_KERNEL);
9666         if (!config)
9667                 goto out_config;
9668
9669         ret = intel_set_config_save_state(dev, config);
9670         if (ret)
9671                 goto out_config;
9672
9673         save_set.crtc = set->crtc;
9674         save_set.mode = &set->crtc->mode;
9675         save_set.x = set->crtc->x;
9676         save_set.y = set->crtc->y;
9677         save_set.fb = set->crtc->fb;
9678
9679         /* Compute whether we need a full modeset, only an fb base update or no
9680          * change at all. In the future we might also check whether only the
9681          * mode changed, e.g. for LVDS where we only change the panel fitter in
9682          * such cases. */
9683         intel_set_config_compute_mode_changes(set, config);
9684
9685         ret = intel_modeset_stage_output_state(dev, set, config);
9686         if (ret)
9687                 goto fail;
9688
9689         if (config->mode_changed) {
9690                 ret = intel_set_mode(set->crtc, set->mode,
9691                                      set->x, set->y, set->fb);
9692         } else if (config->fb_changed) {
9693                 intel_crtc_wait_for_pending_flips(set->crtc);
9694
9695                 ret = intel_pipe_set_base(set->crtc,
9696                                           set->x, set->y, set->fb);
9697         }
9698
9699         if (ret) {
9700                 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9701                               set->crtc->base.id, ret);
9702 fail:
9703                 intel_set_config_restore_state(dev, config);
9704
9705                 /* Try to restore the config */
9706                 if (config->mode_changed &&
9707                     intel_set_mode(save_set.crtc, save_set.mode,
9708                                    save_set.x, save_set.y, save_set.fb))
9709                         DRM_ERROR("failed to restore config after modeset failure\n");
9710         }
9711
9712 out_config:
9713         intel_set_config_free(config);
9714         return ret;
9715 }
9716
9717 static const struct drm_crtc_funcs intel_crtc_funcs = {
9718         .cursor_set = intel_crtc_cursor_set,
9719         .cursor_move = intel_crtc_cursor_move,
9720         .gamma_set = intel_crtc_gamma_set,
9721         .set_config = intel_crtc_set_config,
9722         .destroy = intel_crtc_destroy,
9723         .page_flip = intel_crtc_page_flip,
9724 };
9725
9726 static void intel_cpu_pll_init(struct drm_device *dev)
9727 {
9728         if (HAS_DDI(dev))
9729                 intel_ddi_pll_init(dev);
9730 }
9731
9732 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9733                                       struct intel_shared_dpll *pll,
9734                                       struct intel_dpll_hw_state *hw_state)
9735 {
9736         uint32_t val;
9737
9738         val = I915_READ(PCH_DPLL(pll->id));
9739         hw_state->dpll = val;
9740         hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9741         hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
9742
9743         return val & DPLL_VCO_ENABLE;
9744 }
9745
9746 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9747                                   struct intel_shared_dpll *pll)
9748 {
9749         I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9750         I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9751 }
9752
9753 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9754                                 struct intel_shared_dpll *pll)
9755 {
9756         /* PCH refclock must be enabled first */
9757         assert_pch_refclk_enabled(dev_priv);
9758
9759         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9760
9761         /* Wait for the clocks to stabilize. */
9762         POSTING_READ(PCH_DPLL(pll->id));
9763         udelay(150);
9764
9765         /* The pixel multiplier can only be updated once the
9766          * DPLL is enabled and the clocks are stable.
9767          *
9768          * So write it again.
9769          */
9770         I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9771         POSTING_READ(PCH_DPLL(pll->id));
9772         udelay(200);
9773 }
9774
9775 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9776                                  struct intel_shared_dpll *pll)
9777 {
9778         struct drm_device *dev = dev_priv->dev;
9779         struct intel_crtc *crtc;
9780
9781         /* Make sure no transcoder isn't still depending on us. */
9782         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9783                 if (intel_crtc_to_shared_dpll(crtc) == pll)
9784                         assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
9785         }
9786
9787         I915_WRITE(PCH_DPLL(pll->id), 0);
9788         POSTING_READ(PCH_DPLL(pll->id));
9789         udelay(200);
9790 }
9791
9792 static char *ibx_pch_dpll_names[] = {
9793         "PCH DPLL A",
9794         "PCH DPLL B",
9795 };
9796
9797 static void ibx_pch_dpll_init(struct drm_device *dev)
9798 {
9799         struct drm_i915_private *dev_priv = dev->dev_private;
9800         int i;
9801
9802         dev_priv->num_shared_dpll = 2;
9803
9804         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9805                 dev_priv->shared_dplls[i].id = i;
9806                 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
9807                 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
9808                 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9809                 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
9810                 dev_priv->shared_dplls[i].get_hw_state =
9811                         ibx_pch_dpll_get_hw_state;
9812         }
9813 }
9814
9815 static void intel_shared_dpll_init(struct drm_device *dev)
9816 {
9817         struct drm_i915_private *dev_priv = dev->dev_private;
9818
9819         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9820                 ibx_pch_dpll_init(dev);
9821         else
9822                 dev_priv->num_shared_dpll = 0;
9823
9824         BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9825         DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9826                       dev_priv->num_shared_dpll);
9827 }
9828
9829 static void intel_crtc_init(struct drm_device *dev, int pipe)
9830 {
9831         drm_i915_private_t *dev_priv = dev->dev_private;
9832         struct intel_crtc *intel_crtc;
9833         int i;
9834
9835         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
9836         if (intel_crtc == NULL)
9837                 return;
9838
9839         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9840
9841         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
9842         for (i = 0; i < 256; i++) {
9843                 intel_crtc->lut_r[i] = i;
9844                 intel_crtc->lut_g[i] = i;
9845                 intel_crtc->lut_b[i] = i;
9846         }
9847
9848         /* Swap pipes & planes for FBC on pre-965 */
9849         intel_crtc->pipe = pipe;
9850         intel_crtc->plane = pipe;
9851         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
9852                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9853                 intel_crtc->plane = !pipe;
9854         }
9855
9856         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9857                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9858         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9859         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9860
9861         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
9862 }
9863
9864 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
9865                                 struct drm_file *file)
9866 {
9867         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
9868         struct drm_mode_object *drmmode_obj;
9869         struct intel_crtc *crtc;
9870
9871         if (!drm_core_check_feature(dev, DRIVER_MODESET))
9872                 return -ENODEV;
9873
9874         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9875                         DRM_MODE_OBJECT_CRTC);
9876
9877         if (!drmmode_obj) {
9878                 DRM_ERROR("no such CRTC id\n");
9879                 return -EINVAL;
9880         }
9881
9882         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9883         pipe_from_crtc_id->pipe = crtc->pipe;
9884
9885         return 0;
9886 }
9887
9888 static int intel_encoder_clones(struct intel_encoder *encoder)
9889 {
9890         struct drm_device *dev = encoder->base.dev;
9891         struct intel_encoder *source_encoder;
9892         int index_mask = 0;
9893         int entry = 0;
9894
9895         list_for_each_entry(source_encoder,
9896                             &dev->mode_config.encoder_list, base.head) {
9897
9898                 if (encoder == source_encoder)
9899                         index_mask |= (1 << entry);
9900
9901                 /* Intel hw has only one MUX where enocoders could be cloned. */
9902                 if (encoder->cloneable && source_encoder->cloneable)
9903                         index_mask |= (1 << entry);
9904
9905                 entry++;
9906         }
9907
9908         return index_mask;
9909 }
9910
9911 static bool has_edp_a(struct drm_device *dev)
9912 {
9913         struct drm_i915_private *dev_priv = dev->dev_private;
9914
9915         if (!IS_MOBILE(dev))
9916                 return false;
9917
9918         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9919                 return false;
9920
9921         if (IS_GEN5(dev) &&
9922             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9923                 return false;
9924
9925         return true;
9926 }
9927
9928 static void intel_setup_outputs(struct drm_device *dev)
9929 {
9930         struct drm_i915_private *dev_priv = dev->dev_private;
9931         struct intel_encoder *encoder;
9932         bool dpd_is_edp = false;
9933
9934         intel_lvds_init(dev);
9935
9936         if (!IS_ULT(dev))
9937                 intel_crt_init(dev);
9938
9939         if (HAS_DDI(dev)) {
9940                 int found;
9941
9942                 /* Haswell uses DDI functions to detect digital outputs */
9943                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9944                 /* DDI A only supports eDP */
9945                 if (found)
9946                         intel_ddi_init(dev, PORT_A);
9947
9948                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9949                  * register */
9950                 found = I915_READ(SFUSE_STRAP);
9951
9952                 if (found & SFUSE_STRAP_DDIB_DETECTED)
9953                         intel_ddi_init(dev, PORT_B);
9954                 if (found & SFUSE_STRAP_DDIC_DETECTED)
9955                         intel_ddi_init(dev, PORT_C);
9956                 if (found & SFUSE_STRAP_DDID_DETECTED)
9957                         intel_ddi_init(dev, PORT_D);
9958         } else if (HAS_PCH_SPLIT(dev)) {
9959                 int found;
9960                 dpd_is_edp = intel_dpd_is_edp(dev);
9961
9962                 if (has_edp_a(dev))
9963                         intel_dp_init(dev, DP_A, PORT_A);
9964
9965                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9966                         /* PCH SDVOB multiplex with HDMIB */
9967                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
9968                         if (!found)
9969                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9970                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9971                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
9972                 }
9973
9974                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9975                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9976
9977                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9978                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9979
9980                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9981                         intel_dp_init(dev, PCH_DP_C, PORT_C);
9982
9983                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9984                         intel_dp_init(dev, PCH_DP_D, PORT_D);
9985         } else if (IS_VALLEYVIEW(dev)) {
9986                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9987                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9988                                         PORT_B);
9989                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9990                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9991                 }
9992
9993                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9994                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9995                                         PORT_C);
9996                         if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9997                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9998                                               PORT_C);
9999                 }
10000
10001                 intel_dsi_init(dev);
10002         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10003                 bool found = false;
10004
10005                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10006                         DRM_DEBUG_KMS("probing SDVOB\n");
10007                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10008                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10009                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10010                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10011                         }
10012
10013                         if (!found && SUPPORTS_INTEGRATED_DP(dev))
10014                                 intel_dp_init(dev, DP_B, PORT_B);
10015                 }
10016
10017                 /* Before G4X SDVOC doesn't have its own detect register */
10018
10019                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10020                         DRM_DEBUG_KMS("probing SDVOC\n");
10021                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10022                 }
10023
10024                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10025
10026                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10027                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10028                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10029                         }
10030                         if (SUPPORTS_INTEGRATED_DP(dev))
10031                                 intel_dp_init(dev, DP_C, PORT_C);
10032                 }
10033
10034                 if (SUPPORTS_INTEGRATED_DP(dev) &&
10035                     (I915_READ(DP_D) & DP_DETECTED))
10036                         intel_dp_init(dev, DP_D, PORT_D);
10037         } else if (IS_GEN2(dev))
10038                 intel_dvo_init(dev);
10039
10040         if (SUPPORTS_TV(dev))
10041                 intel_tv_init(dev);
10042
10043         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10044                 encoder->base.possible_crtcs = encoder->crtc_mask;
10045                 encoder->base.possible_clones =
10046                         intel_encoder_clones(encoder);
10047         }
10048
10049         intel_init_pch_refclk(dev);
10050
10051         drm_helper_move_panel_connectors_to_head(dev);
10052 }
10053
10054 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10055 {
10056         drm_framebuffer_cleanup(&fb->base);
10057         WARN_ON(!fb->obj->framebuffer_references--);
10058         drm_gem_object_unreference_unlocked(&fb->obj->base);
10059 }
10060
10061 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10062 {
10063         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10064
10065         intel_framebuffer_fini(intel_fb);
10066         kfree(intel_fb);
10067 }
10068
10069 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10070                                                 struct drm_file *file,
10071                                                 unsigned int *handle)
10072 {
10073         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10074         struct drm_i915_gem_object *obj = intel_fb->obj;
10075
10076         return drm_gem_handle_create(file, &obj->base, handle);
10077 }
10078
10079 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10080         .destroy = intel_user_framebuffer_destroy,
10081         .create_handle = intel_user_framebuffer_create_handle,
10082 };
10083
10084 int intel_framebuffer_init(struct drm_device *dev,
10085                            struct intel_framebuffer *intel_fb,
10086                            struct drm_mode_fb_cmd2 *mode_cmd,
10087                            struct drm_i915_gem_object *obj)
10088 {
10089         int aligned_height, tile_height;
10090         int pitch_limit;
10091         int ret;
10092
10093         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10094
10095         if (obj->tiling_mode == I915_TILING_Y) {
10096                 DRM_DEBUG("hardware does not support tiling Y\n");
10097                 return -EINVAL;
10098         }
10099
10100         if (mode_cmd->pitches[0] & 63) {
10101                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10102                           mode_cmd->pitches[0]);
10103                 return -EINVAL;
10104         }
10105
10106         if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10107                 pitch_limit = 32*1024;
10108         } else if (INTEL_INFO(dev)->gen >= 4) {
10109                 if (obj->tiling_mode)
10110                         pitch_limit = 16*1024;
10111                 else
10112                         pitch_limit = 32*1024;
10113         } else if (INTEL_INFO(dev)->gen >= 3) {
10114                 if (obj->tiling_mode)
10115                         pitch_limit = 8*1024;
10116                 else
10117                         pitch_limit = 16*1024;
10118         } else
10119                 /* XXX DSPC is limited to 4k tiled */
10120                 pitch_limit = 8*1024;
10121
10122         if (mode_cmd->pitches[0] > pitch_limit) {
10123                 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10124                           obj->tiling_mode ? "tiled" : "linear",
10125                           mode_cmd->pitches[0], pitch_limit);
10126                 return -EINVAL;
10127         }
10128
10129         if (obj->tiling_mode != I915_TILING_NONE &&
10130             mode_cmd->pitches[0] != obj->stride) {
10131                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10132                           mode_cmd->pitches[0], obj->stride);
10133                 return -EINVAL;
10134         }
10135
10136         /* Reject formats not supported by any plane early. */
10137         switch (mode_cmd->pixel_format) {
10138         case DRM_FORMAT_C8:
10139         case DRM_FORMAT_RGB565:
10140         case DRM_FORMAT_XRGB8888:
10141         case DRM_FORMAT_ARGB8888:
10142                 break;
10143         case DRM_FORMAT_XRGB1555:
10144         case DRM_FORMAT_ARGB1555:
10145                 if (INTEL_INFO(dev)->gen > 3) {
10146                         DRM_DEBUG("unsupported pixel format: %s\n",
10147                                   drm_get_format_name(mode_cmd->pixel_format));
10148                         return -EINVAL;
10149                 }
10150                 break;
10151         case DRM_FORMAT_XBGR8888:
10152         case DRM_FORMAT_ABGR8888:
10153         case DRM_FORMAT_XRGB2101010:
10154         case DRM_FORMAT_ARGB2101010:
10155         case DRM_FORMAT_XBGR2101010:
10156         case DRM_FORMAT_ABGR2101010:
10157                 if (INTEL_INFO(dev)->gen < 4) {
10158                         DRM_DEBUG("unsupported pixel format: %s\n",
10159                                   drm_get_format_name(mode_cmd->pixel_format));
10160                         return -EINVAL;
10161                 }
10162                 break;
10163         case DRM_FORMAT_YUYV:
10164         case DRM_FORMAT_UYVY:
10165         case DRM_FORMAT_YVYU:
10166         case DRM_FORMAT_VYUY:
10167                 if (INTEL_INFO(dev)->gen < 5) {
10168                         DRM_DEBUG("unsupported pixel format: %s\n",
10169                                   drm_get_format_name(mode_cmd->pixel_format));
10170                         return -EINVAL;
10171                 }
10172                 break;
10173         default:
10174                 DRM_DEBUG("unsupported pixel format: %s\n",
10175                           drm_get_format_name(mode_cmd->pixel_format));
10176                 return -EINVAL;
10177         }
10178
10179         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10180         if (mode_cmd->offsets[0] != 0)
10181                 return -EINVAL;
10182
10183         tile_height = IS_GEN2(dev) ? 16 : 8;
10184         aligned_height = ALIGN(mode_cmd->height,
10185                                obj->tiling_mode ? tile_height : 1);
10186         /* FIXME drm helper for size checks (especially planar formats)? */
10187         if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10188                 return -EINVAL;
10189
10190         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10191         intel_fb->obj = obj;
10192         intel_fb->obj->framebuffer_references++;
10193
10194         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10195         if (ret) {
10196                 DRM_ERROR("framebuffer init failed %d\n", ret);
10197                 return ret;
10198         }
10199
10200         return 0;
10201 }
10202
10203 static struct drm_framebuffer *
10204 intel_user_framebuffer_create(struct drm_device *dev,
10205                               struct drm_file *filp,
10206                               struct drm_mode_fb_cmd2 *mode_cmd)
10207 {
10208         struct drm_i915_gem_object *obj;
10209
10210         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10211                                                 mode_cmd->handles[0]));
10212         if (&obj->base == NULL)
10213                 return ERR_PTR(-ENOENT);
10214
10215         return intel_framebuffer_create(dev, mode_cmd, obj);
10216 }
10217
10218 #ifndef CONFIG_DRM_I915_FBDEV
10219 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10220 {
10221 }
10222 #endif
10223
10224 static const struct drm_mode_config_funcs intel_mode_funcs = {
10225         .fb_create = intel_user_framebuffer_create,
10226         .output_poll_changed = intel_fbdev_output_poll_changed,
10227 };
10228
10229 /* Set up chip specific display functions */
10230 static void intel_init_display(struct drm_device *dev)
10231 {
10232         struct drm_i915_private *dev_priv = dev->dev_private;
10233
10234         if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10235                 dev_priv->display.find_dpll = g4x_find_best_dpll;
10236         else if (IS_VALLEYVIEW(dev))
10237                 dev_priv->display.find_dpll = vlv_find_best_dpll;
10238         else if (IS_PINEVIEW(dev))
10239                 dev_priv->display.find_dpll = pnv_find_best_dpll;
10240         else
10241                 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10242
10243         if (HAS_DDI(dev)) {
10244                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10245                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10246                 dev_priv->display.crtc_enable = haswell_crtc_enable;
10247                 dev_priv->display.crtc_disable = haswell_crtc_disable;
10248                 dev_priv->display.off = haswell_crtc_off;
10249                 dev_priv->display.update_plane = ironlake_update_plane;
10250         } else if (HAS_PCH_SPLIT(dev)) {
10251                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10252                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10253                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10254                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10255                 dev_priv->display.off = ironlake_crtc_off;
10256                 dev_priv->display.update_plane = ironlake_update_plane;
10257         } else if (IS_VALLEYVIEW(dev)) {
10258                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10259                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10260                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10261                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10262                 dev_priv->display.off = i9xx_crtc_off;
10263                 dev_priv->display.update_plane = i9xx_update_plane;
10264         } else {
10265                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10266                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10267                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10268                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10269                 dev_priv->display.off = i9xx_crtc_off;
10270                 dev_priv->display.update_plane = i9xx_update_plane;
10271         }
10272
10273         /* Returns the core display clock speed */
10274         if (IS_VALLEYVIEW(dev))
10275                 dev_priv->display.get_display_clock_speed =
10276                         valleyview_get_display_clock_speed;
10277         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10278                 dev_priv->display.get_display_clock_speed =
10279                         i945_get_display_clock_speed;
10280         else if (IS_I915G(dev))
10281                 dev_priv->display.get_display_clock_speed =
10282                         i915_get_display_clock_speed;
10283         else if (IS_I945GM(dev) || IS_845G(dev))
10284                 dev_priv->display.get_display_clock_speed =
10285                         i9xx_misc_get_display_clock_speed;
10286         else if (IS_PINEVIEW(dev))
10287                 dev_priv->display.get_display_clock_speed =
10288                         pnv_get_display_clock_speed;
10289         else if (IS_I915GM(dev))
10290                 dev_priv->display.get_display_clock_speed =
10291                         i915gm_get_display_clock_speed;
10292         else if (IS_I865G(dev))
10293                 dev_priv->display.get_display_clock_speed =
10294                         i865_get_display_clock_speed;
10295         else if (IS_I85X(dev))
10296                 dev_priv->display.get_display_clock_speed =
10297                         i855_get_display_clock_speed;
10298         else /* 852, 830 */
10299                 dev_priv->display.get_display_clock_speed =
10300                         i830_get_display_clock_speed;
10301
10302         if (HAS_PCH_SPLIT(dev)) {
10303                 if (IS_GEN5(dev)) {
10304                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10305                         dev_priv->display.write_eld = ironlake_write_eld;
10306                 } else if (IS_GEN6(dev)) {
10307                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10308                         dev_priv->display.write_eld = ironlake_write_eld;
10309                 } else if (IS_IVYBRIDGE(dev)) {
10310                         /* FIXME: detect B0+ stepping and use auto training */
10311                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10312                         dev_priv->display.write_eld = ironlake_write_eld;
10313                         dev_priv->display.modeset_global_resources =
10314                                 ivb_modeset_global_resources;
10315                 } else if (IS_HASWELL(dev)) {
10316                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10317                         dev_priv->display.write_eld = haswell_write_eld;
10318                         dev_priv->display.modeset_global_resources =
10319                                 haswell_modeset_global_resources;
10320                 }
10321         } else if (IS_G4X(dev)) {
10322                 dev_priv->display.write_eld = g4x_write_eld;
10323         }
10324
10325         /* Default just returns -ENODEV to indicate unsupported */
10326         dev_priv->display.queue_flip = intel_default_queue_flip;
10327
10328         switch (INTEL_INFO(dev)->gen) {
10329         case 2:
10330                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10331                 break;
10332
10333         case 3:
10334                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10335                 break;
10336
10337         case 4:
10338         case 5:
10339                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10340                 break;
10341
10342         case 6:
10343                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10344                 break;
10345         case 7:
10346                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10347                 break;
10348         }
10349 }
10350
10351 /*
10352  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10353  * resume, or other times.  This quirk makes sure that's the case for
10354  * affected systems.
10355  */
10356 static void quirk_pipea_force(struct drm_device *dev)
10357 {
10358         struct drm_i915_private *dev_priv = dev->dev_private;
10359
10360         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10361         DRM_INFO("applying pipe a force quirk\n");
10362 }
10363
10364 /*
10365  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10366  */
10367 static void quirk_ssc_force_disable(struct drm_device *dev)
10368 {
10369         struct drm_i915_private *dev_priv = dev->dev_private;
10370         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10371         DRM_INFO("applying lvds SSC disable quirk\n");
10372 }
10373
10374 /*
10375  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10376  * brightness value
10377  */
10378 static void quirk_invert_brightness(struct drm_device *dev)
10379 {
10380         struct drm_i915_private *dev_priv = dev->dev_private;
10381         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10382         DRM_INFO("applying inverted panel brightness quirk\n");
10383 }
10384
10385 /*
10386  * Some machines (Dell XPS13) suffer broken backlight controls if
10387  * BLM_PCH_PWM_ENABLE is set.
10388  */
10389 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10390 {
10391         struct drm_i915_private *dev_priv = dev->dev_private;
10392         dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10393         DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10394 }
10395
10396 struct intel_quirk {
10397         int device;
10398         int subsystem_vendor;
10399         int subsystem_device;
10400         void (*hook)(struct drm_device *dev);
10401 };
10402
10403 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10404 struct intel_dmi_quirk {
10405         void (*hook)(struct drm_device *dev);
10406         const struct dmi_system_id (*dmi_id_list)[];
10407 };
10408
10409 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10410 {
10411         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10412         return 1;
10413 }
10414
10415 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10416         {
10417                 .dmi_id_list = &(const struct dmi_system_id[]) {
10418                         {
10419                                 .callback = intel_dmi_reverse_brightness,
10420                                 .ident = "NCR Corporation",
10421                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10422                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
10423                                 },
10424                         },
10425                         { }  /* terminating entry */
10426                 },
10427                 .hook = quirk_invert_brightness,
10428         },
10429 };
10430
10431 static struct intel_quirk intel_quirks[] = {
10432         /* HP Mini needs pipe A force quirk (LP: #322104) */
10433         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10434
10435         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10436         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10437
10438         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10439         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10440
10441         /* 830 needs to leave pipe A & dpll A up */
10442         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10443
10444         /* Lenovo U160 cannot use SSC on LVDS */
10445         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10446
10447         /* Sony Vaio Y cannot use SSC on LVDS */
10448         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10449
10450         /*
10451          * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10452          * seem to use inverted backlight PWM.
10453          */
10454         { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10455
10456         /* Dell XPS13 HD Sandy Bridge */
10457         { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10458         /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10459         { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10460 };
10461
10462 static void intel_init_quirks(struct drm_device *dev)
10463 {
10464         struct pci_dev *d = dev->pdev;
10465         int i;
10466
10467         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10468                 struct intel_quirk *q = &intel_quirks[i];
10469
10470                 if (d->device == q->device &&
10471                     (d->subsystem_vendor == q->subsystem_vendor ||
10472                      q->subsystem_vendor == PCI_ANY_ID) &&
10473                     (d->subsystem_device == q->subsystem_device ||
10474                      q->subsystem_device == PCI_ANY_ID))
10475                         q->hook(dev);
10476         }
10477         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10478                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10479                         intel_dmi_quirks[i].hook(dev);
10480         }
10481 }
10482
10483 /* Disable the VGA plane that we never use */
10484 static void i915_disable_vga(struct drm_device *dev)
10485 {
10486         struct drm_i915_private *dev_priv = dev->dev_private;
10487         u8 sr1;
10488         u32 vga_reg = i915_vgacntrl_reg(dev);
10489
10490         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10491         outb(SR01, VGA_SR_INDEX);
10492         sr1 = inb(VGA_SR_DATA);
10493         outb(sr1 | 1<<5, VGA_SR_DATA);
10494         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10495         udelay(300);
10496
10497         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10498         POSTING_READ(vga_reg);
10499 }
10500
10501 static void i915_enable_vga_mem(struct drm_device *dev)
10502 {
10503         /* Enable VGA memory on Intel HD */
10504         if (HAS_PCH_SPLIT(dev)) {
10505                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10506                 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10507                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10508                                                    VGA_RSRC_LEGACY_MEM |
10509                                                    VGA_RSRC_NORMAL_IO |
10510                                                    VGA_RSRC_NORMAL_MEM);
10511                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10512         }
10513 }
10514
10515 void i915_disable_vga_mem(struct drm_device *dev)
10516 {
10517         /* Disable VGA memory on Intel HD */
10518         if (HAS_PCH_SPLIT(dev)) {
10519                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10520                 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10521                 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10522                                                    VGA_RSRC_NORMAL_IO |
10523                                                    VGA_RSRC_NORMAL_MEM);
10524                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10525         }
10526 }
10527
10528 void intel_modeset_init_hw(struct drm_device *dev)
10529 {
10530         struct drm_i915_private *dev_priv = dev->dev_private;
10531
10532         intel_prepare_ddi(dev);
10533
10534         intel_init_clock_gating(dev);
10535
10536         /* Enable the CRI clock source so we can get at the display */
10537         if (IS_VALLEYVIEW(dev))
10538                 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10539                            DPLL_INTEGRATED_CRI_CLK_VLV);
10540
10541         intel_init_dpio(dev);
10542
10543         mutex_lock(&dev->struct_mutex);
10544         intel_enable_gt_powersave(dev);
10545         mutex_unlock(&dev->struct_mutex);
10546 }
10547
10548 void intel_modeset_suspend_hw(struct drm_device *dev)
10549 {
10550         intel_suspend_hw(dev);
10551 }
10552
10553 void intel_modeset_init(struct drm_device *dev)
10554 {
10555         struct drm_i915_private *dev_priv = dev->dev_private;
10556         int i, j, ret;
10557
10558         drm_mode_config_init(dev);
10559
10560         dev->mode_config.min_width = 0;
10561         dev->mode_config.min_height = 0;
10562
10563         dev->mode_config.preferred_depth = 24;
10564         dev->mode_config.prefer_shadow = 1;
10565
10566         dev->mode_config.funcs = &intel_mode_funcs;
10567
10568         intel_init_quirks(dev);
10569
10570         intel_init_pm(dev);
10571
10572         if (INTEL_INFO(dev)->num_pipes == 0)
10573                 return;
10574
10575         intel_init_display(dev);
10576
10577         if (IS_GEN2(dev)) {
10578                 dev->mode_config.max_width = 2048;
10579                 dev->mode_config.max_height = 2048;
10580         } else if (IS_GEN3(dev)) {
10581                 dev->mode_config.max_width = 4096;
10582                 dev->mode_config.max_height = 4096;
10583         } else {
10584                 dev->mode_config.max_width = 8192;
10585                 dev->mode_config.max_height = 8192;
10586         }
10587         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10588
10589         DRM_DEBUG_KMS("%d display pipe%s available.\n",
10590                       INTEL_INFO(dev)->num_pipes,
10591                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10592
10593         for_each_pipe(i) {
10594                 intel_crtc_init(dev, i);
10595                 for (j = 0; j < dev_priv->num_plane; j++) {
10596                         ret = intel_plane_init(dev, i, j);
10597                         if (ret)
10598                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10599                                               pipe_name(i), sprite_name(i, j), ret);
10600                 }
10601         }
10602
10603         intel_cpu_pll_init(dev);
10604         intel_shared_dpll_init(dev);
10605
10606         /* Just disable it once at startup */
10607         i915_disable_vga(dev);
10608         intel_setup_outputs(dev);
10609
10610         /* Just in case the BIOS is doing something questionable. */
10611         intel_disable_fbc(dev);
10612 }
10613
10614 static void
10615 intel_connector_break_all_links(struct intel_connector *connector)
10616 {
10617         connector->base.dpms = DRM_MODE_DPMS_OFF;
10618         connector->base.encoder = NULL;
10619         connector->encoder->connectors_active = false;
10620         connector->encoder->base.crtc = NULL;
10621 }
10622
10623 static void intel_enable_pipe_a(struct drm_device *dev)
10624 {
10625         struct intel_connector *connector;
10626         struct drm_connector *crt = NULL;
10627         struct intel_load_detect_pipe load_detect_temp;
10628
10629         /* We can't just switch on the pipe A, we need to set things up with a
10630          * proper mode and output configuration. As a gross hack, enable pipe A
10631          * by enabling the load detect pipe once. */
10632         list_for_each_entry(connector,
10633                             &dev->mode_config.connector_list,
10634                             base.head) {
10635                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10636                         crt = &connector->base;
10637                         break;
10638                 }
10639         }
10640
10641         if (!crt)
10642                 return;
10643
10644         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10645                 intel_release_load_detect_pipe(crt, &load_detect_temp);
10646
10647
10648 }
10649
10650 static bool
10651 intel_check_plane_mapping(struct intel_crtc *crtc)
10652 {
10653         struct drm_device *dev = crtc->base.dev;
10654         struct drm_i915_private *dev_priv = dev->dev_private;
10655         u32 reg, val;
10656
10657         if (INTEL_INFO(dev)->num_pipes == 1)
10658                 return true;
10659
10660         reg = DSPCNTR(!crtc->plane);
10661         val = I915_READ(reg);
10662
10663         if ((val & DISPLAY_PLANE_ENABLE) &&
10664             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10665                 return false;
10666
10667         return true;
10668 }
10669
10670 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10671 {
10672         struct drm_device *dev = crtc->base.dev;
10673         struct drm_i915_private *dev_priv = dev->dev_private;
10674         u32 reg;
10675
10676         /* Clear any frame start delays used for debugging left by the BIOS */
10677         reg = PIPECONF(crtc->config.cpu_transcoder);
10678         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10679
10680         /* We need to sanitize the plane -> pipe mapping first because this will
10681          * disable the crtc (and hence change the state) if it is wrong. Note
10682          * that gen4+ has a fixed plane -> pipe mapping.  */
10683         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10684                 struct intel_connector *connector;
10685                 bool plane;
10686
10687                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10688                               crtc->base.base.id);
10689
10690                 /* Pipe has the wrong plane attached and the plane is active.
10691                  * Temporarily change the plane mapping and disable everything
10692                  * ...  */
10693                 plane = crtc->plane;
10694                 crtc->plane = !plane;
10695                 dev_priv->display.crtc_disable(&crtc->base);
10696                 crtc->plane = plane;
10697
10698                 /* ... and break all links. */
10699                 list_for_each_entry(connector, &dev->mode_config.connector_list,
10700                                     base.head) {
10701                         if (connector->encoder->base.crtc != &crtc->base)
10702                                 continue;
10703
10704                         intel_connector_break_all_links(connector);
10705                 }
10706
10707                 WARN_ON(crtc->active);
10708                 crtc->base.enabled = false;
10709         }
10710
10711         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10712             crtc->pipe == PIPE_A && !crtc->active) {
10713                 /* BIOS forgot to enable pipe A, this mostly happens after
10714                  * resume. Force-enable the pipe to fix this, the update_dpms
10715                  * call below we restore the pipe to the right state, but leave
10716                  * the required bits on. */
10717                 intel_enable_pipe_a(dev);
10718         }
10719
10720         /* Adjust the state of the output pipe according to whether we
10721          * have active connectors/encoders. */
10722         intel_crtc_update_dpms(&crtc->base);
10723
10724         if (crtc->active != crtc->base.enabled) {
10725                 struct intel_encoder *encoder;
10726
10727                 /* This can happen either due to bugs in the get_hw_state
10728                  * functions or because the pipe is force-enabled due to the
10729                  * pipe A quirk. */
10730                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10731                               crtc->base.base.id,
10732                               crtc->base.enabled ? "enabled" : "disabled",
10733                               crtc->active ? "enabled" : "disabled");
10734
10735                 crtc->base.enabled = crtc->active;
10736
10737                 /* Because we only establish the connector -> encoder ->
10738                  * crtc links if something is active, this means the
10739                  * crtc is now deactivated. Break the links. connector
10740                  * -> encoder links are only establish when things are
10741                  *  actually up, hence no need to break them. */
10742                 WARN_ON(crtc->active);
10743
10744                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10745                         WARN_ON(encoder->connectors_active);
10746                         encoder->base.crtc = NULL;
10747                 }
10748         }
10749 }
10750
10751 static void intel_sanitize_encoder(struct intel_encoder *encoder)
10752 {
10753         struct intel_connector *connector;
10754         struct drm_device *dev = encoder->base.dev;
10755
10756         /* We need to check both for a crtc link (meaning that the
10757          * encoder is active and trying to read from a pipe) and the
10758          * pipe itself being active. */
10759         bool has_active_crtc = encoder->base.crtc &&
10760                 to_intel_crtc(encoder->base.crtc)->active;
10761
10762         if (encoder->connectors_active && !has_active_crtc) {
10763                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10764                               encoder->base.base.id,
10765                               drm_get_encoder_name(&encoder->base));
10766
10767                 /* Connector is active, but has no active pipe. This is
10768                  * fallout from our resume register restoring. Disable
10769                  * the encoder manually again. */
10770                 if (encoder->base.crtc) {
10771                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10772                                       encoder->base.base.id,
10773                                       drm_get_encoder_name(&encoder->base));
10774                         encoder->disable(encoder);
10775                 }
10776
10777                 /* Inconsistent output/port/pipe state happens presumably due to
10778                  * a bug in one of the get_hw_state functions. Or someplace else
10779                  * in our code, like the register restore mess on resume. Clamp
10780                  * things to off as a safer default. */
10781                 list_for_each_entry(connector,
10782                                     &dev->mode_config.connector_list,
10783                                     base.head) {
10784                         if (connector->encoder != encoder)
10785                                 continue;
10786
10787                         intel_connector_break_all_links(connector);
10788                 }
10789         }
10790         /* Enabled encoders without active connectors will be fixed in
10791          * the crtc fixup. */
10792 }
10793
10794 void i915_redisable_vga(struct drm_device *dev)
10795 {
10796         struct drm_i915_private *dev_priv = dev->dev_private;
10797         u32 vga_reg = i915_vgacntrl_reg(dev);
10798
10799         /* This function can be called both from intel_modeset_setup_hw_state or
10800          * at a very early point in our resume sequence, where the power well
10801          * structures are not yet restored. Since this function is at a very
10802          * paranoid "someone might have enabled VGA while we were not looking"
10803          * level, just check if the power well is enabled instead of trying to
10804          * follow the "don't touch the power well if we don't need it" policy
10805          * the rest of the driver uses. */
10806         if (HAS_POWER_WELL(dev) &&
10807             (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10808                 return;
10809
10810         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
10811                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10812                 i915_disable_vga(dev);
10813                 i915_disable_vga_mem(dev);
10814         }
10815 }
10816
10817 static void intel_modeset_readout_hw_state(struct drm_device *dev)
10818 {
10819         struct drm_i915_private *dev_priv = dev->dev_private;
10820         enum pipe pipe;
10821         struct intel_crtc *crtc;
10822         struct intel_encoder *encoder;
10823         struct intel_connector *connector;
10824         int i;
10825
10826         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10827                             base.head) {
10828                 memset(&crtc->config, 0, sizeof(crtc->config));
10829
10830                 crtc->active = dev_priv->display.get_pipe_config(crtc,
10831                                                                  &crtc->config);
10832
10833                 crtc->base.enabled = crtc->active;
10834                 crtc->primary_enabled = crtc->active;
10835
10836                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10837                               crtc->base.base.id,
10838                               crtc->active ? "enabled" : "disabled");
10839         }
10840
10841         /* FIXME: Smash this into the new shared dpll infrastructure. */
10842         if (HAS_DDI(dev))
10843                 intel_ddi_setup_hw_pll_state(dev);
10844
10845         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10846                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10847
10848                 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10849                 pll->active = 0;
10850                 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10851                                     base.head) {
10852                         if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10853                                 pll->active++;
10854                 }
10855                 pll->refcount = pll->active;
10856
10857                 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10858                               pll->name, pll->refcount, pll->on);
10859         }
10860
10861         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10862                             base.head) {
10863                 pipe = 0;
10864
10865                 if (encoder->get_hw_state(encoder, &pipe)) {
10866                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10867                         encoder->base.crtc = &crtc->base;
10868                         if (encoder->get_config)
10869                                 encoder->get_config(encoder, &crtc->config);
10870                 } else {
10871                         encoder->base.crtc = NULL;
10872                 }
10873
10874                 encoder->connectors_active = false;
10875                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
10876                               encoder->base.base.id,
10877                               drm_get_encoder_name(&encoder->base),
10878                               encoder->base.crtc ? "enabled" : "disabled",
10879                               pipe_name(pipe));
10880         }
10881
10882         list_for_each_entry(connector, &dev->mode_config.connector_list,
10883                             base.head) {
10884                 if (connector->get_hw_state(connector)) {
10885                         connector->base.dpms = DRM_MODE_DPMS_ON;
10886                         connector->encoder->connectors_active = true;
10887                         connector->base.encoder = &connector->encoder->base;
10888                 } else {
10889                         connector->base.dpms = DRM_MODE_DPMS_OFF;
10890                         connector->base.encoder = NULL;
10891                 }
10892                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10893                               connector->base.base.id,
10894                               drm_get_connector_name(&connector->base),
10895                               connector->base.encoder ? "enabled" : "disabled");
10896         }
10897 }
10898
10899 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10900  * and i915 state tracking structures. */
10901 void intel_modeset_setup_hw_state(struct drm_device *dev,
10902                                   bool force_restore)
10903 {
10904         struct drm_i915_private *dev_priv = dev->dev_private;
10905         enum pipe pipe;
10906         struct intel_crtc *crtc;
10907         struct intel_encoder *encoder;
10908         int i;
10909
10910         intel_modeset_readout_hw_state(dev);
10911
10912         /*
10913          * Now that we have the config, copy it to each CRTC struct
10914          * Note that this could go away if we move to using crtc_config
10915          * checking everywhere.
10916          */
10917         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10918                             base.head) {
10919                 if (crtc->active && i915_fastboot) {
10920                         intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10921
10922                         DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10923                                       crtc->base.base.id);
10924                         drm_mode_debug_printmodeline(&crtc->base.mode);
10925                 }
10926         }
10927
10928         /* HW state is read out, now we need to sanitize this mess. */
10929         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10930                             base.head) {
10931                 intel_sanitize_encoder(encoder);
10932         }
10933
10934         for_each_pipe(pipe) {
10935                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10936                 intel_sanitize_crtc(crtc);
10937                 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
10938         }
10939
10940         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10941                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10942
10943                 if (!pll->on || pll->active)
10944                         continue;
10945
10946                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10947
10948                 pll->disable(dev_priv, pll);
10949                 pll->on = false;
10950         }
10951
10952         if (IS_HASWELL(dev))
10953                 ilk_wm_get_hw_state(dev);
10954
10955         if (force_restore) {
10956                 i915_redisable_vga(dev);
10957
10958                 /*
10959                  * We need to use raw interfaces for restoring state to avoid
10960                  * checking (bogus) intermediate states.
10961                  */
10962                 for_each_pipe(pipe) {
10963                         struct drm_crtc *crtc =
10964                                 dev_priv->pipe_to_crtc_mapping[pipe];
10965
10966                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10967                                          crtc->fb);
10968                 }
10969         } else {
10970                 intel_modeset_update_staged_output_state(dev);
10971         }
10972
10973         intel_modeset_check_state(dev);
10974
10975         drm_mode_config_reset(dev);
10976 }
10977
10978 void intel_modeset_gem_init(struct drm_device *dev)
10979 {
10980         intel_modeset_init_hw(dev);
10981
10982         intel_setup_overlay(dev);
10983
10984         intel_modeset_setup_hw_state(dev, false);
10985 }
10986
10987 void intel_modeset_cleanup(struct drm_device *dev)
10988 {
10989         struct drm_i915_private *dev_priv = dev->dev_private;
10990         struct drm_crtc *crtc;
10991         struct drm_connector *connector;
10992
10993         /*
10994          * Interrupts and polling as the first thing to avoid creating havoc.
10995          * Too much stuff here (turning of rps, connectors, ...) would
10996          * experience fancy races otherwise.
10997          */
10998         drm_irq_uninstall(dev);
10999         cancel_work_sync(&dev_priv->hotplug_work);
11000         /*
11001          * Due to the hpd irq storm handling the hotplug work can re-arm the
11002          * poll handlers. Hence disable polling after hpd handling is shut down.
11003          */
11004         drm_kms_helper_poll_fini(dev);
11005
11006         mutex_lock(&dev->struct_mutex);
11007
11008         intel_unregister_dsm_handler();
11009
11010         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11011                 /* Skip inactive CRTCs */
11012                 if (!crtc->fb)
11013                         continue;
11014
11015                 intel_increase_pllclock(crtc);
11016         }
11017
11018         intel_disable_fbc(dev);
11019
11020         i915_enable_vga_mem(dev);
11021
11022         intel_disable_gt_powersave(dev);
11023
11024         ironlake_teardown_rc6(dev);
11025
11026         mutex_unlock(&dev->struct_mutex);
11027
11028         /* flush any delayed tasks or pending work */
11029         flush_scheduled_work();
11030
11031         /* destroy backlight, if any, before the connectors */
11032         intel_panel_destroy_backlight(dev);
11033
11034         /* destroy the sysfs files before encoders/connectors */
11035         list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11036                 drm_sysfs_connector_remove(connector);
11037
11038         drm_mode_config_cleanup(dev);
11039
11040         intel_cleanup_overlay(dev);
11041 }
11042
11043 /*
11044  * Return which encoder is currently attached for connector.
11045  */
11046 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11047 {
11048         return &intel_attached_encoder(connector)->base;
11049 }
11050
11051 void intel_connector_attach_encoder(struct intel_connector *connector,
11052                                     struct intel_encoder *encoder)
11053 {
11054         connector->encoder = encoder;
11055         drm_mode_connector_attach_encoder(&connector->base,
11056                                           &encoder->base);
11057 }
11058
11059 /*
11060  * set vga decode state - true == enable VGA decode
11061  */
11062 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11063 {
11064         struct drm_i915_private *dev_priv = dev->dev_private;
11065         u16 gmch_ctrl;
11066
11067         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11068         if (state)
11069                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11070         else
11071                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11072         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11073         return 0;
11074 }
11075
11076 struct intel_display_error_state {
11077
11078         u32 power_well_driver;
11079
11080         int num_transcoders;
11081
11082         struct intel_cursor_error_state {
11083                 u32 control;
11084                 u32 position;
11085                 u32 base;
11086                 u32 size;
11087         } cursor[I915_MAX_PIPES];
11088
11089         struct intel_pipe_error_state {
11090                 u32 source;
11091         } pipe[I915_MAX_PIPES];
11092
11093         struct intel_plane_error_state {
11094                 u32 control;
11095                 u32 stride;
11096                 u32 size;
11097                 u32 pos;
11098                 u32 addr;
11099                 u32 surface;
11100                 u32 tile_offset;
11101         } plane[I915_MAX_PIPES];
11102
11103         struct intel_transcoder_error_state {
11104                 enum transcoder cpu_transcoder;
11105
11106                 u32 conf;
11107
11108                 u32 htotal;
11109                 u32 hblank;
11110                 u32 hsync;
11111                 u32 vtotal;
11112                 u32 vblank;
11113                 u32 vsync;
11114         } transcoder[4];
11115 };
11116
11117 struct intel_display_error_state *
11118 intel_display_capture_error_state(struct drm_device *dev)
11119 {
11120         drm_i915_private_t *dev_priv = dev->dev_private;
11121         struct intel_display_error_state *error;
11122         int transcoders[] = {
11123                 TRANSCODER_A,
11124                 TRANSCODER_B,
11125                 TRANSCODER_C,
11126                 TRANSCODER_EDP,
11127         };
11128         int i;
11129
11130         if (INTEL_INFO(dev)->num_pipes == 0)
11131                 return NULL;
11132
11133         error = kzalloc(sizeof(*error), GFP_ATOMIC);
11134         if (error == NULL)
11135                 return NULL;
11136
11137         if (HAS_POWER_WELL(dev))
11138                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11139
11140         for_each_pipe(i) {
11141                 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i)))
11142                         continue;
11143
11144                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11145                         error->cursor[i].control = I915_READ(CURCNTR(i));
11146                         error->cursor[i].position = I915_READ(CURPOS(i));
11147                         error->cursor[i].base = I915_READ(CURBASE(i));
11148                 } else {
11149                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11150                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11151                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11152                 }
11153
11154                 error->plane[i].control = I915_READ(DSPCNTR(i));
11155                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11156                 if (INTEL_INFO(dev)->gen <= 3) {
11157                         error->plane[i].size = I915_READ(DSPSIZE(i));
11158                         error->plane[i].pos = I915_READ(DSPPOS(i));
11159                 }
11160                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11161                         error->plane[i].addr = I915_READ(DSPADDR(i));
11162                 if (INTEL_INFO(dev)->gen >= 4) {
11163                         error->plane[i].surface = I915_READ(DSPSURF(i));
11164                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11165                 }
11166
11167                 error->pipe[i].source = I915_READ(PIPESRC(i));
11168         }
11169
11170         error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11171         if (HAS_DDI(dev_priv->dev))
11172                 error->num_transcoders++; /* Account for eDP. */
11173
11174         for (i = 0; i < error->num_transcoders; i++) {
11175                 enum transcoder cpu_transcoder = transcoders[i];
11176
11177                 if (!intel_display_power_enabled(dev,
11178                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
11179                         continue;
11180
11181                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11182
11183                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11184                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11185                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11186                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11187                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11188                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11189                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11190         }
11191
11192         return error;
11193 }
11194
11195 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11196
11197 void
11198 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11199                                 struct drm_device *dev,
11200                                 struct intel_display_error_state *error)
11201 {
11202         int i;
11203
11204         if (!error)
11205                 return;
11206
11207         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11208         if (HAS_POWER_WELL(dev))
11209                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11210                            error->power_well_driver);
11211         for_each_pipe(i) {
11212                 err_printf(m, "Pipe [%d]:\n", i);
11213                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
11214
11215                 err_printf(m, "Plane [%d]:\n", i);
11216                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
11217                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
11218                 if (INTEL_INFO(dev)->gen <= 3) {
11219                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
11220                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
11221                 }
11222                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11223                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
11224                 if (INTEL_INFO(dev)->gen >= 4) {
11225                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
11226                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
11227                 }
11228
11229                 err_printf(m, "Cursor [%d]:\n", i);
11230                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
11231                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
11232                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
11233         }
11234
11235         for (i = 0; i < error->num_transcoders; i++) {
11236                 err_printf(m, "CPU transcoder: %c\n",
11237                            transcoder_name(error->transcoder[i].cpu_transcoder));
11238                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
11239                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
11240                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
11241                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
11242                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
11243                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
11244                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
11245         }
11246 }