2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
57 #define INTEL_P2_NUM 2
58 typedef struct intel_limit intel_limit_t;
60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
73 * Returns true on success, false on failure.
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
83 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
86 intel_pch_rawclk(struct drm_device *dev)
88 struct drm_i915_private *dev_priv = dev->dev_private;
90 WARN_ON(!HAS_PCH_SPLIT(dev));
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
109 static inline u32 /* units of 100MHz */
110 intel_fdi_link_freq(struct drm_device *dev)
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
130 .find_pll = intel_find_best_PLL,
133 static const intel_limit_t intel_limits_i8xx_lvds = {
134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
144 .find_pll = intel_find_best_PLL,
147 static const intel_limit_t intel_limits_i9xx_sdvo = {
148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
158 .find_pll = intel_find_best_PLL,
161 static const intel_limit_t intel_limits_i9xx_lvds = {
162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
172 .find_pll = intel_find_best_PLL,
176 static const intel_limit_t intel_limits_g4x_sdvo = {
177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
189 .find_pll = intel_g4x_find_best_PLL,
192 static const intel_limit_t intel_limits_g4x_hdmi = {
193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
203 .find_pll = intel_g4x_find_best_PLL,
206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
218 .find_pll = intel_g4x_find_best_PLL,
221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
233 .find_pll = intel_g4x_find_best_PLL,
236 static const intel_limit_t intel_limits_pineview_sdvo = {
237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
239 /* Pineview's Ncounter is a ring counter */
240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
242 /* Pineview only has one combined m divider, which we treat as m2. */
243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
249 .find_pll = intel_find_best_PLL,
252 static const intel_limit_t intel_limits_pineview_lvds = {
253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
263 .find_pll = intel_find_best_PLL,
266 /* Ironlake / Sandybridge
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
271 static const intel_limit_t intel_limits_ironlake_dac = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
282 .find_pll = intel_g4x_find_best_PLL,
285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
296 .find_pll = intel_g4x_find_best_PLL,
299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 .find_pll = intel_g4x_find_best_PLL,
313 /* LVDS 100mhz refclk limits. */
314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
322 .p1 = { .min = 2, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
325 .find_pll = intel_g4x_find_best_PLL,
328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
336 .p1 = { .min = 2, .max = 6 },
337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
339 .find_pll = intel_g4x_find_best_PLL,
342 static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
350 .p1 = { .min = 1, .max = 3 },
351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
356 static const intel_limit_t intel_limits_vlv_hdmi = {
357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
370 static const intel_limit_t intel_limits_vlv_dp = {
371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
373 .n = { .min = 1, .max = 7 },
374 .m = { .min = 22, .max = 450 },
375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
378 .p1 = { .min = 1, .max = 3 },
379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
401 return I915_READ(DPIO_DATA);
404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
424 struct drm_device *dev = crtc->dev;
425 const intel_limit_t *limit;
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
428 if (intel_is_dual_link_lvds(dev)) {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_dual_lvds_100m;
432 limit = &intel_limits_ironlake_dual_lvds;
434 if (refclk == 100000)
435 limit = &intel_limits_ironlake_single_lvds_100m;
437 limit = &intel_limits_ironlake_single_lvds;
440 limit = &intel_limits_ironlake_dac;
445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
447 struct drm_device *dev = crtc->dev;
448 const intel_limit_t *limit;
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev))
452 limit = &intel_limits_g4x_dual_channel_lvds;
454 limit = &intel_limits_g4x_single_channel_lvds;
455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
457 limit = &intel_limits_g4x_hdmi;
458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
459 limit = &intel_limits_g4x_sdvo;
460 } else /* The option is for other outputs */
461 limit = &intel_limits_i9xx_sdvo;
466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
471 if (HAS_PCH_SPLIT(dev))
472 limit = intel_ironlake_limit(crtc, refclk);
473 else if (IS_G4X(dev)) {
474 limit = intel_g4x_limit(crtc);
475 } else if (IS_PINEVIEW(dev)) {
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
477 limit = &intel_limits_pineview_lvds;
479 limit = &intel_limits_pineview_sdvo;
480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
486 limit = &intel_limits_vlv_dp;
487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
491 limit = &intel_limits_i9xx_sdvo;
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
494 limit = &intel_limits_i8xx_lvds;
496 limit = &intel_limits_i8xx_dvo;
501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
502 static void pineview_clock(int refclk, intel_clock_t *clock)
504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
521 clock->m = i9xx_dpll_compute_m(clock);
522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
528 * Returns whether any output on the specified pipe is of the specified type
530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
532 struct drm_device *dev = crtc->dev;
533 struct intel_encoder *encoder;
535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
553 INTELPllInvalid("p1 out of range\n");
554 if (clock->p < limit->p.min || limit->p.max < clock->p)
555 INTELPllInvalid("p out of range\n");
556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
559 INTELPllInvalid("m1 out of range\n");
560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
561 INTELPllInvalid("m1 <= m2\n");
562 if (clock->m < limit->m.min || limit->m.max < clock->m)
563 INTELPllInvalid("m out of range\n");
564 if (clock->n < limit->n.min || limit->n.max < clock->n)
565 INTELPllInvalid("n out of range\n");
566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
567 INTELPllInvalid("vco out of range\n");
568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
572 INTELPllInvalid("dot out of range\n");
578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
583 struct drm_device *dev = crtc->dev;
587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
593 if (intel_is_dual_link_lvds(dev))
594 clock.p2 = limit->p2.p2_fast;
596 clock.p2 = limit->p2.p2_slow;
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
601 clock.p2 = limit->p2.p2_fast;
604 memset(best_clock, 0, sizeof(*best_clock));
606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
619 intel_clock(dev, refclk, &clock);
620 if (!intel_PLL_is_valid(dev, limit,
624 clock.p != match_clock->p)
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
637 return (err != target);
641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
645 struct drm_device *dev = crtc->dev;
649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
657 clock.p2 = limit->p2.p2_slow;
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
662 clock.p2 = limit->p2.p2_fast;
665 memset(best_clock, 0, sizeof(*best_clock));
666 max_n = limit->n.max;
667 /* based on hardware requirement, prefer smaller n to precision */
668 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
669 /* based on hardware requirement, prefere larger m1,m2 */
670 for (clock.m1 = limit->m1.max;
671 clock.m1 >= limit->m1.min; clock.m1--) {
672 for (clock.m2 = limit->m2.max;
673 clock.m2 >= limit->m2.min; clock.m2--) {
674 for (clock.p1 = limit->p1.max;
675 clock.p1 >= limit->p1.min; clock.p1--) {
678 intel_clock(dev, refclk, &clock);
679 if (!intel_PLL_is_valid(dev, limit,
683 this_err = abs(clock.dot - target);
684 if (this_err < err_most) {
698 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
702 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
704 u32 updrate, minupdate, fracbits, p;
705 unsigned long bestppm, ppm, absppm;
709 dotclk = target * 1000;
712 fastclk = dotclk / (2*100);
716 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
717 bestm1 = bestm2 = bestp1 = bestp2 = 0;
719 /* based on hardware requirement, prefer smaller n to precision */
720 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
721 updrate = refclk / n;
722 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
723 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
727 /* based on hardware requirement, prefer bigger m1,m2 values */
728 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
729 m2 = (((2*(fastclk * p * n / m1 )) +
730 refclk) / (2*refclk));
733 if (vco >= limit->vco.min && vco < limit->vco.max) {
734 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
735 absppm = (ppm > 0) ? ppm : (-ppm);
736 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
740 if (absppm < bestppm - 10) {
757 best_clock->n = bestn;
758 best_clock->m1 = bestm1;
759 best_clock->m2 = bestm2;
760 best_clock->p1 = bestp1;
761 best_clock->p2 = bestp2;
766 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
769 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
772 return intel_crtc->config.cpu_transcoder;
775 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 u32 frame, frame_reg = PIPEFRAME(pipe);
780 frame = I915_READ(frame_reg);
782 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
783 DRM_DEBUG_KMS("vblank wait timed out\n");
787 * intel_wait_for_vblank - wait for vblank on a given pipe
789 * @pipe: pipe to wait for
791 * Wait for vblank to occur on a given pipe. Needed for various bits of
794 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 int pipestat_reg = PIPESTAT(pipe);
799 if (INTEL_INFO(dev)->gen >= 5) {
800 ironlake_wait_for_vblank(dev, pipe);
804 /* Clear existing vblank status. Note this will clear any other
805 * sticky status fields as well.
807 * This races with i915_driver_irq_handler() with the result
808 * that either function could miss a vblank event. Here it is not
809 * fatal, as we will either wait upon the next vblank interrupt or
810 * timeout. Generally speaking intel_wait_for_vblank() is only
811 * called during modeset at which time the GPU should be idle and
812 * should *not* be performing page flips and thus not waiting on
814 * Currently, the result of us stealing a vblank from the irq
815 * handler is that a single frame will be skipped during swapbuffers.
817 I915_WRITE(pipestat_reg,
818 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
820 /* Wait for vblank interrupt bit to set */
821 if (wait_for(I915_READ(pipestat_reg) &
822 PIPE_VBLANK_INTERRUPT_STATUS,
824 DRM_DEBUG_KMS("vblank wait timed out\n");
828 * intel_wait_for_pipe_off - wait for pipe to turn off
830 * @pipe: pipe to wait for
832 * After disabling a pipe, we can't wait for vblank in the usual way,
833 * spinning on the vblank interrupt status bit, since we won't actually
834 * see an interrupt when the pipe is disabled.
837 * wait for the pipe register state bit to turn off
840 * wait for the display line value to settle (it usually
841 * ends up stopping at the start of the next frame).
844 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
846 struct drm_i915_private *dev_priv = dev->dev_private;
847 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
850 if (INTEL_INFO(dev)->gen >= 4) {
851 int reg = PIPECONF(cpu_transcoder);
853 /* Wait for the Pipe State to go off */
854 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 WARN(1, "pipe_off wait timed out\n");
858 u32 last_line, line_mask;
859 int reg = PIPEDSL(pipe);
860 unsigned long timeout = jiffies + msecs_to_jiffies(100);
863 line_mask = DSL_LINEMASK_GEN2;
865 line_mask = DSL_LINEMASK_GEN3;
867 /* Wait for the display line to settle */
869 last_line = I915_READ(reg) & line_mask;
871 } while (((I915_READ(reg) & line_mask) != last_line) &&
872 time_after(timeout, jiffies));
873 if (time_after(jiffies, timeout))
874 WARN(1, "pipe_off wait timed out\n");
879 * ibx_digital_port_connected - is the specified port connected?
880 * @dev_priv: i915 private structure
881 * @port: the port to test
883 * Returns true if @port is connected, false otherwise.
885 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
886 struct intel_digital_port *port)
890 if (HAS_PCH_IBX(dev_priv->dev)) {
893 bit = SDE_PORTB_HOTPLUG;
896 bit = SDE_PORTC_HOTPLUG;
899 bit = SDE_PORTD_HOTPLUG;
907 bit = SDE_PORTB_HOTPLUG_CPT;
910 bit = SDE_PORTC_HOTPLUG_CPT;
913 bit = SDE_PORTD_HOTPLUG_CPT;
920 return I915_READ(SDEISR) & bit;
923 static const char *state_string(bool enabled)
925 return enabled ? "on" : "off";
928 /* Only for pre-ILK configs */
929 static void assert_pll(struct drm_i915_private *dev_priv,
930 enum pipe pipe, bool state)
937 val = I915_READ(reg);
938 cur_state = !!(val & DPLL_VCO_ENABLE);
939 WARN(cur_state != state,
940 "PLL state assertion failure (expected %s, current %s)\n",
941 state_string(state), state_string(cur_state));
943 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
944 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
947 static void assert_pch_pll(struct drm_i915_private *dev_priv,
948 struct intel_pch_pll *pll,
949 struct intel_crtc *crtc,
955 if (HAS_PCH_LPT(dev_priv->dev)) {
956 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
961 "asserting PCH PLL %s with no PLL\n", state_string(state)))
964 val = I915_READ(pll->pll_reg);
965 cur_state = !!(val & DPLL_VCO_ENABLE);
966 WARN(cur_state != state,
967 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
968 pll->pll_reg, state_string(state), state_string(cur_state), val);
970 /* Make sure the selected PLL is correctly attached to the transcoder */
971 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
974 pch_dpll = I915_READ(PCH_DPLL_SEL);
975 cur_state = pll->pll_reg == _PCH_DPLL_B;
976 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
977 "PLL[%d] not attached to this transcoder %c: %08x\n",
978 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
979 cur_state = !!(val >> (4*crtc->pipe + 3));
980 WARN(cur_state != state,
981 "PLL[%d] not %s on this transcoder %c: %08x\n",
982 pll->pll_reg == _PCH_DPLL_B,
984 pipe_name(crtc->pipe),
989 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
990 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
992 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1001 if (HAS_DDI(dev_priv->dev)) {
1002 /* DDI does not have a specific FDI_TX register */
1003 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1004 val = I915_READ(reg);
1005 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1007 reg = FDI_TX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_TX_ENABLE);
1011 WARN(cur_state != state,
1012 "FDI TX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1015 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1018 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool state)
1025 reg = FDI_RX_CTL(pipe);
1026 val = I915_READ(reg);
1027 cur_state = !!(val & FDI_RX_ENABLE);
1028 WARN(cur_state != state,
1029 "FDI RX state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1032 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1035 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1041 /* ILK FDI PLL is always enabled */
1042 if (dev_priv->info->gen == 5)
1045 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1046 if (HAS_DDI(dev_priv->dev))
1049 reg = FDI_TX_CTL(pipe);
1050 val = I915_READ(reg);
1051 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1054 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1060 reg = FDI_RX_CTL(pipe);
1061 val = I915_READ(reg);
1062 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1065 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1068 int pp_reg, lvds_reg;
1070 enum pipe panel_pipe = PIPE_A;
1073 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074 pp_reg = PCH_PP_CONTROL;
1075 lvds_reg = PCH_LVDS;
1077 pp_reg = PP_CONTROL;
1081 val = I915_READ(pp_reg);
1082 if (!(val & PANEL_POWER_ON) ||
1083 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1086 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087 panel_pipe = PIPE_B;
1089 WARN(panel_pipe == pipe && locked,
1090 "panel assertion failure, pipe %c regs locked\n",
1094 void assert_pipe(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1103 /* if we need the pipe A quirk it must be always on */
1104 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1107 if (!intel_display_power_enabled(dev_priv->dev,
1108 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1111 reg = PIPECONF(cpu_transcoder);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & PIPECONF_ENABLE);
1116 WARN(cur_state != state,
1117 "pipe %c assertion failure (expected %s, current %s)\n",
1118 pipe_name(pipe), state_string(state), state_string(cur_state));
1121 static void assert_plane(struct drm_i915_private *dev_priv,
1122 enum plane plane, bool state)
1128 reg = DSPCNTR(plane);
1129 val = I915_READ(reg);
1130 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131 WARN(cur_state != state,
1132 "plane %c assertion failure (expected %s, current %s)\n",
1133 plane_name(plane), state_string(state), state_string(cur_state));
1136 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1139 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 /* Planes are fixed to pipes on ILK+ */
1147 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1148 reg = DSPCNTR(pipe);
1149 val = I915_READ(reg);
1150 WARN((val & DISPLAY_PLANE_ENABLE),
1151 "plane %c assertion failure, should be disabled but not\n",
1156 /* Need to check both planes against the pipe */
1157 for (i = 0; i < 2; i++) {
1159 val = I915_READ(reg);
1160 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161 DISPPLANE_SEL_PIPE_SHIFT;
1162 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1163 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164 plane_name(i), pipe_name(pipe));
1168 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1174 if (!IS_VALLEYVIEW(dev_priv->dev))
1177 /* Need to check both planes against the pipe */
1178 for (i = 0; i < dev_priv->num_plane; i++) {
1179 reg = SPCNTR(pipe, i);
1180 val = I915_READ(reg);
1181 WARN((val & SP_ENABLE),
1182 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183 sprite_name(pipe, i), pipe_name(pipe));
1187 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1192 if (HAS_PCH_LPT(dev_priv->dev)) {
1193 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1197 val = I915_READ(PCH_DREF_CONTROL);
1198 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199 DREF_SUPERSPREAD_SOURCE_MASK));
1200 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1203 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 reg = PCH_TRANSCONF(pipe);
1211 val = I915_READ(reg);
1212 enabled = !!(val & TRANS_ENABLE);
1214 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1218 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 port_sel, u32 val)
1221 if ((val & DP_PORT_EN) == 0)
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1230 if ((val & DP_PIPE_MASK) != (pipe << 30))
1236 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1239 if ((val & SDVO_ENABLE) == 0)
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
1243 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1246 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1252 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1255 if ((val & LVDS_PORT_EN) == 0)
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1262 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1268 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1271 if ((val & ADPA_DAC_ENABLE) == 0)
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1277 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1283 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1284 enum pipe pipe, int reg, u32 port_sel)
1286 u32 val = I915_READ(reg);
1287 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1288 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1289 reg, pipe_name(pipe));
1291 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292 && (val & DP_PIPEB_SELECT),
1293 "IBX PCH dp port still using transcoder B\n");
1296 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, int reg)
1299 u32 val = I915_READ(reg);
1300 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1301 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1302 reg, pipe_name(pipe));
1304 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1305 && (val & SDVO_PIPE_B_SELECT),
1306 "IBX PCH hdmi port still using transcoder B\n");
1309 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1315 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1320 val = I915_READ(reg);
1321 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
1326 val = I915_READ(reg);
1327 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1328 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1331 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1337 * intel_enable_pll - enable a PLL
1338 * @dev_priv: i915 private structure
1339 * @pipe: pipe PLL to enable
1341 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1342 * make sure the PLL reg is writable first though, since the panel write
1343 * protect mechanism may be enabled.
1345 * Note! This is for pre-ILK only.
1347 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1349 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1354 assert_pipe_disabled(dev_priv, pipe);
1356 /* No really, not for ILK+ */
1357 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1359 /* PLL is protected by panel, make sure we can write it */
1360 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361 assert_panel_unlocked(dev_priv, pipe);
1364 val = I915_READ(reg);
1365 val |= DPLL_VCO_ENABLE;
1367 /* We do this three times for luck */
1368 I915_WRITE(reg, val);
1370 udelay(150); /* wait for warmup */
1371 I915_WRITE(reg, val);
1373 udelay(150); /* wait for warmup */
1374 I915_WRITE(reg, val);
1376 udelay(150); /* wait for warmup */
1380 * intel_disable_pll - disable a PLL
1381 * @dev_priv: i915 private structure
1382 * @pipe: pipe PLL to disable
1384 * Disable the PLL for @pipe, making sure the pipe is off first.
1386 * Note! This is for pre-ILK only.
1388 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1393 /* Don't disable pipe A or pipe A PLLs if needed */
1394 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1397 /* Make sure the pipe isn't still relying on us */
1398 assert_pipe_disabled(dev_priv, pipe);
1401 val = I915_READ(reg);
1402 val &= ~DPLL_VCO_ENABLE;
1403 I915_WRITE(reg, val);
1409 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410 enum intel_sbi_destination destination)
1414 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1416 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1418 DRM_ERROR("timeout waiting for SBI to become ready\n");
1422 I915_WRITE(SBI_ADDR, (reg << 16));
1423 I915_WRITE(SBI_DATA, value);
1425 if (destination == SBI_ICLK)
1426 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1428 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1431 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1433 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1439 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440 enum intel_sbi_destination destination)
1443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1445 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1447 DRM_ERROR("timeout waiting for SBI to become ready\n");
1451 I915_WRITE(SBI_ADDR, (reg << 16));
1453 if (destination == SBI_ICLK)
1454 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1456 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1459 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1461 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1465 return I915_READ(SBI_DATA);
1468 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1475 port_mask = DPLL_PORTC_READY_MASK;
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1483 * ironlake_enable_pch_pll - enable PCH PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1490 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1492 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1493 struct intel_pch_pll *pll;
1497 /* PCH PLLs only available on ILK, SNB and IVB */
1498 BUG_ON(dev_priv->info->gen < 5);
1499 pll = intel_crtc->pch_pll;
1503 if (WARN_ON(pll->refcount == 0))
1506 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507 pll->pll_reg, pll->active, pll->on,
1508 intel_crtc->base.base.id);
1510 /* PCH refclock must be enabled first */
1511 assert_pch_refclk_enabled(dev_priv);
1513 if (pll->active++ && pll->on) {
1514 assert_pch_pll_enabled(dev_priv, pll, NULL);
1518 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1521 val = I915_READ(reg);
1522 val |= DPLL_VCO_ENABLE;
1523 I915_WRITE(reg, val);
1530 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1532 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1542 if (WARN_ON(pll->refcount == 0))
1545 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546 pll->pll_reg, pll->active, pll->on,
1547 intel_crtc->base.base.id);
1549 if (WARN_ON(pll->active == 0)) {
1550 assert_pch_pll_disabled(dev_priv, pll, NULL);
1554 if (--pll->active) {
1555 assert_pch_pll_enabled(dev_priv, pll, NULL);
1559 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1561 /* Make sure transcoder isn't still depending on us */
1562 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1565 val = I915_READ(reg);
1566 val &= ~DPLL_VCO_ENABLE;
1567 I915_WRITE(reg, val);
1574 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1577 struct drm_device *dev = dev_priv->dev;
1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1579 uint32_t reg, val, pipeconf_val;
1581 /* PCH only available on ILK+ */
1582 BUG_ON(dev_priv->info->gen < 5);
1584 /* Make sure PCH DPLL is enabled */
1585 assert_pch_pll_enabled(dev_priv,
1586 to_intel_crtc(crtc)->pch_pll,
1587 to_intel_crtc(crtc));
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
1602 reg = PCH_TRANSCONF(pipe);
1603 val = I915_READ(reg);
1604 pipeconf_val = I915_READ(PIPECONF(pipe));
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1621 val |= TRANS_INTERLACED;
1623 val |= TRANS_PROGRESSIVE;
1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1630 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1631 enum transcoder cpu_transcoder)
1633 u32 val, pipeconf_val;
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1638 /* FDI must be feeding us bits for PCH ports */
1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
1652 val |= TRANS_INTERLACED;
1654 val |= TRANS_PROGRESSIVE;
1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1658 DRM_ERROR("Failed to enable PCH transcoder\n");
1661 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1664 struct drm_device *dev = dev_priv->dev;
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1674 reg = PCH_TRANSCONF(pipe);
1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1691 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1695 val = I915_READ(LPT_TRANSCONF);
1696 val &= ~TRANS_ENABLE;
1697 I915_WRITE(LPT_TRANSCONF, val);
1698 /* wait for PCH transcoder off, transcoder state */
1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1700 DRM_ERROR("Failed to disable PCH transcoder\n");
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1705 I915_WRITE(_TRANSA_CHICKEN2, val);
1709 * intel_enable_pipe - enable a pipe, asserting requirements
1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1717 * @pipe should be %PIPE_A or %PIPE_B.
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1722 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 enum pipe pch_transcoder;
1731 assert_planes_disabled(dev_priv, pipe);
1732 assert_sprites_disabled(dev_priv, pipe);
1734 if (HAS_PCH_LPT(dev_priv->dev))
1735 pch_transcoder = TRANSCODER_A;
1737 pch_transcoder = pipe;
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1750 assert_fdi_tx_pll_enabled(dev_priv,
1751 (enum pipe) cpu_transcoder);
1753 /* FIXME: assert CPU port conditions for SNB+ */
1756 reg = PIPECONF(cpu_transcoder);
1757 val = I915_READ(reg);
1758 if (val & PIPECONF_ENABLE)
1761 I915_WRITE(reg, val | PIPECONF_ENABLE);
1762 intel_wait_for_vblank(dev_priv->dev, pipe);
1766 * intel_disable_pipe - disable a pipe, asserting requirements
1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe to disable
1770 * Disable @pipe, making sure that various hardware specific requirements
1771 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1773 * @pipe should be %PIPE_A or %PIPE_B.
1775 * Will wait until the pipe has shut down before returning.
1777 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1780 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1786 * Make sure planes won't keep trying to pump pixels to us,
1787 * or we might hang the display.
1789 assert_planes_disabled(dev_priv, pipe);
1790 assert_sprites_disabled(dev_priv, pipe);
1792 /* Don't disable pipe A or pipe A PLLs if needed */
1793 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1796 reg = PIPECONF(cpu_transcoder);
1797 val = I915_READ(reg);
1798 if ((val & PIPECONF_ENABLE) == 0)
1801 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1802 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1806 * Plane regs are double buffered, going from enabled->disabled needs a
1807 * trigger in order to latch. The display address reg provides this.
1809 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1812 if (dev_priv->info->gen >= 4)
1813 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1815 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1819 * intel_enable_plane - enable a display plane on a given pipe
1820 * @dev_priv: i915 private structure
1821 * @plane: plane to enable
1822 * @pipe: pipe being fed
1824 * Enable @plane on @pipe, making sure that @pipe is running first.
1826 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827 enum plane plane, enum pipe pipe)
1832 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833 assert_pipe_enabled(dev_priv, pipe);
1835 reg = DSPCNTR(plane);
1836 val = I915_READ(reg);
1837 if (val & DISPLAY_PLANE_ENABLE)
1840 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1841 intel_flush_display_plane(dev_priv, plane);
1842 intel_wait_for_vblank(dev_priv->dev, pipe);
1846 * intel_disable_plane - disable a display plane
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to disable
1849 * @pipe: pipe consuming the data
1851 * Disable @plane; should be an independent operation.
1853 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1859 reg = DSPCNTR(plane);
1860 val = I915_READ(reg);
1861 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1864 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1865 intel_flush_display_plane(dev_priv, plane);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1869 static bool need_vtd_wa(struct drm_device *dev)
1871 #ifdef CONFIG_INTEL_IOMMU
1872 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1880 struct drm_i915_gem_object *obj,
1881 struct intel_ring_buffer *pipelined)
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1887 switch (obj->tiling_mode) {
1888 case I915_TILING_NONE:
1889 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890 alignment = 128 * 1024;
1891 else if (INTEL_INFO(dev)->gen >= 4)
1892 alignment = 4 * 1024;
1894 alignment = 64 * 1024;
1897 /* pin() will align the object as required by fence */
1901 /* Despite that we check this in framebuffer_init userspace can
1902 * screw us over and change the tiling after the fact. Only
1903 * pinned buffers can't change their tiling. */
1904 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1910 /* Note that the w/a also requires 64 PTE of padding following the
1911 * bo. We currently fill all unused PTE with the shadow page and so
1912 * we should always have valid PTE following the scanout preventing
1915 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916 alignment = 256 * 1024;
1918 dev_priv->mm.interruptible = false;
1919 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1921 goto err_interruptible;
1923 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924 * fence, whereas 965+ only requires a fence if using
1925 * framebuffer compression. For simplicity, we always install
1926 * a fence as the cost is not that onerous.
1928 ret = i915_gem_object_get_fence(obj);
1932 i915_gem_object_pin_fence(obj);
1934 dev_priv->mm.interruptible = true;
1938 i915_gem_object_unpin(obj);
1940 dev_priv->mm.interruptible = true;
1944 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1946 i915_gem_object_unpin_fence(obj);
1947 i915_gem_object_unpin(obj);
1950 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951 * is assumed to be a power-of-two. */
1952 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953 unsigned int tiling_mode,
1957 if (tiling_mode != I915_TILING_NONE) {
1958 unsigned int tile_rows, tiles;
1963 tiles = *x / (512/cpp);
1966 return tile_rows * pitch * 8 + tiles * 4096;
1968 unsigned int offset;
1970 offset = *y * pitch + *x * cpp;
1972 *x = (offset & 4095) / cpp;
1973 return offset & -4096;
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
1984 struct drm_i915_gem_object *obj;
1985 int plane = intel_crtc->plane;
1986 unsigned long linear_offset;
1995 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006 switch (fb->pixel_format) {
2008 dspcntr |= DISPPLANE_8BPP;
2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
2037 if (INTEL_INFO(dev)->gen >= 4) {
2038 if (obj->tiling_mode != I915_TILING_NONE)
2039 dspcntr |= DISPPLANE_TILED;
2041 dspcntr &= ~DISPPLANE_TILED;
2044 I915_WRITE(reg, dspcntr);
2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2053 linear_offset -= intel_crtc->dspaddr_offset;
2055 intel_crtc->dspaddr_offset = linear_offset;
2058 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2060 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2061 if (INTEL_INFO(dev)->gen >= 4) {
2062 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063 obj->gtt_offset + intel_crtc->dspaddr_offset);
2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2065 I915_WRITE(DSPLINOFF(plane), linear_offset);
2067 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2073 static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
2082 unsigned long linear_offset;
2092 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2096 intel_fb = to_intel_framebuffer(fb);
2097 obj = intel_fb->obj;
2099 reg = DSPCNTR(plane);
2100 dspcntr = I915_READ(reg);
2101 /* Mask out pixel format bits in case we change it */
2102 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2103 switch (fb->pixel_format) {
2105 dspcntr |= DISPPLANE_8BPP;
2107 case DRM_FORMAT_RGB565:
2108 dspcntr |= DISPPLANE_BGRX565;
2110 case DRM_FORMAT_XRGB8888:
2111 case DRM_FORMAT_ARGB8888:
2112 dspcntr |= DISPPLANE_BGRX888;
2114 case DRM_FORMAT_XBGR8888:
2115 case DRM_FORMAT_ABGR8888:
2116 dspcntr |= DISPPLANE_RGBX888;
2118 case DRM_FORMAT_XRGB2101010:
2119 case DRM_FORMAT_ARGB2101010:
2120 dspcntr |= DISPPLANE_BGRX101010;
2122 case DRM_FORMAT_XBGR2101010:
2123 case DRM_FORMAT_ABGR2101010:
2124 dspcntr |= DISPPLANE_RGBX101010;
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2133 dspcntr &= ~DISPPLANE_TILED;
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138 I915_WRITE(reg, dspcntr);
2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2141 intel_crtc->dspaddr_offset =
2142 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143 fb->bits_per_pixel / 8,
2145 linear_offset -= intel_crtc->dspaddr_offset;
2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
2152 if (IS_HASWELL(dev)) {
2153 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2155 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2165 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166 int x, int y, enum mode_set_atomic state)
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
2171 if (dev_priv->display.disable_fbc)
2172 dev_priv->display.disable_fbc(dev);
2173 intel_increase_pllclock(crtc);
2175 return dev_priv->display.update_plane(crtc, fb, x, y);
2178 void intel_display_handle_reset(struct drm_device *dev)
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct drm_crtc *crtc;
2184 * Flips in the rings have been nuked by the reset,
2185 * so complete all pending flips so that user space
2186 * will get its events and not get stuck.
2188 * Also update the base address of all primary
2189 * planes to the the last fb to make sure we're
2190 * showing the correct fb after a reset.
2192 * Need to make two loops over the crtcs so that we
2193 * don't try to grab a crtc mutex before the
2194 * pending_flip_queue really got woken up.
2197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 enum plane plane = intel_crtc->plane;
2201 intel_prepare_page_flip(dev, plane);
2202 intel_finish_page_flip_plane(dev, plane);
2205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2208 mutex_lock(&crtc->mutex);
2209 if (intel_crtc->active)
2210 dev_priv->display.update_plane(crtc, crtc->fb,
2212 mutex_unlock(&crtc->mutex);
2217 intel_finish_fb(struct drm_framebuffer *old_fb)
2219 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221 bool was_interruptible = dev_priv->mm.interruptible;
2224 /* Big Hammer, we also need to ensure that any pending
2225 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226 * current scanout is retired before unpinning the old
2229 * This should only fail upon a hung GPU, in which case we
2230 * can safely continue.
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_finish_gpu(obj);
2234 dev_priv->mm.interruptible = was_interruptible;
2239 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_master_private *master_priv;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2245 if (!dev->primary->master)
2248 master_priv = dev->primary->master->driver_priv;
2249 if (!master_priv->sarea_priv)
2252 switch (intel_crtc->pipe) {
2254 master_priv->sarea_priv->pipeA_x = x;
2255 master_priv->sarea_priv->pipeA_y = y;
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2267 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2268 struct drm_framebuffer *fb)
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2273 struct drm_framebuffer *old_fb;
2278 DRM_ERROR("No FB bound\n");
2282 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2283 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284 plane_name(intel_crtc->plane),
2285 INTEL_INFO(dev)->num_pipes);
2289 mutex_lock(&dev->struct_mutex);
2290 ret = intel_pin_and_fence_fb_obj(dev,
2291 to_intel_framebuffer(fb)->obj,
2294 mutex_unlock(&dev->struct_mutex);
2295 DRM_ERROR("pin & fence failed\n");
2299 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2301 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2302 mutex_unlock(&dev->struct_mutex);
2303 DRM_ERROR("failed to update base address\n");
2313 intel_wait_for_vblank(dev, intel_crtc->pipe);
2314 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2317 intel_update_fbc(dev);
2318 mutex_unlock(&dev->struct_mutex);
2320 intel_crtc_update_sarea_pos(crtc, x, y);
2325 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2327 struct drm_device *dev = crtc->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330 int pipe = intel_crtc->pipe;
2333 /* enable normal train */
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (IS_IVYBRIDGE(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2343 I915_WRITE(reg, temp);
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 if (HAS_PCH_CPT(dev)) {
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2351 temp &= ~FDI_LINK_TRAIN_NONE;
2352 temp |= FDI_LINK_TRAIN_NONE;
2354 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2356 /* wait one idle pattern time */
2360 /* IVB wants error correction enabled */
2361 if (IS_IVYBRIDGE(dev))
2362 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363 FDI_FE_ERRC_ENABLE);
2366 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2368 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2371 static void ivb_modeset_global_resources(struct drm_device *dev)
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381 * When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. Note that we don't care about enabled pipes without
2383 * an enabled pch encoder.
2385 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386 !pipe_has_enabled_pch(pipe_C_crtc)) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2397 /* The FDI link training functions for ILK/Ibexpeak. */
2398 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 int plane = intel_crtc->plane;
2405 u32 reg, temp, tries;
2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
2417 I915_WRITE(reg, temp);
2421 /* enable CPU FDI TX and PCH FDI RX */
2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
2444 reg = FDI_RX_IIR(pipe);
2445 for (tries = 0; tries < 5; tries++) {
2446 temp = I915_READ(reg);
2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2456 DRM_ERROR("FDI train 1 fail!\n");
2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
2463 I915_WRITE(reg, temp);
2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
2469 I915_WRITE(reg, temp);
2474 reg = FDI_RX_IIR(pipe);
2475 for (tries = 0; tries < 5; tries++) {
2476 temp = I915_READ(reg);
2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2486 DRM_ERROR("FDI train 2 fail!\n");
2488 DRM_DEBUG_KMS("FDI train done\n");
2492 static const int snb_b_fdi_train_param[] = {
2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2499 /* The FDI link training functions for SNB/Cougarpoint. */
2500 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
2506 u32 reg, temp, i, retry;
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
2514 I915_WRITE(reg, temp);
2519 /* enable CPU FDI TX and PCH FDI RX */
2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
2522 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2548 for (i = 0; i < 4; i++) {
2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
2553 I915_WRITE(reg, temp);
2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2573 DRM_ERROR("FDI train 1 fail!\n");
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2585 I915_WRITE(reg, temp);
2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2596 I915_WRITE(reg, temp);
2601 for (i = 0; i < 4; i++) {
2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2626 DRM_ERROR("FDI train 2 fail!\n");
2628 DRM_DEBUG_KMS("FDI train done.\n");
2631 /* Manual link training for Ivy Bridge A0 parts */
2632 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2663 temp |= FDI_COMPOSITE_SYNC;
2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2674 temp |= FDI_COMPOSITE_SYNC;
2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2680 for (i = 0; i < 4; i++) {
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2702 DRM_ERROR("FDI train 1 fail!\n");
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2722 for (i = 0; i < 4; i++) {
2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2743 DRM_ERROR("FDI train 2 fail!\n");
2745 DRM_DEBUG_KMS("FDI train done.\n");
2748 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2750 struct drm_device *dev = intel_crtc->base.dev;
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 int pipe = intel_crtc->pipe;
2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2767 /* Switch from Rawclk to PCDclk */
2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2809 /* Wait for the clocks to turn off. */
2814 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2861 I915_WRITE(reg, temp);
2867 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2872 unsigned long flags;
2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2886 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2888 struct drm_device *dev = crtc->dev;
2889 struct drm_i915_private *dev_priv = dev->dev_private;
2891 if (crtc->fb == NULL)
2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2912 mutex_lock(&dev_priv->dpio_lock);
2914 /* It is necessary to ungate the pixclk gate prior to programming
2915 * the divisors, and gate it back when it is done.
2917 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2919 /* Disable SSCCTL */
2920 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2921 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2925 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926 if (crtc->mode.clock == 20000) {
2931 /* The iCLK virtual clock root frequency is in MHz,
2932 * but the crtc->mode.clock in in KHz. To get the divisors,
2933 * it is necessary to divide one by another, so we
2934 * convert the virtual clock precision to KHz here for higher
2937 u32 iclk_virtual_root_freq = 172800 * 1000;
2938 u32 iclk_pi_range = 64;
2939 u32 desired_divisor, msb_divisor_value, pi_value;
2941 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942 msb_divisor_value = desired_divisor / iclk_pi_range;
2943 pi_value = desired_divisor % iclk_pi_range;
2946 divsel = msb_divisor_value - 2;
2947 phaseinc = pi_value;
2950 /* This should not happen with any sane values */
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 /* Program SSCDIVINTPHASE6 */
2964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2965 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2971 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2979 /* Enable modulator and associated divider */
2980 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2981 temp &= ~SBI_SSCCTL_DISABLE;
2982 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2984 /* Wait for initialization time */
2987 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2989 mutex_unlock(&dev_priv->dpio_lock);
2992 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993 enum pipe pch_transcoder)
2995 struct drm_device *dev = crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000 I915_READ(HTOTAL(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002 I915_READ(HBLANK(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004 I915_READ(HSYNC(cpu_transcoder)));
3006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007 I915_READ(VTOTAL(cpu_transcoder)));
3008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009 I915_READ(VBLANK(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011 I915_READ(VSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3017 * Enable PCH resources required for PCH ports:
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3024 static void ironlake_pch_enable(struct drm_crtc *crtc)
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
3032 assert_pch_transcoder_disabled(dev_priv, pipe);
3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3039 /* For PCH output, training FDI link */
3040 dev_priv->display.fdi_link_train(crtc);
3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
3049 ironlake_enable_pch_pll(intel_crtc);
3051 if (HAS_PCH_CPT(dev)) {
3054 temp = I915_READ(PCH_DPLL_SEL);
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3074 I915_WRITE(PCH_DPLL_SEL, temp);
3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
3079 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3081 intel_fdi_normal_train(crtc);
3083 /* For PCH DP, enable TRANS_DP_CTL */
3084 if (HAS_PCH_CPT(dev) &&
3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3087 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3088 reg = TRANS_DP_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3091 TRANS_DP_SYNC_MASK |
3093 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094 TRANS_DP_ENH_FRAMING);
3095 temp |= bpc << 9; /* same format but at 11:9 */
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3098 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3100 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3102 switch (intel_trans_dp_port_sel(crtc)) {
3104 temp |= TRANS_DP_PORT_SEL_B;
3107 temp |= TRANS_DP_PORT_SEL_C;
3110 temp |= TRANS_DP_PORT_SEL_D;
3116 I915_WRITE(reg, temp);
3119 ironlake_enable_pch_transcoder(dev_priv, pipe);
3122 static void lpt_pch_enable(struct drm_crtc *crtc)
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3129 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3131 lpt_program_iclkip(crtc);
3133 /* Set transcoder timing. */
3134 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3136 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3139 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3141 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3146 if (pll->refcount == 0) {
3147 WARN(1, "bad PCH PLL refcount\n");
3152 intel_crtc->pch_pll = NULL;
3155 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3157 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158 struct intel_pch_pll *pll;
3161 pll = intel_crtc->pch_pll;
3163 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i = intel_crtc->pipe;
3171 pll = &dev_priv->pch_plls[i];
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3179 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180 pll = &dev_priv->pch_plls[i];
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3186 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187 fp == I915_READ(pll->fp0_reg)) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189 intel_crtc->base.base.id,
3190 pll->pll_reg, pll->refcount, pll->active);
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198 pll = &dev_priv->pch_plls[i];
3199 if (pll->refcount == 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3209 intel_crtc->pch_pll = pll;
3211 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3212 prepare: /* separate function? */
3213 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3215 /* Wait for the clocks to stabilize before rewriting the regs */
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3217 POSTING_READ(pll->pll_reg);
3220 I915_WRITE(pll->fp0_reg, fp);
3221 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3226 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int dslreg = PIPEDSL(pipe);
3232 temp = I915_READ(dslreg);
3234 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3235 if (wait_for(I915_READ(dslreg) != temp, 5))
3236 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3240 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3242 struct drm_device *dev = crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = crtc->pipe;
3246 if (crtc->config.pch_pfit.size) {
3247 /* Force use of hard-coded filter coefficients
3248 * as some pre-programmed values are broken,
3251 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253 PF_PIPE_SEL_IVB(pipe));
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3261 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266 struct intel_encoder *encoder;
3267 int pipe = intel_crtc->pipe;
3268 int plane = intel_crtc->plane;
3271 WARN_ON(!crtc->enabled);
3273 if (intel_crtc->active)
3276 intel_crtc->active = true;
3278 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3281 intel_update_watermarks(dev);
3283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284 temp = I915_READ(PCH_LVDS);
3285 if ((temp & LVDS_PORT_EN) == 0)
3286 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3290 if (intel_crtc->config.has_pch_encoder) {
3291 /* Note: FDI PLL enabling _must_ be done before we enable the
3292 * cpu pipes, hence this is separate from all the other fdi/pch
3294 ironlake_fdi_pll_enable(intel_crtc);
3296 assert_fdi_tx_disabled(dev_priv, pipe);
3297 assert_fdi_rx_disabled(dev_priv, pipe);
3300 for_each_encoder_on_crtc(dev, crtc, encoder)
3301 if (encoder->pre_enable)
3302 encoder->pre_enable(encoder);
3304 /* Enable panel fitting for LVDS */
3305 ironlake_pfit_enable(intel_crtc);
3308 * On ILK+ LUT must be loaded before the pipe is running but with
3311 intel_crtc_load_lut(crtc);
3313 intel_enable_pipe(dev_priv, pipe,
3314 intel_crtc->config.has_pch_encoder);
3315 intel_enable_plane(dev_priv, plane, pipe);
3317 if (intel_crtc->config.has_pch_encoder)
3318 ironlake_pch_enable(crtc);
3320 mutex_lock(&dev->struct_mutex);
3321 intel_update_fbc(dev);
3322 mutex_unlock(&dev->struct_mutex);
3324 intel_crtc_update_cursor(crtc, true);
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
3329 if (HAS_PCH_CPT(dev))
3330 cpt_verify_modeset(dev, intel_crtc->pipe);
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
3343 static void haswell_crtc_enable(struct drm_crtc *crtc)
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
3352 WARN_ON(!crtc->enabled);
3354 if (intel_crtc->active)
3357 intel_crtc->active = true;
3359 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360 if (intel_crtc->config.has_pch_encoder)
3361 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3363 intel_update_watermarks(dev);
3365 if (intel_crtc->config.has_pch_encoder)
3366 dev_priv->display.fdi_link_train(crtc);
3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
3372 intel_ddi_enable_pipe_clock(intel_crtc);
3374 /* Enable panel fitting for eDP */
3375 ironlake_pfit_enable(intel_crtc);
3378 * On ILK+ LUT must be loaded before the pipe is running but with
3381 intel_crtc_load_lut(crtc);
3383 intel_ddi_set_pipe_settings(crtc);
3384 intel_ddi_enable_transcoder_func(crtc);
3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
3388 intel_enable_plane(dev_priv, plane, pipe);
3390 if (intel_crtc->config.has_pch_encoder)
3391 lpt_pch_enable(crtc);
3393 mutex_lock(&dev->struct_mutex);
3394 intel_update_fbc(dev);
3395 mutex_unlock(&dev->struct_mutex);
3397 intel_crtc_update_cursor(crtc, true);
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happend, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3413 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3415 struct drm_device *dev = crtc->base.dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 int pipe = crtc->pipe;
3419 /* To avoid upsetting the power well on haswell only disable the pfit if
3420 * it's in use. The hw state code will make sure we get this right. */
3421 if (crtc->config.pch_pfit.size) {
3422 I915_WRITE(PF_CTL(pipe), 0);
3423 I915_WRITE(PF_WIN_POS(pipe), 0);
3424 I915_WRITE(PF_WIN_SZ(pipe), 0);
3428 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3430 struct drm_device *dev = crtc->dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433 struct intel_encoder *encoder;
3434 int pipe = intel_crtc->pipe;
3435 int plane = intel_crtc->plane;
3439 if (!intel_crtc->active)
3442 for_each_encoder_on_crtc(dev, crtc, encoder)
3443 encoder->disable(encoder);
3445 intel_crtc_wait_for_pending_flips(crtc);
3446 drm_vblank_off(dev, pipe);
3447 intel_crtc_update_cursor(crtc, false);
3449 intel_disable_plane(dev_priv, plane, pipe);
3451 if (dev_priv->cfb_plane == plane)
3452 intel_disable_fbc(dev);
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3455 intel_disable_pipe(dev_priv, pipe);
3457 ironlake_pfit_disable(intel_crtc);
3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->post_disable)
3461 encoder->post_disable(encoder);
3463 ironlake_fdi_disable(crtc);
3465 ironlake_disable_pch_transcoder(dev_priv, pipe);
3466 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3468 if (HAS_PCH_CPT(dev)) {
3469 /* disable TRANS_DP_CTL */
3470 reg = TRANS_DP_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3473 temp |= TRANS_DP_PORT_SEL_NONE;
3474 I915_WRITE(reg, temp);
3476 /* disable DPLL_SEL */
3477 temp = I915_READ(PCH_DPLL_SEL);
3480 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3483 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3486 /* C shares PLL A or B */
3487 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3492 I915_WRITE(PCH_DPLL_SEL, temp);
3495 /* disable PCH DPLL */
3496 intel_disable_pch_pll(intel_crtc);
3498 ironlake_fdi_pll_disable(intel_crtc);
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3508 static void haswell_crtc_disable(struct drm_crtc *crtc)
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3513 struct intel_encoder *encoder;
3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
3516 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3518 if (!intel_crtc->active)
3521 for_each_encoder_on_crtc(dev, crtc, encoder)
3522 encoder->disable(encoder);
3524 intel_crtc_wait_for_pending_flips(crtc);
3525 drm_vblank_off(dev, pipe);
3526 intel_crtc_update_cursor(crtc, false);
3528 /* FBC must be disabled before disabling the plane on HSW. */
3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3532 intel_disable_plane(dev_priv, plane, pipe);
3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3536 intel_disable_pipe(dev_priv, pipe);
3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3540 ironlake_pfit_disable(intel_crtc);
3542 intel_ddi_disable_pipe_clock(intel_crtc);
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3548 if (intel_crtc->config.has_pch_encoder) {
3549 lpt_disable_pch_transcoder(dev_priv);
3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3551 intel_ddi_fdi_disable(crtc);
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3562 static void ironlake_crtc_off(struct drm_crtc *crtc)
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 intel_put_pch_pll(intel_crtc);
3568 static void haswell_crtc_off(struct drm_crtc *crtc)
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3572 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573 * start using it. */
3574 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3576 intel_ddi_put_crtc_pll(crtc);
3579 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3581 if (!enable && intel_crtc->overlay) {
3582 struct drm_device *dev = intel_crtc->base.dev;
3583 struct drm_i915_private *dev_priv = dev->dev_private;
3585 mutex_lock(&dev->struct_mutex);
3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
3589 mutex_unlock(&dev->struct_mutex);
3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3601 * This workaround avoids occasional blank screens when self refresh is
3605 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3621 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3627 if (!crtc->config.gmch_pfit.control)
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3634 * Enable automatic panel scaling so that non-native modes
3635 * fill the screen. The panel fitter should only be
3636 * adjusted whilst the pipe is disabled, according to
3637 * register description and PRM.
3639 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640 pipe_config->gmch_pfit.control,
3641 pipe_config->gmch_pfit.pgm_ratios);
3643 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3646 /* Border color in case we don't scale up to the full screen. Black by
3647 * default, change to something else for debugging. */
3648 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_encoder *encoder;
3657 int pipe = intel_crtc->pipe;
3658 int plane = intel_crtc->plane;
3660 WARN_ON(!crtc->enabled);
3662 if (intel_crtc->active)
3665 intel_crtc->active = true;
3666 intel_update_watermarks(dev);
3668 mutex_lock(&dev_priv->dpio_lock);
3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 if (encoder->pre_pll_enable)
3672 encoder->pre_pll_enable(encoder);
3674 intel_enable_pll(dev_priv, pipe);
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3680 /* VLV wants encoder enabling _before_ the pipe is up. */
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3684 /* Enable panel fitting for eDP */
3685 i9xx_pfit_enable(intel_crtc);
3687 intel_enable_pipe(dev_priv, pipe, false);
3688 intel_enable_plane(dev_priv, plane, pipe);
3690 intel_crtc_load_lut(crtc);
3691 intel_update_fbc(dev);
3693 /* Give the overlay scaler a chance to enable if it's on this pipe */
3694 intel_crtc_dpms_overlay(intel_crtc, true);
3695 intel_crtc_update_cursor(crtc, true);
3697 mutex_unlock(&dev_priv->dpio_lock);
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705 struct intel_encoder *encoder;
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3709 WARN_ON(!crtc->enabled);
3711 if (intel_crtc->active)
3714 intel_crtc->active = true;
3715 intel_update_watermarks(dev);
3717 intel_enable_pll(dev_priv, pipe);
3719 for_each_encoder_on_crtc(dev, crtc, encoder)
3720 if (encoder->pre_enable)
3721 encoder->pre_enable(encoder);
3723 /* Enable panel fitting for LVDS */
3724 i9xx_pfit_enable(intel_crtc);
3726 intel_enable_pipe(dev_priv, pipe, false);
3727 intel_enable_plane(dev_priv, plane, pipe);
3729 g4x_fixup_plane(dev_priv, pipe);
3731 intel_crtc_load_lut(crtc);
3732 intel_update_fbc(dev);
3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
3736 intel_crtc_update_cursor(crtc, true);
3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 encoder->enable(encoder);
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
3747 if (!crtc->config.gmch_pfit.control)
3750 assert_pipe_disabled(dev_priv, crtc->pipe);
3752 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3753 I915_READ(PFIT_CONTROL));
3754 I915_WRITE(PFIT_CONTROL, 0);
3757 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3762 struct intel_encoder *encoder;
3763 int pipe = intel_crtc->pipe;
3764 int plane = intel_crtc->plane;
3766 if (!intel_crtc->active)
3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 encoder->disable(encoder);
3772 /* Give the overlay scaler a chance to disable if it's on this pipe */
3773 intel_crtc_wait_for_pending_flips(crtc);
3774 drm_vblank_off(dev, pipe);
3775 intel_crtc_dpms_overlay(intel_crtc, false);
3776 intel_crtc_update_cursor(crtc, false);
3778 if (dev_priv->cfb_plane == plane)
3779 intel_disable_fbc(dev);
3781 intel_disable_plane(dev_priv, plane, pipe);
3782 intel_disable_pipe(dev_priv, pipe);
3784 i9xx_pfit_disable(intel_crtc);
3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3790 intel_disable_pll(dev_priv, pipe);
3792 intel_crtc->active = false;
3793 intel_update_fbc(dev);
3794 intel_update_watermarks(dev);
3797 static void i9xx_crtc_off(struct drm_crtc *crtc)
3801 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_master_private *master_priv;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
3809 if (!dev->primary->master)
3812 master_priv = dev->primary->master->driver_priv;
3813 if (!master_priv->sarea_priv)
3818 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3819 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3822 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3823 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3826 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3832 * Sets the power management mode of the pipe and plane.
3834 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_encoder *intel_encoder;
3839 bool enable = false;
3841 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3842 enable |= intel_encoder->connectors_active;
3845 dev_priv->display.crtc_enable(crtc);
3847 dev_priv->display.crtc_disable(crtc);
3849 intel_crtc_update_sarea(crtc, enable);
3852 static void intel_crtc_disable(struct drm_crtc *crtc)
3854 struct drm_device *dev = crtc->dev;
3855 struct drm_connector *connector;
3856 struct drm_i915_private *dev_priv = dev->dev_private;
3857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3859 /* crtc should still be enabled when we disable it. */
3860 WARN_ON(!crtc->enabled);
3862 dev_priv->display.crtc_disable(crtc);
3863 intel_crtc->eld_vld = false;
3864 intel_crtc_update_sarea(crtc, false);
3865 dev_priv->display.off(crtc);
3867 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3868 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3871 mutex_lock(&dev->struct_mutex);
3872 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3873 mutex_unlock(&dev->struct_mutex);
3877 /* Update computed state. */
3878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3879 if (!connector->encoder || !connector->encoder->crtc)
3882 if (connector->encoder->crtc != crtc)
3885 connector->dpms = DRM_MODE_DPMS_OFF;
3886 to_intel_encoder(connector->encoder)->connectors_active = false;
3890 void intel_modeset_disable(struct drm_device *dev)
3892 struct drm_crtc *crtc;
3894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3896 intel_crtc_disable(crtc);
3900 void intel_encoder_destroy(struct drm_encoder *encoder)
3902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3904 drm_encoder_cleanup(encoder);
3905 kfree(intel_encoder);
3908 /* Simple dpms helper for encodres with just one connector, no cloning and only
3909 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3910 * state of the entire output pipe. */
3911 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3913 if (mode == DRM_MODE_DPMS_ON) {
3914 encoder->connectors_active = true;
3916 intel_crtc_update_dpms(encoder->base.crtc);
3918 encoder->connectors_active = false;
3920 intel_crtc_update_dpms(encoder->base.crtc);
3924 /* Cross check the actual hw state with our own modeset state tracking (and it's
3925 * internal consistency). */
3926 static void intel_connector_check_state(struct intel_connector *connector)
3928 if (connector->get_hw_state(connector)) {
3929 struct intel_encoder *encoder = connector->encoder;
3930 struct drm_crtc *crtc;
3931 bool encoder_enabled;
3934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3935 connector->base.base.id,
3936 drm_get_connector_name(&connector->base));
3938 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3939 "wrong connector dpms state\n");
3940 WARN(connector->base.encoder != &encoder->base,
3941 "active connector not linked to encoder\n");
3942 WARN(!encoder->connectors_active,
3943 "encoder->connectors_active not set\n");
3945 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3946 WARN(!encoder_enabled, "encoder not enabled\n");
3947 if (WARN_ON(!encoder->base.crtc))
3950 crtc = encoder->base.crtc;
3952 WARN(!crtc->enabled, "crtc not enabled\n");
3953 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3954 WARN(pipe != to_intel_crtc(crtc)->pipe,
3955 "encoder active on the wrong pipe\n");
3959 /* Even simpler default implementation, if there's really no special case to
3961 void intel_connector_dpms(struct drm_connector *connector, int mode)
3963 struct intel_encoder *encoder = intel_attached_encoder(connector);
3965 /* All the simple cases only support two dpms states. */
3966 if (mode != DRM_MODE_DPMS_ON)
3967 mode = DRM_MODE_DPMS_OFF;
3969 if (mode == connector->dpms)
3972 connector->dpms = mode;
3974 /* Only need to change hw state when actually enabled */
3975 if (encoder->base.crtc)
3976 intel_encoder_dpms(encoder, mode);
3978 WARN_ON(encoder->connectors_active != false);
3980 intel_modeset_check_state(connector->dev);
3983 /* Simple connector->get_hw_state implementation for encoders that support only
3984 * one connector and no cloning and hence the encoder state determines the state
3985 * of the connector. */
3986 bool intel_connector_get_hw_state(struct intel_connector *connector)
3989 struct intel_encoder *encoder = connector->encoder;
3991 return encoder->get_hw_state(encoder, &pipe);
3994 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3995 struct intel_crtc_config *pipe_config)
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 struct intel_crtc *pipe_B_crtc =
3999 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4001 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4002 pipe_name(pipe), pipe_config->fdi_lanes);
4003 if (pipe_config->fdi_lanes > 4) {
4004 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4005 pipe_name(pipe), pipe_config->fdi_lanes);
4009 if (IS_HASWELL(dev)) {
4010 if (pipe_config->fdi_lanes > 2) {
4011 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4012 pipe_config->fdi_lanes);
4019 if (INTEL_INFO(dev)->num_pipes == 2)
4022 /* Ivybridge 3 pipe is really complicated */
4027 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4028 pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4035 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4036 pipe_B_crtc->config.fdi_lanes <= 2) {
4037 if (pipe_config->fdi_lanes > 2) {
4038 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4039 pipe_name(pipe), pipe_config->fdi_lanes);
4043 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4053 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4054 struct intel_crtc_config *pipe_config)
4056 struct drm_device *dev = intel_crtc->base.dev;
4057 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4058 int target_clock, lane, link_bw;
4059 bool setup_ok, needs_recompute = false;
4062 /* FDI is a binary signal running at ~2.7GHz, encoding
4063 * each output octet as 10 bits. The actual frequency
4064 * is stored as a divider into a 100MHz clock, and the
4065 * mode pixel clock is stored in units of 1KHz.
4066 * Hence the bw of each lane in terms of the mode signal
4069 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4071 if (pipe_config->pixel_target_clock)
4072 target_clock = pipe_config->pixel_target_clock;
4074 target_clock = adjusted_mode->clock;
4076 lane = ironlake_get_lanes_required(target_clock, link_bw,
4077 pipe_config->pipe_bpp);
4079 pipe_config->fdi_lanes = lane;
4081 if (pipe_config->pixel_multiplier > 1)
4082 link_bw *= pipe_config->pixel_multiplier;
4083 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4084 link_bw, &pipe_config->fdi_m_n);
4086 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4087 intel_crtc->pipe, pipe_config);
4088 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4089 pipe_config->pipe_bpp -= 2*3;
4090 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4091 pipe_config->pipe_bpp);
4092 needs_recompute = true;
4093 pipe_config->bw_constrained = true;
4098 if (needs_recompute)
4101 return setup_ok ? 0 : -EINVAL;
4104 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4105 struct intel_crtc_config *pipe_config)
4107 struct drm_device *dev = crtc->dev;
4108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4110 if (HAS_PCH_SPLIT(dev)) {
4111 /* FDI link clock is fixed at 2.7G */
4112 if (pipe_config->requested_mode.clock * 3
4113 > IRONLAKE_FDI_FREQ * 4)
4117 /* All interlaced capable intel hw wants timings in frames. Note though
4118 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119 * timings, so we need to be careful not to clobber these.*/
4120 if (!pipe_config->timings_set)
4121 drm_mode_set_crtcinfo(adjusted_mode, 0);
4123 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4126 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4130 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4131 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4132 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4133 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4135 pipe_config->pipe_bpp = 8*3;
4138 if (pipe_config->has_pch_encoder)
4139 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4144 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4146 return 400000; /* FIXME */
4149 static int i945_get_display_clock_speed(struct drm_device *dev)
4154 static int i915_get_display_clock_speed(struct drm_device *dev)
4159 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4164 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4168 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4173 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4174 case GC_DISPLAY_CLOCK_333_MHZ:
4177 case GC_DISPLAY_CLOCK_190_200_MHZ:
4183 static int i865_get_display_clock_speed(struct drm_device *dev)
4188 static int i855_get_display_clock_speed(struct drm_device *dev)
4191 /* Assume that the hardware is in the high speed state. This
4192 * should be the default.
4194 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4195 case GC_CLOCK_133_200:
4196 case GC_CLOCK_100_200:
4198 case GC_CLOCK_166_250:
4200 case GC_CLOCK_100_133:
4204 /* Shouldn't happen */
4208 static int i830_get_display_clock_speed(struct drm_device *dev)
4214 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4216 while (*num > DATA_LINK_M_N_MASK ||
4217 *den > DATA_LINK_M_N_MASK) {
4223 static void compute_m_n(unsigned int m, unsigned int n,
4224 uint32_t *ret_m, uint32_t *ret_n)
4226 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4227 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4228 intel_reduce_m_n_ratio(ret_m, ret_n);
4232 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4233 int pixel_clock, int link_clock,
4234 struct intel_link_m_n *m_n)
4238 compute_m_n(bits_per_pixel * pixel_clock,
4239 link_clock * nlanes * 8,
4240 &m_n->gmch_m, &m_n->gmch_n);
4242 compute_m_n(pixel_clock, link_clock,
4243 &m_n->link_m, &m_n->link_n);
4246 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4248 if (i915_panel_use_ssc >= 0)
4249 return i915_panel_use_ssc != 0;
4250 return dev_priv->vbt.lvds_use_ssc
4251 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4254 static int vlv_get_refclk(struct drm_crtc *crtc)
4256 struct drm_device *dev = crtc->dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int refclk = 27000; /* for DP & HDMI */
4260 return 100000; /* only one validated so far */
4262 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4265 if (intel_panel_use_ssc(dev_priv))
4269 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4276 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4278 struct drm_device *dev = crtc->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4282 if (IS_VALLEYVIEW(dev)) {
4283 refclk = vlv_get_refclk(crtc);
4284 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4285 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4286 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4287 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4289 } else if (!IS_GEN2(dev)) {
4298 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4300 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4303 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4305 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4308 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4309 intel_clock_t *reduced_clock)
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4316 if (IS_PINEVIEW(dev)) {
4317 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4319 fp2 = pnv_dpll_compute_fp(reduced_clock);
4321 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4323 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4326 I915_WRITE(FP0(pipe), fp);
4328 crtc->lowfreq_avail = false;
4329 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4330 reduced_clock && i915_powersave) {
4331 I915_WRITE(FP1(pipe), fp2);
4332 crtc->lowfreq_avail = true;
4334 I915_WRITE(FP1(pipe), fp);
4338 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4343 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4344 * and set it to a reasonable value instead.
4346 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4347 reg_val &= 0xffffff00;
4348 reg_val |= 0x00000030;
4349 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4351 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4352 reg_val &= 0x8cffffff;
4353 reg_val = 0x8c000000;
4354 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4356 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4357 reg_val &= 0xffffff00;
4358 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4360 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4361 reg_val &= 0x00ffffff;
4362 reg_val |= 0xb0000000;
4363 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4366 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4367 struct intel_link_m_n *m_n)
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 int pipe = crtc->pipe;
4373 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4375 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4376 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4379 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4380 struct intel_link_m_n *m_n)
4382 struct drm_device *dev = crtc->base.dev;
4383 struct drm_i915_private *dev_priv = dev->dev_private;
4384 int pipe = crtc->pipe;
4385 enum transcoder transcoder = crtc->config.cpu_transcoder;
4387 if (INTEL_INFO(dev)->gen >= 5) {
4388 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4390 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4391 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4393 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4395 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4396 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4400 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4402 if (crtc->config.has_pch_encoder)
4403 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4405 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4408 static void vlv_update_pll(struct intel_crtc *crtc)
4410 struct drm_device *dev = crtc->base.dev;
4411 struct drm_i915_private *dev_priv = dev->dev_private;
4412 struct drm_display_mode *adjusted_mode =
4413 &crtc->config.adjusted_mode;
4414 struct intel_encoder *encoder;
4415 int pipe = crtc->pipe;
4417 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4419 u32 coreclk, reg_val, dpll_md;
4421 mutex_lock(&dev_priv->dpio_lock);
4423 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4425 bestn = crtc->config.dpll.n;
4426 bestm1 = crtc->config.dpll.m1;
4427 bestm2 = crtc->config.dpll.m2;
4428 bestp1 = crtc->config.dpll.p1;
4429 bestp2 = crtc->config.dpll.p2;
4431 /* See eDP HDMI DPIO driver vbios notes doc */
4433 /* PLL B needs special handling */
4435 vlv_pllb_recal_opamp(dev_priv);
4437 /* Set up Tx target for periodic Rcomp update */
4438 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4440 /* Disable target IRef on PLL */
4441 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4442 reg_val &= 0x00ffffff;
4443 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4445 /* Disable fast lock */
4446 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4448 /* Set idtafcrecal before PLL is enabled */
4449 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4450 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4451 mdiv |= ((bestn << DPIO_N_SHIFT));
4452 mdiv |= (1 << DPIO_K_SHIFT);
4455 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4456 * but we don't support that).
4457 * Note: don't use the DAC post divider as it seems unstable.
4459 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4460 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4462 mdiv |= DPIO_ENABLE_CALIBRATION;
4463 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4465 /* Set HBR and RBR LPF coefficients */
4466 if (adjusted_mode->clock == 162000 ||
4467 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4468 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4471 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4474 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4475 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4476 /* Use SSC source */
4478 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4481 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4483 } else { /* HDMI or VGA */
4484 /* Use bend source */
4486 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4489 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4493 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4494 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4495 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4496 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4497 coreclk |= 0x01000000;
4498 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4500 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4502 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4503 if (encoder->pre_pll_enable)
4504 encoder->pre_pll_enable(encoder);
4506 /* Enable DPIO clock input */
4507 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4508 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4510 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4512 dpll |= DPLL_VCO_ENABLE;
4513 I915_WRITE(DPLL(pipe), dpll);
4514 POSTING_READ(DPLL(pipe));
4517 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4518 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4521 if (crtc->config.pixel_multiplier > 1) {
4522 dpll_md = (crtc->config.pixel_multiplier - 1)
4523 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4525 I915_WRITE(DPLL_MD(pipe), dpll_md);
4526 POSTING_READ(DPLL_MD(pipe));
4528 if (crtc->config.has_dp_encoder)
4529 intel_dp_set_m_n(crtc);
4531 mutex_unlock(&dev_priv->dpio_lock);
4534 static void i9xx_update_pll(struct intel_crtc *crtc,
4535 intel_clock_t *reduced_clock,
4538 struct drm_device *dev = crtc->base.dev;
4539 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_encoder *encoder;
4541 int pipe = crtc->pipe;
4544 struct dpll *clock = &crtc->config.dpll;
4546 i9xx_update_pll_dividers(crtc, reduced_clock);
4548 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4549 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4551 dpll = DPLL_VGA_MODE_DIS;
4553 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4554 dpll |= DPLLB_MODE_LVDS;
4556 dpll |= DPLLB_MODE_DAC_SERIAL;
4558 if ((crtc->config.pixel_multiplier > 1) &&
4559 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4560 dpll |= (crtc->config.pixel_multiplier - 1)
4561 << SDVO_MULTIPLIER_SHIFT_HIRES;
4565 dpll |= DPLL_DVO_HIGH_SPEED;
4567 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4568 dpll |= DPLL_DVO_HIGH_SPEED;
4570 /* compute bitmask from p1 value */
4571 if (IS_PINEVIEW(dev))
4572 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4574 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4575 if (IS_G4X(dev) && reduced_clock)
4576 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4578 switch (clock->p2) {
4580 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4583 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4586 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4589 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4592 if (INTEL_INFO(dev)->gen >= 4)
4593 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4595 if (crtc->config.sdvo_tv_clock)
4596 dpll |= PLL_REF_INPUT_TVCLKINBC;
4597 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4598 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4601 dpll |= PLL_REF_INPUT_DREFCLK;
4603 dpll |= DPLL_VCO_ENABLE;
4604 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605 POSTING_READ(DPLL(pipe));
4608 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4609 if (encoder->pre_pll_enable)
4610 encoder->pre_pll_enable(encoder);
4612 if (crtc->config.has_dp_encoder)
4613 intel_dp_set_m_n(crtc);
4615 I915_WRITE(DPLL(pipe), dpll);
4617 /* Wait for the clocks to stabilize. */
4618 POSTING_READ(DPLL(pipe));
4621 if (INTEL_INFO(dev)->gen >= 4) {
4623 if (crtc->config.pixel_multiplier > 1) {
4624 dpll_md = (crtc->config.pixel_multiplier - 1)
4625 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4627 I915_WRITE(DPLL_MD(pipe), dpll_md);
4629 /* The pixel multiplier can only be updated once the
4630 * DPLL is enabled and the clocks are stable.
4632 * So write it again.
4634 I915_WRITE(DPLL(pipe), dpll);
4638 static void i8xx_update_pll(struct intel_crtc *crtc,
4639 struct drm_display_mode *adjusted_mode,
4640 intel_clock_t *reduced_clock,
4643 struct drm_device *dev = crtc->base.dev;
4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645 struct intel_encoder *encoder;
4646 int pipe = crtc->pipe;
4648 struct dpll *clock = &crtc->config.dpll;
4650 i9xx_update_pll_dividers(crtc, reduced_clock);
4652 dpll = DPLL_VGA_MODE_DIS;
4654 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4655 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4658 dpll |= PLL_P1_DIVIDE_BY_TWO;
4660 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4662 dpll |= PLL_P2_DIVIDE_BY_4;
4665 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4666 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4667 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4669 dpll |= PLL_REF_INPUT_DREFCLK;
4671 dpll |= DPLL_VCO_ENABLE;
4672 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4673 POSTING_READ(DPLL(pipe));
4676 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4677 if (encoder->pre_pll_enable)
4678 encoder->pre_pll_enable(encoder);
4680 I915_WRITE(DPLL(pipe), dpll);
4682 /* Wait for the clocks to stabilize. */
4683 POSTING_READ(DPLL(pipe));
4686 /* The pixel multiplier can only be updated once the
4687 * DPLL is enabled and the clocks are stable.
4689 * So write it again.
4691 I915_WRITE(DPLL(pipe), dpll);
4694 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4695 struct drm_display_mode *mode,
4696 struct drm_display_mode *adjusted_mode)
4698 struct drm_device *dev = intel_crtc->base.dev;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 enum pipe pipe = intel_crtc->pipe;
4701 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4702 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4704 /* We need to be careful not to changed the adjusted mode, for otherwise
4705 * the hw state checker will get angry at the mismatch. */
4706 crtc_vtotal = adjusted_mode->crtc_vtotal;
4707 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4709 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4710 /* the chip adds 2 halflines automatically */
4712 crtc_vblank_end -= 1;
4713 vsyncshift = adjusted_mode->crtc_hsync_start
4714 - adjusted_mode->crtc_htotal / 2;
4719 if (INTEL_INFO(dev)->gen > 3)
4720 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4722 I915_WRITE(HTOTAL(cpu_transcoder),
4723 (adjusted_mode->crtc_hdisplay - 1) |
4724 ((adjusted_mode->crtc_htotal - 1) << 16));
4725 I915_WRITE(HBLANK(cpu_transcoder),
4726 (adjusted_mode->crtc_hblank_start - 1) |
4727 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4728 I915_WRITE(HSYNC(cpu_transcoder),
4729 (adjusted_mode->crtc_hsync_start - 1) |
4730 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4732 I915_WRITE(VTOTAL(cpu_transcoder),
4733 (adjusted_mode->crtc_vdisplay - 1) |
4734 ((crtc_vtotal - 1) << 16));
4735 I915_WRITE(VBLANK(cpu_transcoder),
4736 (adjusted_mode->crtc_vblank_start - 1) |
4737 ((crtc_vblank_end - 1) << 16));
4738 I915_WRITE(VSYNC(cpu_transcoder),
4739 (adjusted_mode->crtc_vsync_start - 1) |
4740 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4742 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4743 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4744 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4746 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4747 (pipe == PIPE_B || pipe == PIPE_C))
4748 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4750 /* pipesrc controls the size that is scaled from, which should
4751 * always be the user's requested size.
4753 I915_WRITE(PIPESRC(pipe),
4754 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4757 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4758 struct intel_crtc_config *pipe_config)
4760 struct drm_device *dev = crtc->base.dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4765 tmp = I915_READ(HTOTAL(cpu_transcoder));
4766 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4767 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4768 tmp = I915_READ(HBLANK(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(HSYNC(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4775 tmp = I915_READ(VTOTAL(cpu_transcoder));
4776 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4777 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4778 tmp = I915_READ(VBLANK(cpu_transcoder));
4779 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4780 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4781 tmp = I915_READ(VSYNC(cpu_transcoder));
4782 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4783 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4785 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4786 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4787 pipe_config->adjusted_mode.crtc_vtotal += 1;
4788 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4791 tmp = I915_READ(PIPESRC(crtc->pipe));
4792 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4793 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4796 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4798 struct drm_device *dev = intel_crtc->base.dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4802 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4804 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4808 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4811 if (intel_crtc->config.requested_mode.clock >
4812 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813 pipeconf |= PIPECONF_DOUBLE_WIDE;
4815 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4818 /* only g4x and later have fancy bpc/dither controls */
4819 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4820 pipeconf &= ~(PIPECONF_BPC_MASK |
4821 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4823 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4824 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4825 pipeconf |= PIPECONF_DITHER_EN |
4826 PIPECONF_DITHER_TYPE_SP;
4828 switch (intel_crtc->config.pipe_bpp) {
4830 pipeconf |= PIPECONF_6BPC;
4833 pipeconf |= PIPECONF_8BPC;
4836 pipeconf |= PIPECONF_10BPC;
4839 /* Case prevented by intel_choose_pipe_bpp_dither. */
4844 if (HAS_PIPE_CXSR(dev)) {
4845 if (intel_crtc->lowfreq_avail) {
4846 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4847 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4849 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4850 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4854 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4855 if (!IS_GEN2(dev) &&
4856 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4857 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4859 pipeconf |= PIPECONF_PROGRESSIVE;
4861 if (IS_VALLEYVIEW(dev)) {
4862 if (intel_crtc->config.limited_color_range)
4863 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4865 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4868 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4869 POSTING_READ(PIPECONF(intel_crtc->pipe));
4872 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4874 struct drm_framebuffer *fb)
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct drm_display_mode *adjusted_mode =
4880 &intel_crtc->config.adjusted_mode;
4881 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4882 int pipe = intel_crtc->pipe;
4883 int plane = intel_crtc->plane;
4884 int refclk, num_connectors = 0;
4885 intel_clock_t clock, reduced_clock;
4887 bool ok, has_reduced_clock = false;
4888 bool is_lvds = false;
4889 struct intel_encoder *encoder;
4890 const intel_limit_t *limit;
4893 for_each_encoder_on_crtc(dev, crtc, encoder) {
4894 switch (encoder->type) {
4895 case INTEL_OUTPUT_LVDS:
4903 refclk = i9xx_get_refclk(crtc, num_connectors);
4906 * Returns a set of divisors for the desired target clock with the given
4907 * refclk, or FALSE. The returned values represent the clock equation:
4908 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4910 limit = intel_limit(crtc, refclk);
4911 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4918 /* Ensure that the cursor is valid for the new mode before changing... */
4919 intel_crtc_update_cursor(crtc, true);
4921 if (is_lvds && dev_priv->lvds_downclock_avail) {
4923 * Ensure we match the reduced clock's P to the target clock.
4924 * If the clocks don't match, we can't switch the display clock
4925 * by using the FP0/FP1. In such case we will disable the LVDS
4926 * downclock feature.
4928 has_reduced_clock = limit->find_pll(limit, crtc,
4929 dev_priv->lvds_downclock,
4934 /* Compat-code for transition, will disappear. */
4935 if (!intel_crtc->config.clock_set) {
4936 intel_crtc->config.dpll.n = clock.n;
4937 intel_crtc->config.dpll.m1 = clock.m1;
4938 intel_crtc->config.dpll.m2 = clock.m2;
4939 intel_crtc->config.dpll.p1 = clock.p1;
4940 intel_crtc->config.dpll.p2 = clock.p2;
4944 i8xx_update_pll(intel_crtc, adjusted_mode,
4945 has_reduced_clock ? &reduced_clock : NULL,
4947 else if (IS_VALLEYVIEW(dev))
4948 vlv_update_pll(intel_crtc);
4950 i9xx_update_pll(intel_crtc,
4951 has_reduced_clock ? &reduced_clock : NULL,
4954 /* Set up the display plane register */
4955 dspcntr = DISPPLANE_GAMMA_ENABLE;
4957 if (!IS_VALLEYVIEW(dev)) {
4959 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4961 dspcntr |= DISPPLANE_SEL_PIPE_B;
4964 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4965 drm_mode_debug_printmodeline(mode);
4967 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4969 /* pipesrc and dspsize control the size that is scaled from,
4970 * which should always be the user's requested size.
4972 I915_WRITE(DSPSIZE(plane),
4973 ((mode->vdisplay - 1) << 16) |
4974 (mode->hdisplay - 1));
4975 I915_WRITE(DSPPOS(plane), 0);
4977 i9xx_set_pipeconf(intel_crtc);
4979 I915_WRITE(DSPCNTR(plane), dspcntr);
4980 POSTING_READ(DSPCNTR(plane));
4982 ret = intel_pipe_set_base(crtc, x, y, fb);
4984 intel_update_watermarks(dev);
4989 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4990 struct intel_crtc_config *pipe_config)
4992 struct drm_device *dev = crtc->base.dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4996 tmp = I915_READ(PFIT_CONTROL);
4998 if (INTEL_INFO(dev)->gen < 4) {
4999 if (crtc->pipe != PIPE_B)
5002 /* gen2/3 store dither state in pfit control, needs to match */
5003 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
5005 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5009 if (!(tmp & PFIT_ENABLE))
5012 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5013 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5014 if (INTEL_INFO(dev)->gen < 5)
5015 pipe_config->gmch_pfit.lvds_border_bits =
5016 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5019 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5020 struct intel_crtc_config *pipe_config)
5022 struct drm_device *dev = crtc->base.dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5026 tmp = I915_READ(PIPECONF(crtc->pipe));
5027 if (!(tmp & PIPECONF_ENABLE))
5030 intel_get_pipe_timings(crtc, pipe_config);
5032 i9xx_get_pfit_config(crtc, pipe_config);
5037 static void ironlake_init_pch_refclk(struct drm_device *dev)
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct drm_mode_config *mode_config = &dev->mode_config;
5041 struct intel_encoder *encoder;
5043 bool has_lvds = false;
5044 bool has_cpu_edp = false;
5045 bool has_panel = false;
5046 bool has_ck505 = false;
5047 bool can_ssc = false;
5049 /* We need to take the global config into account */
5050 list_for_each_entry(encoder, &mode_config->encoder_list,
5052 switch (encoder->type) {
5053 case INTEL_OUTPUT_LVDS:
5057 case INTEL_OUTPUT_EDP:
5059 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5065 if (HAS_PCH_IBX(dev)) {
5066 has_ck505 = dev_priv->vbt.display_clock_mode;
5067 can_ssc = has_ck505;
5073 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5074 has_panel, has_lvds, has_ck505);
5076 /* Ironlake: try to setup display ref clock before DPLL
5077 * enabling. This is only under driver's control after
5078 * PCH B stepping, previous chipset stepping should be
5079 * ignoring this setting.
5081 val = I915_READ(PCH_DREF_CONTROL);
5083 /* As we must carefully and slowly disable/enable each source in turn,
5084 * compute the final state we want first and check if we need to
5085 * make any changes at all.
5088 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5090 final |= DREF_NONSPREAD_CK505_ENABLE;
5092 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5094 final &= ~DREF_SSC_SOURCE_MASK;
5095 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5096 final &= ~DREF_SSC1_ENABLE;
5099 final |= DREF_SSC_SOURCE_ENABLE;
5101 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5102 final |= DREF_SSC1_ENABLE;
5105 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5106 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5108 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5110 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5112 final |= DREF_SSC_SOURCE_DISABLE;
5113 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5119 /* Always enable nonspread source */
5120 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5123 val |= DREF_NONSPREAD_CK505_ENABLE;
5125 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5128 val &= ~DREF_SSC_SOURCE_MASK;
5129 val |= DREF_SSC_SOURCE_ENABLE;
5131 /* SSC must be turned on before enabling the CPU output */
5132 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5133 DRM_DEBUG_KMS("Using SSC on panel\n");
5134 val |= DREF_SSC1_ENABLE;
5136 val &= ~DREF_SSC1_ENABLE;
5138 /* Get SSC going before enabling the outputs */
5139 I915_WRITE(PCH_DREF_CONTROL, val);
5140 POSTING_READ(PCH_DREF_CONTROL);
5143 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5145 /* Enable CPU source on CPU attached eDP */
5147 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5148 DRM_DEBUG_KMS("Using SSC on eDP\n");
5149 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5152 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5154 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5156 I915_WRITE(PCH_DREF_CONTROL, val);
5157 POSTING_READ(PCH_DREF_CONTROL);
5160 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5162 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5164 /* Turn off CPU output */
5165 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5167 I915_WRITE(PCH_DREF_CONTROL, val);
5168 POSTING_READ(PCH_DREF_CONTROL);
5171 /* Turn off the SSC source */
5172 val &= ~DREF_SSC_SOURCE_MASK;
5173 val |= DREF_SSC_SOURCE_DISABLE;
5176 val &= ~DREF_SSC1_ENABLE;
5178 I915_WRITE(PCH_DREF_CONTROL, val);
5179 POSTING_READ(PCH_DREF_CONTROL);
5183 BUG_ON(val != final);
5186 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5187 static void lpt_init_pch_refclk(struct drm_device *dev)
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct drm_mode_config *mode_config = &dev->mode_config;
5191 struct intel_encoder *encoder;
5192 bool has_vga = false;
5193 bool is_sdv = false;
5196 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5197 switch (encoder->type) {
5198 case INTEL_OUTPUT_ANALOG:
5207 mutex_lock(&dev_priv->dpio_lock);
5209 /* XXX: Rip out SDV support once Haswell ships for real. */
5210 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5213 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5214 tmp &= ~SBI_SSCCTL_DISABLE;
5215 tmp |= SBI_SSCCTL_PATHALT;
5216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5220 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5221 tmp &= ~SBI_SSCCTL_PATHALT;
5222 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5225 tmp = I915_READ(SOUTH_CHICKEN2);
5226 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5227 I915_WRITE(SOUTH_CHICKEN2, tmp);
5229 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5230 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5231 DRM_ERROR("FDI mPHY reset assert timeout\n");
5233 tmp = I915_READ(SOUTH_CHICKEN2);
5234 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5235 I915_WRITE(SOUTH_CHICKEN2, tmp);
5237 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5238 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5240 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5243 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5244 tmp &= ~(0xFF << 24);
5245 tmp |= (0x12 << 24);
5246 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5249 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5251 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5254 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5256 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5258 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5260 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5263 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5264 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5265 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5267 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5268 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5269 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5271 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5273 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5275 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5277 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5280 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5281 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5282 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5284 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5285 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5286 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5289 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5292 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5294 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5297 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5300 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5303 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5305 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5308 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5310 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5311 tmp &= ~(0xFF << 16);
5312 tmp |= (0x1C << 16);
5313 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5315 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5316 tmp &= ~(0xFF << 16);
5317 tmp |= (0x1C << 16);
5318 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5321 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5323 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5325 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5327 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5329 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5330 tmp &= ~(0xF << 28);
5332 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5334 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5335 tmp &= ~(0xF << 28);
5337 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5340 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5341 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5342 tmp |= SBI_DBUFF0_ENABLE;
5343 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5345 mutex_unlock(&dev_priv->dpio_lock);
5349 * Initialize reference clocks when the driver loads
5351 void intel_init_pch_refclk(struct drm_device *dev)
5353 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5354 ironlake_init_pch_refclk(dev);
5355 else if (HAS_PCH_LPT(dev))
5356 lpt_init_pch_refclk(dev);
5359 static int ironlake_get_refclk(struct drm_crtc *crtc)
5361 struct drm_device *dev = crtc->dev;
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363 struct intel_encoder *encoder;
5364 int num_connectors = 0;
5365 bool is_lvds = false;
5367 for_each_encoder_on_crtc(dev, crtc, encoder) {
5368 switch (encoder->type) {
5369 case INTEL_OUTPUT_LVDS:
5376 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5377 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5378 dev_priv->vbt.lvds_ssc_freq);
5379 return dev_priv->vbt.lvds_ssc_freq * 1000;
5385 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5387 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389 int pipe = intel_crtc->pipe;
5392 val = I915_READ(PIPECONF(pipe));
5394 val &= ~PIPECONF_BPC_MASK;
5395 switch (intel_crtc->config.pipe_bpp) {
5397 val |= PIPECONF_6BPC;
5400 val |= PIPECONF_8BPC;
5403 val |= PIPECONF_10BPC;
5406 val |= PIPECONF_12BPC;
5409 /* Case prevented by intel_choose_pipe_bpp_dither. */
5413 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5414 if (intel_crtc->config.dither)
5415 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5417 val &= ~PIPECONF_INTERLACE_MASK;
5418 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5419 val |= PIPECONF_INTERLACED_ILK;
5421 val |= PIPECONF_PROGRESSIVE;
5423 if (intel_crtc->config.limited_color_range)
5424 val |= PIPECONF_COLOR_RANGE_SELECT;
5426 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5428 I915_WRITE(PIPECONF(pipe), val);
5429 POSTING_READ(PIPECONF(pipe));
5433 * Set up the pipe CSC unit.
5435 * Currently only full range RGB to limited range RGB conversion
5436 * is supported, but eventually this should handle various
5437 * RGB<->YCbCr scenarios as well.
5439 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5441 struct drm_device *dev = crtc->dev;
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5444 int pipe = intel_crtc->pipe;
5445 uint16_t coeff = 0x7800; /* 1.0 */
5448 * TODO: Check what kind of values actually come out of the pipe
5449 * with these coeff/postoff values and adjust to get the best
5450 * accuracy. Perhaps we even need to take the bpc value into
5454 if (intel_crtc->config.limited_color_range)
5455 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5458 * GY/GU and RY/RU should be the other way around according
5459 * to BSpec, but reality doesn't agree. Just set them up in
5460 * a way that results in the correct picture.
5462 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5463 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5465 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5466 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5468 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5469 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5471 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5472 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5473 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5475 if (INTEL_INFO(dev)->gen > 6) {
5476 uint16_t postoff = 0;
5478 if (intel_crtc->config.limited_color_range)
5479 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5481 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5482 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5483 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5485 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5487 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5489 if (intel_crtc->config.limited_color_range)
5490 mode |= CSC_BLACK_SCREEN_OFFSET;
5492 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5496 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5498 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5500 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5503 val = I915_READ(PIPECONF(cpu_transcoder));
5505 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5506 if (intel_crtc->config.dither)
5507 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5509 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5510 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5511 val |= PIPECONF_INTERLACED_ILK;
5513 val |= PIPECONF_PROGRESSIVE;
5515 I915_WRITE(PIPECONF(cpu_transcoder), val);
5516 POSTING_READ(PIPECONF(cpu_transcoder));
5519 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5520 struct drm_display_mode *adjusted_mode,
5521 intel_clock_t *clock,
5522 bool *has_reduced_clock,
5523 intel_clock_t *reduced_clock)
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_encoder *intel_encoder;
5529 const intel_limit_t *limit;
5530 bool ret, is_lvds = false;
5532 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5533 switch (intel_encoder->type) {
5534 case INTEL_OUTPUT_LVDS:
5540 refclk = ironlake_get_refclk(crtc);
5543 * Returns a set of divisors for the desired target clock with the given
5544 * refclk, or FALSE. The returned values represent the clock equation:
5545 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5547 limit = intel_limit(crtc, refclk);
5548 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5553 if (is_lvds && dev_priv->lvds_downclock_avail) {
5555 * Ensure we match the reduced clock's P to the target clock.
5556 * If the clocks don't match, we can't switch the display clock
5557 * by using the FP0/FP1. In such case we will disable the LVDS
5558 * downclock feature.
5560 *has_reduced_clock = limit->find_pll(limit, crtc,
5561 dev_priv->lvds_downclock,
5570 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5572 struct drm_i915_private *dev_priv = dev->dev_private;
5575 temp = I915_READ(SOUTH_CHICKEN1);
5576 if (temp & FDI_BC_BIFURCATION_SELECT)
5579 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5580 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5582 temp |= FDI_BC_BIFURCATION_SELECT;
5583 DRM_DEBUG_KMS("enabling fdi C rx\n");
5584 I915_WRITE(SOUTH_CHICKEN1, temp);
5585 POSTING_READ(SOUTH_CHICKEN1);
5588 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5590 struct drm_device *dev = intel_crtc->base.dev;
5591 struct drm_i915_private *dev_priv = dev->dev_private;
5593 switch (intel_crtc->pipe) {
5597 if (intel_crtc->config.fdi_lanes > 2)
5598 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5600 cpt_enable_fdi_bc_bifurcation(dev);
5604 cpt_enable_fdi_bc_bifurcation(dev);
5612 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5615 * Account for spread spectrum to avoid
5616 * oversubscribing the link. Max center spread
5617 * is 2.5%; use 5% for safety's sake.
5619 u32 bps = target_clock * bpp * 21 / 20;
5620 return bps / (link_bw * 8) + 1;
5623 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5625 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5628 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5630 intel_clock_t *reduced_clock, u32 *fp2)
5632 struct drm_crtc *crtc = &intel_crtc->base;
5633 struct drm_device *dev = crtc->dev;
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 struct intel_encoder *intel_encoder;
5637 int factor, num_connectors = 0;
5638 bool is_lvds = false, is_sdvo = false;
5640 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5641 switch (intel_encoder->type) {
5642 case INTEL_OUTPUT_LVDS:
5645 case INTEL_OUTPUT_SDVO:
5646 case INTEL_OUTPUT_HDMI:
5654 /* Enable autotuning of the PLL clock (if permissible) */
5657 if ((intel_panel_use_ssc(dev_priv) &&
5658 dev_priv->vbt.lvds_ssc_freq == 100) ||
5659 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5661 } else if (intel_crtc->config.sdvo_tv_clock)
5664 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5667 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5673 dpll |= DPLLB_MODE_LVDS;
5675 dpll |= DPLLB_MODE_DAC_SERIAL;
5677 if (intel_crtc->config.pixel_multiplier > 1) {
5678 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5679 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5683 dpll |= DPLL_DVO_HIGH_SPEED;
5684 if (intel_crtc->config.has_dp_encoder)
5685 dpll |= DPLL_DVO_HIGH_SPEED;
5687 /* compute bitmask from p1 value */
5688 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5690 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5692 switch (intel_crtc->config.dpll.p2) {
5694 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5697 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5700 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5703 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5707 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5708 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5710 dpll |= PLL_REF_INPUT_DREFCLK;
5715 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5717 struct drm_framebuffer *fb)
5719 struct drm_device *dev = crtc->dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5722 struct drm_display_mode *adjusted_mode =
5723 &intel_crtc->config.adjusted_mode;
5724 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5725 int pipe = intel_crtc->pipe;
5726 int plane = intel_crtc->plane;
5727 int num_connectors = 0;
5728 intel_clock_t clock, reduced_clock;
5729 u32 dpll = 0, fp = 0, fp2 = 0;
5730 bool ok, has_reduced_clock = false;
5731 bool is_lvds = false;
5732 struct intel_encoder *encoder;
5735 for_each_encoder_on_crtc(dev, crtc, encoder) {
5736 switch (encoder->type) {
5737 case INTEL_OUTPUT_LVDS:
5745 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5746 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5748 intel_crtc->config.cpu_transcoder = pipe;
5750 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5751 &has_reduced_clock, &reduced_clock);
5753 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5756 /* Compat-code for transition, will disappear. */
5757 if (!intel_crtc->config.clock_set) {
5758 intel_crtc->config.dpll.n = clock.n;
5759 intel_crtc->config.dpll.m1 = clock.m1;
5760 intel_crtc->config.dpll.m2 = clock.m2;
5761 intel_crtc->config.dpll.p1 = clock.p1;
5762 intel_crtc->config.dpll.p2 = clock.p2;
5765 /* Ensure that the cursor is valid for the new mode before changing... */
5766 intel_crtc_update_cursor(crtc, true);
5768 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5769 drm_mode_debug_printmodeline(mode);
5771 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5772 if (intel_crtc->config.has_pch_encoder) {
5773 struct intel_pch_pll *pll;
5775 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5776 if (has_reduced_clock)
5777 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5779 dpll = ironlake_compute_dpll(intel_crtc,
5780 &fp, &reduced_clock,
5781 has_reduced_clock ? &fp2 : NULL);
5783 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5785 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5790 intel_put_pch_pll(intel_crtc);
5792 if (intel_crtc->config.has_dp_encoder)
5793 intel_dp_set_m_n(intel_crtc);
5795 for_each_encoder_on_crtc(dev, crtc, encoder)
5796 if (encoder->pre_pll_enable)
5797 encoder->pre_pll_enable(encoder);
5799 if (intel_crtc->pch_pll) {
5800 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5802 /* Wait for the clocks to stabilize. */
5803 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5806 /* The pixel multiplier can only be updated once the
5807 * DPLL is enabled and the clocks are stable.
5809 * So write it again.
5811 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5814 intel_crtc->lowfreq_avail = false;
5815 if (intel_crtc->pch_pll) {
5816 if (is_lvds && has_reduced_clock && i915_powersave) {
5817 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5818 intel_crtc->lowfreq_avail = true;
5820 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5824 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5826 if (intel_crtc->config.has_pch_encoder) {
5827 intel_cpu_transcoder_set_m_n(intel_crtc,
5828 &intel_crtc->config.fdi_m_n);
5831 if (IS_IVYBRIDGE(dev))
5832 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5834 ironlake_set_pipeconf(crtc);
5836 /* Set up the display plane register */
5837 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5838 POSTING_READ(DSPCNTR(plane));
5840 ret = intel_pipe_set_base(crtc, x, y, fb);
5842 intel_update_watermarks(dev);
5844 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5849 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5850 struct intel_crtc_config *pipe_config)
5852 struct drm_device *dev = crtc->base.dev;
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 enum transcoder transcoder = pipe_config->cpu_transcoder;
5856 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5857 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5858 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5860 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5861 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5862 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5865 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5866 struct intel_crtc_config *pipe_config)
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5872 tmp = I915_READ(PF_CTL(crtc->pipe));
5874 if (tmp & PF_ENABLE) {
5875 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5876 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5880 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5881 struct intel_crtc_config *pipe_config)
5883 struct drm_device *dev = crtc->base.dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5887 tmp = I915_READ(PIPECONF(crtc->pipe));
5888 if (!(tmp & PIPECONF_ENABLE))
5891 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5892 pipe_config->has_pch_encoder = true;
5894 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5895 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5896 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5898 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5901 intel_get_pipe_timings(crtc, pipe_config);
5903 ironlake_get_pfit_config(crtc, pipe_config);
5908 static void haswell_modeset_global_resources(struct drm_device *dev)
5910 bool enable = false;
5911 struct intel_crtc *crtc;
5912 struct intel_encoder *encoder;
5914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5915 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5917 /* XXX: Should check for edp transcoder here, but thanks to init
5918 * sequence that's not yet available. Just in case desktop eDP
5919 * on PORT D is possible on haswell, too. */
5920 /* Even the eDP panel fitter is outside the always-on well. */
5921 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5925 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5927 if (encoder->type != INTEL_OUTPUT_EDP &&
5928 encoder->connectors_active)
5932 intel_set_power_well(dev, enable);
5935 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5937 struct drm_framebuffer *fb)
5939 struct drm_device *dev = crtc->dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5942 struct drm_display_mode *adjusted_mode =
5943 &intel_crtc->config.adjusted_mode;
5944 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5945 int pipe = intel_crtc->pipe;
5946 int plane = intel_crtc->plane;
5947 int num_connectors = 0;
5948 bool is_cpu_edp = false;
5949 struct intel_encoder *encoder;
5952 for_each_encoder_on_crtc(dev, crtc, encoder) {
5953 switch (encoder->type) {
5954 case INTEL_OUTPUT_EDP:
5955 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5964 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5966 intel_crtc->config.cpu_transcoder = pipe;
5968 /* We are not sure yet this won't happen. */
5969 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5970 INTEL_PCH_TYPE(dev));
5972 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5973 num_connectors, pipe_name(pipe));
5975 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5976 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5978 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5980 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5983 /* Ensure that the cursor is valid for the new mode before changing... */
5984 intel_crtc_update_cursor(crtc, true);
5986 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5987 drm_mode_debug_printmodeline(mode);
5989 if (intel_crtc->config.has_dp_encoder)
5990 intel_dp_set_m_n(intel_crtc);
5992 intel_crtc->lowfreq_avail = false;
5994 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5996 if (intel_crtc->config.has_pch_encoder) {
5997 intel_cpu_transcoder_set_m_n(intel_crtc,
5998 &intel_crtc->config.fdi_m_n);
6001 haswell_set_pipeconf(crtc);
6003 intel_set_pipe_csc(crtc);
6005 /* Set up the display plane register */
6006 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6007 POSTING_READ(DSPCNTR(plane));
6009 ret = intel_pipe_set_base(crtc, x, y, fb);
6011 intel_update_watermarks(dev);
6013 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6018 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6019 struct intel_crtc_config *pipe_config)
6021 struct drm_device *dev = crtc->base.dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
6023 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6024 enum intel_display_power_domain pfit_domain;
6027 if (!intel_display_power_enabled(dev,
6028 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
6031 tmp = I915_READ(PIPECONF(cpu_transcoder));
6032 if (!(tmp & PIPECONF_ENABLE))
6036 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6037 * DDI E. So just check whether this pipe is wired to DDI E and whether
6038 * the PCH transcoder is on.
6040 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6041 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6042 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6043 pipe_config->has_pch_encoder = true;
6045 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6046 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6047 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6049 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6052 intel_get_pipe_timings(crtc, pipe_config);
6054 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6055 if (intel_display_power_enabled(dev, pfit_domain))
6056 ironlake_get_pfit_config(crtc, pipe_config);
6061 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6063 struct drm_framebuffer *fb)
6065 struct drm_device *dev = crtc->dev;
6066 struct drm_i915_private *dev_priv = dev->dev_private;
6067 struct drm_encoder_helper_funcs *encoder_funcs;
6068 struct intel_encoder *encoder;
6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6070 struct drm_display_mode *adjusted_mode =
6071 &intel_crtc->config.adjusted_mode;
6072 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6073 int pipe = intel_crtc->pipe;
6076 drm_vblank_pre_modeset(dev, pipe);
6078 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6080 drm_vblank_post_modeset(dev, pipe);
6085 for_each_encoder_on_crtc(dev, crtc, encoder) {
6086 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6087 encoder->base.base.id,
6088 drm_get_encoder_name(&encoder->base),
6089 mode->base.id, mode->name);
6090 if (encoder->mode_set) {
6091 encoder->mode_set(encoder);
6093 encoder_funcs = encoder->base.helper_private;
6094 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6101 static bool intel_eld_uptodate(struct drm_connector *connector,
6102 int reg_eldv, uint32_t bits_eldv,
6103 int reg_elda, uint32_t bits_elda,
6106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6107 uint8_t *eld = connector->eld;
6110 i = I915_READ(reg_eldv);
6119 i = I915_READ(reg_elda);
6121 I915_WRITE(reg_elda, i);
6123 for (i = 0; i < eld[2]; i++)
6124 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6130 static void g4x_write_eld(struct drm_connector *connector,
6131 struct drm_crtc *crtc)
6133 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6134 uint8_t *eld = connector->eld;
6139 i = I915_READ(G4X_AUD_VID_DID);
6141 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6142 eldv = G4X_ELDV_DEVCL_DEVBLC;
6144 eldv = G4X_ELDV_DEVCTG;
6146 if (intel_eld_uptodate(connector,
6147 G4X_AUD_CNTL_ST, eldv,
6148 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6149 G4X_HDMIW_HDMIEDID))
6152 i = I915_READ(G4X_AUD_CNTL_ST);
6153 i &= ~(eldv | G4X_ELD_ADDR);
6154 len = (i >> 9) & 0x1f; /* ELD buffer size */
6155 I915_WRITE(G4X_AUD_CNTL_ST, i);
6160 len = min_t(uint8_t, eld[2], len);
6161 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6162 for (i = 0; i < len; i++)
6163 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6165 i = I915_READ(G4X_AUD_CNTL_ST);
6167 I915_WRITE(G4X_AUD_CNTL_ST, i);
6170 static void haswell_write_eld(struct drm_connector *connector,
6171 struct drm_crtc *crtc)
6173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6174 uint8_t *eld = connector->eld;
6175 struct drm_device *dev = crtc->dev;
6176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 int pipe = to_intel_crtc(crtc)->pipe;
6183 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6184 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6185 int aud_config = HSW_AUD_CFG(pipe);
6186 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6189 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6191 /* Audio output enable */
6192 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6193 tmp = I915_READ(aud_cntrl_st2);
6194 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6195 I915_WRITE(aud_cntrl_st2, tmp);
6197 /* Wait for 1 vertical blank */
6198 intel_wait_for_vblank(dev, pipe);
6200 /* Set ELD valid state */
6201 tmp = I915_READ(aud_cntrl_st2);
6202 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6203 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6204 I915_WRITE(aud_cntrl_st2, tmp);
6205 tmp = I915_READ(aud_cntrl_st2);
6206 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6208 /* Enable HDMI mode */
6209 tmp = I915_READ(aud_config);
6210 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6211 /* clear N_programing_enable and N_value_index */
6212 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6213 I915_WRITE(aud_config, tmp);
6215 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6217 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6218 intel_crtc->eld_vld = true;
6220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6221 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6222 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6223 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6225 I915_WRITE(aud_config, 0);
6227 if (intel_eld_uptodate(connector,
6228 aud_cntrl_st2, eldv,
6229 aud_cntl_st, IBX_ELD_ADDRESS,
6233 i = I915_READ(aud_cntrl_st2);
6235 I915_WRITE(aud_cntrl_st2, i);
6240 i = I915_READ(aud_cntl_st);
6241 i &= ~IBX_ELD_ADDRESS;
6242 I915_WRITE(aud_cntl_st, i);
6243 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6244 DRM_DEBUG_DRIVER("port num:%d\n", i);
6246 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6247 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6248 for (i = 0; i < len; i++)
6249 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6251 i = I915_READ(aud_cntrl_st2);
6253 I915_WRITE(aud_cntrl_st2, i);
6257 static void ironlake_write_eld(struct drm_connector *connector,
6258 struct drm_crtc *crtc)
6260 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6261 uint8_t *eld = connector->eld;
6269 int pipe = to_intel_crtc(crtc)->pipe;
6271 if (HAS_PCH_IBX(connector->dev)) {
6272 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6273 aud_config = IBX_AUD_CFG(pipe);
6274 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6275 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6277 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6278 aud_config = CPT_AUD_CFG(pipe);
6279 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6280 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6283 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6285 i = I915_READ(aud_cntl_st);
6286 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6288 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6289 /* operate blindly on all ports */
6290 eldv = IBX_ELD_VALIDB;
6291 eldv |= IBX_ELD_VALIDB << 4;
6292 eldv |= IBX_ELD_VALIDB << 8;
6294 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6295 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6298 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6299 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6300 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6301 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6303 I915_WRITE(aud_config, 0);
6305 if (intel_eld_uptodate(connector,
6306 aud_cntrl_st2, eldv,
6307 aud_cntl_st, IBX_ELD_ADDRESS,
6311 i = I915_READ(aud_cntrl_st2);
6313 I915_WRITE(aud_cntrl_st2, i);
6318 i = I915_READ(aud_cntl_st);
6319 i &= ~IBX_ELD_ADDRESS;
6320 I915_WRITE(aud_cntl_st, i);
6322 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6323 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6324 for (i = 0; i < len; i++)
6325 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6327 i = I915_READ(aud_cntrl_st2);
6329 I915_WRITE(aud_cntrl_st2, i);
6332 void intel_write_eld(struct drm_encoder *encoder,
6333 struct drm_display_mode *mode)
6335 struct drm_crtc *crtc = encoder->crtc;
6336 struct drm_connector *connector;
6337 struct drm_device *dev = encoder->dev;
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6340 connector = drm_select_eld(encoder, mode);
6344 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6346 drm_get_connector_name(connector),
6347 connector->encoder->base.id,
6348 drm_get_encoder_name(connector->encoder));
6350 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6352 if (dev_priv->display.write_eld)
6353 dev_priv->display.write_eld(connector, crtc);
6356 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6357 void intel_crtc_load_lut(struct drm_crtc *crtc)
6359 struct drm_device *dev = crtc->dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 int palreg = PALETTE(intel_crtc->pipe);
6365 /* The clocks have to be on to load the palette. */
6366 if (!crtc->enabled || !intel_crtc->active)
6369 /* use legacy palette for Ironlake */
6370 if (HAS_PCH_SPLIT(dev))
6371 palreg = LGC_PALETTE(intel_crtc->pipe);
6373 for (i = 0; i < 256; i++) {
6374 I915_WRITE(palreg + 4 * i,
6375 (intel_crtc->lut_r[i] << 16) |
6376 (intel_crtc->lut_g[i] << 8) |
6377 intel_crtc->lut_b[i]);
6381 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6383 struct drm_device *dev = crtc->dev;
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386 bool visible = base != 0;
6389 if (intel_crtc->cursor_visible == visible)
6392 cntl = I915_READ(_CURACNTR);
6394 /* On these chipsets we can only modify the base whilst
6395 * the cursor is disabled.
6397 I915_WRITE(_CURABASE, base);
6399 cntl &= ~(CURSOR_FORMAT_MASK);
6400 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6401 cntl |= CURSOR_ENABLE |
6402 CURSOR_GAMMA_ENABLE |
6405 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6406 I915_WRITE(_CURACNTR, cntl);
6408 intel_crtc->cursor_visible = visible;
6411 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6413 struct drm_device *dev = crtc->dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416 int pipe = intel_crtc->pipe;
6417 bool visible = base != 0;
6419 if (intel_crtc->cursor_visible != visible) {
6420 uint32_t cntl = I915_READ(CURCNTR(pipe));
6422 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6423 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6424 cntl |= pipe << 28; /* Connect to correct pipe */
6426 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6427 cntl |= CURSOR_MODE_DISABLE;
6429 I915_WRITE(CURCNTR(pipe), cntl);
6431 intel_crtc->cursor_visible = visible;
6433 /* and commit changes on next vblank */
6434 I915_WRITE(CURBASE(pipe), base);
6437 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6439 struct drm_device *dev = crtc->dev;
6440 struct drm_i915_private *dev_priv = dev->dev_private;
6441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6442 int pipe = intel_crtc->pipe;
6443 bool visible = base != 0;
6445 if (intel_crtc->cursor_visible != visible) {
6446 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6448 cntl &= ~CURSOR_MODE;
6449 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6451 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6452 cntl |= CURSOR_MODE_DISABLE;
6454 if (IS_HASWELL(dev))
6455 cntl |= CURSOR_PIPE_CSC_ENABLE;
6456 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6458 intel_crtc->cursor_visible = visible;
6460 /* and commit changes on next vblank */
6461 I915_WRITE(CURBASE_IVB(pipe), base);
6464 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6465 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6468 struct drm_device *dev = crtc->dev;
6469 struct drm_i915_private *dev_priv = dev->dev_private;
6470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6471 int pipe = intel_crtc->pipe;
6472 int x = intel_crtc->cursor_x;
6473 int y = intel_crtc->cursor_y;
6479 if (on && crtc->enabled && crtc->fb) {
6480 base = intel_crtc->cursor_addr;
6481 if (x > (int) crtc->fb->width)
6484 if (y > (int) crtc->fb->height)
6490 if (x + intel_crtc->cursor_width < 0)
6493 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6496 pos |= x << CURSOR_X_SHIFT;
6499 if (y + intel_crtc->cursor_height < 0)
6502 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6505 pos |= y << CURSOR_Y_SHIFT;
6507 visible = base != 0;
6508 if (!visible && !intel_crtc->cursor_visible)
6511 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6512 I915_WRITE(CURPOS_IVB(pipe), pos);
6513 ivb_update_cursor(crtc, base);
6515 I915_WRITE(CURPOS(pipe), pos);
6516 if (IS_845G(dev) || IS_I865G(dev))
6517 i845_update_cursor(crtc, base);
6519 i9xx_update_cursor(crtc, base);
6523 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6524 struct drm_file *file,
6526 uint32_t width, uint32_t height)
6528 struct drm_device *dev = crtc->dev;
6529 struct drm_i915_private *dev_priv = dev->dev_private;
6530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6531 struct drm_i915_gem_object *obj;
6535 /* if we want to turn off the cursor ignore width and height */
6537 DRM_DEBUG_KMS("cursor off\n");
6540 mutex_lock(&dev->struct_mutex);
6544 /* Currently we only support 64x64 cursors */
6545 if (width != 64 || height != 64) {
6546 DRM_ERROR("we currently only support 64x64 cursors\n");
6550 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6551 if (&obj->base == NULL)
6554 if (obj->base.size < width * height * 4) {
6555 DRM_ERROR("buffer is to small\n");
6560 /* we only need to pin inside GTT if cursor is non-phy */
6561 mutex_lock(&dev->struct_mutex);
6562 if (!dev_priv->info->cursor_needs_physical) {
6565 if (obj->tiling_mode) {
6566 DRM_ERROR("cursor cannot be tiled\n");
6571 /* Note that the w/a also requires 2 PTE of padding following
6572 * the bo. We currently fill all unused PTE with the shadow
6573 * page and so we should always have valid PTE following the
6574 * cursor preventing the VT-d warning.
6577 if (need_vtd_wa(dev))
6578 alignment = 64*1024;
6580 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6582 DRM_ERROR("failed to move cursor bo into the GTT\n");
6586 ret = i915_gem_object_put_fence(obj);
6588 DRM_ERROR("failed to release fence for cursor");
6592 addr = obj->gtt_offset;
6594 int align = IS_I830(dev) ? 16 * 1024 : 256;
6595 ret = i915_gem_attach_phys_object(dev, obj,
6596 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6599 DRM_ERROR("failed to attach phys object\n");
6602 addr = obj->phys_obj->handle->busaddr;
6606 I915_WRITE(CURSIZE, (height << 12) | width);
6609 if (intel_crtc->cursor_bo) {
6610 if (dev_priv->info->cursor_needs_physical) {
6611 if (intel_crtc->cursor_bo != obj)
6612 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6614 i915_gem_object_unpin(intel_crtc->cursor_bo);
6615 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6618 mutex_unlock(&dev->struct_mutex);
6620 intel_crtc->cursor_addr = addr;
6621 intel_crtc->cursor_bo = obj;
6622 intel_crtc->cursor_width = width;
6623 intel_crtc->cursor_height = height;
6625 intel_crtc_update_cursor(crtc, true);
6629 i915_gem_object_unpin(obj);
6631 mutex_unlock(&dev->struct_mutex);
6633 drm_gem_object_unreference_unlocked(&obj->base);
6637 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6641 intel_crtc->cursor_x = x;
6642 intel_crtc->cursor_y = y;
6644 intel_crtc_update_cursor(crtc, true);
6649 /** Sets the color ramps on behalf of RandR */
6650 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6651 u16 blue, int regno)
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6655 intel_crtc->lut_r[regno] = red >> 8;
6656 intel_crtc->lut_g[regno] = green >> 8;
6657 intel_crtc->lut_b[regno] = blue >> 8;
6660 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6661 u16 *blue, int regno)
6663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6665 *red = intel_crtc->lut_r[regno] << 8;
6666 *green = intel_crtc->lut_g[regno] << 8;
6667 *blue = intel_crtc->lut_b[regno] << 8;
6670 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6671 u16 *blue, uint32_t start, uint32_t size)
6673 int end = (start + size > 256) ? 256 : start + size, i;
6674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6676 for (i = start; i < end; i++) {
6677 intel_crtc->lut_r[i] = red[i] >> 8;
6678 intel_crtc->lut_g[i] = green[i] >> 8;
6679 intel_crtc->lut_b[i] = blue[i] >> 8;
6682 intel_crtc_load_lut(crtc);
6685 /* VESA 640x480x72Hz mode to set on the pipe */
6686 static struct drm_display_mode load_detect_mode = {
6687 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6688 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6691 static struct drm_framebuffer *
6692 intel_framebuffer_create(struct drm_device *dev,
6693 struct drm_mode_fb_cmd2 *mode_cmd,
6694 struct drm_i915_gem_object *obj)
6696 struct intel_framebuffer *intel_fb;
6699 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6701 drm_gem_object_unreference_unlocked(&obj->base);
6702 return ERR_PTR(-ENOMEM);
6705 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6707 drm_gem_object_unreference_unlocked(&obj->base);
6709 return ERR_PTR(ret);
6712 return &intel_fb->base;
6716 intel_framebuffer_pitch_for_width(int width, int bpp)
6718 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6719 return ALIGN(pitch, 64);
6723 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6725 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6726 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6729 static struct drm_framebuffer *
6730 intel_framebuffer_create_for_mode(struct drm_device *dev,
6731 struct drm_display_mode *mode,
6734 struct drm_i915_gem_object *obj;
6735 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6737 obj = i915_gem_alloc_object(dev,
6738 intel_framebuffer_size_for_mode(mode, bpp));
6740 return ERR_PTR(-ENOMEM);
6742 mode_cmd.width = mode->hdisplay;
6743 mode_cmd.height = mode->vdisplay;
6744 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6746 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6748 return intel_framebuffer_create(dev, &mode_cmd, obj);
6751 static struct drm_framebuffer *
6752 mode_fits_in_fbdev(struct drm_device *dev,
6753 struct drm_display_mode *mode)
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 struct drm_i915_gem_object *obj;
6757 struct drm_framebuffer *fb;
6759 if (dev_priv->fbdev == NULL)
6762 obj = dev_priv->fbdev->ifb.obj;
6766 fb = &dev_priv->fbdev->ifb.base;
6767 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6768 fb->bits_per_pixel))
6771 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6777 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6778 struct drm_display_mode *mode,
6779 struct intel_load_detect_pipe *old)
6781 struct intel_crtc *intel_crtc;
6782 struct intel_encoder *intel_encoder =
6783 intel_attached_encoder(connector);
6784 struct drm_crtc *possible_crtc;
6785 struct drm_encoder *encoder = &intel_encoder->base;
6786 struct drm_crtc *crtc = NULL;
6787 struct drm_device *dev = encoder->dev;
6788 struct drm_framebuffer *fb;
6791 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6792 connector->base.id, drm_get_connector_name(connector),
6793 encoder->base.id, drm_get_encoder_name(encoder));
6796 * Algorithm gets a little messy:
6798 * - if the connector already has an assigned crtc, use it (but make
6799 * sure it's on first)
6801 * - try to find the first unused crtc that can drive this connector,
6802 * and use that if we find one
6805 /* See if we already have a CRTC for this connector */
6806 if (encoder->crtc) {
6807 crtc = encoder->crtc;
6809 mutex_lock(&crtc->mutex);
6811 old->dpms_mode = connector->dpms;
6812 old->load_detect_temp = false;
6814 /* Make sure the crtc and connector are running */
6815 if (connector->dpms != DRM_MODE_DPMS_ON)
6816 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6821 /* Find an unused one (if possible) */
6822 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6824 if (!(encoder->possible_crtcs & (1 << i)))
6826 if (!possible_crtc->enabled) {
6827 crtc = possible_crtc;
6833 * If we didn't find an unused CRTC, don't use any.
6836 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6840 mutex_lock(&crtc->mutex);
6841 intel_encoder->new_crtc = to_intel_crtc(crtc);
6842 to_intel_connector(connector)->new_encoder = intel_encoder;
6844 intel_crtc = to_intel_crtc(crtc);
6845 old->dpms_mode = connector->dpms;
6846 old->load_detect_temp = true;
6847 old->release_fb = NULL;
6850 mode = &load_detect_mode;
6852 /* We need a framebuffer large enough to accommodate all accesses
6853 * that the plane may generate whilst we perform load detection.
6854 * We can not rely on the fbcon either being present (we get called
6855 * during its initialisation to detect all boot displays, or it may
6856 * not even exist) or that it is large enough to satisfy the
6859 fb = mode_fits_in_fbdev(dev, mode);
6861 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6862 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6863 old->release_fb = fb;
6865 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6867 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6868 mutex_unlock(&crtc->mutex);
6872 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6873 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6874 if (old->release_fb)
6875 old->release_fb->funcs->destroy(old->release_fb);
6876 mutex_unlock(&crtc->mutex);
6880 /* let the connector get through one full cycle before testing */
6881 intel_wait_for_vblank(dev, intel_crtc->pipe);
6885 void intel_release_load_detect_pipe(struct drm_connector *connector,
6886 struct intel_load_detect_pipe *old)
6888 struct intel_encoder *intel_encoder =
6889 intel_attached_encoder(connector);
6890 struct drm_encoder *encoder = &intel_encoder->base;
6891 struct drm_crtc *crtc = encoder->crtc;
6893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6894 connector->base.id, drm_get_connector_name(connector),
6895 encoder->base.id, drm_get_encoder_name(encoder));
6897 if (old->load_detect_temp) {
6898 to_intel_connector(connector)->new_encoder = NULL;
6899 intel_encoder->new_crtc = NULL;
6900 intel_set_mode(crtc, NULL, 0, 0, NULL);
6902 if (old->release_fb) {
6903 drm_framebuffer_unregister_private(old->release_fb);
6904 drm_framebuffer_unreference(old->release_fb);
6907 mutex_unlock(&crtc->mutex);
6911 /* Switch crtc and encoder back off if necessary */
6912 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6913 connector->funcs->dpms(connector, old->dpms_mode);
6915 mutex_unlock(&crtc->mutex);
6918 /* Returns the clock of the currently programmed mode of the given pipe. */
6919 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6921 struct drm_i915_private *dev_priv = dev->dev_private;
6922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6923 int pipe = intel_crtc->pipe;
6924 u32 dpll = I915_READ(DPLL(pipe));
6926 intel_clock_t clock;
6928 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6929 fp = I915_READ(FP0(pipe));
6931 fp = I915_READ(FP1(pipe));
6933 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6934 if (IS_PINEVIEW(dev)) {
6935 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6936 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6938 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6939 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6942 if (!IS_GEN2(dev)) {
6943 if (IS_PINEVIEW(dev))
6944 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6945 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6947 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6948 DPLL_FPA01_P1_POST_DIV_SHIFT);
6950 switch (dpll & DPLL_MODE_MASK) {
6951 case DPLLB_MODE_DAC_SERIAL:
6952 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6955 case DPLLB_MODE_LVDS:
6956 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6960 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6961 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6965 /* XXX: Handle the 100Mhz refclk */
6966 intel_clock(dev, 96000, &clock);
6968 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6971 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6972 DPLL_FPA01_P1_POST_DIV_SHIFT);
6975 if ((dpll & PLL_REF_INPUT_MASK) ==
6976 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6977 /* XXX: might not be 66MHz */
6978 intel_clock(dev, 66000, &clock);
6980 intel_clock(dev, 48000, &clock);
6982 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6985 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6986 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6988 if (dpll & PLL_P2_DIVIDE_BY_4)
6993 intel_clock(dev, 48000, &clock);
6997 /* XXX: It would be nice to validate the clocks, but we can't reuse
6998 * i830PllIsValid() because it relies on the xf86_config connector
6999 * configuration being accurate, which it isn't necessarily.
7005 /** Returns the currently programmed mode of the given pipe. */
7006 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7007 struct drm_crtc *crtc)
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7012 struct drm_display_mode *mode;
7013 int htot = I915_READ(HTOTAL(cpu_transcoder));
7014 int hsync = I915_READ(HSYNC(cpu_transcoder));
7015 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7016 int vsync = I915_READ(VSYNC(cpu_transcoder));
7018 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7022 mode->clock = intel_crtc_clock_get(dev, crtc);
7023 mode->hdisplay = (htot & 0xffff) + 1;
7024 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7025 mode->hsync_start = (hsync & 0xffff) + 1;
7026 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7027 mode->vdisplay = (vtot & 0xffff) + 1;
7028 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7029 mode->vsync_start = (vsync & 0xffff) + 1;
7030 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7032 drm_mode_set_name(mode);
7037 static void intel_increase_pllclock(struct drm_crtc *crtc)
7039 struct drm_device *dev = crtc->dev;
7040 drm_i915_private_t *dev_priv = dev->dev_private;
7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042 int pipe = intel_crtc->pipe;
7043 int dpll_reg = DPLL(pipe);
7046 if (HAS_PCH_SPLIT(dev))
7049 if (!dev_priv->lvds_downclock_avail)
7052 dpll = I915_READ(dpll_reg);
7053 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7054 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7056 assert_panel_unlocked(dev_priv, pipe);
7058 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
7060 intel_wait_for_vblank(dev, pipe);
7062 dpll = I915_READ(dpll_reg);
7063 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7064 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7068 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7070 struct drm_device *dev = crtc->dev;
7071 drm_i915_private_t *dev_priv = dev->dev_private;
7072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7074 if (HAS_PCH_SPLIT(dev))
7077 if (!dev_priv->lvds_downclock_avail)
7081 * Since this is called by a timer, we should never get here in
7084 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7085 int pipe = intel_crtc->pipe;
7086 int dpll_reg = DPLL(pipe);
7089 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7091 assert_panel_unlocked(dev_priv, pipe);
7093 dpll = I915_READ(dpll_reg);
7094 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
7096 intel_wait_for_vblank(dev, pipe);
7097 dpll = I915_READ(dpll_reg);
7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7104 void intel_mark_busy(struct drm_device *dev)
7106 i915_update_gfx_val(dev->dev_private);
7109 void intel_mark_idle(struct drm_device *dev)
7111 struct drm_crtc *crtc;
7113 if (!i915_powersave)
7116 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7120 intel_decrease_pllclock(crtc);
7124 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7126 struct drm_device *dev = obj->base.dev;
7127 struct drm_crtc *crtc;
7129 if (!i915_powersave)
7132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7136 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7137 intel_increase_pllclock(crtc);
7141 static void intel_crtc_destroy(struct drm_crtc *crtc)
7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7144 struct drm_device *dev = crtc->dev;
7145 struct intel_unpin_work *work;
7146 unsigned long flags;
7148 spin_lock_irqsave(&dev->event_lock, flags);
7149 work = intel_crtc->unpin_work;
7150 intel_crtc->unpin_work = NULL;
7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7154 cancel_work_sync(&work->work);
7158 drm_crtc_cleanup(crtc);
7163 static void intel_unpin_work_fn(struct work_struct *__work)
7165 struct intel_unpin_work *work =
7166 container_of(__work, struct intel_unpin_work, work);
7167 struct drm_device *dev = work->crtc->dev;
7169 mutex_lock(&dev->struct_mutex);
7170 intel_unpin_fb_obj(work->old_fb_obj);
7171 drm_gem_object_unreference(&work->pending_flip_obj->base);
7172 drm_gem_object_unreference(&work->old_fb_obj->base);
7174 intel_update_fbc(dev);
7175 mutex_unlock(&dev->struct_mutex);
7177 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7178 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7183 static void do_intel_finish_page_flip(struct drm_device *dev,
7184 struct drm_crtc *crtc)
7186 drm_i915_private_t *dev_priv = dev->dev_private;
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 struct intel_unpin_work *work;
7189 unsigned long flags;
7191 /* Ignore early vblank irqs */
7192 if (intel_crtc == NULL)
7195 spin_lock_irqsave(&dev->event_lock, flags);
7196 work = intel_crtc->unpin_work;
7198 /* Ensure we don't miss a work->pending update ... */
7201 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7202 spin_unlock_irqrestore(&dev->event_lock, flags);
7206 /* and that the unpin work is consistent wrt ->pending. */
7209 intel_crtc->unpin_work = NULL;
7212 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7214 drm_vblank_put(dev, intel_crtc->pipe);
7216 spin_unlock_irqrestore(&dev->event_lock, flags);
7218 wake_up_all(&dev_priv->pending_flip_queue);
7220 queue_work(dev_priv->wq, &work->work);
7222 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7225 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7227 drm_i915_private_t *dev_priv = dev->dev_private;
7228 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7230 do_intel_finish_page_flip(dev, crtc);
7233 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7235 drm_i915_private_t *dev_priv = dev->dev_private;
7236 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7238 do_intel_finish_page_flip(dev, crtc);
7241 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc =
7245 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7246 unsigned long flags;
7248 /* NB: An MMIO update of the plane base pointer will also
7249 * generate a page-flip completion irq, i.e. every modeset
7250 * is also accompanied by a spurious intel_prepare_page_flip().
7252 spin_lock_irqsave(&dev->event_lock, flags);
7253 if (intel_crtc->unpin_work)
7254 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7255 spin_unlock_irqrestore(&dev->event_lock, flags);
7258 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7260 /* Ensure that the work item is consistent when activating it ... */
7262 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7263 /* and that it is marked active as soon as the irq could fire. */
7267 static int intel_gen2_queue_flip(struct drm_device *dev,
7268 struct drm_crtc *crtc,
7269 struct drm_framebuffer *fb,
7270 struct drm_i915_gem_object *obj)
7272 struct drm_i915_private *dev_priv = dev->dev_private;
7273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7275 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7278 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7282 ret = intel_ring_begin(ring, 6);
7286 /* Can't queue multiple flips, so wait for the previous
7287 * one to finish before executing the next.
7289 if (intel_crtc->plane)
7290 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7292 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7293 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7294 intel_ring_emit(ring, MI_NOOP);
7295 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7296 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7297 intel_ring_emit(ring, fb->pitches[0]);
7298 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7299 intel_ring_emit(ring, 0); /* aux display base address, unused */
7301 intel_mark_page_flip_active(intel_crtc);
7302 intel_ring_advance(ring);
7306 intel_unpin_fb_obj(obj);
7311 static int intel_gen3_queue_flip(struct drm_device *dev,
7312 struct drm_crtc *crtc,
7313 struct drm_framebuffer *fb,
7314 struct drm_i915_gem_object *obj)
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7322 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7326 ret = intel_ring_begin(ring, 6);
7330 if (intel_crtc->plane)
7331 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7333 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7334 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7335 intel_ring_emit(ring, MI_NOOP);
7336 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7337 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7338 intel_ring_emit(ring, fb->pitches[0]);
7339 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7340 intel_ring_emit(ring, MI_NOOP);
7342 intel_mark_page_flip_active(intel_crtc);
7343 intel_ring_advance(ring);
7347 intel_unpin_fb_obj(obj);
7352 static int intel_gen4_queue_flip(struct drm_device *dev,
7353 struct drm_crtc *crtc,
7354 struct drm_framebuffer *fb,
7355 struct drm_i915_gem_object *obj)
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359 uint32_t pf, pipesrc;
7360 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7363 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7367 ret = intel_ring_begin(ring, 4);
7371 /* i965+ uses the linear or tiled offsets from the
7372 * Display Registers (which do not change across a page-flip)
7373 * so we need only reprogram the base address.
7375 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7377 intel_ring_emit(ring, fb->pitches[0]);
7378 intel_ring_emit(ring,
7379 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7382 /* XXX Enabling the panel-fitter across page-flip is so far
7383 * untested on non-native modes, so ignore it for now.
7384 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7387 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7388 intel_ring_emit(ring, pf | pipesrc);
7390 intel_mark_page_flip_active(intel_crtc);
7391 intel_ring_advance(ring);
7395 intel_unpin_fb_obj(obj);
7400 static int intel_gen6_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7408 uint32_t pf, pipesrc;
7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7415 ret = intel_ring_begin(ring, 4);
7419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7421 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7422 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7424 /* Contrary to the suggestions in the documentation,
7425 * "Enable Panel Fitter" does not seem to be required when page
7426 * flipping with a non-native mode, and worse causes a normal
7428 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7432 intel_ring_emit(ring, pf | pipesrc);
7434 intel_mark_page_flip_active(intel_crtc);
7435 intel_ring_advance(ring);
7439 intel_unpin_fb_obj(obj);
7445 * On gen7 we currently use the blit ring because (in early silicon at least)
7446 * the render ring doesn't give us interrpts for page flip completion, which
7447 * means clients will hang after the first flip is queued. Fortunately the
7448 * blit ring generates interrupts properly, so use it instead.
7450 static int intel_gen7_queue_flip(struct drm_device *dev,
7451 struct drm_crtc *crtc,
7452 struct drm_framebuffer *fb,
7453 struct drm_i915_gem_object *obj)
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7458 uint32_t plane_bit = 0;
7461 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7465 switch(intel_crtc->plane) {
7467 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7470 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7473 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7476 WARN_ONCE(1, "unknown plane in flip command\n");
7481 ret = intel_ring_begin(ring, 4);
7485 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7486 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7487 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7488 intel_ring_emit(ring, (MI_NOOP));
7490 intel_mark_page_flip_active(intel_crtc);
7491 intel_ring_advance(ring);
7495 intel_unpin_fb_obj(obj);
7500 static int intel_default_queue_flip(struct drm_device *dev,
7501 struct drm_crtc *crtc,
7502 struct drm_framebuffer *fb,
7503 struct drm_i915_gem_object *obj)
7508 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7509 struct drm_framebuffer *fb,
7510 struct drm_pending_vblank_event *event)
7512 struct drm_device *dev = crtc->dev;
7513 struct drm_i915_private *dev_priv = dev->dev_private;
7514 struct drm_framebuffer *old_fb = crtc->fb;
7515 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7517 struct intel_unpin_work *work;
7518 unsigned long flags;
7521 /* Can't change pixel format via MI display flips. */
7522 if (fb->pixel_format != crtc->fb->pixel_format)
7526 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7527 * Note that pitch changes could also affect these register.
7529 if (INTEL_INFO(dev)->gen > 3 &&
7530 (fb->offsets[0] != crtc->fb->offsets[0] ||
7531 fb->pitches[0] != crtc->fb->pitches[0]))
7534 work = kzalloc(sizeof *work, GFP_KERNEL);
7538 work->event = event;
7540 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7541 INIT_WORK(&work->work, intel_unpin_work_fn);
7543 ret = drm_vblank_get(dev, intel_crtc->pipe);
7547 /* We borrow the event spin lock for protecting unpin_work */
7548 spin_lock_irqsave(&dev->event_lock, flags);
7549 if (intel_crtc->unpin_work) {
7550 spin_unlock_irqrestore(&dev->event_lock, flags);
7552 drm_vblank_put(dev, intel_crtc->pipe);
7554 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7557 intel_crtc->unpin_work = work;
7558 spin_unlock_irqrestore(&dev->event_lock, flags);
7560 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7561 flush_workqueue(dev_priv->wq);
7563 ret = i915_mutex_lock_interruptible(dev);
7567 /* Reference the objects for the scheduled work. */
7568 drm_gem_object_reference(&work->old_fb_obj->base);
7569 drm_gem_object_reference(&obj->base);
7573 work->pending_flip_obj = obj;
7575 work->enable_stall_check = true;
7577 atomic_inc(&intel_crtc->unpin_work_count);
7578 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7580 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7582 goto cleanup_pending;
7584 intel_disable_fbc(dev);
7585 intel_mark_fb_busy(obj);
7586 mutex_unlock(&dev->struct_mutex);
7588 trace_i915_flip_request(intel_crtc->plane, obj);
7593 atomic_dec(&intel_crtc->unpin_work_count);
7595 drm_gem_object_unreference(&work->old_fb_obj->base);
7596 drm_gem_object_unreference(&obj->base);
7597 mutex_unlock(&dev->struct_mutex);
7600 spin_lock_irqsave(&dev->event_lock, flags);
7601 intel_crtc->unpin_work = NULL;
7602 spin_unlock_irqrestore(&dev->event_lock, flags);
7604 drm_vblank_put(dev, intel_crtc->pipe);
7611 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7612 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7613 .load_lut = intel_crtc_load_lut,
7616 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7618 struct intel_encoder *other_encoder;
7619 struct drm_crtc *crtc = &encoder->new_crtc->base;
7624 list_for_each_entry(other_encoder,
7625 &crtc->dev->mode_config.encoder_list,
7628 if (&other_encoder->new_crtc->base != crtc ||
7629 encoder == other_encoder)
7638 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7639 struct drm_crtc *crtc)
7641 struct drm_device *dev;
7642 struct drm_crtc *tmp;
7645 WARN(!crtc, "checking null crtc?\n");
7649 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7655 if (encoder->possible_crtcs & crtc_mask)
7661 * intel_modeset_update_staged_output_state
7663 * Updates the staged output configuration state, e.g. after we've read out the
7666 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7668 struct intel_encoder *encoder;
7669 struct intel_connector *connector;
7671 list_for_each_entry(connector, &dev->mode_config.connector_list,
7673 connector->new_encoder =
7674 to_intel_encoder(connector->base.encoder);
7677 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7680 to_intel_crtc(encoder->base.crtc);
7685 * intel_modeset_commit_output_state
7687 * This function copies the stage display pipe configuration to the real one.
7689 static void intel_modeset_commit_output_state(struct drm_device *dev)
7691 struct intel_encoder *encoder;
7692 struct intel_connector *connector;
7694 list_for_each_entry(connector, &dev->mode_config.connector_list,
7696 connector->base.encoder = &connector->new_encoder->base;
7699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7701 encoder->base.crtc = &encoder->new_crtc->base;
7706 pipe_config_set_bpp(struct drm_crtc *crtc,
7707 struct drm_framebuffer *fb,
7708 struct intel_crtc_config *pipe_config)
7710 struct drm_device *dev = crtc->dev;
7711 struct drm_connector *connector;
7714 switch (fb->pixel_format) {
7716 bpp = 8*3; /* since we go through a colormap */
7718 case DRM_FORMAT_XRGB1555:
7719 case DRM_FORMAT_ARGB1555:
7720 /* checked in intel_framebuffer_init already */
7721 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7723 case DRM_FORMAT_RGB565:
7724 bpp = 6*3; /* min is 18bpp */
7726 case DRM_FORMAT_XBGR8888:
7727 case DRM_FORMAT_ABGR8888:
7728 /* checked in intel_framebuffer_init already */
7729 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7731 case DRM_FORMAT_XRGB8888:
7732 case DRM_FORMAT_ARGB8888:
7735 case DRM_FORMAT_XRGB2101010:
7736 case DRM_FORMAT_ARGB2101010:
7737 case DRM_FORMAT_XBGR2101010:
7738 case DRM_FORMAT_ABGR2101010:
7739 /* checked in intel_framebuffer_init already */
7740 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7744 /* TODO: gen4+ supports 16 bpc floating point, too. */
7746 DRM_DEBUG_KMS("unsupported depth\n");
7750 pipe_config->pipe_bpp = bpp;
7752 /* Clamp display bpp to EDID value */
7753 list_for_each_entry(connector, &dev->mode_config.connector_list,
7755 if (connector->encoder && connector->encoder->crtc != crtc)
7758 /* Don't use an invalid EDID bpc value */
7759 if (connector->display_info.bpc &&
7760 connector->display_info.bpc * 3 < bpp) {
7761 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7762 bpp, connector->display_info.bpc*3);
7763 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7766 /* Clamp bpp to 8 on screens without EDID 1.4 */
7767 if (connector->display_info.bpc == 0 && bpp > 24) {
7768 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7770 pipe_config->pipe_bpp = 24;
7777 static struct intel_crtc_config *
7778 intel_modeset_pipe_config(struct drm_crtc *crtc,
7779 struct drm_framebuffer *fb,
7780 struct drm_display_mode *mode)
7782 struct drm_device *dev = crtc->dev;
7783 struct drm_encoder_helper_funcs *encoder_funcs;
7784 struct intel_encoder *encoder;
7785 struct intel_crtc_config *pipe_config;
7786 int plane_bpp, ret = -EINVAL;
7789 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7791 return ERR_PTR(-ENOMEM);
7793 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7794 drm_mode_copy(&pipe_config->requested_mode, mode);
7796 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7801 /* Pass our mode to the connectors and the CRTC to give them a chance to
7802 * adjust it according to limitations or connector properties, and also
7803 * a chance to reject the mode entirely.
7805 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7808 if (&encoder->new_crtc->base != crtc)
7811 if (encoder->compute_config) {
7812 if (!(encoder->compute_config(encoder, pipe_config))) {
7813 DRM_DEBUG_KMS("Encoder config failure\n");
7820 encoder_funcs = encoder->base.helper_private;
7821 if (!(encoder_funcs->mode_fixup(&encoder->base,
7822 &pipe_config->requested_mode,
7823 &pipe_config->adjusted_mode))) {
7824 DRM_DEBUG_KMS("Encoder fixup failed\n");
7829 ret = intel_crtc_compute_config(crtc, pipe_config);
7831 DRM_DEBUG_KMS("CRTC fixup failed\n");
7836 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7841 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7846 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7848 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7849 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7850 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7855 return ERR_PTR(ret);
7858 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7859 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7861 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7862 unsigned *prepare_pipes, unsigned *disable_pipes)
7864 struct intel_crtc *intel_crtc;
7865 struct drm_device *dev = crtc->dev;
7866 struct intel_encoder *encoder;
7867 struct intel_connector *connector;
7868 struct drm_crtc *tmp_crtc;
7870 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7872 /* Check which crtcs have changed outputs connected to them, these need
7873 * to be part of the prepare_pipes mask. We don't (yet) support global
7874 * modeset across multiple crtcs, so modeset_pipes will only have one
7875 * bit set at most. */
7876 list_for_each_entry(connector, &dev->mode_config.connector_list,
7878 if (connector->base.encoder == &connector->new_encoder->base)
7881 if (connector->base.encoder) {
7882 tmp_crtc = connector->base.encoder->crtc;
7884 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7887 if (connector->new_encoder)
7889 1 << connector->new_encoder->new_crtc->pipe;
7892 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7894 if (encoder->base.crtc == &encoder->new_crtc->base)
7897 if (encoder->base.crtc) {
7898 tmp_crtc = encoder->base.crtc;
7900 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7903 if (encoder->new_crtc)
7904 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7907 /* Check for any pipes that will be fully disabled ... */
7908 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7912 /* Don't try to disable disabled crtcs. */
7913 if (!intel_crtc->base.enabled)
7916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7918 if (encoder->new_crtc == intel_crtc)
7923 *disable_pipes |= 1 << intel_crtc->pipe;
7927 /* set_mode is also used to update properties on life display pipes. */
7928 intel_crtc = to_intel_crtc(crtc);
7930 *prepare_pipes |= 1 << intel_crtc->pipe;
7933 * For simplicity do a full modeset on any pipe where the output routing
7934 * changed. We could be more clever, but that would require us to be
7935 * more careful with calling the relevant encoder->mode_set functions.
7938 *modeset_pipes = *prepare_pipes;
7940 /* ... and mask these out. */
7941 *modeset_pipes &= ~(*disable_pipes);
7942 *prepare_pipes &= ~(*disable_pipes);
7945 * HACK: We don't (yet) fully support global modesets. intel_set_config
7946 * obies this rule, but the modeset restore mode of
7947 * intel_modeset_setup_hw_state does not.
7949 *modeset_pipes &= 1 << intel_crtc->pipe;
7950 *prepare_pipes &= 1 << intel_crtc->pipe;
7952 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7953 *modeset_pipes, *prepare_pipes, *disable_pipes);
7956 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7958 struct drm_encoder *encoder;
7959 struct drm_device *dev = crtc->dev;
7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7962 if (encoder->crtc == crtc)
7969 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7971 struct intel_encoder *intel_encoder;
7972 struct intel_crtc *intel_crtc;
7973 struct drm_connector *connector;
7975 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7977 if (!intel_encoder->base.crtc)
7980 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7982 if (prepare_pipes & (1 << intel_crtc->pipe))
7983 intel_encoder->connectors_active = false;
7986 intel_modeset_commit_output_state(dev);
7988 /* Update computed state. */
7989 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7991 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7994 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7995 if (!connector->encoder || !connector->encoder->crtc)
7998 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8000 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8001 struct drm_property *dpms_property =
8002 dev->mode_config.dpms_property;
8004 connector->dpms = DRM_MODE_DPMS_ON;
8005 drm_object_property_set_value(&connector->base,
8009 intel_encoder = to_intel_encoder(connector->encoder);
8010 intel_encoder->connectors_active = true;
8016 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8017 list_for_each_entry((intel_crtc), \
8018 &(dev)->mode_config.crtc_list, \
8020 if (mask & (1 <<(intel_crtc)->pipe))
8023 intel_pipe_config_compare(struct drm_device *dev,
8024 struct intel_crtc_config *current_config,
8025 struct intel_crtc_config *pipe_config)
8027 #define PIPE_CONF_CHECK_I(name) \
8028 if (current_config->name != pipe_config->name) { \
8029 DRM_ERROR("mismatch in " #name " " \
8030 "(expected %i, found %i)\n", \
8031 current_config->name, \
8032 pipe_config->name); \
8036 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8037 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8038 DRM_ERROR("mismatch in " #name " " \
8039 "(expected %i, found %i)\n", \
8040 current_config->name & (mask), \
8041 pipe_config->name & (mask)); \
8045 PIPE_CONF_CHECK_I(has_pch_encoder);
8046 PIPE_CONF_CHECK_I(fdi_lanes);
8047 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8048 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8049 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8050 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8051 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8064 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8067 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8068 DRM_MODE_FLAG_INTERLACE);
8070 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8071 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8073 PIPE_CONF_CHECK_I(gmch_pfit.control);
8074 /* pfit ratios are autocomputed by the hw on gen4+ */
8075 if (INTEL_INFO(dev)->gen < 4)
8076 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8077 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8078 PIPE_CONF_CHECK_I(pch_pfit.pos);
8079 PIPE_CONF_CHECK_I(pch_pfit.size);
8081 #undef PIPE_CONF_CHECK_I
8082 #undef PIPE_CONF_CHECK_FLAGS
8088 intel_modeset_check_state(struct drm_device *dev)
8090 drm_i915_private_t *dev_priv = dev->dev_private;
8091 struct intel_crtc *crtc;
8092 struct intel_encoder *encoder;
8093 struct intel_connector *connector;
8094 struct intel_crtc_config pipe_config;
8096 list_for_each_entry(connector, &dev->mode_config.connector_list,
8098 /* This also checks the encoder/connector hw state with the
8099 * ->get_hw_state callbacks. */
8100 intel_connector_check_state(connector);
8102 WARN(&connector->new_encoder->base != connector->base.encoder,
8103 "connector's staged encoder doesn't match current encoder\n");
8106 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8108 bool enabled = false;
8109 bool active = false;
8110 enum pipe pipe, tracked_pipe;
8112 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8113 encoder->base.base.id,
8114 drm_get_encoder_name(&encoder->base));
8116 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8117 "encoder's stage crtc doesn't match current crtc\n");
8118 WARN(encoder->connectors_active && !encoder->base.crtc,
8119 "encoder's active_connectors set, but no crtc\n");
8121 list_for_each_entry(connector, &dev->mode_config.connector_list,
8123 if (connector->base.encoder != &encoder->base)
8126 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8129 WARN(!!encoder->base.crtc != enabled,
8130 "encoder's enabled state mismatch "
8131 "(expected %i, found %i)\n",
8132 !!encoder->base.crtc, enabled);
8133 WARN(active && !encoder->base.crtc,
8134 "active encoder with no crtc\n");
8136 WARN(encoder->connectors_active != active,
8137 "encoder's computed active state doesn't match tracked active state "
8138 "(expected %i, found %i)\n", active, encoder->connectors_active);
8140 active = encoder->get_hw_state(encoder, &pipe);
8141 WARN(active != encoder->connectors_active,
8142 "encoder's hw state doesn't match sw tracking "
8143 "(expected %i, found %i)\n",
8144 encoder->connectors_active, active);
8146 if (!encoder->base.crtc)
8149 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8150 WARN(active && pipe != tracked_pipe,
8151 "active encoder's pipe doesn't match"
8152 "(expected %i, found %i)\n",
8153 tracked_pipe, pipe);
8157 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8159 bool enabled = false;
8160 bool active = false;
8162 DRM_DEBUG_KMS("[CRTC:%d]\n",
8163 crtc->base.base.id);
8165 WARN(crtc->active && !crtc->base.enabled,
8166 "active crtc, but not enabled in sw tracking\n");
8168 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8170 if (encoder->base.crtc != &crtc->base)
8173 if (encoder->connectors_active)
8176 WARN(active != crtc->active,
8177 "crtc's computed active state doesn't match tracked active state "
8178 "(expected %i, found %i)\n", active, crtc->active);
8179 WARN(enabled != crtc->base.enabled,
8180 "crtc's computed enabled state doesn't match tracked enabled state "
8181 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8183 memset(&pipe_config, 0, sizeof(pipe_config));
8184 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8185 active = dev_priv->display.get_pipe_config(crtc,
8187 WARN(crtc->active != active,
8188 "crtc active state doesn't match with hw state "
8189 "(expected %i, found %i)\n", crtc->active, active);
8192 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
8193 "pipe state doesn't match!\n");
8197 static int __intel_set_mode(struct drm_crtc *crtc,
8198 struct drm_display_mode *mode,
8199 int x, int y, struct drm_framebuffer *fb)
8201 struct drm_device *dev = crtc->dev;
8202 drm_i915_private_t *dev_priv = dev->dev_private;
8203 struct drm_display_mode *saved_mode, *saved_hwmode;
8204 struct intel_crtc_config *pipe_config = NULL;
8205 struct intel_crtc *intel_crtc;
8206 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8209 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8212 saved_hwmode = saved_mode + 1;
8214 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8215 &prepare_pipes, &disable_pipes);
8217 *saved_hwmode = crtc->hwmode;
8218 *saved_mode = crtc->mode;
8220 /* Hack: Because we don't (yet) support global modeset on multiple
8221 * crtcs, we don't keep track of the new mode for more than one crtc.
8222 * Hence simply check whether any bit is set in modeset_pipes in all the
8223 * pieces of code that are not yet converted to deal with mutliple crtcs
8224 * changing their mode at the same time. */
8225 if (modeset_pipes) {
8226 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8227 if (IS_ERR(pipe_config)) {
8228 ret = PTR_ERR(pipe_config);
8235 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8236 intel_crtc_disable(&intel_crtc->base);
8238 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8239 if (intel_crtc->base.enabled)
8240 dev_priv->display.crtc_disable(&intel_crtc->base);
8243 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8244 * to set it here already despite that we pass it down the callchain.
8246 if (modeset_pipes) {
8247 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8249 /* mode_set/enable/disable functions rely on a correct pipe
8251 to_intel_crtc(crtc)->config = *pipe_config;
8252 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8255 /* Only after disabling all output pipelines that will be changed can we
8256 * update the the output configuration. */
8257 intel_modeset_update_state(dev, prepare_pipes);
8259 if (dev_priv->display.modeset_global_resources)
8260 dev_priv->display.modeset_global_resources(dev);
8262 /* Set up the DPLL and any encoders state that needs to adjust or depend
8265 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8266 ret = intel_crtc_mode_set(&intel_crtc->base,
8272 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8273 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8274 dev_priv->display.crtc_enable(&intel_crtc->base);
8276 if (modeset_pipes) {
8277 /* Store real post-adjustment hardware mode. */
8278 crtc->hwmode = pipe_config->adjusted_mode;
8280 /* Calculate and store various constants which
8281 * are later needed by vblank and swap-completion
8282 * timestamping. They are derived from true hwmode.
8284 drm_calc_timestamping_constants(crtc);
8287 /* FIXME: add subpixel order */
8289 if (ret && crtc->enabled) {
8290 crtc->hwmode = *saved_hwmode;
8291 crtc->mode = *saved_mode;
8300 int intel_set_mode(struct drm_crtc *crtc,
8301 struct drm_display_mode *mode,
8302 int x, int y, struct drm_framebuffer *fb)
8306 ret = __intel_set_mode(crtc, mode, x, y, fb);
8309 intel_modeset_check_state(crtc->dev);
8314 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8316 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8319 #undef for_each_intel_crtc_masked
8321 static void intel_set_config_free(struct intel_set_config *config)
8326 kfree(config->save_connector_encoders);
8327 kfree(config->save_encoder_crtcs);
8331 static int intel_set_config_save_state(struct drm_device *dev,
8332 struct intel_set_config *config)
8334 struct drm_encoder *encoder;
8335 struct drm_connector *connector;
8338 config->save_encoder_crtcs =
8339 kcalloc(dev->mode_config.num_encoder,
8340 sizeof(struct drm_crtc *), GFP_KERNEL);
8341 if (!config->save_encoder_crtcs)
8344 config->save_connector_encoders =
8345 kcalloc(dev->mode_config.num_connector,
8346 sizeof(struct drm_encoder *), GFP_KERNEL);
8347 if (!config->save_connector_encoders)
8350 /* Copy data. Note that driver private data is not affected.
8351 * Should anything bad happen only the expected state is
8352 * restored, not the drivers personal bookkeeping.
8355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8356 config->save_encoder_crtcs[count++] = encoder->crtc;
8360 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8361 config->save_connector_encoders[count++] = connector->encoder;
8367 static void intel_set_config_restore_state(struct drm_device *dev,
8368 struct intel_set_config *config)
8370 struct intel_encoder *encoder;
8371 struct intel_connector *connector;
8375 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8377 to_intel_crtc(config->save_encoder_crtcs[count++]);
8381 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8382 connector->new_encoder =
8383 to_intel_encoder(config->save_connector_encoders[count++]);
8388 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8389 struct intel_set_config *config)
8392 /* We should be able to check here if the fb has the same properties
8393 * and then just flip_or_move it */
8394 if (set->crtc->fb != set->fb) {
8395 /* If we have no fb then treat it as a full mode set */
8396 if (set->crtc->fb == NULL) {
8397 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8398 config->mode_changed = true;
8399 } else if (set->fb == NULL) {
8400 config->mode_changed = true;
8401 } else if (set->fb->pixel_format !=
8402 set->crtc->fb->pixel_format) {
8403 config->mode_changed = true;
8405 config->fb_changed = true;
8408 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8409 config->fb_changed = true;
8411 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8412 DRM_DEBUG_KMS("modes are different, full mode set\n");
8413 drm_mode_debug_printmodeline(&set->crtc->mode);
8414 drm_mode_debug_printmodeline(set->mode);
8415 config->mode_changed = true;
8420 intel_modeset_stage_output_state(struct drm_device *dev,
8421 struct drm_mode_set *set,
8422 struct intel_set_config *config)
8424 struct drm_crtc *new_crtc;
8425 struct intel_connector *connector;
8426 struct intel_encoder *encoder;
8429 /* The upper layers ensure that we either disable a crtc or have a list
8430 * of connectors. For paranoia, double-check this. */
8431 WARN_ON(!set->fb && (set->num_connectors != 0));
8432 WARN_ON(set->fb && (set->num_connectors == 0));
8435 list_for_each_entry(connector, &dev->mode_config.connector_list,
8437 /* Otherwise traverse passed in connector list and get encoders
8439 for (ro = 0; ro < set->num_connectors; ro++) {
8440 if (set->connectors[ro] == &connector->base) {
8441 connector->new_encoder = connector->encoder;
8446 /* If we disable the crtc, disable all its connectors. Also, if
8447 * the connector is on the changing crtc but not on the new
8448 * connector list, disable it. */
8449 if ((!set->fb || ro == set->num_connectors) &&
8450 connector->base.encoder &&
8451 connector->base.encoder->crtc == set->crtc) {
8452 connector->new_encoder = NULL;
8454 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8455 connector->base.base.id,
8456 drm_get_connector_name(&connector->base));
8460 if (&connector->new_encoder->base != connector->base.encoder) {
8461 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8462 config->mode_changed = true;
8465 /* connector->new_encoder is now updated for all connectors. */
8467 /* Update crtc of enabled connectors. */
8469 list_for_each_entry(connector, &dev->mode_config.connector_list,
8471 if (!connector->new_encoder)
8474 new_crtc = connector->new_encoder->base.crtc;
8476 for (ro = 0; ro < set->num_connectors; ro++) {
8477 if (set->connectors[ro] == &connector->base)
8478 new_crtc = set->crtc;
8481 /* Make sure the new CRTC will work with the encoder */
8482 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8486 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8488 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8489 connector->base.base.id,
8490 drm_get_connector_name(&connector->base),
8494 /* Check for any encoders that needs to be disabled. */
8495 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8497 list_for_each_entry(connector,
8498 &dev->mode_config.connector_list,
8500 if (connector->new_encoder == encoder) {
8501 WARN_ON(!connector->new_encoder->new_crtc);
8506 encoder->new_crtc = NULL;
8508 /* Only now check for crtc changes so we don't miss encoders
8509 * that will be disabled. */
8510 if (&encoder->new_crtc->base != encoder->base.crtc) {
8511 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8512 config->mode_changed = true;
8515 /* Now we've also updated encoder->new_crtc for all encoders. */
8520 static int intel_crtc_set_config(struct drm_mode_set *set)
8522 struct drm_device *dev;
8523 struct drm_mode_set save_set;
8524 struct intel_set_config *config;
8529 BUG_ON(!set->crtc->helper_private);
8531 /* Enforce sane interface api - has been abused by the fb helper. */
8532 BUG_ON(!set->mode && set->fb);
8533 BUG_ON(set->fb && set->num_connectors == 0);
8536 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8537 set->crtc->base.id, set->fb->base.id,
8538 (int)set->num_connectors, set->x, set->y);
8540 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8543 dev = set->crtc->dev;
8546 config = kzalloc(sizeof(*config), GFP_KERNEL);
8550 ret = intel_set_config_save_state(dev, config);
8554 save_set.crtc = set->crtc;
8555 save_set.mode = &set->crtc->mode;
8556 save_set.x = set->crtc->x;
8557 save_set.y = set->crtc->y;
8558 save_set.fb = set->crtc->fb;
8560 /* Compute whether we need a full modeset, only an fb base update or no
8561 * change at all. In the future we might also check whether only the
8562 * mode changed, e.g. for LVDS where we only change the panel fitter in
8564 intel_set_config_compute_mode_changes(set, config);
8566 ret = intel_modeset_stage_output_state(dev, set, config);
8570 if (config->mode_changed) {
8572 DRM_DEBUG_KMS("attempting to set mode from"
8574 drm_mode_debug_printmodeline(set->mode);
8577 ret = intel_set_mode(set->crtc, set->mode,
8578 set->x, set->y, set->fb);
8580 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8581 set->crtc->base.id, ret);
8584 } else if (config->fb_changed) {
8585 intel_crtc_wait_for_pending_flips(set->crtc);
8587 ret = intel_pipe_set_base(set->crtc,
8588 set->x, set->y, set->fb);
8591 intel_set_config_free(config);
8596 intel_set_config_restore_state(dev, config);
8598 /* Try to restore the config */
8599 if (config->mode_changed &&
8600 intel_set_mode(save_set.crtc, save_set.mode,
8601 save_set.x, save_set.y, save_set.fb))
8602 DRM_ERROR("failed to restore config after modeset failure\n");
8605 intel_set_config_free(config);
8609 static const struct drm_crtc_funcs intel_crtc_funcs = {
8610 .cursor_set = intel_crtc_cursor_set,
8611 .cursor_move = intel_crtc_cursor_move,
8612 .gamma_set = intel_crtc_gamma_set,
8613 .set_config = intel_crtc_set_config,
8614 .destroy = intel_crtc_destroy,
8615 .page_flip = intel_crtc_page_flip,
8618 static void intel_cpu_pll_init(struct drm_device *dev)
8621 intel_ddi_pll_init(dev);
8624 static void intel_pch_pll_init(struct drm_device *dev)
8626 drm_i915_private_t *dev_priv = dev->dev_private;
8629 if (dev_priv->num_pch_pll == 0) {
8630 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8634 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8635 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8636 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8637 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8641 static void intel_crtc_init(struct drm_device *dev, int pipe)
8643 drm_i915_private_t *dev_priv = dev->dev_private;
8644 struct intel_crtc *intel_crtc;
8647 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8648 if (intel_crtc == NULL)
8651 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8653 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8654 for (i = 0; i < 256; i++) {
8655 intel_crtc->lut_r[i] = i;
8656 intel_crtc->lut_g[i] = i;
8657 intel_crtc->lut_b[i] = i;
8660 /* Swap pipes & planes for FBC on pre-965 */
8661 intel_crtc->pipe = pipe;
8662 intel_crtc->plane = pipe;
8663 intel_crtc->config.cpu_transcoder = pipe;
8664 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8665 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8666 intel_crtc->plane = !pipe;
8669 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8670 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8671 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8672 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8674 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8677 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8678 struct drm_file *file)
8680 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8681 struct drm_mode_object *drmmode_obj;
8682 struct intel_crtc *crtc;
8684 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8687 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8688 DRM_MODE_OBJECT_CRTC);
8691 DRM_ERROR("no such CRTC id\n");
8695 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8696 pipe_from_crtc_id->pipe = crtc->pipe;
8701 static int intel_encoder_clones(struct intel_encoder *encoder)
8703 struct drm_device *dev = encoder->base.dev;
8704 struct intel_encoder *source_encoder;
8708 list_for_each_entry(source_encoder,
8709 &dev->mode_config.encoder_list, base.head) {
8711 if (encoder == source_encoder)
8712 index_mask |= (1 << entry);
8714 /* Intel hw has only one MUX where enocoders could be cloned. */
8715 if (encoder->cloneable && source_encoder->cloneable)
8716 index_mask |= (1 << entry);
8724 static bool has_edp_a(struct drm_device *dev)
8726 struct drm_i915_private *dev_priv = dev->dev_private;
8728 if (!IS_MOBILE(dev))
8731 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8735 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8741 static void intel_setup_outputs(struct drm_device *dev)
8743 struct drm_i915_private *dev_priv = dev->dev_private;
8744 struct intel_encoder *encoder;
8745 bool dpd_is_edp = false;
8748 has_lvds = intel_lvds_init(dev);
8749 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8750 /* disable the panel fitter on everything but LVDS */
8751 I915_WRITE(PFIT_CONTROL, 0);
8755 intel_crt_init(dev);
8760 /* Haswell uses DDI functions to detect digital outputs */
8761 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8762 /* DDI A only supports eDP */
8764 intel_ddi_init(dev, PORT_A);
8766 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8768 found = I915_READ(SFUSE_STRAP);
8770 if (found & SFUSE_STRAP_DDIB_DETECTED)
8771 intel_ddi_init(dev, PORT_B);
8772 if (found & SFUSE_STRAP_DDIC_DETECTED)
8773 intel_ddi_init(dev, PORT_C);
8774 if (found & SFUSE_STRAP_DDID_DETECTED)
8775 intel_ddi_init(dev, PORT_D);
8776 } else if (HAS_PCH_SPLIT(dev)) {
8778 dpd_is_edp = intel_dpd_is_edp(dev);
8781 intel_dp_init(dev, DP_A, PORT_A);
8783 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8784 /* PCH SDVOB multiplex with HDMIB */
8785 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8787 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8788 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8789 intel_dp_init(dev, PCH_DP_B, PORT_B);
8792 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8793 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8795 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8796 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8798 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8799 intel_dp_init(dev, PCH_DP_C, PORT_C);
8801 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8802 intel_dp_init(dev, PCH_DP_D, PORT_D);
8803 } else if (IS_VALLEYVIEW(dev)) {
8804 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8805 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8806 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8808 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8809 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8811 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8812 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8814 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8817 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8818 DRM_DEBUG_KMS("probing SDVOB\n");
8819 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8820 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8821 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8822 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8825 if (!found && SUPPORTS_INTEGRATED_DP(dev))
8826 intel_dp_init(dev, DP_B, PORT_B);
8829 /* Before G4X SDVOC doesn't have its own detect register */
8831 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8832 DRM_DEBUG_KMS("probing SDVOC\n");
8833 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8836 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8838 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8839 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8840 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8842 if (SUPPORTS_INTEGRATED_DP(dev))
8843 intel_dp_init(dev, DP_C, PORT_C);
8846 if (SUPPORTS_INTEGRATED_DP(dev) &&
8847 (I915_READ(DP_D) & DP_DETECTED))
8848 intel_dp_init(dev, DP_D, PORT_D);
8849 } else if (IS_GEN2(dev))
8850 intel_dvo_init(dev);
8852 if (SUPPORTS_TV(dev))
8855 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8856 encoder->base.possible_crtcs = encoder->crtc_mask;
8857 encoder->base.possible_clones =
8858 intel_encoder_clones(encoder);
8861 intel_init_pch_refclk(dev);
8863 drm_helper_move_panel_connectors_to_head(dev);
8866 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8868 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8870 drm_framebuffer_cleanup(fb);
8871 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8876 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8877 struct drm_file *file,
8878 unsigned int *handle)
8880 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8881 struct drm_i915_gem_object *obj = intel_fb->obj;
8883 return drm_gem_handle_create(file, &obj->base, handle);
8886 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8887 .destroy = intel_user_framebuffer_destroy,
8888 .create_handle = intel_user_framebuffer_create_handle,
8891 int intel_framebuffer_init(struct drm_device *dev,
8892 struct intel_framebuffer *intel_fb,
8893 struct drm_mode_fb_cmd2 *mode_cmd,
8894 struct drm_i915_gem_object *obj)
8898 if (obj->tiling_mode == I915_TILING_Y) {
8899 DRM_DEBUG("hardware does not support tiling Y\n");
8903 if (mode_cmd->pitches[0] & 63) {
8904 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8905 mode_cmd->pitches[0]);
8909 /* FIXME <= Gen4 stride limits are bit unclear */
8910 if (mode_cmd->pitches[0] > 32768) {
8911 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8912 mode_cmd->pitches[0]);
8916 if (obj->tiling_mode != I915_TILING_NONE &&
8917 mode_cmd->pitches[0] != obj->stride) {
8918 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8919 mode_cmd->pitches[0], obj->stride);
8923 /* Reject formats not supported by any plane early. */
8924 switch (mode_cmd->pixel_format) {
8926 case DRM_FORMAT_RGB565:
8927 case DRM_FORMAT_XRGB8888:
8928 case DRM_FORMAT_ARGB8888:
8930 case DRM_FORMAT_XRGB1555:
8931 case DRM_FORMAT_ARGB1555:
8932 if (INTEL_INFO(dev)->gen > 3) {
8933 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8937 case DRM_FORMAT_XBGR8888:
8938 case DRM_FORMAT_ABGR8888:
8939 case DRM_FORMAT_XRGB2101010:
8940 case DRM_FORMAT_ARGB2101010:
8941 case DRM_FORMAT_XBGR2101010:
8942 case DRM_FORMAT_ABGR2101010:
8943 if (INTEL_INFO(dev)->gen < 4) {
8944 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8948 case DRM_FORMAT_YUYV:
8949 case DRM_FORMAT_UYVY:
8950 case DRM_FORMAT_YVYU:
8951 case DRM_FORMAT_VYUY:
8952 if (INTEL_INFO(dev)->gen < 5) {
8953 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8958 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8962 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8963 if (mode_cmd->offsets[0] != 0)
8966 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8967 intel_fb->obj = obj;
8969 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8971 DRM_ERROR("framebuffer init failed %d\n", ret);
8978 static struct drm_framebuffer *
8979 intel_user_framebuffer_create(struct drm_device *dev,
8980 struct drm_file *filp,
8981 struct drm_mode_fb_cmd2 *mode_cmd)
8983 struct drm_i915_gem_object *obj;
8985 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8986 mode_cmd->handles[0]));
8987 if (&obj->base == NULL)
8988 return ERR_PTR(-ENOENT);
8990 return intel_framebuffer_create(dev, mode_cmd, obj);
8993 static const struct drm_mode_config_funcs intel_mode_funcs = {
8994 .fb_create = intel_user_framebuffer_create,
8995 .output_poll_changed = intel_fb_output_poll_changed,
8998 /* Set up chip specific display functions */
8999 static void intel_init_display(struct drm_device *dev)
9001 struct drm_i915_private *dev_priv = dev->dev_private;
9004 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9005 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9006 dev_priv->display.crtc_enable = haswell_crtc_enable;
9007 dev_priv->display.crtc_disable = haswell_crtc_disable;
9008 dev_priv->display.off = haswell_crtc_off;
9009 dev_priv->display.update_plane = ironlake_update_plane;
9010 } else if (HAS_PCH_SPLIT(dev)) {
9011 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9012 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9013 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9014 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9015 dev_priv->display.off = ironlake_crtc_off;
9016 dev_priv->display.update_plane = ironlake_update_plane;
9017 } else if (IS_VALLEYVIEW(dev)) {
9018 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9019 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9020 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9021 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9022 dev_priv->display.off = i9xx_crtc_off;
9023 dev_priv->display.update_plane = i9xx_update_plane;
9025 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9026 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9027 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9028 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9029 dev_priv->display.off = i9xx_crtc_off;
9030 dev_priv->display.update_plane = i9xx_update_plane;
9033 /* Returns the core display clock speed */
9034 if (IS_VALLEYVIEW(dev))
9035 dev_priv->display.get_display_clock_speed =
9036 valleyview_get_display_clock_speed;
9037 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9038 dev_priv->display.get_display_clock_speed =
9039 i945_get_display_clock_speed;
9040 else if (IS_I915G(dev))
9041 dev_priv->display.get_display_clock_speed =
9042 i915_get_display_clock_speed;
9043 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9044 dev_priv->display.get_display_clock_speed =
9045 i9xx_misc_get_display_clock_speed;
9046 else if (IS_I915GM(dev))
9047 dev_priv->display.get_display_clock_speed =
9048 i915gm_get_display_clock_speed;
9049 else if (IS_I865G(dev))
9050 dev_priv->display.get_display_clock_speed =
9051 i865_get_display_clock_speed;
9052 else if (IS_I85X(dev))
9053 dev_priv->display.get_display_clock_speed =
9054 i855_get_display_clock_speed;
9056 dev_priv->display.get_display_clock_speed =
9057 i830_get_display_clock_speed;
9059 if (HAS_PCH_SPLIT(dev)) {
9061 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9062 dev_priv->display.write_eld = ironlake_write_eld;
9063 } else if (IS_GEN6(dev)) {
9064 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9065 dev_priv->display.write_eld = ironlake_write_eld;
9066 } else if (IS_IVYBRIDGE(dev)) {
9067 /* FIXME: detect B0+ stepping and use auto training */
9068 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9069 dev_priv->display.write_eld = ironlake_write_eld;
9070 dev_priv->display.modeset_global_resources =
9071 ivb_modeset_global_resources;
9072 } else if (IS_HASWELL(dev)) {
9073 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9074 dev_priv->display.write_eld = haswell_write_eld;
9075 dev_priv->display.modeset_global_resources =
9076 haswell_modeset_global_resources;
9078 } else if (IS_G4X(dev)) {
9079 dev_priv->display.write_eld = g4x_write_eld;
9082 /* Default just returns -ENODEV to indicate unsupported */
9083 dev_priv->display.queue_flip = intel_default_queue_flip;
9085 switch (INTEL_INFO(dev)->gen) {
9087 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9091 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9096 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9100 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9103 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9109 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9110 * resume, or other times. This quirk makes sure that's the case for
9113 static void quirk_pipea_force(struct drm_device *dev)
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9117 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9118 DRM_INFO("applying pipe a force quirk\n");
9122 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9124 static void quirk_ssc_force_disable(struct drm_device *dev)
9126 struct drm_i915_private *dev_priv = dev->dev_private;
9127 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9128 DRM_INFO("applying lvds SSC disable quirk\n");
9132 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9135 static void quirk_invert_brightness(struct drm_device *dev)
9137 struct drm_i915_private *dev_priv = dev->dev_private;
9138 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9139 DRM_INFO("applying inverted panel brightness quirk\n");
9142 struct intel_quirk {
9144 int subsystem_vendor;
9145 int subsystem_device;
9146 void (*hook)(struct drm_device *dev);
9149 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9150 struct intel_dmi_quirk {
9151 void (*hook)(struct drm_device *dev);
9152 const struct dmi_system_id (*dmi_id_list)[];
9155 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9157 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9161 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9163 .dmi_id_list = &(const struct dmi_system_id[]) {
9165 .callback = intel_dmi_reverse_brightness,
9166 .ident = "NCR Corporation",
9167 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9168 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9171 { } /* terminating entry */
9173 .hook = quirk_invert_brightness,
9177 static struct intel_quirk intel_quirks[] = {
9178 /* HP Mini needs pipe A force quirk (LP: #322104) */
9179 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9181 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9182 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9184 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9185 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9187 /* 830/845 need to leave pipe A & dpll A up */
9188 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9189 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9191 /* Lenovo U160 cannot use SSC on LVDS */
9192 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9194 /* Sony Vaio Y cannot use SSC on LVDS */
9195 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9197 /* Acer Aspire 5734Z must invert backlight brightness */
9198 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9200 /* Acer/eMachines G725 */
9201 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9203 /* Acer/eMachines e725 */
9204 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9206 /* Acer/Packard Bell NCL20 */
9207 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9209 /* Acer Aspire 4736Z */
9210 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9213 static void intel_init_quirks(struct drm_device *dev)
9215 struct pci_dev *d = dev->pdev;
9218 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9219 struct intel_quirk *q = &intel_quirks[i];
9221 if (d->device == q->device &&
9222 (d->subsystem_vendor == q->subsystem_vendor ||
9223 q->subsystem_vendor == PCI_ANY_ID) &&
9224 (d->subsystem_device == q->subsystem_device ||
9225 q->subsystem_device == PCI_ANY_ID))
9228 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9229 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9230 intel_dmi_quirks[i].hook(dev);
9234 /* Disable the VGA plane that we never use */
9235 static void i915_disable_vga(struct drm_device *dev)
9237 struct drm_i915_private *dev_priv = dev->dev_private;
9239 u32 vga_reg = i915_vgacntrl_reg(dev);
9241 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9242 outb(SR01, VGA_SR_INDEX);
9243 sr1 = inb(VGA_SR_DATA);
9244 outb(sr1 | 1<<5, VGA_SR_DATA);
9245 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9248 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9249 POSTING_READ(vga_reg);
9252 void intel_modeset_init_hw(struct drm_device *dev)
9254 intel_init_power_well(dev);
9256 intel_prepare_ddi(dev);
9258 intel_init_clock_gating(dev);
9260 mutex_lock(&dev->struct_mutex);
9261 intel_enable_gt_powersave(dev);
9262 mutex_unlock(&dev->struct_mutex);
9265 void intel_modeset_suspend_hw(struct drm_device *dev)
9267 intel_suspend_hw(dev);
9270 void intel_modeset_init(struct drm_device *dev)
9272 struct drm_i915_private *dev_priv = dev->dev_private;
9275 drm_mode_config_init(dev);
9277 dev->mode_config.min_width = 0;
9278 dev->mode_config.min_height = 0;
9280 dev->mode_config.preferred_depth = 24;
9281 dev->mode_config.prefer_shadow = 1;
9283 dev->mode_config.funcs = &intel_mode_funcs;
9285 intel_init_quirks(dev);
9289 if (INTEL_INFO(dev)->num_pipes == 0)
9292 intel_init_display(dev);
9295 dev->mode_config.max_width = 2048;
9296 dev->mode_config.max_height = 2048;
9297 } else if (IS_GEN3(dev)) {
9298 dev->mode_config.max_width = 4096;
9299 dev->mode_config.max_height = 4096;
9301 dev->mode_config.max_width = 8192;
9302 dev->mode_config.max_height = 8192;
9304 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9306 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9307 INTEL_INFO(dev)->num_pipes,
9308 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9310 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9311 intel_crtc_init(dev, i);
9312 for (j = 0; j < dev_priv->num_plane; j++) {
9313 ret = intel_plane_init(dev, i, j);
9315 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9316 pipe_name(i), sprite_name(i, j), ret);
9320 intel_cpu_pll_init(dev);
9321 intel_pch_pll_init(dev);
9323 /* Just disable it once at startup */
9324 i915_disable_vga(dev);
9325 intel_setup_outputs(dev);
9327 /* Just in case the BIOS is doing something questionable. */
9328 intel_disable_fbc(dev);
9332 intel_connector_break_all_links(struct intel_connector *connector)
9334 connector->base.dpms = DRM_MODE_DPMS_OFF;
9335 connector->base.encoder = NULL;
9336 connector->encoder->connectors_active = false;
9337 connector->encoder->base.crtc = NULL;
9340 static void intel_enable_pipe_a(struct drm_device *dev)
9342 struct intel_connector *connector;
9343 struct drm_connector *crt = NULL;
9344 struct intel_load_detect_pipe load_detect_temp;
9346 /* We can't just switch on the pipe A, we need to set things up with a
9347 * proper mode and output configuration. As a gross hack, enable pipe A
9348 * by enabling the load detect pipe once. */
9349 list_for_each_entry(connector,
9350 &dev->mode_config.connector_list,
9352 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9353 crt = &connector->base;
9361 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9362 intel_release_load_detect_pipe(crt, &load_detect_temp);
9368 intel_check_plane_mapping(struct intel_crtc *crtc)
9370 struct drm_device *dev = crtc->base.dev;
9371 struct drm_i915_private *dev_priv = dev->dev_private;
9374 if (INTEL_INFO(dev)->num_pipes == 1)
9377 reg = DSPCNTR(!crtc->plane);
9378 val = I915_READ(reg);
9380 if ((val & DISPLAY_PLANE_ENABLE) &&
9381 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9387 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9389 struct drm_device *dev = crtc->base.dev;
9390 struct drm_i915_private *dev_priv = dev->dev_private;
9393 /* Clear any frame start delays used for debugging left by the BIOS */
9394 reg = PIPECONF(crtc->config.cpu_transcoder);
9395 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9397 /* We need to sanitize the plane -> pipe mapping first because this will
9398 * disable the crtc (and hence change the state) if it is wrong. Note
9399 * that gen4+ has a fixed plane -> pipe mapping. */
9400 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9401 struct intel_connector *connector;
9404 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9405 crtc->base.base.id);
9407 /* Pipe has the wrong plane attached and the plane is active.
9408 * Temporarily change the plane mapping and disable everything
9410 plane = crtc->plane;
9411 crtc->plane = !plane;
9412 dev_priv->display.crtc_disable(&crtc->base);
9413 crtc->plane = plane;
9415 /* ... and break all links. */
9416 list_for_each_entry(connector, &dev->mode_config.connector_list,
9418 if (connector->encoder->base.crtc != &crtc->base)
9421 intel_connector_break_all_links(connector);
9424 WARN_ON(crtc->active);
9425 crtc->base.enabled = false;
9428 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9429 crtc->pipe == PIPE_A && !crtc->active) {
9430 /* BIOS forgot to enable pipe A, this mostly happens after
9431 * resume. Force-enable the pipe to fix this, the update_dpms
9432 * call below we restore the pipe to the right state, but leave
9433 * the required bits on. */
9434 intel_enable_pipe_a(dev);
9437 /* Adjust the state of the output pipe according to whether we
9438 * have active connectors/encoders. */
9439 intel_crtc_update_dpms(&crtc->base);
9441 if (crtc->active != crtc->base.enabled) {
9442 struct intel_encoder *encoder;
9444 /* This can happen either due to bugs in the get_hw_state
9445 * functions or because the pipe is force-enabled due to the
9447 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9449 crtc->base.enabled ? "enabled" : "disabled",
9450 crtc->active ? "enabled" : "disabled");
9452 crtc->base.enabled = crtc->active;
9454 /* Because we only establish the connector -> encoder ->
9455 * crtc links if something is active, this means the
9456 * crtc is now deactivated. Break the links. connector
9457 * -> encoder links are only establish when things are
9458 * actually up, hence no need to break them. */
9459 WARN_ON(crtc->active);
9461 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9462 WARN_ON(encoder->connectors_active);
9463 encoder->base.crtc = NULL;
9468 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9470 struct intel_connector *connector;
9471 struct drm_device *dev = encoder->base.dev;
9473 /* We need to check both for a crtc link (meaning that the
9474 * encoder is active and trying to read from a pipe) and the
9475 * pipe itself being active. */
9476 bool has_active_crtc = encoder->base.crtc &&
9477 to_intel_crtc(encoder->base.crtc)->active;
9479 if (encoder->connectors_active && !has_active_crtc) {
9480 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9481 encoder->base.base.id,
9482 drm_get_encoder_name(&encoder->base));
9484 /* Connector is active, but has no active pipe. This is
9485 * fallout from our resume register restoring. Disable
9486 * the encoder manually again. */
9487 if (encoder->base.crtc) {
9488 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9489 encoder->base.base.id,
9490 drm_get_encoder_name(&encoder->base));
9491 encoder->disable(encoder);
9494 /* Inconsistent output/port/pipe state happens presumably due to
9495 * a bug in one of the get_hw_state functions. Or someplace else
9496 * in our code, like the register restore mess on resume. Clamp
9497 * things to off as a safer default. */
9498 list_for_each_entry(connector,
9499 &dev->mode_config.connector_list,
9501 if (connector->encoder != encoder)
9504 intel_connector_break_all_links(connector);
9507 /* Enabled encoders without active connectors will be fixed in
9508 * the crtc fixup. */
9511 void i915_redisable_vga(struct drm_device *dev)
9513 struct drm_i915_private *dev_priv = dev->dev_private;
9514 u32 vga_reg = i915_vgacntrl_reg(dev);
9516 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9517 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9518 i915_disable_vga(dev);
9522 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9523 * and i915 state tracking structures. */
9524 void intel_modeset_setup_hw_state(struct drm_device *dev,
9527 struct drm_i915_private *dev_priv = dev->dev_private;
9530 struct drm_plane *plane;
9531 struct intel_crtc *crtc;
9532 struct intel_encoder *encoder;
9533 struct intel_connector *connector;
9536 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9538 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9539 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9540 case TRANS_DDI_EDP_INPUT_A_ON:
9541 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9544 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9547 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9551 /* A bogus value has been programmed, disable
9553 WARN(1, "Bogus eDP source %08x\n", tmp);
9554 intel_ddi_disable_transcoder_func(dev_priv,
9559 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9560 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9562 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9568 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9570 enum transcoder tmp = crtc->config.cpu_transcoder;
9571 memset(&crtc->config, 0, sizeof(crtc->config));
9572 crtc->config.cpu_transcoder = tmp;
9574 crtc->active = dev_priv->display.get_pipe_config(crtc,
9577 crtc->base.enabled = crtc->active;
9579 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9581 crtc->active ? "enabled" : "disabled");
9585 intel_ddi_setup_hw_pll_state(dev);
9587 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9591 if (encoder->get_hw_state(encoder, &pipe)) {
9592 encoder->base.crtc =
9593 dev_priv->pipe_to_crtc_mapping[pipe];
9595 encoder->base.crtc = NULL;
9598 encoder->connectors_active = false;
9599 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9600 encoder->base.base.id,
9601 drm_get_encoder_name(&encoder->base),
9602 encoder->base.crtc ? "enabled" : "disabled",
9606 list_for_each_entry(connector, &dev->mode_config.connector_list,
9608 if (connector->get_hw_state(connector)) {
9609 connector->base.dpms = DRM_MODE_DPMS_ON;
9610 connector->encoder->connectors_active = true;
9611 connector->base.encoder = &connector->encoder->base;
9613 connector->base.dpms = DRM_MODE_DPMS_OFF;
9614 connector->base.encoder = NULL;
9616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9617 connector->base.base.id,
9618 drm_get_connector_name(&connector->base),
9619 connector->base.encoder ? "enabled" : "disabled");
9622 /* HW state is read out, now we need to sanitize this mess. */
9623 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9625 intel_sanitize_encoder(encoder);
9628 for_each_pipe(pipe) {
9629 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9630 intel_sanitize_crtc(crtc);
9633 if (force_restore) {
9635 * We need to use raw interfaces for restoring state to avoid
9636 * checking (bogus) intermediate states.
9638 for_each_pipe(pipe) {
9639 struct drm_crtc *crtc =
9640 dev_priv->pipe_to_crtc_mapping[pipe];
9642 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9645 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9646 intel_plane_restore(plane);
9648 i915_redisable_vga(dev);
9650 intel_modeset_update_staged_output_state(dev);
9653 intel_modeset_check_state(dev);
9655 drm_mode_config_reset(dev);
9658 void intel_modeset_gem_init(struct drm_device *dev)
9660 intel_modeset_init_hw(dev);
9662 intel_setup_overlay(dev);
9664 intel_modeset_setup_hw_state(dev, false);
9667 void intel_modeset_cleanup(struct drm_device *dev)
9669 struct drm_i915_private *dev_priv = dev->dev_private;
9670 struct drm_crtc *crtc;
9671 struct intel_crtc *intel_crtc;
9674 * Interrupts and polling as the first thing to avoid creating havoc.
9675 * Too much stuff here (turning of rps, connectors, ...) would
9676 * experience fancy races otherwise.
9678 drm_irq_uninstall(dev);
9679 cancel_work_sync(&dev_priv->hotplug_work);
9681 * Due to the hpd irq storm handling the hotplug work can re-arm the
9682 * poll handlers. Hence disable polling after hpd handling is shut down.
9684 drm_kms_helper_poll_fini(dev);
9686 mutex_lock(&dev->struct_mutex);
9688 intel_unregister_dsm_handler();
9690 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9691 /* Skip inactive CRTCs */
9695 intel_crtc = to_intel_crtc(crtc);
9696 intel_increase_pllclock(crtc);
9699 intel_disable_fbc(dev);
9701 intel_disable_gt_powersave(dev);
9703 ironlake_teardown_rc6(dev);
9705 mutex_unlock(&dev->struct_mutex);
9707 /* flush any delayed tasks or pending work */
9708 flush_scheduled_work();
9710 /* destroy backlight, if any, before the connectors */
9711 intel_panel_destroy_backlight(dev);
9713 drm_mode_config_cleanup(dev);
9715 intel_cleanup_overlay(dev);
9719 * Return which encoder is currently attached for connector.
9721 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9723 return &intel_attached_encoder(connector)->base;
9726 void intel_connector_attach_encoder(struct intel_connector *connector,
9727 struct intel_encoder *encoder)
9729 connector->encoder = encoder;
9730 drm_mode_connector_attach_encoder(&connector->base,
9735 * set vga decode state - true == enable VGA decode
9737 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9739 struct drm_i915_private *dev_priv = dev->dev_private;
9742 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9744 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9746 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9747 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9751 #ifdef CONFIG_DEBUG_FS
9752 #include <linux/seq_file.h>
9754 struct intel_display_error_state {
9756 u32 power_well_driver;
9758 struct intel_cursor_error_state {
9763 } cursor[I915_MAX_PIPES];
9765 struct intel_pipe_error_state {
9766 enum transcoder cpu_transcoder;
9776 } pipe[I915_MAX_PIPES];
9778 struct intel_plane_error_state {
9786 } plane[I915_MAX_PIPES];
9789 struct intel_display_error_state *
9790 intel_display_capture_error_state(struct drm_device *dev)
9792 drm_i915_private_t *dev_priv = dev->dev_private;
9793 struct intel_display_error_state *error;
9794 enum transcoder cpu_transcoder;
9797 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9801 if (HAS_POWER_WELL(dev))
9802 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9805 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9806 error->pipe[i].cpu_transcoder = cpu_transcoder;
9808 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9809 error->cursor[i].control = I915_READ(CURCNTR(i));
9810 error->cursor[i].position = I915_READ(CURPOS(i));
9811 error->cursor[i].base = I915_READ(CURBASE(i));
9813 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9814 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9815 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9818 error->plane[i].control = I915_READ(DSPCNTR(i));
9819 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9820 if (INTEL_INFO(dev)->gen <= 3) {
9821 error->plane[i].size = I915_READ(DSPSIZE(i));
9822 error->plane[i].pos = I915_READ(DSPPOS(i));
9824 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9825 error->plane[i].addr = I915_READ(DSPADDR(i));
9826 if (INTEL_INFO(dev)->gen >= 4) {
9827 error->plane[i].surface = I915_READ(DSPSURF(i));
9828 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9831 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9832 error->pipe[i].source = I915_READ(PIPESRC(i));
9833 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9834 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9835 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9836 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9837 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9838 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9841 /* In the code above we read the registers without checking if the power
9842 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9843 * prevent the next I915_WRITE from detecting it and printing an error
9845 if (HAS_POWER_WELL(dev))
9846 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9852 intel_display_print_error_state(struct seq_file *m,
9853 struct drm_device *dev,
9854 struct intel_display_error_state *error)
9858 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9859 if (HAS_POWER_WELL(dev))
9860 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9861 error->power_well_driver);
9863 seq_printf(m, "Pipe [%d]:\n", i);
9864 seq_printf(m, " CPU transcoder: %c\n",
9865 transcoder_name(error->pipe[i].cpu_transcoder));
9866 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9867 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9868 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9869 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9870 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9871 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9872 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9873 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9875 seq_printf(m, "Plane [%d]:\n", i);
9876 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9877 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9878 if (INTEL_INFO(dev)->gen <= 3) {
9879 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9880 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9882 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9883 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9884 if (INTEL_INFO(dev)->gen >= 4) {
9885 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9886 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9889 seq_printf(m, "Cursor [%d]:\n", i);
9890 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9891 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9892 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);