Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30
  31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  32  * them for both DP and FDI transports, allowing those ports to
  33  * automatically adapt to HDMI connections as well
  34  */
  35 static const u32 hsw_ddi_translations_dp[] = {
  36         0x00FFFFFF, 0x0006000E,         /* DP parameters */
  37         0x00D75FFF, 0x0005000A,
  38         0x00C30FFF, 0x00040006,
  39         0x80AAAFFF, 0x000B0000,
  40         0x00FFFFFF, 0x0005000A,
  41         0x00D75FFF, 0x000C0004,
  42         0x80C30FFF, 0x000B0000,
  43         0x00FFFFFF, 0x00040006,
  44         0x80D75FFF, 0x000B0000,
  45 };
  46
  47 static const u32 hsw_ddi_translations_fdi[] = {
  48         0x00FFFFFF, 0x0007000E,         /* FDI parameters */
  49         0x00D75FFF, 0x000F000A,
  50         0x00C30FFF, 0x00060006,
  51         0x00AAAFFF, 0x001E0000,
  52         0x00FFFFFF, 0x000F000A,
  53         0x00D75FFF, 0x00160004,
  54         0x00C30FFF, 0x001E0000,
  55         0x00FFFFFF, 0x00060006,
  56         0x00D75FFF, 0x001E0000,
  57 };
  58
  59 static const u32 hsw_ddi_translations_hdmi[] = {
  60                                 /* Idx  NT mV diff      T mV diff       db  */
  61         0x00FFFFFF, 0x0006000E, /* 0:   400             400             0   */
  62         0x00E79FFF, 0x000E000C, /* 1:   400             500             2   */
  63         0x00D75FFF, 0x0005000A, /* 2:   400             600             3.5 */
  64         0x00FFFFFF, 0x0005000A, /* 3:   600             600             0   */
  65         0x00E79FFF, 0x001D0007, /* 4:   600             750             2   */
  66         0x00D75FFF, 0x000C0004, /* 5:   600             900             3.5 */
  67         0x00FFFFFF, 0x00040006, /* 6:   800             800             0   */
  68         0x80E79FFF, 0x00030002, /* 7:   800             1000            2   */
  69         0x00FFFFFF, 0x00140005, /* 8:   850             850             0   */
  70         0x00FFFFFF, 0x000C0004, /* 9:   900             900             0   */
  71         0x00FFFFFF, 0x001C0003, /* 10:  950             950             0   */
  72         0x80FFFFFF, 0x00030002, /* 11:  1000            1000            0   */
  73 };
  74
  75 static const u32 bdw_ddi_translations_edp[] = {
  76         0x00FFFFFF, 0x00000012,         /* eDP parameters */
  77         0x00EBAFFF, 0x00020011,
  78         0x00C71FFF, 0x0006000F,
  79         0x00FFFFFF, 0x00020011,
  80         0x00DB6FFF, 0x0005000F,
  81         0x00BEEFFF, 0x000A000C,
  82         0x00FFFFFF, 0x0005000F,
  83         0x00DB6FFF, 0x000A000C,
  84         0x00FFFFFF, 0x000A000C,
  85         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  86 };
  87
  88 static const u32 bdw_ddi_translations_dp[] = {
  89         0x00FFFFFF, 0x0007000E,         /* DP parameters */
  90         0x00D75FFF, 0x000E000A,
  91         0x00BEFFFF, 0x00140006,
  92         0x00FFFFFF, 0x000E000A,
  93         0x00D75FFF, 0x00180004,
  94         0x80CB2FFF, 0x001B0002,
  95         0x00F7DFFF, 0x00180004,
  96         0x80D75FFF, 0x001B0002,
  97         0x80FFFFFF, 0x001B0002,
  98         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
  99 };
 100
 101 static const u32 bdw_ddi_translations_fdi[] = {
 102         0x00FFFFFF, 0x0001000E,         /* FDI parameters */
 103         0x00D75FFF, 0x0004000A,
 104         0x00C30FFF, 0x00070006,
 105         0x00AAAFFF, 0x000C0000,
 106         0x00FFFFFF, 0x0004000A,
 107         0x00D75FFF, 0x00090004,
 108         0x00C30FFF, 0x000C0000,
 109         0x00FFFFFF, 0x00070006,
 110         0x00D75FFF, 0x000C0000,
 111         0x00FFFFFF, 0x00140006          /* HDMI parameters 800mV 0dB*/
 112 };
 113
 114 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
 115 {
 116         struct drm_encoder *encoder = &intel_encoder->base;
 117         int type = intel_encoder->type;
 118
 119         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
 120             type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
 121                 struct intel_digital_port *intel_dig_port =
 122                         enc_to_dig_port(encoder);
 123                 return intel_dig_port->port;
 124
 125         } else if (type == INTEL_OUTPUT_ANALOG) {
 126                 return PORT_E;
 127
 128         } else {
 129                 DRM_ERROR("Invalid DDI encoder type %d\n", type);
 130                 BUG();
 131         }
 132 }
 133
 134 /*
 135  * Starting with Haswell, DDI port buffers must be programmed with correct
 136  * values in advance. The buffer values are different for FDI and DP modes,
 137  * but the HDMI/DVI fields are shared among those. So we program the DDI
 138  * in either FDI or DP modes only, as HDMI connections will work with both
 139  * of those
 140  */
 141 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port)
 142 {
 143         struct drm_i915_private *dev_priv = dev->dev_private;
 144         u32 reg;
 145         int i;
 146         int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 147         const u32 *ddi_translations_fdi;
 148         const u32 *ddi_translations_dp;
 149         const u32 *ddi_translations_edp;
 150         const u32 *ddi_translations;
 151
 152         if (IS_BROADWELL(dev)) {
 153                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 154                 ddi_translations_dp = bdw_ddi_translations_dp;
 155                 ddi_translations_edp = bdw_ddi_translations_edp;
 156         } else if (IS_HASWELL(dev)) {
 157                 ddi_translations_fdi = hsw_ddi_translations_fdi;
 158                 ddi_translations_dp = hsw_ddi_translations_dp;
 159                 ddi_translations_edp = hsw_ddi_translations_dp;
 160         } else {
 161                 WARN(1, "ddi translation table missing\n");
 162                 ddi_translations_edp = bdw_ddi_translations_dp;
 163                 ddi_translations_fdi = bdw_ddi_translations_fdi;
 164                 ddi_translations_dp = bdw_ddi_translations_dp;
 165         }
 166
 167         switch (port) {
 168         case PORT_A:
 169                 ddi_translations = ddi_translations_edp;
 170                 break;
 171         case PORT_B:
 172         case PORT_C:
 173                 ddi_translations = ddi_translations_dp;
 174                 break;
 175         case PORT_D:
 176                 if (intel_dpd_is_edp(dev))
 177                         ddi_translations = ddi_translations_edp;
 178                 else
 179                         ddi_translations = ddi_translations_dp;
 180                 break;
 181         case PORT_E:
 182                 ddi_translations = ddi_translations_fdi;
 183                 break;
 184         default:
 185                 BUG();
 186         }
 187
 188         for (i = 0, reg = DDI_BUF_TRANS(port);
 189              i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
 190                 I915_WRITE(reg, ddi_translations[i]);
 191                 reg += 4;
 192         }
 193         /* Entry 9 is for HDMI: */
 194         for (i = 0; i < 2; i++) {
 195                 I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]);
 196                 reg += 4;
 197         }
 198 }
 199
 200 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
 201  * mode and port E for FDI.
 202  */
 203 void intel_prepare_ddi(struct drm_device *dev)
 204 {
 205         int port;
 206
 207         if (!HAS_DDI(dev))
 208                 return;
 209
 210         for (port = PORT_A; port <= PORT_E; port++)
 211                 intel_prepare_ddi_buffers(dev, port);
 212 }
 213
 214 static const long hsw_ddi_buf_ctl_values[] = {
 215         DDI_BUF_EMP_400MV_0DB_HSW,
 216         DDI_BUF_EMP_400MV_3_5DB_HSW,
 217         DDI_BUF_EMP_400MV_6DB_HSW,
 218         DDI_BUF_EMP_400MV_9_5DB_HSW,
 219         DDI_BUF_EMP_600MV_0DB_HSW,
 220         DDI_BUF_EMP_600MV_3_5DB_HSW,
 221         DDI_BUF_EMP_600MV_6DB_HSW,
 222         DDI_BUF_EMP_800MV_0DB_HSW,
 223         DDI_BUF_EMP_800MV_3_5DB_HSW
 224 };
 225
 226 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 227                                     enum port port)
 228 {
 229         uint32_t reg = DDI_BUF_CTL(port);
 230         int i;
 231
 232         for (i = 0; i < 8; i++) {
 233                 udelay(1);
 234                 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 235                         return;
 236         }
 237         DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
 238 }
 239
 240 /* Starting with Haswell, different DDI ports can work in FDI mode for
 241  * connection to the PCH-located connectors. For this, it is necessary to train
 242  * both the DDI port and PCH receiver for the desired DDI buffer settings.
 243  *
 244  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 245  * please note that when FDI mode is active on DDI E, it shares 2 lines with
 246  * DDI A (which is used for eDP)
 247  */
 248
 249 void hsw_fdi_link_train(struct drm_crtc *crtc)
 250 {
 251         struct drm_device *dev = crtc->dev;
 252         struct drm_i915_private *dev_priv = dev->dev_private;
 253         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 254         u32 temp, i, rx_ctl_val;
 255
 256         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
 257          * mode set "sequence for CRT port" document:
 258          * - TP1 to TP2 time with the default value
 259          * - FDI delay to 90h
 260          *
 261          * WaFDIAutoLinkSetTimingOverrride:hsw
 262          */
 263         I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
 264                                   FDI_RX_PWRDN_LANE0_VAL(2) |
 265                                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
 266
 267         /* Enable the PCH Receiver FDI PLL */
 268         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
 269                      FDI_RX_PLL_ENABLE |
 270                      FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
 271         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 272         POSTING_READ(_FDI_RXA_CTL);
 273         udelay(220);
 274
 275         /* Switch from Rawclk to PCDclk */
 276         rx_ctl_val |= FDI_PCDCLK;
 277         I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 278
 279         /* Configure Port Clock Select */
 280         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
 281
 282         /* Start the training iterating through available voltages and emphasis,
 283          * testing each value twice. */
 284         for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
 285                 /* Configure DP_TP_CTL with auto-training */
 286                 I915_WRITE(DP_TP_CTL(PORT_E),
 287                                         DP_TP_CTL_FDI_AUTOTRAIN |
 288                                         DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 289                                         DP_TP_CTL_LINK_TRAIN_PAT1 |
 290                                         DP_TP_CTL_ENABLE);
 291
 292                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
 293                  * DDI E does not support port reversal, the functionality is
 294                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
 295                  * port reversal bit */
 296                 I915_WRITE(DDI_BUF_CTL(PORT_E),
 297                            DDI_BUF_CTL_ENABLE |
 298                            ((intel_crtc->config.fdi_lanes - 1) << 1) |
 299                            hsw_ddi_buf_ctl_values[i / 2]);
 300                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 301
 302                 udelay(600);
 303
 304                 /* Program PCH FDI Receiver TU */
 305                 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
 306
 307                 /* Enable PCH FDI Receiver with auto-training */
 308                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
 309                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 310                 POSTING_READ(_FDI_RXA_CTL);
 311
 312                 /* Wait for FDI receiver lane calibration */
 313                 udelay(30);
 314
 315                 /* Unset FDI_RX_MISC pwrdn lanes */
 316                 temp = I915_READ(_FDI_RXA_MISC);
 317                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 318                 I915_WRITE(_FDI_RXA_MISC, temp);
 319                 POSTING_READ(_FDI_RXA_MISC);
 320
 321                 /* Wait for FDI auto training time */
 322                 udelay(5);
 323
 324                 temp = I915_READ(DP_TP_STATUS(PORT_E));
 325                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
 326                         DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
 327
 328                         /* Enable normal pixel sending for FDI */
 329                         I915_WRITE(DP_TP_CTL(PORT_E),
 330                                    DP_TP_CTL_FDI_AUTOTRAIN |
 331                                    DP_TP_CTL_LINK_TRAIN_NORMAL |
 332                                    DP_TP_CTL_ENHANCED_FRAME_ENABLE |
 333                                    DP_TP_CTL_ENABLE);
 334
 335                         return;
 336                 }
 337
 338                 temp = I915_READ(DDI_BUF_CTL(PORT_E));
 339                 temp &= ~DDI_BUF_CTL_ENABLE;
 340                 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
 341                 POSTING_READ(DDI_BUF_CTL(PORT_E));
 342
 343                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
 344                 temp = I915_READ(DP_TP_CTL(PORT_E));
 345                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
 346                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
 347                 I915_WRITE(DP_TP_CTL(PORT_E), temp);
 348                 POSTING_READ(DP_TP_CTL(PORT_E));
 349
 350                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
 351
 352                 rx_ctl_val &= ~FDI_RX_ENABLE;
 353                 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 354                 POSTING_READ(_FDI_RXA_CTL);
 355
 356                 /* Reset FDI_RX_MISC pwrdn lanes */
 357                 temp = I915_READ(_FDI_RXA_MISC);
 358                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
 359                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
 360                 I915_WRITE(_FDI_RXA_MISC, temp);
 361                 POSTING_READ(_FDI_RXA_MISC);
 362         }
 363
 364         DRM_ERROR("FDI link training failed!\n");
 365 }
 366
 367 static void intel_ddi_mode_set(struct intel_encoder *encoder)
 368 {
 369         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 370         int port = intel_ddi_get_encoder_port(encoder);
 371         int pipe = crtc->pipe;
 372         int type = encoder->type;
 373         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 374
 375         DRM_DEBUG_KMS("Preparing DDI mode on port %c, pipe %c\n",
 376                       port_name(port), pipe_name(pipe));
 377
 378         crtc->eld_vld = false;
 379         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 380                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 381                 struct intel_digital_port *intel_dig_port =
 382                         enc_to_dig_port(&encoder->base);
 383
 384                 intel_dp->DP = intel_dig_port->saved_port_bits |
 385                                DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;
 386                 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
 387
 388                 if (intel_dp->has_audio) {
 389                         DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
 390                                          pipe_name(crtc->pipe));
 391
 392                         /* write eld */
 393                         DRM_DEBUG_DRIVER("DP audio: write eld information\n");
 394                         intel_write_eld(&encoder->base, adjusted_mode);
 395                 }
 396         } else if (type == INTEL_OUTPUT_HDMI) {
 397                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 398
 399                 if (intel_hdmi->has_audio) {
 400                         /* Proper support for digital audio needs a new logic
 401                          * and a new set of registers, so we leave it for future
 402                          * patch bombing.
 403                          */
 404                         DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
 405                                          pipe_name(crtc->pipe));
 406
 407                         /* write eld */
 408                         DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
 409                         intel_write_eld(&encoder->base, adjusted_mode);
 410                 }
 411
 412                 intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
 413         }
 414 }
 415
 416 static struct intel_encoder *
 417 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
 418 {
 419         struct drm_device *dev = crtc->dev;
 420         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 421         struct intel_encoder *intel_encoder, *ret = NULL;
 422         int num_encoders = 0;
 423
 424         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 425                 ret = intel_encoder;
 426                 num_encoders++;
 427         }
 428
 429         if (num_encoders != 1)
 430                 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
 431                      pipe_name(intel_crtc->pipe));
 432
 433         BUG_ON(ret == NULL);
 434         return ret;
 435 }
 436
 437 void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
 438 {
 439         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 440         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 441         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 442         uint32_t val;
 443
 444         switch (intel_crtc->ddi_pll_sel) {
 445         case PORT_CLK_SEL_SPLL:
 446                 plls->spll_refcount--;
 447                 if (plls->spll_refcount == 0) {
 448                         DRM_DEBUG_KMS("Disabling SPLL\n");
 449                         val = I915_READ(SPLL_CTL);
 450                         WARN_ON(!(val & SPLL_PLL_ENABLE));
 451                         I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
 452                         POSTING_READ(SPLL_CTL);
 453                 }
 454                 break;
 455         case PORT_CLK_SEL_WRPLL1:
 456                 plls->wrpll1_refcount--;
 457                 if (plls->wrpll1_refcount == 0) {
 458                         DRM_DEBUG_KMS("Disabling WRPLL 1\n");
 459                         val = I915_READ(WRPLL_CTL1);
 460                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 461                         I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
 462                         POSTING_READ(WRPLL_CTL1);
 463                 }
 464                 break;
 465         case PORT_CLK_SEL_WRPLL2:
 466                 plls->wrpll2_refcount--;
 467                 if (plls->wrpll2_refcount == 0) {
 468                         DRM_DEBUG_KMS("Disabling WRPLL 2\n");
 469                         val = I915_READ(WRPLL_CTL2);
 470                         WARN_ON(!(val & WRPLL_PLL_ENABLE));
 471                         I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
 472                         POSTING_READ(WRPLL_CTL2);
 473                 }
 474                 break;
 475         }
 476
 477         WARN(plls->spll_refcount < 0, "Invalid SPLL refcount\n");
 478         WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
 479         WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
 480
 481         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_NONE;
 482 }
 483
 484 #define LC_FREQ 2700
 485 #define LC_FREQ_2K (LC_FREQ * 2000)
 486
 487 #define P_MIN 2
 488 #define P_MAX 64
 489 #define P_INC 2
 490
 491 /* Constraints for PLL good behavior */
 492 #define REF_MIN 48
 493 #define REF_MAX 400
 494 #define VCO_MIN 2400
 495 #define VCO_MAX 4800
 496
 497 #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a))
 498
 499 struct wrpll_rnp {
 500         unsigned p, n2, r2;
 501 };
 502
 503 static unsigned wrpll_get_budget_for_freq(int clock)
 504 {
 505         unsigned budget;
 506
 507         switch (clock) {
 508         case 25175000:
 509         case 25200000:
 510         case 27000000:
 511         case 27027000:
 512         case 37762500:
 513         case 37800000:
 514         case 40500000:
 515         case 40541000:
 516         case 54000000:
 517         case 54054000:
 518         case 59341000:
 519         case 59400000:
 520         case 72000000:
 521         case 74176000:
 522         case 74250000:
 523         case 81000000:
 524         case 81081000:
 525         case 89012000:
 526         case 89100000:
 527         case 108000000:
 528         case 108108000:
 529         case 111264000:
 530         case 111375000:
 531         case 148352000:
 532         case 148500000:
 533         case 162000000:
 534         case 162162000:
 535         case 222525000:
 536         case 222750000:
 537         case 296703000:
 538         case 297000000:
 539                 budget = 0;
 540                 break;
 541         case 233500000:
 542         case 245250000:
 543         case 247750000:
 544         case 253250000:
 545         case 298000000:
 546                 budget = 1500;
 547                 break;
 548         case 169128000:
 549         case 169500000:
 550         case 179500000:
 551         case 202000000:
 552                 budget = 2000;
 553                 break;
 554         case 256250000:
 555         case 262500000:
 556         case 270000000:
 557         case 272500000:
 558         case 273750000:
 559         case 280750000:
 560         case 281250000:
 561         case 286000000:
 562         case 291750000:
 563                 budget = 4000;
 564                 break;
 565         case 267250000:
 566         case 268500000:
 567                 budget = 5000;
 568                 break;
 569         default:
 570                 budget = 1000;
 571                 break;
 572         }
 573
 574         return budget;
 575 }
 576
 577 static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
 578                              unsigned r2, unsigned n2, unsigned p,
 579                              struct wrpll_rnp *best)
 580 {
 581         uint64_t a, b, c, d, diff, diff_best;
 582
 583         /* No best (r,n,p) yet */
 584         if (best->p == 0) {
 585                 best->p = p;
 586                 best->n2 = n2;
 587                 best->r2 = r2;
 588                 return;
 589         }
 590
 591         /*
 592          * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
 593          * freq2k.
 594          *
 595          * delta = 1e6 *
 596          *         abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
 597          *         freq2k;
 598          *
 599          * and we would like delta <= budget.
 600          *
 601          * If the discrepancy is above the PPM-based budget, always prefer to
 602          * improve upon the previous solution.  However, if you're within the
 603          * budget, try to maximize Ref * VCO, that is N / (P * R^2).
 604          */
 605         a = freq2k * budget * p * r2;
 606         b = freq2k * budget * best->p * best->r2;
 607         diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2));
 608         diff_best = ABS_DIFF((freq2k * best->p * best->r2),
 609                              (LC_FREQ_2K * best->n2));
 610         c = 1000000 * diff;
 611         d = 1000000 * diff_best;
 612
 613         if (a < c && b < d) {
 614                 /* If both are above the budget, pick the closer */
 615                 if (best->p * best->r2 * diff < p * r2 * diff_best) {
 616                         best->p = p;
 617                         best->n2 = n2;
 618                         best->r2 = r2;
 619                 }
 620         } else if (a >= c && b < d) {
 621                 /* If A is below the threshold but B is above it?  Update. */
 622                 best->p = p;
 623                 best->n2 = n2;
 624                 best->r2 = r2;
 625         } else if (a >= c && b >= d) {
 626                 /* Both are below the limit, so pick the higher n2/(r2*r2) */
 627                 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
 628                         best->p = p;
 629                         best->n2 = n2;
 630                         best->r2 = r2;
 631                 }
 632         }
 633         /* Otherwise a < c && b >= d, do nothing */
 634 }
 635
 636 static void
 637 intel_ddi_calculate_wrpll(int clock /* in Hz */,
 638                           unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
 639 {
 640         uint64_t freq2k;
 641         unsigned p, n2, r2;
 642         struct wrpll_rnp best = { 0, 0, 0 };
 643         unsigned budget;
 644
 645         freq2k = clock / 100;
 646
 647         budget = wrpll_get_budget_for_freq(clock);
 648
 649         /* Special case handling for 540 pixel clock: bypass WR PLL entirely
 650          * and directly pass the LC PLL to it. */
 651         if (freq2k == 5400000) {
 652                 *n2_out = 2;
 653                 *p_out = 1;
 654                 *r2_out = 2;
 655                 return;
 656         }
 657
 658         /*
 659          * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
 660          * the WR PLL.
 661          *
 662          * We want R so that REF_MIN <= Ref <= REF_MAX.
 663          * Injecting R2 = 2 * R gives:
 664          *   REF_MAX * r2 > LC_FREQ * 2 and
 665          *   REF_MIN * r2 < LC_FREQ * 2
 666          *
 667          * Which means the desired boundaries for r2 are:
 668          *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
 669          *
 670          */
 671         for (r2 = LC_FREQ * 2 / REF_MAX + 1;
 672              r2 <= LC_FREQ * 2 / REF_MIN;
 673              r2++) {
 674
 675                 /*
 676                  * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
 677                  *
 678                  * Once again we want VCO_MIN <= VCO <= VCO_MAX.
 679                  * Injecting R2 = 2 * R and N2 = 2 * N, we get:
 680                  *   VCO_MAX * r2 > n2 * LC_FREQ and
 681                  *   VCO_MIN * r2 < n2 * LC_FREQ)
 682                  *
 683                  * Which means the desired boundaries for n2 are:
 684                  * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
 685                  */
 686                 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
 687                      n2 <= VCO_MAX * r2 / LC_FREQ;
 688                      n2++) {
 689
 690                         for (p = P_MIN; p <= P_MAX; p += P_INC)
 691                                 wrpll_update_rnp(freq2k, budget,
 692                                                  r2, n2, p, &best);
 693                 }
 694         }
 695
 696         *n2_out = best.n2;
 697         *p_out = best.p;
 698         *r2_out = best.r2;
 699
 700         DRM_DEBUG_KMS("WRPLL: %dHz refresh rate with p=%d, n2=%d r2=%d\n",
 701                       clock, *p_out, *n2_out, *r2_out);
 702 }
 703
 704 bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
 705 {
 706         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 707         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 708         struct drm_encoder *encoder = &intel_encoder->base;
 709         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 710         struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
 711         int type = intel_encoder->type;
 712         enum pipe pipe = intel_crtc->pipe;
 713         uint32_t reg, val;
 714         int clock = intel_crtc->config.port_clock;
 715
 716         intel_ddi_put_crtc_pll(crtc);
 717
 718         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 719                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 720
 721                 switch (intel_dp->link_bw) {
 722                 case DP_LINK_BW_1_62:
 723                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 724                         break;
 725                 case DP_LINK_BW_2_7:
 726                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 727                         break;
 728                 case DP_LINK_BW_5_4:
 729                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 730                         break;
 731                 default:
 732                         DRM_ERROR("Link bandwidth %d unsupported\n",
 733                                   intel_dp->link_bw);
 734                         return false;
 735                 }
 736
 737                 /* We don't need to turn any PLL on because we'll use LCPLL. */
 738                 return true;
 739
 740         } else if (type == INTEL_OUTPUT_HDMI) {
 741                 unsigned p, n2, r2;
 742
 743                 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
 744
 745                 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
 746                       WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 747                       WRPLL_DIVIDER_POST(p);
 748
 749                 if (val == I915_READ(WRPLL_CTL1)) {
 750                         DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
 751                                       pipe_name(pipe));
 752                         reg = WRPLL_CTL1;
 753                 } else if (val == I915_READ(WRPLL_CTL2)) {
 754                         DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
 755                                       pipe_name(pipe));
 756                         reg = WRPLL_CTL2;
 757                 } else if (plls->wrpll1_refcount == 0) {
 758                         DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
 759                                       pipe_name(pipe));
 760                         reg = WRPLL_CTL1;
 761                 } else if (plls->wrpll2_refcount == 0) {
 762                         DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
 763                                       pipe_name(pipe));
 764                         reg = WRPLL_CTL2;
 765                 } else {
 766                         DRM_ERROR("No WRPLLs available!\n");
 767                         return false;
 768                 }
 769
 770                 if (reg == WRPLL_CTL1) {
 771                         plls->wrpll1_refcount++;
 772                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
 773                 } else {
 774                         plls->wrpll2_refcount++;
 775                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
 776                 }
 777
 778         } else if (type == INTEL_OUTPUT_ANALOG) {
 779                 if (plls->spll_refcount == 0) {
 780                         DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
 781                                       pipe_name(pipe));
 782                         plls->spll_refcount++;
 783                         reg = SPLL_CTL;
 784                         intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL;
 785                 } else {
 786                         DRM_ERROR("SPLL already in use\n");
 787                         return false;
 788                 }
 789
 790                 WARN(I915_READ(reg) & SPLL_PLL_ENABLE,
 791                      "SPLL already enabled\n");
 792
 793                 val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
 794
 795         } else {
 796                 WARN(1, "Invalid DDI encoder type %d\n", type);
 797                 return false;
 798         }
 799
 800         I915_WRITE(reg, val);
 801         udelay(20);
 802
 803         return true;
 804 }
 805
 806 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
 807 {
 808         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
 809         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 810         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 811         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 812         int type = intel_encoder->type;
 813         uint32_t temp;
 814
 815         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
 816
 817                 temp = TRANS_MSA_SYNC_CLK;
 818                 switch (intel_crtc->config.pipe_bpp) {
 819                 case 18:
 820                         temp |= TRANS_MSA_6_BPC;
 821                         break;
 822                 case 24:
 823                         temp |= TRANS_MSA_8_BPC;
 824                         break;
 825                 case 30:
 826                         temp |= TRANS_MSA_10_BPC;
 827                         break;
 828                 case 36:
 829                         temp |= TRANS_MSA_12_BPC;
 830                         break;
 831                 default:
 832                         BUG();
 833                 }
 834                 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 835         }
 836 }
 837
 838 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
 839 {
 840         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 841         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 842         struct drm_encoder *encoder = &intel_encoder->base;
 843         struct drm_device *dev = crtc->dev;
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         enum pipe pipe = intel_crtc->pipe;
 846         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
 847         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 848         int type = intel_encoder->type;
 849         uint32_t temp;
 850
 851         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 852         temp = TRANS_DDI_FUNC_ENABLE;
 853         temp |= TRANS_DDI_SELECT_PORT(port);
 854
 855         switch (intel_crtc->config.pipe_bpp) {
 856         case 18:
 857                 temp |= TRANS_DDI_BPC_6;
 858                 break;
 859         case 24:
 860                 temp |= TRANS_DDI_BPC_8;
 861                 break;
 862         case 30:
 863                 temp |= TRANS_DDI_BPC_10;
 864                 break;
 865         case 36:
 866                 temp |= TRANS_DDI_BPC_12;
 867                 break;
 868         default:
 869                 BUG();
 870         }
 871
 872         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 873                 temp |= TRANS_DDI_PVSYNC;
 874         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 875                 temp |= TRANS_DDI_PHSYNC;
 876
 877         if (cpu_transcoder == TRANSCODER_EDP) {
 878                 switch (pipe) {
 879                 case PIPE_A:
 880                         /* On Haswell, can only use the always-on power well for
 881                          * eDP when not using the panel fitter, and when not
 882                          * using motion blur mitigation (which we don't
 883                          * support). */
 884                         if (IS_HASWELL(dev) && intel_crtc->config.pch_pfit.enabled)
 885                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 886                         else
 887                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 888                         break;
 889                 case PIPE_B:
 890                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 891                         break;
 892                 case PIPE_C:
 893                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 894                         break;
 895                 default:
 896                         BUG();
 897                         break;
 898                 }
 899         }
 900
 901         if (type == INTEL_OUTPUT_HDMI) {
 902                 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 903
 904                 if (intel_hdmi->has_hdmi_sink)
 905                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 906                 else
 907                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 908
 909         } else if (type == INTEL_OUTPUT_ANALOG) {
 910                 temp |= TRANS_DDI_MODE_SELECT_FDI;
 911                 temp |= (intel_crtc->config.fdi_lanes - 1) << 1;
 912
 913         } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
 914                    type == INTEL_OUTPUT_EDP) {
 915                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 916
 917                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 918
 919                 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
 920         } else {
 921                 WARN(1, "Invalid encoder type %d for pipe %c\n",
 922                      intel_encoder->type, pipe_name(pipe));
 923         }
 924
 925         I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
 926 }
 927
 928 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
 929                                        enum transcoder cpu_transcoder)
 930 {
 931         uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
 932         uint32_t val = I915_READ(reg);
 933
 934         val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK);
 935         val |= TRANS_DDI_PORT_NONE;
 936         I915_WRITE(reg, val);
 937 }
 938
 939 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 940 {
 941         struct drm_device *dev = intel_connector->base.dev;
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         struct intel_encoder *intel_encoder = intel_connector->encoder;
 944         int type = intel_connector->base.connector_type;
 945         enum port port = intel_ddi_get_encoder_port(intel_encoder);
 946         enum pipe pipe = 0;
 947         enum transcoder cpu_transcoder;
 948         uint32_t tmp;
 949
 950         if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
 951                 return false;
 952
 953         if (port == PORT_A)
 954                 cpu_transcoder = TRANSCODER_EDP;
 955         else
 956                 cpu_transcoder = (enum transcoder) pipe;
 957
 958         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 959
 960         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 961         case TRANS_DDI_MODE_SELECT_HDMI:
 962         case TRANS_DDI_MODE_SELECT_DVI:
 963                 return (type == DRM_MODE_CONNECTOR_HDMIA);
 964
 965         case TRANS_DDI_MODE_SELECT_DP_SST:
 966                 if (type == DRM_MODE_CONNECTOR_eDP)
 967                         return true;
 968         case TRANS_DDI_MODE_SELECT_DP_MST:
 969                 return (type == DRM_MODE_CONNECTOR_DisplayPort);
 970
 971         case TRANS_DDI_MODE_SELECT_FDI:
 972                 return (type == DRM_MODE_CONNECTOR_VGA);
 973
 974         default:
 975                 return false;
 976         }
 977 }
 978
 979 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 980                             enum pipe *pipe)
 981 {
 982         struct drm_device *dev = encoder->base.dev;
 983         struct drm_i915_private *dev_priv = dev->dev_private;
 984         enum port port = intel_ddi_get_encoder_port(encoder);
 985         u32 tmp;
 986         int i;
 987
 988         tmp = I915_READ(DDI_BUF_CTL(port));
 989
 990         if (!(tmp & DDI_BUF_CTL_ENABLE))
 991                 return false;
 992
 993         if (port == PORT_A) {
 994                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 995
 996                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 997                 case TRANS_DDI_EDP_INPUT_A_ON:
 998                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 999                         *pipe = PIPE_A;
1000                         break;
1001                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1002                         *pipe = PIPE_B;
1003                         break;
1004                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1005                         *pipe = PIPE_C;
1006                         break;
1007                 }
1008
1009                 return true;
1010         } else {
1011                 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1012                         tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1013
1014                         if ((tmp & TRANS_DDI_PORT_MASK)
1015                             == TRANS_DDI_SELECT_PORT(port)) {
1016                                 *pipe = i;
1017                                 return true;
1018                         }
1019                 }
1020         }
1021
1022         DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1023
1024         return false;
1025 }
1026
1027 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv,
1028                                        enum pipe pipe)
1029 {
1030         uint32_t temp, ret;
1031         enum port port = I915_MAX_PORTS;
1032         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1033                                                                       pipe);
1034         int i;
1035
1036         if (cpu_transcoder == TRANSCODER_EDP) {
1037                 port = PORT_A;
1038         } else {
1039                 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1040                 temp &= TRANS_DDI_PORT_MASK;
1041
1042                 for (i = PORT_B; i <= PORT_E; i++)
1043                         if (temp == TRANS_DDI_SELECT_PORT(i))
1044                                 port = i;
1045         }
1046
1047         if (port == I915_MAX_PORTS) {
1048                 WARN(1, "Pipe %c enabled on an unknown port\n",
1049                      pipe_name(pipe));
1050                 ret = PORT_CLK_SEL_NONE;
1051         } else {
1052                 ret = I915_READ(PORT_CLK_SEL(port));
1053                 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock "
1054                               "0x%08x\n", pipe_name(pipe), port_name(port),
1055                               ret);
1056         }
1057
1058         return ret;
1059 }
1060
1061 void intel_ddi_setup_hw_pll_state(struct drm_device *dev)
1062 {
1063         struct drm_i915_private *dev_priv = dev->dev_private;
1064         enum pipe pipe;
1065         struct intel_crtc *intel_crtc;
1066
1067         for_each_pipe(pipe) {
1068                 intel_crtc =
1069                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1070
1071                 if (!intel_crtc->active)
1072                         continue;
1073
1074                 intel_crtc->ddi_pll_sel = intel_ddi_get_crtc_pll(dev_priv,
1075                                                                  pipe);
1076
1077                 switch (intel_crtc->ddi_pll_sel) {
1078                 case PORT_CLK_SEL_SPLL:
1079                         dev_priv->ddi_plls.spll_refcount++;
1080                         break;
1081                 case PORT_CLK_SEL_WRPLL1:
1082                         dev_priv->ddi_plls.wrpll1_refcount++;
1083                         break;
1084                 case PORT_CLK_SEL_WRPLL2:
1085                         dev_priv->ddi_plls.wrpll2_refcount++;
1086                         break;
1087                 }
1088         }
1089 }
1090
1091 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1092 {
1093         struct drm_crtc *crtc = &intel_crtc->base;
1094         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1095         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1096         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1097         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1098
1099         if (cpu_transcoder != TRANSCODER_EDP)
1100                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1101                            TRANS_CLK_SEL_PORT(port));
1102 }
1103
1104 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1105 {
1106         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1107         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1108
1109         if (cpu_transcoder != TRANSCODER_EDP)
1110                 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1111                            TRANS_CLK_SEL_DISABLED);
1112 }
1113
1114 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1115 {
1116         struct drm_encoder *encoder = &intel_encoder->base;
1117         struct drm_crtc *crtc = encoder->crtc;
1118         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1120         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1121         int type = intel_encoder->type;
1122
1123         if (type == INTEL_OUTPUT_EDP) {
1124                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1125                 ironlake_edp_panel_vdd_on(intel_dp);
1126                 ironlake_edp_panel_on(intel_dp);
1127                 ironlake_edp_panel_vdd_off(intel_dp, true);
1128         }
1129
1130         WARN_ON(intel_crtc->ddi_pll_sel == PORT_CLK_SEL_NONE);
1131         I915_WRITE(PORT_CLK_SEL(port), intel_crtc->ddi_pll_sel);
1132
1133         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1134                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1135
1136                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1137                 intel_dp_start_link_train(intel_dp);
1138                 intel_dp_complete_link_train(intel_dp);
1139                 if (port != PORT_A)
1140                         intel_dp_stop_link_train(intel_dp);
1141         }
1142 }
1143
1144 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
1145 {
1146         struct drm_encoder *encoder = &intel_encoder->base;
1147         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1148         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1149         int type = intel_encoder->type;
1150         uint32_t val;
1151         bool wait = false;
1152
1153         val = I915_READ(DDI_BUF_CTL(port));
1154         if (val & DDI_BUF_CTL_ENABLE) {
1155                 val &= ~DDI_BUF_CTL_ENABLE;
1156                 I915_WRITE(DDI_BUF_CTL(port), val);
1157                 wait = true;
1158         }
1159
1160         val = I915_READ(DP_TP_CTL(port));
1161         val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1162         val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1163         I915_WRITE(DP_TP_CTL(port), val);
1164
1165         if (wait)
1166                 intel_wait_ddi_buf_idle(dev_priv, port);
1167
1168         if (type == INTEL_OUTPUT_EDP) {
1169                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1170                 ironlake_edp_panel_vdd_on(intel_dp);
1171                 ironlake_edp_panel_off(intel_dp);
1172         }
1173
1174         I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1175 }
1176
1177 static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1178 {
1179         struct drm_encoder *encoder = &intel_encoder->base;
1180         struct drm_crtc *crtc = encoder->crtc;
1181         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1182         int pipe = intel_crtc->pipe;
1183         struct drm_device *dev = encoder->dev;
1184         struct drm_i915_private *dev_priv = dev->dev_private;
1185         enum port port = intel_ddi_get_encoder_port(intel_encoder);
1186         int type = intel_encoder->type;
1187         uint32_t tmp;
1188
1189         if (type == INTEL_OUTPUT_HDMI) {
1190                 struct intel_digital_port *intel_dig_port =
1191                         enc_to_dig_port(encoder);
1192
1193                 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1194                  * are ignored so nothing special needs to be done besides
1195                  * enabling the port.
1196                  */
1197                 I915_WRITE(DDI_BUF_CTL(port),
1198                            intel_dig_port->saved_port_bits |
1199                            DDI_BUF_CTL_ENABLE);
1200         } else if (type == INTEL_OUTPUT_EDP) {
1201                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1202
1203                 if (port == PORT_A)
1204                         intel_dp_stop_link_train(intel_dp);
1205
1206                 ironlake_edp_backlight_on(intel_dp);
1207                 intel_edp_psr_enable(intel_dp);
1208         }
1209
1210         if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1211                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1212                 tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
1213                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1214         }
1215 }
1216
1217 static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1218 {
1219         struct drm_encoder *encoder = &intel_encoder->base;
1220         struct drm_crtc *crtc = encoder->crtc;
1221         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1222         int pipe = intel_crtc->pipe;
1223         int type = intel_encoder->type;
1224         struct drm_device *dev = encoder->dev;
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         uint32_t tmp;
1227
1228         if (intel_crtc->eld_vld && type != INTEL_OUTPUT_EDP) {
1229                 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
1230                 tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) <<
1231                          (pipe * 4));
1232                 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
1233         }
1234
1235         if (type == INTEL_OUTPUT_EDP) {
1236                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1237
1238                 intel_edp_psr_disable(intel_dp);
1239                 ironlake_edp_backlight_off(intel_dp);
1240         }
1241 }
1242
1243 int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1244 {
1245         struct drm_device *dev = dev_priv->dev;
1246         uint32_t lcpll = I915_READ(LCPLL_CTL);
1247         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
1248
1249         if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1250                 return 800000;
1251         } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1252                 return 450000;
1253         } else if (freq == LCPLL_CLK_FREQ_450) {
1254                 return 450000;
1255         } else if (IS_HASWELL(dev)) {
1256                 if (IS_ULT(dev))
1257                         return 337500;
1258                 else
1259                         return 540000;
1260         } else {
1261                 if (freq == LCPLL_CLK_FREQ_54O_BDW)
1262                         return 540000;
1263                 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
1264                         return 337500;
1265                 else
1266                         return 675000;
1267         }
1268 }
1269
1270 void intel_ddi_pll_init(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273         uint32_t val = I915_READ(LCPLL_CTL);
1274
1275         /* The LCPLL register should be turned on by the BIOS. For now let's
1276          * just check its state and print errors in case something is wrong.
1277          * Don't even try to turn it on.
1278          */
1279
1280         DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
1281                       intel_ddi_get_cdclk_freq(dev_priv));
1282
1283         if (val & LCPLL_CD_SOURCE_FCLK)
1284                 DRM_ERROR("CDCLK source is not LCPLL\n");
1285
1286         if (val & LCPLL_PLL_DISABLE)
1287                 DRM_ERROR("LCPLL is disabled\n");
1288 }
1289
1290 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
1291 {
1292         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
1293         struct intel_dp *intel_dp = &intel_dig_port->dp;
1294         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
1295         enum port port = intel_dig_port->port;
1296         uint32_t val;
1297         bool wait = false;
1298
1299         if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
1300                 val = I915_READ(DDI_BUF_CTL(port));
1301                 if (val & DDI_BUF_CTL_ENABLE) {
1302                         val &= ~DDI_BUF_CTL_ENABLE;
1303                         I915_WRITE(DDI_BUF_CTL(port), val);
1304                         wait = true;
1305                 }
1306
1307                 val = I915_READ(DP_TP_CTL(port));
1308                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1309                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1310                 I915_WRITE(DP_TP_CTL(port), val);
1311                 POSTING_READ(DP_TP_CTL(port));
1312
1313                 if (wait)
1314                         intel_wait_ddi_buf_idle(dev_priv, port);
1315         }
1316
1317         val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
1318               DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1319         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1320                 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
1321         I915_WRITE(DP_TP_CTL(port), val);
1322         POSTING_READ(DP_TP_CTL(port));
1323
1324         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
1325         I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
1326         POSTING_READ(DDI_BUF_CTL(port));
1327
1328         udelay(600);
1329 }
1330
1331 void intel_ddi_fdi_disable(struct drm_crtc *crtc)
1332 {
1333         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1334         struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1335         uint32_t val;
1336
1337         intel_ddi_post_disable(intel_encoder);
1338
1339         val = I915_READ(_FDI_RXA_CTL);
1340         val &= ~FDI_RX_ENABLE;
1341         I915_WRITE(_FDI_RXA_CTL, val);
1342
1343         val = I915_READ(_FDI_RXA_MISC);
1344         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1345         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1346         I915_WRITE(_FDI_RXA_MISC, val);
1347
1348         val = I915_READ(_FDI_RXA_CTL);
1349         val &= ~FDI_PCDCLK;
1350         I915_WRITE(_FDI_RXA_CTL, val);
1351
1352         val = I915_READ(_FDI_RXA_CTL);
1353         val &= ~FDI_RX_PLL_ENABLE;
1354         I915_WRITE(_FDI_RXA_CTL, val);
1355 }
1356
1357 static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
1358 {
1359         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
1360         int type = intel_encoder->type;
1361
1362         if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP)
1363                 intel_dp_check_link_status(intel_dp);
1364 }
1365
1366 void intel_ddi_get_config(struct intel_encoder *encoder,
1367                           struct intel_crtc_config *pipe_config)
1368 {
1369         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1370         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1371         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1372         u32 temp, flags = 0;
1373
1374         temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1375         if (temp & TRANS_DDI_PHSYNC)
1376                 flags |= DRM_MODE_FLAG_PHSYNC;
1377         else
1378                 flags |= DRM_MODE_FLAG_NHSYNC;
1379         if (temp & TRANS_DDI_PVSYNC)
1380                 flags |= DRM_MODE_FLAG_PVSYNC;
1381         else
1382                 flags |= DRM_MODE_FLAG_NVSYNC;
1383
1384         pipe_config->adjusted_mode.flags |= flags;
1385
1386         switch (temp & TRANS_DDI_BPC_MASK) {
1387         case TRANS_DDI_BPC_6:
1388                 pipe_config->pipe_bpp = 18;
1389                 break;
1390         case TRANS_DDI_BPC_8:
1391                 pipe_config->pipe_bpp = 24;
1392                 break;
1393         case TRANS_DDI_BPC_10:
1394                 pipe_config->pipe_bpp = 30;
1395                 break;
1396         case TRANS_DDI_BPC_12:
1397                 pipe_config->pipe_bpp = 36;
1398                 break;
1399         default:
1400                 break;
1401         }
1402
1403         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
1404         case TRANS_DDI_MODE_SELECT_HDMI:
1405         case TRANS_DDI_MODE_SELECT_DVI:
1406         case TRANS_DDI_MODE_SELECT_FDI:
1407                 break;
1408         case TRANS_DDI_MODE_SELECT_DP_SST:
1409         case TRANS_DDI_MODE_SELECT_DP_MST:
1410                 pipe_config->has_dp_encoder = true;
1411                 intel_dp_get_m_n(intel_crtc, pipe_config);
1412                 break;
1413         default:
1414                 break;
1415         }
1416
1417         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
1418             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1419                 /*
1420                  * This is a big fat ugly hack.
1421                  *
1422                  * Some machines in UEFI boot mode provide us a VBT that has 18
1423                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1424                  * unknown we fail to light up. Yet the same BIOS boots up with
1425                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1426                  * max, not what it tells us to use.
1427                  *
1428                  * Note: This will still be broken if the eDP panel is not lit
1429                  * up by the BIOS, and thus we can't get the mode at module
1430                  * load.
1431                  */
1432                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1433                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1434                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1435         }
1436 }
1437
1438 static void intel_ddi_destroy(struct drm_encoder *encoder)
1439 {
1440         /* HDMI has nothing special to destroy, so we can go with this. */
1441         intel_dp_encoder_destroy(encoder);
1442 }
1443
1444 static bool intel_ddi_compute_config(struct intel_encoder *encoder,
1445                                      struct intel_crtc_config *pipe_config)
1446 {
1447         int type = encoder->type;
1448         int port = intel_ddi_get_encoder_port(encoder);
1449
1450         WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
1451
1452         if (port == PORT_A)
1453                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
1454
1455         if (type == INTEL_OUTPUT_HDMI)
1456                 return intel_hdmi_compute_config(encoder, pipe_config);
1457         else
1458                 return intel_dp_compute_config(encoder, pipe_config);
1459 }
1460
1461 static const struct drm_encoder_funcs intel_ddi_funcs = {
1462         .destroy = intel_ddi_destroy,
1463 };
1464
1465 static struct intel_connector *
1466 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
1467 {
1468         struct intel_connector *connector;
1469         enum port port = intel_dig_port->port;
1470
1471         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1472         if (!connector)
1473                 return NULL;
1474
1475         intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
1476         if (!intel_dp_init_connector(intel_dig_port, connector)) {
1477                 kfree(connector);
1478                 return NULL;
1479         }
1480
1481         return connector;
1482 }
1483
1484 static struct intel_connector *
1485 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
1486 {
1487         struct intel_connector *connector;
1488         enum port port = intel_dig_port->port;
1489
1490         connector = kzalloc(sizeof(*connector), GFP_KERNEL);
1491         if (!connector)
1492                 return NULL;
1493
1494         intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
1495         intel_hdmi_init_connector(intel_dig_port, connector);
1496
1497         return connector;
1498 }
1499
1500 void intel_ddi_init(struct drm_device *dev, enum port port)
1501 {
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503         struct intel_digital_port *intel_dig_port;
1504         struct intel_encoder *intel_encoder;
1505         struct drm_encoder *encoder;
1506         struct intel_connector *hdmi_connector = NULL;
1507         struct intel_connector *dp_connector = NULL;
1508         bool init_hdmi, init_dp;
1509
1510         init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
1511                      dev_priv->vbt.ddi_port_info[port].supports_hdmi);
1512         init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
1513         if (!init_dp && !init_hdmi) {
1514                 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n",
1515                               port_name(port));
1516                 init_hdmi = true;
1517                 init_dp = true;
1518         }
1519
1520         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1521         if (!intel_dig_port)
1522                 return;
1523
1524         intel_encoder = &intel_dig_port->base;
1525         encoder = &intel_encoder->base;
1526
1527         drm_encoder_init(dev, encoder, &intel_ddi_funcs,
1528                          DRM_MODE_ENCODER_TMDS);
1529
1530         intel_encoder->compute_config = intel_ddi_compute_config;
1531         intel_encoder->mode_set = intel_ddi_mode_set;
1532         intel_encoder->enable = intel_enable_ddi;
1533         intel_encoder->pre_enable = intel_ddi_pre_enable;
1534         intel_encoder->disable = intel_disable_ddi;
1535         intel_encoder->post_disable = intel_ddi_post_disable;
1536         intel_encoder->get_hw_state = intel_ddi_get_hw_state;
1537         intel_encoder->get_config = intel_ddi_get_config;
1538
1539         intel_dig_port->port = port;
1540         intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
1541                                           (DDI_BUF_PORT_REVERSAL |
1542                                            DDI_A_4_LANES);
1543
1544         intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
1545         intel_encoder->crtc_mask =  (1 << 0) | (1 << 1) | (1 << 2);
1546         intel_encoder->cloneable = false;
1547         intel_encoder->hot_plug = intel_ddi_hot_plug;
1548
1549         if (init_dp)
1550                 dp_connector = intel_ddi_init_dp_connector(intel_dig_port);
1551
1552         /* In theory we don't need the encoder->type check, but leave it just in
1553          * case we have some really bad VBTs... */
1554         if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi)
1555                 hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port);
1556
1557         if (!dp_connector && !hdmi_connector) {
1558                 drm_encoder_cleanup(encoder);
1559                 kfree(intel_dig_port);
1560         }
1561 }