Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <drm/drmP.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include <drm/drm_crtc_helper.h>
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 1;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
  54                 "-1=force lid closed, -2=force lid open)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6. "
  70                 "Different stages can be selected via bitmask values "
  71                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
  72                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
  73                 "default: -1 (use per-chip default)");
  74
  75 int i915_enable_fbc __read_mostly = -1;
  76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  77 MODULE_PARM_DESC(i915_enable_fbc,
  78                 "Enable frame buffer compression for power savings "
  79                 "(default: -1 (use per-chip default))");
  80
  81 unsigned int i915_lvds_downclock __read_mostly = 0;
  82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  83 MODULE_PARM_DESC(lvds_downclock,
  84                 "Use panel (LVDS/eDP) downclocking for power savings "
  85                 "(default: false)");
  86
  87 int i915_lvds_channel_mode __read_mostly;
  88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  89 MODULE_PARM_DESC(lvds_channel_mode,
  90                  "Specify LVDS channel mode "
  91                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  92
  93 int i915_panel_use_ssc __read_mostly = -1;
  94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  95 MODULE_PARM_DESC(lvds_use_ssc,
  96                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  97                 "(default: auto from VBT)");
  98
  99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
 100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
 101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
 102                 "Override/Ignore selection of SDVO panel mode in the VBT "
 103                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 104
 105 static bool i915_try_reset __read_mostly = true;
 106 module_param_named(reset, i915_try_reset, bool, 0600);
 107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 108
 109 bool i915_enable_hangcheck __read_mostly = true;
 110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 111 MODULE_PARM_DESC(enable_hangcheck,
 112                 "Periodically check GPU activity for detecting hangs. "
 113                 "WARNING: Disabling this can cause system wide hangs. "
 114                 "(default: true)");
 115
 116 int i915_enable_ppgtt __read_mostly = -1;
 117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
 118 MODULE_PARM_DESC(i915_enable_ppgtt,
 119                 "Enable PPGTT (default: true)");
 120
 121 int i915_enable_psr __read_mostly = 0;
 122 module_param_named(enable_psr, i915_enable_psr, int, 0600);
 123 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
 124
 125 unsigned int i915_preliminary_hw_support __read_mostly = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT);
 126 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
 127 MODULE_PARM_DESC(preliminary_hw_support,
 128                 "Enable preliminary hardware support.");
 129
 130 int i915_disable_power_well __read_mostly = 1;
 131 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
 132 MODULE_PARM_DESC(disable_power_well,
 133                  "Disable the power well when possible (default: true)");
 134
 135 int i915_enable_ips __read_mostly = 1;
 136 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 137 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 138
 139 bool i915_fastboot __read_mostly = 0;
 140 module_param_named(fastboot, i915_fastboot, bool, 0600);
 141 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
 142                  "(default: false)");
 143
 144 int i915_enable_pc8 __read_mostly = 1;
 145 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
 146 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
 147
 148 int i915_pc8_timeout __read_mostly = 5000;
 149 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
 150 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
 151
 152 bool i915_prefault_disable __read_mostly;
 153 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
 154 MODULE_PARM_DESC(prefault_disable,
 155                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
 156
 157 static struct drm_driver driver;
 158 extern int intel_agp_enabled;
 159
 160 static const struct intel_device_info intel_i830_info = {
 161         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163 };
 164
 165 static const struct intel_device_info intel_845g_info = {
 166         .gen = 2, .num_pipes = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168 };
 169
 170 static const struct intel_device_info intel_i85x_info = {
 171         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
 172         .cursor_needs_physical = 1,
 173         .has_overlay = 1, .overlay_needs_physical = 1,
 174 };
 175
 176 static const struct intel_device_info intel_i865g_info = {
 177         .gen = 2, .num_pipes = 1,
 178         .has_overlay = 1, .overlay_needs_physical = 1,
 179 };
 180
 181 static const struct intel_device_info intel_i915g_info = {
 182         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 183         .has_overlay = 1, .overlay_needs_physical = 1,
 184 };
 185 static const struct intel_device_info intel_i915gm_info = {
 186         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 187         .cursor_needs_physical = 1,
 188         .has_overlay = 1, .overlay_needs_physical = 1,
 189         .supports_tv = 1,
 190 };
 191 static const struct intel_device_info intel_i945g_info = {
 192         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 193         .has_overlay = 1, .overlay_needs_physical = 1,
 194 };
 195 static const struct intel_device_info intel_i945gm_info = {
 196         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 197         .has_hotplug = 1, .cursor_needs_physical = 1,
 198         .has_overlay = 1, .overlay_needs_physical = 1,
 199         .supports_tv = 1,
 200 };
 201
 202 static const struct intel_device_info intel_i965g_info = {
 203         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 204         .has_hotplug = 1,
 205         .has_overlay = 1,
 206 };
 207
 208 static const struct intel_device_info intel_i965gm_info = {
 209         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 210         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 211         .has_overlay = 1,
 212         .supports_tv = 1,
 213 };
 214
 215 static const struct intel_device_info intel_g33_info = {
 216         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 217         .need_gfx_hws = 1, .has_hotplug = 1,
 218         .has_overlay = 1,
 219 };
 220
 221 static const struct intel_device_info intel_g45_info = {
 222         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 223         .has_pipe_cxsr = 1, .has_hotplug = 1,
 224         .has_bsd_ring = 1,
 225 };
 226
 227 static const struct intel_device_info intel_gm45_info = {
 228         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 229         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 230         .has_pipe_cxsr = 1, .has_hotplug = 1,
 231         .supports_tv = 1,
 232         .has_bsd_ring = 1,
 233 };
 234
 235 static const struct intel_device_info intel_pineview_info = {
 236         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 237         .need_gfx_hws = 1, .has_hotplug = 1,
 238         .has_overlay = 1,
 239 };
 240
 241 static const struct intel_device_info intel_ironlake_d_info = {
 242         .gen = 5, .num_pipes = 2,
 243         .need_gfx_hws = 1, .has_hotplug = 1,
 244         .has_bsd_ring = 1,
 245 };
 246
 247 static const struct intel_device_info intel_ironlake_m_info = {
 248         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 249         .need_gfx_hws = 1, .has_hotplug = 1,
 250         .has_fbc = 1,
 251         .has_bsd_ring = 1,
 252 };
 253
 254 static const struct intel_device_info intel_sandybridge_d_info = {
 255         .gen = 6, .num_pipes = 2,
 256         .need_gfx_hws = 1, .has_hotplug = 1,
 257         .has_bsd_ring = 1,
 258         .has_blt_ring = 1,
 259         .has_llc = 1,
 260         .has_force_wake = 1,
 261 };
 262
 263 static const struct intel_device_info intel_sandybridge_m_info = {
 264         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 265         .need_gfx_hws = 1, .has_hotplug = 1,
 266         .has_fbc = 1,
 267         .has_bsd_ring = 1,
 268         .has_blt_ring = 1,
 269         .has_llc = 1,
 270         .has_force_wake = 1,
 271 };
 272
 273 #define GEN7_FEATURES  \
 274         .gen = 7, .num_pipes = 3, \
 275         .need_gfx_hws = 1, .has_hotplug = 1, \
 276         .has_bsd_ring = 1, \
 277         .has_blt_ring = 1, \
 278         .has_llc = 1, \
 279         .has_force_wake = 1
 280
 281 static const struct intel_device_info intel_ivybridge_d_info = {
 282         GEN7_FEATURES,
 283         .is_ivybridge = 1,
 284 };
 285
 286 static const struct intel_device_info intel_ivybridge_m_info = {
 287         GEN7_FEATURES,
 288         .is_ivybridge = 1,
 289         .is_mobile = 1,
 290         .has_fbc = 1,
 291 };
 292
 293 static const struct intel_device_info intel_ivybridge_q_info = {
 294         GEN7_FEATURES,
 295         .is_ivybridge = 1,
 296         .num_pipes = 0, /* legal, last one wins */
 297 };
 298
 299 static const struct intel_device_info intel_valleyview_m_info = {
 300         GEN7_FEATURES,
 301         .is_mobile = 1,
 302         .num_pipes = 2,
 303         .is_valleyview = 1,
 304         .display_mmio_offset = VLV_DISPLAY_BASE,
 305         .has_llc = 0, /* legal, last one wins */
 306 };
 307
 308 static const struct intel_device_info intel_valleyview_d_info = {
 309         GEN7_FEATURES,
 310         .num_pipes = 2,
 311         .is_valleyview = 1,
 312         .display_mmio_offset = VLV_DISPLAY_BASE,
 313         .has_llc = 0, /* legal, last one wins */
 314 };
 315
 316 static const struct intel_device_info intel_haswell_d_info = {
 317         GEN7_FEATURES,
 318         .is_haswell = 1,
 319         .has_ddi = 1,
 320         .has_fpga_dbg = 1,
 321         .has_vebox_ring = 1,
 322 };
 323
 324 static const struct intel_device_info intel_haswell_m_info = {
 325         GEN7_FEATURES,
 326         .is_haswell = 1,
 327         .is_mobile = 1,
 328         .has_ddi = 1,
 329         .has_fpga_dbg = 1,
 330         .has_fbc = 1,
 331         .has_vebox_ring = 1,
 332 };
 333
 334 /*
 335  * Make sure any device matches here are from most specific to most
 336  * general.  For example, since the Quanta match is based on the subsystem
 337  * and subvendor IDs, we need it to come before the more general IVB
 338  * PCI ID matches, otherwise we'll use the wrong info struct above.
 339  */
 340 #define INTEL_PCI_IDS \
 341         INTEL_I830_IDS(&intel_i830_info),       \
 342         INTEL_I845G_IDS(&intel_845g_info),      \
 343         INTEL_I85X_IDS(&intel_i85x_info),       \
 344         INTEL_I865G_IDS(&intel_i865g_info),     \
 345         INTEL_I915G_IDS(&intel_i915g_info),     \
 346         INTEL_I915GM_IDS(&intel_i915gm_info),   \
 347         INTEL_I945G_IDS(&intel_i945g_info),     \
 348         INTEL_I945GM_IDS(&intel_i945gm_info),   \
 349         INTEL_I965G_IDS(&intel_i965g_info),     \
 350         INTEL_G33_IDS(&intel_g33_info),         \
 351         INTEL_I965GM_IDS(&intel_i965gm_info),   \
 352         INTEL_GM45_IDS(&intel_gm45_info),       \
 353         INTEL_G45_IDS(&intel_g45_info),         \
 354         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
 355         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
 356         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
 357         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
 358         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
 359         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
 360         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
 361         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
 362         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
 363         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
 364         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
 365         INTEL_VLV_D_IDS(&intel_valleyview_d_info)
 366
 367 static const struct pci_device_id pciidlist[] = {               /* aka */
 368         INTEL_PCI_IDS,
 369         {0, 0, 0}
 370 };
 371
 372 #if defined(CONFIG_DRM_I915_KMS)
 373 MODULE_DEVICE_TABLE(pci, pciidlist);
 374 #endif
 375
 376 void intel_detect_pch(struct drm_device *dev)
 377 {
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         struct pci_dev *pch;
 380
 381         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 382          * (which really amounts to a PCH but no South Display).
 383          */
 384         if (INTEL_INFO(dev)->num_pipes == 0) {
 385                 dev_priv->pch_type = PCH_NOP;
 386                 return;
 387         }
 388
 389         /*
 390          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 391          * make graphics device passthrough work easy for VMM, that only
 392          * need to expose ISA bridge to let driver know the real hardware
 393          * underneath. This is a requirement from virtualization team.
 394          *
 395          * In some virtualized environments (e.g. XEN), there is irrelevant
 396          * ISA bridge in the system. To work reliably, we should scan trhough
 397          * all the ISA bridge devices and check for the first match, instead
 398          * of only checking the first one.
 399          */
 400         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 401         while (pch) {
 402                 struct pci_dev *curr = pch;
 403                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 404                         unsigned short id;
 405                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 406                         dev_priv->pch_id = id;
 407
 408                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 409                                 dev_priv->pch_type = PCH_IBX;
 410                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 411                                 WARN_ON(!IS_GEN5(dev));
 412                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 413                                 dev_priv->pch_type = PCH_CPT;
 414                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 415                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 416                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 417                                 /* PantherPoint is CPT compatible */
 418                                 dev_priv->pch_type = PCH_CPT;
 419                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 420                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 421                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 422                                 dev_priv->pch_type = PCH_LPT;
 423                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 424                                 WARN_ON(!IS_HASWELL(dev));
 425                                 WARN_ON(IS_ULT(dev));
 426                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 427                                 dev_priv->pch_type = PCH_LPT;
 428                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 429                                 WARN_ON(!IS_HASWELL(dev));
 430                                 WARN_ON(!IS_ULT(dev));
 431                         } else {
 432                                 goto check_next;
 433                         }
 434                         pci_dev_put(pch);
 435                         break;
 436                 }
 437 check_next:
 438                 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, curr);
 439                 pci_dev_put(curr);
 440         }
 441         if (!pch)
 442                 DRM_DEBUG_KMS("No PCH found?\n");
 443 }
 444
 445 bool i915_semaphore_is_enabled(struct drm_device *dev)
 446 {
 447         if (INTEL_INFO(dev)->gen < 6)
 448                 return 0;
 449
 450         if (i915_semaphores >= 0)
 451                 return i915_semaphores;
 452
 453 #ifdef CONFIG_INTEL_IOMMU
 454         /* Enable semaphores on SNB when IO remapping is off */
 455         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 456                 return false;
 457 #endif
 458
 459         return 1;
 460 }
 461
 462 static int i915_drm_freeze(struct drm_device *dev)
 463 {
 464         struct drm_i915_private *dev_priv = dev->dev_private;
 465         struct drm_crtc *crtc;
 466
 467         /* ignore lid events during suspend */
 468         mutex_lock(&dev_priv->modeset_restore_lock);
 469         dev_priv->modeset_restore = MODESET_SUSPENDED;
 470         mutex_unlock(&dev_priv->modeset_restore_lock);
 471
 472         /* We do a lot of poking in a lot of registers, make sure they work
 473          * properly. */
 474         hsw_disable_package_c8(dev_priv);
 475         intel_set_power_well(dev, true);
 476
 477         drm_kms_helper_poll_disable(dev);
 478
 479         pci_save_state(dev->pdev);
 480
 481         /* If KMS is active, we do the leavevt stuff here */
 482         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 483                 int error;
 484
 485                 mutex_lock(&dev->struct_mutex);
 486                 error = i915_gem_idle(dev);
 487                 mutex_unlock(&dev->struct_mutex);
 488                 if (error) {
 489                         dev_err(&dev->pdev->dev,
 490                                 "GEM idle failed, resume might fail\n");
 491                         return error;
 492                 }
 493
 494                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 495
 496                 drm_irq_uninstall(dev);
 497                 dev_priv->enable_hotplug_processing = false;
 498                 /*
 499                  * Disable CRTCs directly since we want to preserve sw state
 500                  * for _thaw.
 501                  */
 502                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 503                         dev_priv->display.crtc_disable(crtc);
 504
 505                 intel_modeset_suspend_hw(dev);
 506         }
 507
 508         i915_gem_suspend_gtt_mappings(dev);
 509
 510         i915_save_state(dev);
 511
 512         intel_opregion_fini(dev);
 513
 514         console_lock();
 515         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
 516         console_unlock();
 517
 518         return 0;
 519 }
 520
 521 int i915_suspend(struct drm_device *dev, pm_message_t state)
 522 {
 523         int error;
 524
 525         if (!dev || !dev->dev_private) {
 526                 DRM_ERROR("dev: %p\n", dev);
 527                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 528                 return -ENODEV;
 529         }
 530
 531         if (state.event == PM_EVENT_PRETHAW)
 532                 return 0;
 533
 534
 535         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 536                 return 0;
 537
 538         error = i915_drm_freeze(dev);
 539         if (error)
 540                 return error;
 541
 542         if (state.event == PM_EVENT_SUSPEND) {
 543                 /* Shut down the device */
 544                 pci_disable_device(dev->pdev);
 545                 pci_set_power_state(dev->pdev, PCI_D3hot);
 546         }
 547
 548         return 0;
 549 }
 550
 551 void intel_console_resume(struct work_struct *work)
 552 {
 553         struct drm_i915_private *dev_priv =
 554                 container_of(work, struct drm_i915_private,
 555                              console_resume_work);
 556         struct drm_device *dev = dev_priv->dev;
 557
 558         console_lock();
 559         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 560         console_unlock();
 561 }
 562
 563 static void intel_resume_hotplug(struct drm_device *dev)
 564 {
 565         struct drm_mode_config *mode_config = &dev->mode_config;
 566         struct intel_encoder *encoder;
 567
 568         mutex_lock(&mode_config->mutex);
 569         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 570
 571         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 572                 if (encoder->hot_plug)
 573                         encoder->hot_plug(encoder);
 574
 575         mutex_unlock(&mode_config->mutex);
 576
 577         /* Just fire off a uevent and let userspace tell us what to do */
 578         drm_helper_hpd_irq_event(dev);
 579 }
 580
 581 static int __i915_drm_thaw(struct drm_device *dev)
 582 {
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         int error = 0;
 585
 586         i915_restore_state(dev);
 587         intel_opregion_setup(dev);
 588
 589         /* KMS EnterVT equivalent */
 590         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 591                 intel_init_pch_refclk(dev);
 592
 593                 mutex_lock(&dev->struct_mutex);
 594
 595                 error = i915_gem_init_hw(dev);
 596                 mutex_unlock(&dev->struct_mutex);
 597
 598                 /* We need working interrupts for modeset enabling ... */
 599                 drm_irq_install(dev);
 600
 601                 intel_modeset_init_hw(dev);
 602
 603                 drm_modeset_lock_all(dev);
 604                 intel_modeset_setup_hw_state(dev, true);
 605                 drm_modeset_unlock_all(dev);
 606
 607                 /*
 608                  * ... but also need to make sure that hotplug processing
 609                  * doesn't cause havoc. Like in the driver load code we don't
 610                  * bother with the tiny race here where we might loose hotplug
 611                  * notifications.
 612                  * */
 613                 intel_hpd_init(dev);
 614                 dev_priv->enable_hotplug_processing = true;
 615                 /* Config may have changed between suspend and resume */
 616                 intel_resume_hotplug(dev);
 617         }
 618
 619         intel_opregion_init(dev);
 620
 621         /*
 622          * The console lock can be pretty contented on resume due
 623          * to all the printk activity.  Try to keep it out of the hot
 624          * path of resume if possible.
 625          */
 626         if (console_trylock()) {
 627                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
 628                 console_unlock();
 629         } else {
 630                 schedule_work(&dev_priv->console_resume_work);
 631         }
 632
 633         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
 634          * expected level. */
 635         hsw_enable_package_c8(dev_priv);
 636
 637         mutex_lock(&dev_priv->modeset_restore_lock);
 638         dev_priv->modeset_restore = MODESET_DONE;
 639         mutex_unlock(&dev_priv->modeset_restore_lock);
 640         return error;
 641 }
 642
 643 static int i915_drm_thaw(struct drm_device *dev)
 644 {
 645         int error = 0;
 646
 647         intel_uncore_sanitize(dev);
 648
 649         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 650                 mutex_lock(&dev->struct_mutex);
 651                 i915_gem_restore_gtt_mappings(dev);
 652                 mutex_unlock(&dev->struct_mutex);
 653         } else if (drm_core_check_feature(dev, DRIVER_MODESET))
 654                 i915_check_and_clear_faults(dev);
 655
 656         __i915_drm_thaw(dev);
 657
 658         return error;
 659 }
 660
 661 int i915_resume(struct drm_device *dev)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         int ret;
 665
 666         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 667                 return 0;
 668
 669         if (pci_enable_device(dev->pdev))
 670                 return -EIO;
 671
 672         pci_set_master(dev->pdev);
 673
 674         intel_uncore_sanitize(dev);
 675
 676         /*
 677          * Platforms with opregion should have sane BIOS, older ones (gen3 and
 678          * earlier) need this since the BIOS might clear all our scratch PTEs.
 679          */
 680         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
 681             !dev_priv->opregion.header) {
 682                 mutex_lock(&dev->struct_mutex);
 683                 i915_gem_restore_gtt_mappings(dev);
 684                 mutex_unlock(&dev->struct_mutex);
 685         }
 686
 687         ret = __i915_drm_thaw(dev);
 688         if (ret)
 689                 return ret;
 690
 691         drm_kms_helper_poll_enable(dev);
 692         return 0;
 693 }
 694
 695 /**
 696  * i915_reset - reset chip after a hang
 697  * @dev: drm device to reset
 698  *
 699  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 700  * reset or otherwise an error code.
 701  *
 702  * Procedure is fairly simple:
 703  *   - reset the chip using the reset reg
 704  *   - re-init context state
 705  *   - re-init hardware status page
 706  *   - re-init ring buffer
 707  *   - re-init interrupt state
 708  *   - re-init display
 709  */
 710 int i915_reset(struct drm_device *dev)
 711 {
 712         drm_i915_private_t *dev_priv = dev->dev_private;
 713         bool simulated;
 714         int ret;
 715
 716         if (!i915_try_reset)
 717                 return 0;
 718
 719         mutex_lock(&dev->struct_mutex);
 720
 721         i915_gem_reset(dev);
 722
 723         simulated = dev_priv->gpu_error.stop_rings != 0;
 724
 725         if (!simulated && get_seconds() - dev_priv->gpu_error.last_reset < 5) {
 726                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 727                 ret = -ENODEV;
 728         } else {
 729                 ret = intel_gpu_reset(dev);
 730
 731                 /* Also reset the gpu hangman. */
 732                 if (simulated) {
 733                         DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 734                         dev_priv->gpu_error.stop_rings = 0;
 735                         if (ret == -ENODEV) {
 736                                 DRM_ERROR("Reset not implemented, but ignoring "
 737                                           "error for simulated gpu hangs\n");
 738                                 ret = 0;
 739                         }
 740                 } else
 741                         dev_priv->gpu_error.last_reset = get_seconds();
 742         }
 743         if (ret) {
 744                 DRM_ERROR("Failed to reset chip.\n");
 745                 mutex_unlock(&dev->struct_mutex);
 746                 return ret;
 747         }
 748
 749         /* Ok, now get things going again... */
 750
 751         /*
 752          * Everything depends on having the GTT running, so we need to start
 753          * there.  Fortunately we don't need to do this unless we reset the
 754          * chip at a PCI level.
 755          *
 756          * Next we need to restore the context, but we don't use those
 757          * yet either...
 758          *
 759          * Ring buffer needs to be re-initialized in the KMS case, or if X
 760          * was running at the time of the reset (i.e. we weren't VT
 761          * switched away).
 762          */
 763         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 764                         !dev_priv->ums.mm_suspended) {
 765                 struct intel_ring_buffer *ring;
 766                 int i;
 767
 768                 dev_priv->ums.mm_suspended = 0;
 769
 770                 i915_gem_init_swizzling(dev);
 771
 772                 for_each_ring(ring, dev_priv, i)
 773                         ring->init(ring);
 774
 775                 i915_gem_context_init(dev);
 776                 if (dev_priv->mm.aliasing_ppgtt) {
 777                         ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
 778                         if (ret)
 779                                 i915_gem_cleanup_aliasing_ppgtt(dev);
 780                 }
 781
 782                 /*
 783                  * It would make sense to re-init all the other hw state, at
 784                  * least the rps/rc6/emon init done within modeset_init_hw. For
 785                  * some unknown reason, this blows up my ilk, so don't.
 786                  */
 787
 788                 mutex_unlock(&dev->struct_mutex);
 789
 790                 drm_irq_uninstall(dev);
 791                 drm_irq_install(dev);
 792                 intel_hpd_init(dev);
 793         } else {
 794                 mutex_unlock(&dev->struct_mutex);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 801 {
 802         struct intel_device_info *intel_info =
 803                 (struct intel_device_info *) ent->driver_data;
 804
 805         /* Only bind to function 0 of the device. Early generations
 806          * used function 1 as a placeholder for multi-head. This causes
 807          * us confusion instead, especially on the systems where both
 808          * functions have the same PCI-ID!
 809          */
 810         if (PCI_FUNC(pdev->devfn))
 811                 return -ENODEV;
 812
 813         /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
 814          * implementation for gen3 (and only gen3) that used legacy drm maps
 815          * (gasp!) to share buffers between X and the client. Hence we need to
 816          * keep around the fake agp stuff for gen3, even when kms is enabled. */
 817         if (intel_info->gen != 3) {
 818                 driver.driver_features &=
 819                         ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
 820         } else if (!intel_agp_enabled) {
 821                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 822                 return -ENODEV;
 823         }
 824
 825         return drm_get_pci_dev(pdev, ent, &driver);
 826 }
 827
 828 static void
 829 i915_pci_remove(struct pci_dev *pdev)
 830 {
 831         struct drm_device *dev = pci_get_drvdata(pdev);
 832
 833         drm_put_dev(dev);
 834 }
 835
 836 static int i915_pm_suspend(struct device *dev)
 837 {
 838         struct pci_dev *pdev = to_pci_dev(dev);
 839         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 840         int error;
 841
 842         if (!drm_dev || !drm_dev->dev_private) {
 843                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 844                 return -ENODEV;
 845         }
 846
 847         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 848                 return 0;
 849
 850         error = i915_drm_freeze(drm_dev);
 851         if (error)
 852                 return error;
 853
 854         pci_disable_device(pdev);
 855         pci_set_power_state(pdev, PCI_D3hot);
 856
 857         return 0;
 858 }
 859
 860 static int i915_pm_resume(struct device *dev)
 861 {
 862         struct pci_dev *pdev = to_pci_dev(dev);
 863         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 864
 865         return i915_resume(drm_dev);
 866 }
 867
 868 static int i915_pm_freeze(struct device *dev)
 869 {
 870         struct pci_dev *pdev = to_pci_dev(dev);
 871         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 872
 873         if (!drm_dev || !drm_dev->dev_private) {
 874                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 875                 return -ENODEV;
 876         }
 877
 878         return i915_drm_freeze(drm_dev);
 879 }
 880
 881 static int i915_pm_thaw(struct device *dev)
 882 {
 883         struct pci_dev *pdev = to_pci_dev(dev);
 884         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 885
 886         return i915_drm_thaw(drm_dev);
 887 }
 888
 889 static int i915_pm_poweroff(struct device *dev)
 890 {
 891         struct pci_dev *pdev = to_pci_dev(dev);
 892         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 893
 894         return i915_drm_freeze(drm_dev);
 895 }
 896
 897 static const struct dev_pm_ops i915_pm_ops = {
 898         .suspend = i915_pm_suspend,
 899         .resume = i915_pm_resume,
 900         .freeze = i915_pm_freeze,
 901         .thaw = i915_pm_thaw,
 902         .poweroff = i915_pm_poweroff,
 903         .restore = i915_pm_resume,
 904 };
 905
 906 static const struct vm_operations_struct i915_gem_vm_ops = {
 907         .fault = i915_gem_fault,
 908         .open = drm_gem_vm_open,
 909         .close = drm_gem_vm_close,
 910 };
 911
 912 static const struct file_operations i915_driver_fops = {
 913         .owner = THIS_MODULE,
 914         .open = drm_open,
 915         .release = drm_release,
 916         .unlocked_ioctl = drm_ioctl,
 917         .mmap = drm_gem_mmap,
 918         .poll = drm_poll,
 919         .read = drm_read,
 920 #ifdef CONFIG_COMPAT
 921         .compat_ioctl = i915_compat_ioctl,
 922 #endif
 923         .llseek = noop_llseek,
 924 };
 925
 926 static struct drm_driver driver = {
 927         /* Don't use MTRRs here; the Xserver or userspace app should
 928          * deal with them for Intel hardware.
 929          */
 930         .driver_features =
 931             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 932             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
 933             DRIVER_RENDER,
 934         .load = i915_driver_load,
 935         .unload = i915_driver_unload,
 936         .open = i915_driver_open,
 937         .lastclose = i915_driver_lastclose,
 938         .preclose = i915_driver_preclose,
 939         .postclose = i915_driver_postclose,
 940
 941         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 942         .suspend = i915_suspend,
 943         .resume = i915_resume,
 944
 945         .device_is_agp = i915_driver_device_is_agp,
 946         .master_create = i915_master_create,
 947         .master_destroy = i915_master_destroy,
 948 #if defined(CONFIG_DEBUG_FS)
 949         .debugfs_init = i915_debugfs_init,
 950         .debugfs_cleanup = i915_debugfs_cleanup,
 951 #endif
 952         .gem_init_object = i915_gem_init_object,
 953         .gem_free_object = i915_gem_free_object,
 954         .gem_vm_ops = &i915_gem_vm_ops,
 955
 956         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 957         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 958         .gem_prime_export = i915_gem_prime_export,
 959         .gem_prime_import = i915_gem_prime_import,
 960
 961         .dumb_create = i915_gem_dumb_create,
 962         .dumb_map_offset = i915_gem_mmap_gtt,
 963         .dumb_destroy = drm_gem_dumb_destroy,
 964         .ioctls = i915_ioctls,
 965         .fops = &i915_driver_fops,
 966         .name = DRIVER_NAME,
 967         .desc = DRIVER_DESC,
 968         .date = DRIVER_DATE,
 969         .major = DRIVER_MAJOR,
 970         .minor = DRIVER_MINOR,
 971         .patchlevel = DRIVER_PATCHLEVEL,
 972 };
 973
 974 static struct pci_driver i915_pci_driver = {
 975         .name = DRIVER_NAME,
 976         .id_table = pciidlist,
 977         .probe = i915_pci_probe,
 978         .remove = i915_pci_remove,
 979         .driver.pm = &i915_pm_ops,
 980 };
 981
 982 static int __init i915_init(void)
 983 {
 984         driver.num_ioctls = i915_max_ioctl;
 985
 986         /*
 987          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 988          * explicitly disabled with the module pararmeter.
 989          *
 990          * Otherwise, just follow the parameter (defaulting to off).
 991          *
 992          * Allow optional vga_text_mode_force boot option to override
 993          * the default behavior.
 994          */
 995 #if defined(CONFIG_DRM_I915_KMS)
 996         if (i915_modeset != 0)
 997                 driver.driver_features |= DRIVER_MODESET;
 998 #endif
 999         if (i915_modeset == 1)
1000                 driver.driver_features |= DRIVER_MODESET;
1001
1002 #ifdef CONFIG_VGA_CONSOLE
1003         if (vgacon_text_force() && i915_modeset == -1)
1004                 driver.driver_features &= ~DRIVER_MODESET;
1005 #endif
1006
1007         if (!(driver.driver_features & DRIVER_MODESET))
1008                 driver.get_vblank_timestamp = NULL;
1009
1010         return drm_pci_init(&driver, &i915_pci_driver);
1011 }
1012
1013 static void __exit i915_exit(void)
1014 {
1015         drm_pci_exit(&driver, &i915_pci_driver);
1016 }
1017
1018 module_init(i915_init);
1019 module_exit(i915_exit);
1020
1021 MODULE_AUTHOR(DRIVER_AUTHOR);
1022 MODULE_DESCRIPTION(DRIVER_DESC);
1023 MODULE_LICENSE("GPL and additional rights");