Pileus Git - ~andy/linux/blob - drivers/cpufreq/cpufreq-cpu0.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * The OPP code in function cpu0_set_target() is reused from
   5  * drivers/cpufreq/omap-cpufreq.c
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/clk.h>
  15 #include <linux/cpufreq.h>
  16 #include <linux/err.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/opp.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/slab.h>
  23
  24 static unsigned int transition_latency;
  25 static unsigned int voltage_tolerance; /* in percentage */
  26
  27 static struct device *cpu_dev;
  28 static struct clk *cpu_clk;
  29 static struct regulator *cpu_reg;
  30 static struct cpufreq_frequency_table *freq_table;
  31
  32 static int cpu0_verify_speed(struct cpufreq_policy *policy)
  33 {
  34         return cpufreq_frequency_table_verify(policy, freq_table);
  35 }
  36
  37 static unsigned int cpu0_get_speed(unsigned int cpu)
  38 {
  39         return clk_get_rate(cpu_clk) / 1000;
  40 }
  41
  42 static int cpu0_set_target(struct cpufreq_policy *policy,
  43                            unsigned int target_freq, unsigned int relation)
  44 {
  45         struct cpufreq_freqs freqs;
  46         struct opp *opp;
  47         unsigned long volt = 0, volt_old = 0, tol = 0;
  48         long freq_Hz;
  49         unsigned int index;
  50         int ret;
  51
  52         ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
  53                                              relation, &index);
  54         if (ret) {
  55                 pr_err("failed to match target freqency %d: %d\n",
  56                        target_freq, ret);
  57                 return ret;
  58         }
  59
  60         freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
  61         if (freq_Hz < 0)
  62                 freq_Hz = freq_table[index].frequency * 1000;
  63         freqs.new = freq_Hz / 1000;
  64         freqs.old = clk_get_rate(cpu_clk) / 1000;
  65
  66         if (freqs.old == freqs.new)
  67                 return 0;
  68
  69         cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
  70
  71         if (cpu_reg) {
  72                 rcu_read_lock();
  73                 opp = opp_find_freq_ceil(cpu_dev, &freq_Hz);
  74                 if (IS_ERR(opp)) {
  75                         rcu_read_unlock();
  76                         pr_err("failed to find OPP for %ld\n", freq_Hz);
  77                         freqs.new = freqs.old;
  78                         ret = PTR_ERR(opp);
  79                         goto post_notify;
  80                 }
  81                 volt = opp_get_voltage(opp);
  82                 rcu_read_unlock();
  83                 tol = volt * voltage_tolerance / 100;
  84                 volt_old = regulator_get_voltage(cpu_reg);
  85         }
  86
  87         pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
  88                  freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
  89                  freqs.new / 1000, volt ? volt / 1000 : -1);
  90
  91         /* scaling up?  scale voltage before frequency */
  92         if (cpu_reg && freqs.new > freqs.old) {
  93                 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
  94                 if (ret) {
  95                         pr_err("failed to scale voltage up: %d\n", ret);
  96                         freqs.new = freqs.old;
  97                         goto post_notify;
  98                 }
  99         }
 100
 101         ret = clk_set_rate(cpu_clk, freqs.new * 1000);
 102         if (ret) {
 103                 pr_err("failed to set clock rate: %d\n", ret);
 104                 if (cpu_reg)
 105                         regulator_set_voltage_tol(cpu_reg, volt_old, tol);
 106                 freqs.new = freqs.old;
 107                 goto post_notify;
 108         }
 109
 110         /* scaling down?  scale voltage after frequency */
 111         if (cpu_reg && freqs.new < freqs.old) {
 112                 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
 113                 if (ret) {
 114                         pr_err("failed to scale voltage down: %d\n", ret);
 115                         clk_set_rate(cpu_clk, freqs.old * 1000);
 116                         freqs.new = freqs.old;
 117                 }
 118         }
 119
 120 post_notify:
 121         cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
 122
 123         return ret;
 124 }
 125
 126 static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
 127 {
 128         int ret;
 129
 130         ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
 131         if (ret) {
 132                 pr_err("invalid frequency table: %d\n", ret);
 133                 return ret;
 134         }
 135
 136         policy->cpuinfo.transition_latency = transition_latency;
 137         policy->cur = clk_get_rate(cpu_clk) / 1000;
 138
 139         /*
 140          * The driver only supports the SMP configuartion where all processors
 141          * share the clock and voltage and clock.  Use cpufreq affected_cpus
 142          * interface to have all CPUs scaled together.
 143          */
 144         cpumask_setall(policy->cpus);
 145
 146         cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
 147
 148         return 0;
 149 }
 150
 151 static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
 152 {
 153         cpufreq_frequency_table_put_attr(policy->cpu);
 154
 155         return 0;
 156 }
 157
 158 static struct freq_attr *cpu0_cpufreq_attr[] = {
 159         &cpufreq_freq_attr_scaling_available_freqs,
 160         NULL,
 161 };
 162
 163 static struct cpufreq_driver cpu0_cpufreq_driver = {
 164         .flags = CPUFREQ_STICKY,
 165         .verify = cpu0_verify_speed,
 166         .target = cpu0_set_target,
 167         .get = cpu0_get_speed,
 168         .init = cpu0_cpufreq_init,
 169         .exit = cpu0_cpufreq_exit,
 170         .name = "generic_cpu0",
 171         .attr = cpu0_cpufreq_attr,
 172 };
 173
 174 static int cpu0_cpufreq_probe(struct platform_device *pdev)
 175 {
 176         struct device_node *np, *parent;
 177         int ret;
 178
 179         parent = of_find_node_by_path("/cpus");
 180         if (!parent) {
 181                 pr_err("failed to find OF /cpus\n");
 182                 return -ENOENT;
 183         }
 184
 185         for_each_child_of_node(parent, np) {
 186                 if (of_get_property(np, "operating-points", NULL))
 187                         break;
 188         }
 189
 190         if (!np) {
 191                 pr_err("failed to find cpu0 node\n");
 192                 return -ENOENT;
 193         }
 194
 195         cpu_dev = &pdev->dev;
 196         cpu_dev->of_node = np;
 197
 198         cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
 199         if (IS_ERR(cpu_reg)) {
 200                 /*
 201                  * If cpu0 regulator supply node is present, but regulator is
 202                  * not yet registered, we should try defering probe.
 203                  */
 204                 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
 205                         dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
 206                         ret = -EPROBE_DEFER;
 207                         goto out_put_node;
 208                 }
 209                 pr_warn("failed to get cpu0 regulator: %ld\n",
 210                         PTR_ERR(cpu_reg));
 211                 cpu_reg = NULL;
 212         }
 213
 214         cpu_clk = devm_clk_get(cpu_dev, NULL);
 215         if (IS_ERR(cpu_clk)) {
 216                 ret = PTR_ERR(cpu_clk);
 217                 pr_err("failed to get cpu0 clock: %d\n", ret);
 218                 goto out_put_node;
 219         }
 220
 221         ret = of_init_opp_table(cpu_dev);
 222         if (ret) {
 223                 pr_err("failed to init OPP table: %d\n", ret);
 224                 goto out_put_node;
 225         }
 226
 227         ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
 228         if (ret) {
 229                 pr_err("failed to init cpufreq table: %d\n", ret);
 230                 goto out_put_node;
 231         }
 232
 233         of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
 234
 235         if (of_property_read_u32(np, "clock-latency", &transition_latency))
 236                 transition_latency = CPUFREQ_ETERNAL;
 237
 238         if (cpu_reg) {
 239                 struct opp *opp;
 240                 unsigned long min_uV, max_uV;
 241                 int i;
 242
 243                 /*
 244                  * OPP is maintained in order of increasing frequency, and
 245                  * freq_table initialised from OPP is therefore sorted in the
 246                  * same order.
 247                  */
 248                 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
 249                         ;
 250                 rcu_read_lock();
 251                 opp = opp_find_freq_exact(cpu_dev,
 252                                 freq_table[0].frequency * 1000, true);
 253                 min_uV = opp_get_voltage(opp);
 254                 opp = opp_find_freq_exact(cpu_dev,
 255                                 freq_table[i-1].frequency * 1000, true);
 256                 max_uV = opp_get_voltage(opp);
 257                 rcu_read_unlock();
 258                 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
 259                 if (ret > 0)
 260                         transition_latency += ret * 1000;
 261         }
 262
 263         ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
 264         if (ret) {
 265                 pr_err("failed register driver: %d\n", ret);
 266                 goto out_free_table;
 267         }
 268
 269         of_node_put(np);
 270         of_node_put(parent);
 271         return 0;
 272
 273 out_free_table:
 274         opp_free_cpufreq_table(cpu_dev, &freq_table);
 275 out_put_node:
 276         of_node_put(np);
 277         return ret;
 278 }
 279
 280 static int cpu0_cpufreq_remove(struct platform_device *pdev)
 281 {
 282         cpufreq_unregister_driver(&cpu0_cpufreq_driver);
 283         opp_free_cpufreq_table(cpu_dev, &freq_table);
 284
 285         return 0;
 286 }
 287
 288 static struct platform_driver cpu0_cpufreq_platdrv = {
 289         .driver = {
 290                 .name   = "cpufreq-cpu0",
 291                 .owner  = THIS_MODULE,
 292         },
 293         .probe          = cpu0_cpufreq_probe,
 294         .remove         = cpu0_cpufreq_remove,
 295 };
 296 module_platform_driver(cpu0_cpufreq_platdrv);
 297
 298 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
 299 MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
 300 MODULE_LICENSE("GPL");