Pileus Git - ~andy/linux/blob - drivers/char/agp/nvidia-agp.c

   1 /*
   2  * Nvidia AGPGART routines.
   3  * Based upon a 2.4 agpgart diff by the folks from NVIDIA, and hacked up
   4  * to work in 2.5 by Dave Jones <davej@redhat.com>
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/pci.h>
   9 #include <linux/init.h>
  10 #include <linux/agp_backend.h>
  11 #include <linux/page-flags.h>
  12 #include <linux/mm.h>
  13 #include <linux/jiffies.h>
  14 #include "agp.h"
  15
  16 /* NVIDIA registers */
  17 #define NVIDIA_0_APSIZE         0x80
  18 #define NVIDIA_1_WBC            0xf0
  19 #define NVIDIA_2_GARTCTRL       0xd0
  20 #define NVIDIA_2_APBASE         0xd8
  21 #define NVIDIA_2_APLIMIT        0xdc
  22 #define NVIDIA_2_ATTBASE(i)     (0xe0 + (i) * 4)
  23 #define NVIDIA_3_APBASE         0x50
  24 #define NVIDIA_3_APLIMIT        0x54
  25
  26
  27 static struct _nvidia_private {
  28         struct pci_dev *dev_1;
  29         struct pci_dev *dev_2;
  30         struct pci_dev *dev_3;
  31         volatile u32 __iomem *aperture;
  32         int num_active_entries;
  33         off_t pg_offset;
  34         u32 wbc_mask;
  35 } nvidia_private;
  36
  37
  38 static int nvidia_fetch_size(void)
  39 {
  40         int i;
  41         u8 size_value;
  42         struct aper_size_info_8 *values;
  43
  44         pci_read_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE, &size_value);
  45         size_value &= 0x0f;
  46         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
  47
  48         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
  49                 if (size_value == values[i].size_value) {
  50                         agp_bridge->previous_size =
  51                                 agp_bridge->current_size = (void *) (values + i);
  52                         agp_bridge->aperture_size_idx = i;
  53                         return values[i].size;
  54                 }
  55         }
  56
  57         return 0;
  58 }
  59
  60 #define SYSCFG          0xC0010010
  61 #define IORR_BASE0      0xC0010016
  62 #define IORR_MASK0      0xC0010017
  63 #define AMD_K7_NUM_IORR 2
  64
  65 static int nvidia_init_iorr(u32 base, u32 size)
  66 {
  67         u32 base_hi, base_lo;
  68         u32 mask_hi, mask_lo;
  69         u32 sys_hi, sys_lo;
  70         u32 iorr_addr, free_iorr_addr;
  71
  72         /* Find the iorr that is already used for the base */
  73         /* If not found, determine the uppermost available iorr */
  74         free_iorr_addr = AMD_K7_NUM_IORR;
  75         for (iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
  76                 rdmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
  77                 rdmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
  78
  79                 if ((base_lo & 0xfffff000) == (base & 0xfffff000))
  80                         break;
  81
  82                 if ((mask_lo & 0x00000800) == 0)
  83                         free_iorr_addr = iorr_addr;
  84         }
  85
  86         if (iorr_addr >= AMD_K7_NUM_IORR) {
  87                 iorr_addr = free_iorr_addr;
  88                 if (iorr_addr >= AMD_K7_NUM_IORR)
  89                         return -EINVAL;
  90         }
  91     base_hi = 0x0;
  92     base_lo = (base & ~0xfff) | 0x18;
  93     mask_hi = 0xf;
  94     mask_lo = ((~(size - 1)) & 0xfffff000) | 0x800;
  95     wrmsr(IORR_BASE0 + 2 * iorr_addr, base_lo, base_hi);
  96     wrmsr(IORR_MASK0 + 2 * iorr_addr, mask_lo, mask_hi);
  97
  98     rdmsr(SYSCFG, sys_lo, sys_hi);
  99     sys_lo |= 0x00100000;
 100     wrmsr(SYSCFG, sys_lo, sys_hi);
 101
 102         return 0;
 103 }
 104
 105 static int nvidia_configure(void)
 106 {
 107         int i, rc, num_dirs;
 108         u32 apbase, aplimit;
 109         struct aper_size_info_8 *current_size;
 110         u32 temp;
 111
 112         current_size = A_SIZE_8(agp_bridge->current_size);
 113
 114         /* aperture size */
 115         pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
 116                 current_size->size_value);
 117
 118         /* address to map to */
 119         apbase = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
 120         agp_bridge->gart_bus_addr = apbase;
 121         aplimit = apbase + (current_size->size * 1024 * 1024) - 1;
 122         pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APBASE, apbase);
 123         pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_APLIMIT, aplimit);
 124         pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APBASE, apbase);
 125         pci_write_config_dword(nvidia_private.dev_3, NVIDIA_3_APLIMIT, aplimit);
 126         if (0 != (rc = nvidia_init_iorr(apbase, current_size->size * 1024 * 1024)))
 127                 return rc;
 128
 129         /* directory size is 64k */
 130         num_dirs = current_size->size / 64;
 131         nvidia_private.num_active_entries = current_size->num_entries;
 132         nvidia_private.pg_offset = 0;
 133         if (num_dirs == 0) {
 134                 num_dirs = 1;
 135                 nvidia_private.num_active_entries /= (64 / current_size->size);
 136                 nvidia_private.pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
 137                         ~(current_size->size * 1024 * 1024 - 1)) / PAGE_SIZE;
 138         }
 139
 140         /* attbase */
 141         for (i = 0; i < 8; i++) {
 142                 pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_ATTBASE(i),
 143                         (agp_bridge->gatt_bus_addr + (i % num_dirs) * 64 * 1024) | 1);
 144         }
 145
 146         /* gtlb control */
 147         pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
 148         pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp | 0x11);
 149
 150         /* gart control */
 151         pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
 152         pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
 153
 154         /* map aperture */
 155         nvidia_private.aperture =
 156                 (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
 157
 158         if (!nvidia_private.aperture)
 159                 return -ENOMEM;
 160
 161         return 0;
 162 }
 163
 164 static void nvidia_cleanup(void)
 165 {
 166         struct aper_size_info_8 *previous_size;
 167         u32 temp;
 168
 169         /* gart control */
 170         pci_read_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, &temp);
 171         pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp & ~(0x100));
 172
 173         /* gtlb control */
 174         pci_read_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, &temp);
 175         pci_write_config_dword(nvidia_private.dev_2, NVIDIA_2_GARTCTRL, temp & ~(0x11));
 176
 177         /* unmap aperture */
 178         iounmap((void __iomem *) nvidia_private.aperture);
 179
 180         /* restore previous aperture size */
 181         previous_size = A_SIZE_8(agp_bridge->previous_size);
 182         pci_write_config_byte(agp_bridge->dev, NVIDIA_0_APSIZE,
 183                 previous_size->size_value);
 184
 185         /* restore iorr for previous aperture size */
 186         nvidia_init_iorr(agp_bridge->gart_bus_addr,
 187                 previous_size->size * 1024 * 1024);
 188 }
 189
 190
 191 /*
 192  * Note we can't use the generic routines, even though they are 99% the same.
 193  * Aperture sizes <64M still requires a full 64k GART directory, but
 194  * only use the portion of the TLB entries that correspond to the apertures
 195  * alignment inside the surrounding 64M block.
 196  */
 197 extern int agp_memory_reserved;
 198
 199 static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
 200 {
 201         int i, j;
 202         int mask_type;
 203
 204         mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
 205         if (mask_type != 0 || type != mem->type)
 206                 return -EINVAL;
 207
 208         if (mem->page_count == 0)
 209                 return 0;
 210
 211         if ((pg_start + mem->page_count) >
 212                 (nvidia_private.num_active_entries - agp_memory_reserved/PAGE_SIZE))
 213                 return -EINVAL;
 214
 215         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 216                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j)))
 217                         return -EBUSY;
 218         }
 219
 220         if (!mem->is_flushed) {
 221                 global_cache_flush();
 222                 mem->is_flushed = true;
 223         }
 224         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 225                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 226                                page_to_phys(mem->pages[i]), mask_type),
 227                         agp_bridge->gatt_table+nvidia_private.pg_offset+j);
 228         }
 229
 230         /* PCI Posting. */
 231         readl(agp_bridge->gatt_table+nvidia_private.pg_offset+j - 1);
 232
 233         agp_bridge->driver->tlb_flush(mem);
 234         return 0;
 235 }
 236
 237
 238 static int nvidia_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
 239 {
 240         int i;
 241
 242         int mask_type;
 243
 244         mask_type = agp_generic_type_to_mask_type(mem->bridge, type);
 245         if (mask_type != 0 || type != mem->type)
 246                 return -EINVAL;
 247
 248         if (mem->page_count == 0)
 249                 return 0;
 250
 251         for (i = pg_start; i < (mem->page_count + pg_start); i++)
 252                 writel(agp_bridge->scratch_page, agp_bridge->gatt_table+nvidia_private.pg_offset+i);
 253
 254         agp_bridge->driver->tlb_flush(mem);
 255         return 0;
 256 }
 257
 258
 259 static void nvidia_tlbflush(struct agp_memory *mem)
 260 {
 261         unsigned long end;
 262         u32 wbc_reg, temp;
 263         int i;
 264
 265         /* flush chipset */
 266         if (nvidia_private.wbc_mask) {
 267                 pci_read_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, &wbc_reg);
 268                 wbc_reg |= nvidia_private.wbc_mask;
 269                 pci_write_config_dword(nvidia_private.dev_1, NVIDIA_1_WBC, wbc_reg);
 270
 271                 end = jiffies + 3*HZ;
 272                 do {
 273                         pci_read_config_dword(nvidia_private.dev_1,
 274                                         NVIDIA_1_WBC, &wbc_reg);
 275                         if (time_before_eq(end, jiffies)) {
 276                                 printk(KERN_ERR PFX
 277                                     "TLB flush took more than 3 seconds.\n");
 278                         }
 279                 } while (wbc_reg & nvidia_private.wbc_mask);
 280         }
 281
 282         /* flush TLB entries */
 283         for (i = 0; i < 32 + 1; i++)
 284                 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
 285         for (i = 0; i < 32 + 1; i++)
 286                 temp = readl(nvidia_private.aperture+(i * PAGE_SIZE / sizeof(u32)));
 287 }
 288
 289
 290 static const struct aper_size_info_8 nvidia_generic_sizes[5] =
 291 {
 292         {512, 131072, 7, 0},
 293         {256, 65536, 6, 8},
 294         {128, 32768, 5, 12},
 295         {64, 16384, 4, 14},
 296         /* The 32M mode still requires a 64k gatt */
 297         {32, 16384, 4, 15}
 298 };
 299
 300
 301 static const struct gatt_mask nvidia_generic_masks[] =
 302 {
 303         { .mask = 1, .type = 0}
 304 };
 305
 306
 307 static const struct agp_bridge_driver nvidia_driver = {
 308         .owner                  = THIS_MODULE,
 309         .aperture_sizes         = nvidia_generic_sizes,
 310         .size_type              = U8_APER_SIZE,
 311         .num_aperture_sizes     = 5,
 312         .needs_scratch_page     = true,
 313         .configure              = nvidia_configure,
 314         .fetch_size             = nvidia_fetch_size,
 315         .cleanup                = nvidia_cleanup,
 316         .tlb_flush              = nvidia_tlbflush,
 317         .mask_memory            = agp_generic_mask_memory,
 318         .masks                  = nvidia_generic_masks,
 319         .agp_enable             = agp_generic_enable,
 320         .cache_flush            = global_cache_flush,
 321         .create_gatt_table      = agp_generic_create_gatt_table,
 322         .free_gatt_table        = agp_generic_free_gatt_table,
 323         .insert_memory          = nvidia_insert_memory,
 324         .remove_memory          = nvidia_remove_memory,
 325         .alloc_by_type          = agp_generic_alloc_by_type,
 326         .free_by_type           = agp_generic_free_by_type,
 327         .agp_alloc_page         = agp_generic_alloc_page,
 328         .agp_alloc_pages        = agp_generic_alloc_pages,
 329         .agp_destroy_page       = agp_generic_destroy_page,
 330         .agp_destroy_pages      = agp_generic_destroy_pages,
 331         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 332 };
 333
 334 static int agp_nvidia_probe(struct pci_dev *pdev,
 335                             const struct pci_device_id *ent)
 336 {
 337         struct agp_bridge_data *bridge;
 338         u8 cap_ptr;
 339
 340         nvidia_private.dev_1 =
 341                 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
 342         nvidia_private.dev_2 =
 343                 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
 344         nvidia_private.dev_3 =
 345                 pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
 346
 347         if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
 348                 printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
 349                         "chipset, but could not find the secondary devices.\n");
 350                 return -ENODEV;
 351         }
 352
 353         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 354         if (!cap_ptr)
 355                 return -ENODEV;
 356
 357         switch (pdev->device) {
 358         case PCI_DEVICE_ID_NVIDIA_NFORCE:
 359                 printk(KERN_INFO PFX "Detected NVIDIA nForce chipset\n");
 360                 nvidia_private.wbc_mask = 0x00010000;
 361                 break;
 362         case PCI_DEVICE_ID_NVIDIA_NFORCE2:
 363                 printk(KERN_INFO PFX "Detected NVIDIA nForce2 chipset\n");
 364                 nvidia_private.wbc_mask = 0x80000000;
 365                 break;
 366         default:
 367                 printk(KERN_ERR PFX "Unsupported NVIDIA chipset (device id: %04x)\n",
 368                             pdev->device);
 369                 return -ENODEV;
 370         }
 371
 372         bridge = agp_alloc_bridge();
 373         if (!bridge)
 374                 return -ENOMEM;
 375
 376         bridge->driver = &nvidia_driver;
 377         bridge->dev_private_data = &nvidia_private,
 378         bridge->dev = pdev;
 379         bridge->capndx = cap_ptr;
 380
 381         /* Fill in the mode register */
 382         pci_read_config_dword(pdev,
 383                         bridge->capndx+PCI_AGP_STATUS,
 384                         &bridge->mode);
 385
 386         pci_set_drvdata(pdev, bridge);
 387         return agp_add_bridge(bridge);
 388 }
 389
 390 static void agp_nvidia_remove(struct pci_dev *pdev)
 391 {
 392         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 393
 394         agp_remove_bridge(bridge);
 395         agp_put_bridge(bridge);
 396 }
 397
 398 #ifdef CONFIG_PM
 399 static int agp_nvidia_suspend(struct pci_dev *pdev, pm_message_t state)
 400 {
 401         pci_save_state(pdev);
 402         pci_set_power_state(pdev, PCI_D3hot);
 403
 404         return 0;
 405 }
 406
 407 static int agp_nvidia_resume(struct pci_dev *pdev)
 408 {
 409         /* set power state 0 and restore PCI space */
 410         pci_set_power_state(pdev, PCI_D0);
 411         pci_restore_state(pdev);
 412
 413         /* reconfigure AGP hardware again */
 414         nvidia_configure();
 415
 416         return 0;
 417 }
 418 #endif
 419
 420
 421 static struct pci_device_id agp_nvidia_pci_table[] = {
 422         {
 423         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 424         .class_mask     = ~0,
 425         .vendor         = PCI_VENDOR_ID_NVIDIA,
 426         .device         = PCI_DEVICE_ID_NVIDIA_NFORCE,
 427         .subvendor      = PCI_ANY_ID,
 428         .subdevice      = PCI_ANY_ID,
 429         },
 430         {
 431         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 432         .class_mask     = ~0,
 433         .vendor         = PCI_VENDOR_ID_NVIDIA,
 434         .device         = PCI_DEVICE_ID_NVIDIA_NFORCE2,
 435         .subvendor      = PCI_ANY_ID,
 436         .subdevice      = PCI_ANY_ID,
 437         },
 438         { }
 439 };
 440
 441 MODULE_DEVICE_TABLE(pci, agp_nvidia_pci_table);
 442
 443 static struct pci_driver agp_nvidia_pci_driver = {
 444         .name           = "agpgart-nvidia",
 445         .id_table       = agp_nvidia_pci_table,
 446         .probe          = agp_nvidia_probe,
 447         .remove         = agp_nvidia_remove,
 448 #ifdef CONFIG_PM
 449         .suspend        = agp_nvidia_suspend,
 450         .resume         = agp_nvidia_resume,
 451 #endif
 452 };
 453
 454 static int __init agp_nvidia_init(void)
 455 {
 456         if (agp_off)
 457                 return -EINVAL;
 458         return pci_register_driver(&agp_nvidia_pci_driver);
 459 }
 460
 461 static void __exit agp_nvidia_cleanup(void)
 462 {
 463         pci_unregister_driver(&agp_nvidia_pci_driver);
 464         pci_dev_put(nvidia_private.dev_1);
 465         pci_dev_put(nvidia_private.dev_2);
 466         pci_dev_put(nvidia_private.dev_3);
 467 }
 468
 469 module_init(agp_nvidia_init);
 470 module_exit(agp_nvidia_cleanup);
 471
 472 MODULE_LICENSE("GPL and additional rights");
 473 MODULE_AUTHOR("NVIDIA Corporation");
 474