Pileus Git - ~andy/linux/blob - arch/sparc/kernel/smp_64.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/export.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/ftrace.h>
  26 #include <linux/cpu.h>
  27 #include <linux/slab.h>
  28
  29 #include <asm/head.h>
  30 #include <asm/ptrace.h>
  31 #include <linux/atomic.h>
  32 #include <asm/tlbflush.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/cpudata.h>
  35 #include <asm/hvtramp.h>
  36 #include <asm/io.h>
  37 #include <asm/timer.h>
  38
  39 #include <asm/irq.h>
  40 #include <asm/irq_regs.h>
  41 #include <asm/page.h>
  42 #include <asm/pgtable.h>
  43 #include <asm/oplib.h>
  44 #include <asm/uaccess.h>
  45 #include <asm/starfire.h>
  46 #include <asm/tlb.h>
  47 #include <asm/sections.h>
  48 #include <asm/prom.h>
  49 #include <asm/mdesc.h>
  50 #include <asm/ldc.h>
  51 #include <asm/hypervisor.h>
  52 #include <asm/pcr.h>
  53
  54 #include "cpumap.h"
  55
  56 int sparc64_multi_core __read_mostly;
  57
  58 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  59 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  60         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  61
  62 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  63 EXPORT_SYMBOL(cpu_core_map);
  64
  65 static cpumask_t smp_commenced_mask;
  66
  67 void smp_info(struct seq_file *m)
  68 {
  69         int i;
  70
  71         seq_printf(m, "State:\n");
  72         for_each_online_cpu(i)
  73                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  74 }
  75
  76 void smp_bogo(struct seq_file *m)
  77 {
  78         int i;
  79
  80         for_each_online_cpu(i)
  81                 seq_printf(m,
  82                            "Cpu%dClkTck\t: %016lx\n",
  83                            i, cpu_data(i).clock_tick);
  84 }
  85
  86 extern void setup_sparc64_timer(void);
  87
  88 static volatile unsigned long callin_flag = 0;
  89
  90 void __cpuinit smp_callin(void)
  91 {
  92         int cpuid = hard_smp_processor_id();
  93
  94         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  95
  96         if (tlb_type == hypervisor)
  97                 sun4v_ktsb_register();
  98
  99         __flush_tlb_all();
 100
 101         setup_sparc64_timer();
 102
 103         if (cheetah_pcache_forced_on)
 104                 cheetah_enable_pcache();
 105
 106         callin_flag = 1;
 107         __asm__ __volatile__("membar #Sync\n\t"
 108                              "flush  %%g6" : : : "memory");
 109
 110         /* Clear this or we will die instantly when we
 111          * schedule back to this idler...
 112          */
 113         current_thread_info()->new_child = 0;
 114
 115         /* Attach to the address space of init_task. */
 116         atomic_inc(&init_mm.mm_count);
 117         current->active_mm = &init_mm;
 118
 119         /* inform the notifiers about the new cpu */
 120         notify_cpu_starting(cpuid);
 121
 122         while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
 123                 rmb();
 124
 125         set_cpu_online(cpuid, true);
 126         local_irq_enable();
 127
 128         /* idle thread is expected to have preempt disabled */
 129         preempt_disable();
 130
 131         cpu_startup_entry(CPUHP_ONLINE);
 132 }
 133
 134 void cpu_panic(void)
 135 {
 136         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 137         panic("SMP bolixed\n");
 138 }
 139
 140 /* This tick register synchronization scheme is taken entirely from
 141  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 142  *
 143  * The only change I've made is to rework it so that the master
 144  * initiates the synchonization instead of the slave. -DaveM
 145  */
 146
 147 #define MASTER  0
 148 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 149
 150 #define NUM_ROUNDS      64      /* magic value */
 151 #define NUM_ITERS       5       /* likewise */
 152
 153 static DEFINE_SPINLOCK(itc_sync_lock);
 154 static unsigned long go[SLAVE + 1];
 155
 156 #define DEBUG_TICK_SYNC 0
 157
 158 static inline long get_delta (long *rt, long *master)
 159 {
 160         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 161         unsigned long tcenter, t0, t1, tm;
 162         unsigned long i;
 163
 164         for (i = 0; i < NUM_ITERS; i++) {
 165                 t0 = tick_ops->get_tick();
 166                 go[MASTER] = 1;
 167                 membar_safe("#StoreLoad");
 168                 while (!(tm = go[SLAVE]))
 169                         rmb();
 170                 go[SLAVE] = 0;
 171                 wmb();
 172                 t1 = tick_ops->get_tick();
 173
 174                 if (t1 - t0 < best_t1 - best_t0)
 175                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 176         }
 177
 178         *rt = best_t1 - best_t0;
 179         *master = best_tm - best_t0;
 180
 181         /* average best_t0 and best_t1 without overflow: */
 182         tcenter = (best_t0/2 + best_t1/2);
 183         if (best_t0 % 2 + best_t1 % 2 == 2)
 184                 tcenter++;
 185         return tcenter - best_tm;
 186 }
 187
 188 void smp_synchronize_tick_client(void)
 189 {
 190         long i, delta, adj, adjust_latency = 0, done = 0;
 191         unsigned long flags, rt, master_time_stamp;
 192 #if DEBUG_TICK_SYNC
 193         struct {
 194                 long rt;        /* roundtrip time */
 195                 long master;    /* master's timestamp */
 196                 long diff;      /* difference between midpoint and master's timestamp */
 197                 long lat;       /* estimate of itc adjustment latency */
 198         } t[NUM_ROUNDS];
 199 #endif
 200
 201         go[MASTER] = 1;
 202
 203         while (go[MASTER])
 204                 rmb();
 205
 206         local_irq_save(flags);
 207         {
 208                 for (i = 0; i < NUM_ROUNDS; i++) {
 209                         delta = get_delta(&rt, &master_time_stamp);
 210                         if (delta == 0)
 211                                 done = 1;       /* let's lock on to this... */
 212
 213                         if (!done) {
 214                                 if (i > 0) {
 215                                         adjust_latency += -delta;
 216                                         adj = -delta + adjust_latency/4;
 217                                 } else
 218                                         adj = -delta;
 219
 220                                 tick_ops->add_tick(adj);
 221                         }
 222 #if DEBUG_TICK_SYNC
 223                         t[i].rt = rt;
 224                         t[i].master = master_time_stamp;
 225                         t[i].diff = delta;
 226                         t[i].lat = adjust_latency/4;
 227 #endif
 228                 }
 229         }
 230         local_irq_restore(flags);
 231
 232 #if DEBUG_TICK_SYNC
 233         for (i = 0; i < NUM_ROUNDS; i++)
 234                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 235                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 236 #endif
 237
 238         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 239                "(last diff %ld cycles, maxerr %lu cycles)\n",
 240                smp_processor_id(), delta, rt);
 241 }
 242
 243 static void smp_start_sync_tick_client(int cpu);
 244
 245 static void smp_synchronize_one_tick(int cpu)
 246 {
 247         unsigned long flags, i;
 248
 249         go[MASTER] = 0;
 250
 251         smp_start_sync_tick_client(cpu);
 252
 253         /* wait for client to be ready */
 254         while (!go[MASTER])
 255                 rmb();
 256
 257         /* now let the client proceed into his loop */
 258         go[MASTER] = 0;
 259         membar_safe("#StoreLoad");
 260
 261         spin_lock_irqsave(&itc_sync_lock, flags);
 262         {
 263                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 264                         while (!go[MASTER])
 265                                 rmb();
 266                         go[MASTER] = 0;
 267                         wmb();
 268                         go[SLAVE] = tick_ops->get_tick();
 269                         membar_safe("#StoreLoad");
 270                 }
 271         }
 272         spin_unlock_irqrestore(&itc_sync_lock, flags);
 273 }
 274
 275 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 276 /* XXX Put this in some common place. XXX */
 277 static unsigned long kimage_addr_to_ra(void *p)
 278 {
 279         unsigned long val = (unsigned long) p;
 280
 281         return kern_base + (val - KERNBASE);
 282 }
 283
 284 static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, void **descrp)
 285 {
 286         extern unsigned long sparc64_ttable_tl0;
 287         extern unsigned long kern_locked_tte_data;
 288         struct hvtramp_descr *hdesc;
 289         unsigned long trampoline_ra;
 290         struct trap_per_cpu *tb;
 291         u64 tte_vaddr, tte_data;
 292         unsigned long hv_err;
 293         int i;
 294
 295         hdesc = kzalloc(sizeof(*hdesc) +
 296                         (sizeof(struct hvtramp_mapping) *
 297                          num_kernel_image_mappings - 1),
 298                         GFP_KERNEL);
 299         if (!hdesc) {
 300                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 301                        "hvtramp_descr.\n");
 302                 return;
 303         }
 304         *descrp = hdesc;
 305
 306         hdesc->cpu = cpu;
 307         hdesc->num_mappings = num_kernel_image_mappings;
 308
 309         tb = &trap_block[cpu];
 310
 311         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 312         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 313
 314         hdesc->thread_reg = thread_reg;
 315
 316         tte_vaddr = (unsigned long) KERNBASE;
 317         tte_data = kern_locked_tte_data;
 318
 319         for (i = 0; i < hdesc->num_mappings; i++) {
 320                 hdesc->maps[i].vaddr = tte_vaddr;
 321                 hdesc->maps[i].tte   = tte_data;
 322                 tte_vaddr += 0x400000;
 323                 tte_data  += 0x400000;
 324         }
 325
 326         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 327
 328         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 329                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 330                                  __pa(hdesc));
 331         if (hv_err)
 332                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 333                        "gives error %lu\n", hv_err);
 334 }
 335 #endif
 336
 337 extern unsigned long sparc64_cpu_startup;
 338
 339 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 340  * 32-bits (I think) so to be safe we have it read the pointer
 341  * contained here so we work on >4GB machines. -DaveM
 342  */
 343 static struct thread_info *cpu_new_thread = NULL;
 344
 345 static int __cpuinit smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
 346 {
 347         unsigned long entry =
 348                 (unsigned long)(&sparc64_cpu_startup);
 349         unsigned long cookie =
 350                 (unsigned long)(&cpu_new_thread);
 351         void *descr = NULL;
 352         int timeout, ret;
 353
 354         callin_flag = 0;
 355         cpu_new_thread = task_thread_info(idle);
 356
 357         if (tlb_type == hypervisor) {
 358 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 359                 if (ldom_domaining_enabled)
 360                         ldom_startcpu_cpuid(cpu,
 361                                             (unsigned long) cpu_new_thread,
 362                                             &descr);
 363                 else
 364 #endif
 365                         prom_startcpu_cpuid(cpu, entry, cookie);
 366         } else {
 367                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 368
 369                 prom_startcpu(dp->phandle, entry, cookie);
 370         }
 371
 372         for (timeout = 0; timeout < 50000; timeout++) {
 373                 if (callin_flag)
 374                         break;
 375                 udelay(100);
 376         }
 377
 378         if (callin_flag) {
 379                 ret = 0;
 380         } else {
 381                 printk("Processor %d is stuck.\n", cpu);
 382                 ret = -ENODEV;
 383         }
 384         cpu_new_thread = NULL;
 385
 386         kfree(descr);
 387
 388         return ret;
 389 }
 390
 391 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 392 {
 393         u64 result, target;
 394         int stuck, tmp;
 395
 396         if (this_is_starfire) {
 397                 /* map to real upaid */
 398                 cpu = (((cpu & 0x3c) << 1) |
 399                         ((cpu & 0x40) >> 4) |
 400                         (cpu & 0x3));
 401         }
 402
 403         target = (cpu << 14) | 0x70;
 404 again:
 405         /* Ok, this is the real Spitfire Errata #54.
 406          * One must read back from a UDB internal register
 407          * after writes to the UDB interrupt dispatch, but
 408          * before the membar Sync for that write.
 409          * So we use the high UDB control register (ASI 0x7f,
 410          * ADDR 0x20) for the dummy read. -DaveM
 411          */
 412         tmp = 0x40;
 413         __asm__ __volatile__(
 414         "wrpr   %1, %2, %%pstate\n\t"
 415         "stxa   %4, [%0] %3\n\t"
 416         "stxa   %5, [%0+%8] %3\n\t"
 417         "add    %0, %8, %0\n\t"
 418         "stxa   %6, [%0+%8] %3\n\t"
 419         "membar #Sync\n\t"
 420         "stxa   %%g0, [%7] %3\n\t"
 421         "membar #Sync\n\t"
 422         "mov    0x20, %%g1\n\t"
 423         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 424         "membar #Sync"
 425         : "=r" (tmp)
 426         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 427           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 428           "r" (0x10), "0" (tmp)
 429         : "g1");
 430
 431         /* NOTE: PSTATE_IE is still clear. */
 432         stuck = 100000;
 433         do {
 434                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 435                         : "=r" (result)
 436                         : "i" (ASI_INTR_DISPATCH_STAT));
 437                 if (result == 0) {
 438                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 439                                              : : "r" (pstate));
 440                         return;
 441                 }
 442                 stuck -= 1;
 443                 if (stuck == 0)
 444                         break;
 445         } while (result & 0x1);
 446         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 447                              : : "r" (pstate));
 448         if (stuck == 0) {
 449                 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 450                        smp_processor_id(), result);
 451         } else {
 452                 udelay(2);
 453                 goto again;
 454         }
 455 }
 456
 457 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 458 {
 459         u64 *mondo, data0, data1, data2;
 460         u16 *cpu_list;
 461         u64 pstate;
 462         int i;
 463
 464         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 465         cpu_list = __va(tb->cpu_list_pa);
 466         mondo = __va(tb->cpu_mondo_block_pa);
 467         data0 = mondo[0];
 468         data1 = mondo[1];
 469         data2 = mondo[2];
 470         for (i = 0; i < cnt; i++)
 471                 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 472 }
 473
 474 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 475  * packet, but we have no use for that.  However we do take advantage of
 476  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 477  */
 478 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 479 {
 480         int nack_busy_id, is_jbus, need_more;
 481         u64 *mondo, pstate, ver, busy_mask;
 482         u16 *cpu_list;
 483
 484         cpu_list = __va(tb->cpu_list_pa);
 485         mondo = __va(tb->cpu_mondo_block_pa);
 486
 487         /* Unfortunately, someone at Sun had the brilliant idea to make the
 488          * busy/nack fields hard-coded by ITID number for this Ultra-III
 489          * derivative processor.
 490          */
 491         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 492         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 493                    (ver >> 32) == __SERRANO_ID);
 494
 495         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 496
 497 retry:
 498         need_more = 0;
 499         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 500                              : : "r" (pstate), "i" (PSTATE_IE));
 501
 502         /* Setup the dispatch data registers. */
 503         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 504                              "stxa      %1, [%4] %6\n\t"
 505                              "stxa      %2, [%5] %6\n\t"
 506                              "membar    #Sync\n\t"
 507                              : /* no outputs */
 508                              : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
 509                                "r" (0x40), "r" (0x50), "r" (0x60),
 510                                "i" (ASI_INTR_W));
 511
 512         nack_busy_id = 0;
 513         busy_mask = 0;
 514         {
 515                 int i;
 516
 517                 for (i = 0; i < cnt; i++) {
 518                         u64 target, nr;
 519
 520                         nr = cpu_list[i];
 521                         if (nr == 0xffff)
 522                                 continue;
 523
 524                         target = (nr << 14) | 0x70;
 525                         if (is_jbus) {
 526                                 busy_mask |= (0x1UL << (nr * 2));
 527                         } else {
 528                                 target |= (nack_busy_id << 24);
 529                                 busy_mask |= (0x1UL <<
 530                                               (nack_busy_id * 2));
 531                         }
 532                         __asm__ __volatile__(
 533                                 "stxa   %%g0, [%0] %1\n\t"
 534                                 "membar #Sync\n\t"
 535                                 : /* no outputs */
 536                                 : "r" (target), "i" (ASI_INTR_W));
 537                         nack_busy_id++;
 538                         if (nack_busy_id == 32) {
 539                                 need_more = 1;
 540                                 break;
 541                         }
 542                 }
 543         }
 544
 545         /* Now, poll for completion. */
 546         {
 547                 u64 dispatch_stat, nack_mask;
 548                 long stuck;
 549
 550                 stuck = 100000 * nack_busy_id;
 551                 nack_mask = busy_mask << 1;
 552                 do {
 553                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 554                                              : "=r" (dispatch_stat)
 555                                              : "i" (ASI_INTR_DISPATCH_STAT));
 556                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 557                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 558                                                      : : "r" (pstate));
 559                                 if (unlikely(need_more)) {
 560                                         int i, this_cnt = 0;
 561                                         for (i = 0; i < cnt; i++) {
 562                                                 if (cpu_list[i] == 0xffff)
 563                                                         continue;
 564                                                 cpu_list[i] = 0xffff;
 565                                                 this_cnt++;
 566                                                 if (this_cnt == 32)
 567                                                         break;
 568                                         }
 569                                         goto retry;
 570                                 }
 571                                 return;
 572                         }
 573                         if (!--stuck)
 574                                 break;
 575                 } while (dispatch_stat & busy_mask);
 576
 577                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 578                                      : : "r" (pstate));
 579
 580                 if (dispatch_stat & busy_mask) {
 581                         /* Busy bits will not clear, continue instead
 582                          * of freezing up on this cpu.
 583                          */
 584                         printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 585                                smp_processor_id(), dispatch_stat);
 586                 } else {
 587                         int i, this_busy_nack = 0;
 588
 589                         /* Delay some random time with interrupts enabled
 590                          * to prevent deadlock.
 591                          */
 592                         udelay(2 * nack_busy_id);
 593
 594                         /* Clear out the mask bits for cpus which did not
 595                          * NACK us.
 596                          */
 597                         for (i = 0; i < cnt; i++) {
 598                                 u64 check_mask, nr;
 599
 600                                 nr = cpu_list[i];
 601                                 if (nr == 0xffff)
 602                                         continue;
 603
 604                                 if (is_jbus)
 605                                         check_mask = (0x2UL << (2*nr));
 606                                 else
 607                                         check_mask = (0x2UL <<
 608                                                       this_busy_nack);
 609                                 if ((dispatch_stat & check_mask) == 0)
 610                                         cpu_list[i] = 0xffff;
 611                                 this_busy_nack += 2;
 612                                 if (this_busy_nack == 64)
 613                                         break;
 614                         }
 615
 616                         goto retry;
 617                 }
 618         }
 619 }
 620
 621 /* Multi-cpu list version.  */
 622 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 623 {
 624         int retries, this_cpu, prev_sent, i, saw_cpu_error;
 625         unsigned long status;
 626         u16 *cpu_list;
 627
 628         this_cpu = smp_processor_id();
 629
 630         cpu_list = __va(tb->cpu_list_pa);
 631
 632         saw_cpu_error = 0;
 633         retries = 0;
 634         prev_sent = 0;
 635         do {
 636                 int forward_progress, n_sent;
 637
 638                 status = sun4v_cpu_mondo_send(cnt,
 639                                               tb->cpu_list_pa,
 640                                               tb->cpu_mondo_block_pa);
 641
 642                 /* HV_EOK means all cpus received the xcall, we're done.  */
 643                 if (likely(status == HV_EOK))
 644                         break;
 645
 646                 /* First, see if we made any forward progress.
 647                  *
 648                  * The hypervisor indicates successful sends by setting
 649                  * cpu list entries to the value 0xffff.
 650                  */
 651                 n_sent = 0;
 652                 for (i = 0; i < cnt; i++) {
 653                         if (likely(cpu_list[i] == 0xffff))
 654                                 n_sent++;
 655                 }
 656
 657                 forward_progress = 0;
 658                 if (n_sent > prev_sent)
 659                         forward_progress = 1;
 660
 661                 prev_sent = n_sent;
 662
 663                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 664                  * in the list are in error state.  Use the cpu_state()
 665                  * hypervisor call to find out which cpus are in error state.
 666                  */
 667                 if (unlikely(status == HV_ECPUERROR)) {
 668                         for (i = 0; i < cnt; i++) {
 669                                 long err;
 670                                 u16 cpu;
 671
 672                                 cpu = cpu_list[i];
 673                                 if (cpu == 0xffff)
 674                                         continue;
 675
 676                                 err = sun4v_cpu_state(cpu);
 677                                 if (err == HV_CPU_STATE_ERROR) {
 678                                         saw_cpu_error = (cpu + 1);
 679                                         cpu_list[i] = 0xffff;
 680                                 }
 681                         }
 682                 } else if (unlikely(status != HV_EWOULDBLOCK))
 683                         goto fatal_mondo_error;
 684
 685                 /* Don't bother rewriting the CPU list, just leave the
 686                  * 0xffff and non-0xffff entries in there and the
 687                  * hypervisor will do the right thing.
 688                  *
 689                  * Only advance timeout state if we didn't make any
 690                  * forward progress.
 691                  */
 692                 if (unlikely(!forward_progress)) {
 693                         if (unlikely(++retries > 10000))
 694                                 goto fatal_mondo_timeout;
 695
 696                         /* Delay a little bit to let other cpus catch up
 697                          * on their cpu mondo queue work.
 698                          */
 699                         udelay(2 * cnt);
 700                 }
 701         } while (1);
 702
 703         if (unlikely(saw_cpu_error))
 704                 goto fatal_mondo_cpu_error;
 705
 706         return;
 707
 708 fatal_mondo_cpu_error:
 709         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 710                "(including %d) were in error state\n",
 711                this_cpu, saw_cpu_error - 1);
 712         return;
 713
 714 fatal_mondo_timeout:
 715         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 716                " progress after %d retries.\n",
 717                this_cpu, retries);
 718         goto dump_cpu_list_and_out;
 719
 720 fatal_mondo_error:
 721         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 722                this_cpu, status);
 723         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 724                "mondo_block_pa(%lx)\n",
 725                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 726
 727 dump_cpu_list_and_out:
 728         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 729         for (i = 0; i < cnt; i++)
 730                 printk("%u ", cpu_list[i]);
 731         printk("]\n");
 732 }
 733
 734 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
 735
 736 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 737 {
 738         struct trap_per_cpu *tb;
 739         int this_cpu, i, cnt;
 740         unsigned long flags;
 741         u16 *cpu_list;
 742         u64 *mondo;
 743
 744         /* We have to do this whole thing with interrupts fully disabled.
 745          * Otherwise if we send an xcall from interrupt context it will
 746          * corrupt both our mondo block and cpu list state.
 747          *
 748          * One consequence of this is that we cannot use timeout mechanisms
 749          * that depend upon interrupts being delivered locally.  So, for
 750          * example, we cannot sample jiffies and expect it to advance.
 751          *
 752          * Fortunately, udelay() uses %stick/%tick so we can use that.
 753          */
 754         local_irq_save(flags);
 755
 756         this_cpu = smp_processor_id();
 757         tb = &trap_block[this_cpu];
 758
 759         mondo = __va(tb->cpu_mondo_block_pa);
 760         mondo[0] = data0;
 761         mondo[1] = data1;
 762         mondo[2] = data2;
 763         wmb();
 764
 765         cpu_list = __va(tb->cpu_list_pa);
 766
 767         /* Setup the initial cpu list.  */
 768         cnt = 0;
 769         for_each_cpu(i, mask) {
 770                 if (i == this_cpu || !cpu_online(i))
 771                         continue;
 772                 cpu_list[cnt++] = i;
 773         }
 774
 775         if (cnt)
 776                 xcall_deliver_impl(tb, cnt);
 777
 778         local_irq_restore(flags);
 779 }
 780
 781 /* Send cross call to all processors mentioned in MASK_P
 782  * except self.  Really, there are only two cases currently,
 783  * "cpu_online_mask" and "mm_cpumask(mm)".
 784  */
 785 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
 786 {
 787         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 788
 789         xcall_deliver(data0, data1, data2, mask);
 790 }
 791
 792 /* Send cross call to all processors except self. */
 793 static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
 794 {
 795         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
 796 }
 797
 798 extern unsigned long xcall_sync_tick;
 799
 800 static void smp_start_sync_tick_client(int cpu)
 801 {
 802         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 803                       cpumask_of(cpu));
 804 }
 805
 806 extern unsigned long xcall_call_function;
 807
 808 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 809 {
 810         xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
 811 }
 812
 813 extern unsigned long xcall_call_function_single;
 814
 815 void arch_send_call_function_single_ipi(int cpu)
 816 {
 817         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 818                       cpumask_of(cpu));
 819 }
 820
 821 void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
 822 {
 823         clear_softint(1 << irq);
 824         generic_smp_call_function_interrupt();
 825 }
 826
 827 void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
 828 {
 829         clear_softint(1 << irq);
 830         generic_smp_call_function_single_interrupt();
 831 }
 832
 833 static void tsb_sync(void *info)
 834 {
 835         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 836         struct mm_struct *mm = info;
 837
 838         /* It is not valid to test "current->active_mm == mm" here.
 839          *
 840          * The value of "current" is not changed atomically with
 841          * switch_mm().  But that's OK, we just need to check the
 842          * current cpu's trap block PGD physical address.
 843          */
 844         if (tp->pgd_paddr == __pa(mm->pgd))
 845                 tsb_context_switch(mm);
 846 }
 847
 848 void smp_tsb_sync(struct mm_struct *mm)
 849 {
 850         smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
 851 }
 852
 853 extern unsigned long xcall_flush_tlb_mm;
 854 extern unsigned long xcall_flush_tlb_pending;
 855 extern unsigned long xcall_flush_tlb_kernel_range;
 856 extern unsigned long xcall_fetch_glob_regs;
 857 extern unsigned long xcall_fetch_glob_pmu;
 858 extern unsigned long xcall_fetch_glob_pmu_n4;
 859 extern unsigned long xcall_receive_signal;
 860 extern unsigned long xcall_new_mmu_context_version;
 861 #ifdef CONFIG_KGDB
 862 extern unsigned long xcall_kgdb_capture;
 863 #endif
 864
 865 #ifdef DCACHE_ALIASING_POSSIBLE
 866 extern unsigned long xcall_flush_dcache_page_cheetah;
 867 #endif
 868 extern unsigned long xcall_flush_dcache_page_spitfire;
 869
 870 #ifdef CONFIG_DEBUG_DCFLUSH
 871 extern atomic_t dcpage_flushes;
 872 extern atomic_t dcpage_flushes_xcall;
 873 #endif
 874
 875 static inline void __local_flush_dcache_page(struct page *page)
 876 {
 877 #ifdef DCACHE_ALIASING_POSSIBLE
 878         __flush_dcache_page(page_address(page),
 879                             ((tlb_type == spitfire) &&
 880                              page_mapping(page) != NULL));
 881 #else
 882         if (page_mapping(page) != NULL &&
 883             tlb_type == spitfire)
 884                 __flush_icache_page(__pa(page_address(page)));
 885 #endif
 886 }
 887
 888 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 889 {
 890         int this_cpu;
 891
 892         if (tlb_type == hypervisor)
 893                 return;
 894
 895 #ifdef CONFIG_DEBUG_DCFLUSH
 896         atomic_inc(&dcpage_flushes);
 897 #endif
 898
 899         this_cpu = get_cpu();
 900
 901         if (cpu == this_cpu) {
 902                 __local_flush_dcache_page(page);
 903         } else if (cpu_online(cpu)) {
 904                 void *pg_addr = page_address(page);
 905                 u64 data0 = 0;
 906
 907                 if (tlb_type == spitfire) {
 908                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 909                         if (page_mapping(page) != NULL)
 910                                 data0 |= ((u64)1 << 32);
 911                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 912 #ifdef DCACHE_ALIASING_POSSIBLE
 913                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 914 #endif
 915                 }
 916                 if (data0) {
 917                         xcall_deliver(data0, __pa(pg_addr),
 918                                       (u64) pg_addr, cpumask_of(cpu));
 919 #ifdef CONFIG_DEBUG_DCFLUSH
 920                         atomic_inc(&dcpage_flushes_xcall);
 921 #endif
 922                 }
 923         }
 924
 925         put_cpu();
 926 }
 927
 928 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 929 {
 930         void *pg_addr;
 931         u64 data0;
 932
 933         if (tlb_type == hypervisor)
 934                 return;
 935
 936         preempt_disable();
 937
 938 #ifdef CONFIG_DEBUG_DCFLUSH
 939         atomic_inc(&dcpage_flushes);
 940 #endif
 941         data0 = 0;
 942         pg_addr = page_address(page);
 943         if (tlb_type == spitfire) {
 944                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 945                 if (page_mapping(page) != NULL)
 946                         data0 |= ((u64)1 << 32);
 947         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 948 #ifdef DCACHE_ALIASING_POSSIBLE
 949                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 950 #endif
 951         }
 952         if (data0) {
 953                 xcall_deliver(data0, __pa(pg_addr),
 954                               (u64) pg_addr, cpu_online_mask);
 955 #ifdef CONFIG_DEBUG_DCFLUSH
 956                 atomic_inc(&dcpage_flushes_xcall);
 957 #endif
 958         }
 959         __local_flush_dcache_page(page);
 960
 961         preempt_enable();
 962 }
 963
 964 void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 965 {
 966         struct mm_struct *mm;
 967         unsigned long flags;
 968
 969         clear_softint(1 << irq);
 970
 971         /* See if we need to allocate a new TLB context because
 972          * the version of the one we are using is now out of date.
 973          */
 974         mm = current->active_mm;
 975         if (unlikely(!mm || (mm == &init_mm)))
 976                 return;
 977
 978         spin_lock_irqsave(&mm->context.lock, flags);
 979
 980         if (unlikely(!CTX_VALID(mm->context)))
 981                 get_new_mmu_context(mm);
 982
 983         spin_unlock_irqrestore(&mm->context.lock, flags);
 984
 985         load_secondary_context(mm);
 986         __flush_tlb_mm(CTX_HWBITS(mm->context),
 987                        SECONDARY_CONTEXT);
 988 }
 989
 990 void smp_new_mmu_context_version(void)
 991 {
 992         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
 993 }
 994
 995 #ifdef CONFIG_KGDB
 996 void kgdb_roundup_cpus(unsigned long flags)
 997 {
 998         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
 999 }
1000 #endif
1001
1002 void smp_fetch_global_regs(void)
1003 {
1004         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1005 }
1006
1007 void smp_fetch_global_pmu(void)
1008 {
1009         if (tlb_type == hypervisor &&
1010             sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1011                 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1012         else
1013                 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1014 }
1015
1016 /* We know that the window frames of the user have been flushed
1017  * to the stack before we get here because all callers of us
1018  * are flush_tlb_*() routines, and these run after flush_cache_*()
1019  * which performs the flushw.
1020  *
1021  * The SMP TLB coherency scheme we use works as follows:
1022  *
1023  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1024  *    space has (potentially) executed on, this is the heuristic
1025  *    we use to avoid doing cross calls.
1026  *
1027  *    Also, for flushing from kswapd and also for clones, we
1028  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1029  *
1030  * 2) TLB context numbers are shared globally across all processors
1031  *    in the system, this allows us to play several games to avoid
1032  *    cross calls.
1033  *
1034  *    One invariant is that when a cpu switches to a process, and
1035  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1036  *    current cpu's bit set, that tlb context is flushed locally.
1037  *
1038  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1039  *    cross calls when we want to flush the currently running process's
1040  *    tlb state.  This is done by clearing all cpu bits except the current
1041  *    processor's in current->mm->cpu_vm_mask and performing the
1042  *    flush locally only.  This will force any subsequent cpus which run
1043  *    this task to flush the context from the local tlb if the process
1044  *    migrates to another cpu (again).
1045  *
1046  * 3) For shared address spaces (threads) and swapping we bite the
1047  *    bullet for most cases and perform the cross call (but only to
1048  *    the cpus listed in cpu_vm_mask).
1049  *
1050  *    The performance gain from "optimizing" away the cross call for threads is
1051  *    questionable (in theory the big win for threads is the massive sharing of
1052  *    address space state across processors).
1053  */
1054
1055 /* This currently is only used by the hugetlb arch pre-fault
1056  * hook on UltraSPARC-III+ and later when changing the pagesize
1057  * bits of the context register for an address space.
1058  */
1059 void smp_flush_tlb_mm(struct mm_struct *mm)
1060 {
1061         u32 ctx = CTX_HWBITS(mm->context);
1062         int cpu = get_cpu();
1063
1064         if (atomic_read(&mm->mm_users) == 1) {
1065                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1066                 goto local_flush_and_out;
1067         }
1068
1069         smp_cross_call_masked(&xcall_flush_tlb_mm,
1070                               ctx, 0, 0,
1071                               mm_cpumask(mm));
1072
1073 local_flush_and_out:
1074         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1075
1076         put_cpu();
1077 }
1078
1079 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1080 {
1081         u32 ctx = CTX_HWBITS(mm->context);
1082         int cpu = get_cpu();
1083
1084         if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1085                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1086         else
1087                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1088                                       ctx, nr, (unsigned long) vaddrs,
1089                                       mm_cpumask(mm));
1090
1091         __flush_tlb_pending(ctx, nr, vaddrs);
1092
1093         put_cpu();
1094 }
1095
1096 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1097 {
1098         start &= PAGE_MASK;
1099         end    = PAGE_ALIGN(end);
1100         if (start != end) {
1101                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1102                                0, start, end);
1103
1104                 __flush_tlb_kernel_range(start, end);
1105         }
1106 }
1107
1108 /* CPU capture. */
1109 /* #define CAPTURE_DEBUG */
1110 extern unsigned long xcall_capture;
1111
1112 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1113 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1114 static unsigned long penguins_are_doing_time;
1115
1116 void smp_capture(void)
1117 {
1118         int result = atomic_add_ret(1, &smp_capture_depth);
1119
1120         if (result == 1) {
1121                 int ncpus = num_online_cpus();
1122
1123 #ifdef CAPTURE_DEBUG
1124                 printk("CPU[%d]: Sending penguins to jail...",
1125                        smp_processor_id());
1126 #endif
1127                 penguins_are_doing_time = 1;
1128                 atomic_inc(&smp_capture_registry);
1129                 smp_cross_call(&xcall_capture, 0, 0, 0);
1130                 while (atomic_read(&smp_capture_registry) != ncpus)
1131                         rmb();
1132 #ifdef CAPTURE_DEBUG
1133                 printk("done\n");
1134 #endif
1135         }
1136 }
1137
1138 void smp_release(void)
1139 {
1140         if (atomic_dec_and_test(&smp_capture_depth)) {
1141 #ifdef CAPTURE_DEBUG
1142                 printk("CPU[%d]: Giving pardon to "
1143                        "imprisoned penguins\n",
1144                        smp_processor_id());
1145 #endif
1146                 penguins_are_doing_time = 0;
1147                 membar_safe("#StoreLoad");
1148                 atomic_dec(&smp_capture_registry);
1149         }
1150 }
1151
1152 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1153  * set, so they can service tlb flush xcalls...
1154  */
1155 extern void prom_world(int);
1156
1157 void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1158 {
1159         clear_softint(1 << irq);
1160
1161         preempt_disable();
1162
1163         __asm__ __volatile__("flushw");
1164         prom_world(1);
1165         atomic_inc(&smp_capture_registry);
1166         membar_safe("#StoreLoad");
1167         while (penguins_are_doing_time)
1168                 rmb();
1169         atomic_dec(&smp_capture_registry);
1170         prom_world(0);
1171
1172         preempt_enable();
1173 }
1174
1175 /* /proc/profile writes can call this, don't __init it please. */
1176 int setup_profiling_timer(unsigned int multiplier)
1177 {
1178         return -EINVAL;
1179 }
1180
1181 void __init smp_prepare_cpus(unsigned int max_cpus)
1182 {
1183 }
1184
1185 void smp_prepare_boot_cpu(void)
1186 {
1187 }
1188
1189 void __init smp_setup_processor_id(void)
1190 {
1191         if (tlb_type == spitfire)
1192                 xcall_deliver_impl = spitfire_xcall_deliver;
1193         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1194                 xcall_deliver_impl = cheetah_xcall_deliver;
1195         else
1196                 xcall_deliver_impl = hypervisor_xcall_deliver;
1197 }
1198
1199 void smp_fill_in_sib_core_maps(void)
1200 {
1201         unsigned int i;
1202
1203         for_each_present_cpu(i) {
1204                 unsigned int j;
1205
1206                 cpumask_clear(&cpu_core_map[i]);
1207                 if (cpu_data(i).core_id == 0) {
1208                         cpumask_set_cpu(i, &cpu_core_map[i]);
1209                         continue;
1210                 }
1211
1212                 for_each_present_cpu(j) {
1213                         if (cpu_data(i).core_id ==
1214                             cpu_data(j).core_id)
1215                                 cpumask_set_cpu(j, &cpu_core_map[i]);
1216                 }
1217         }
1218
1219         for_each_present_cpu(i) {
1220                 unsigned int j;
1221
1222                 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1223                 if (cpu_data(i).proc_id == -1) {
1224                         cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1225                         continue;
1226                 }
1227
1228                 for_each_present_cpu(j) {
1229                         if (cpu_data(i).proc_id ==
1230                             cpu_data(j).proc_id)
1231                                 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1232                 }
1233         }
1234 }
1235
1236 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
1237 {
1238         int ret = smp_boot_one_cpu(cpu, tidle);
1239
1240         if (!ret) {
1241                 cpumask_set_cpu(cpu, &smp_commenced_mask);
1242                 while (!cpu_online(cpu))
1243                         mb();
1244                 if (!cpu_online(cpu)) {
1245                         ret = -ENODEV;
1246                 } else {
1247                         /* On SUN4V, writes to %tick and %stick are
1248                          * not allowed.
1249                          */
1250                         if (tlb_type != hypervisor)
1251                                 smp_synchronize_one_tick(cpu);
1252                 }
1253         }
1254         return ret;
1255 }
1256
1257 #ifdef CONFIG_HOTPLUG_CPU
1258 void cpu_play_dead(void)
1259 {
1260         int cpu = smp_processor_id();
1261         unsigned long pstate;
1262
1263         idle_task_exit();
1264
1265         if (tlb_type == hypervisor) {
1266                 struct trap_per_cpu *tb = &trap_block[cpu];
1267
1268                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1269                                 tb->cpu_mondo_pa, 0);
1270                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1271                                 tb->dev_mondo_pa, 0);
1272                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1273                                 tb->resum_mondo_pa, 0);
1274                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1275                                 tb->nonresum_mondo_pa, 0);
1276         }
1277
1278         cpumask_clear_cpu(cpu, &smp_commenced_mask);
1279         membar_safe("#Sync");
1280
1281         local_irq_disable();
1282
1283         __asm__ __volatile__(
1284                 "rdpr   %%pstate, %0\n\t"
1285                 "wrpr   %0, %1, %%pstate"
1286                 : "=r" (pstate)
1287                 : "i" (PSTATE_IE));
1288
1289         while (1)
1290                 barrier();
1291 }
1292
1293 int __cpu_disable(void)
1294 {
1295         int cpu = smp_processor_id();
1296         cpuinfo_sparc *c;
1297         int i;
1298
1299         for_each_cpu(i, &cpu_core_map[cpu])
1300                 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1301         cpumask_clear(&cpu_core_map[cpu]);
1302
1303         for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1304                 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1305         cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1306
1307         c = &cpu_data(cpu);
1308
1309         c->core_id = 0;
1310         c->proc_id = -1;
1311
1312         smp_wmb();
1313
1314         /* Make sure no interrupts point to this cpu.  */
1315         fixup_irqs();
1316
1317         local_irq_enable();
1318         mdelay(1);
1319         local_irq_disable();
1320
1321         set_cpu_online(cpu, false);
1322
1323         cpu_map_rebuild();
1324
1325         return 0;
1326 }
1327
1328 void __cpu_die(unsigned int cpu)
1329 {
1330         int i;
1331
1332         for (i = 0; i < 100; i++) {
1333                 smp_rmb();
1334                 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1335                         break;
1336                 msleep(100);
1337         }
1338         if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1339                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1340         } else {
1341 #if defined(CONFIG_SUN_LDOMS)
1342                 unsigned long hv_err;
1343                 int limit = 100;
1344
1345                 do {
1346                         hv_err = sun4v_cpu_stop(cpu);
1347                         if (hv_err == HV_EOK) {
1348                                 set_cpu_present(cpu, false);
1349                                 break;
1350                         }
1351                 } while (--limit > 0);
1352                 if (limit <= 0) {
1353                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1354                                hv_err);
1355                 }
1356 #endif
1357         }
1358 }
1359 #endif
1360
1361 void __init smp_cpus_done(unsigned int max_cpus)
1362 {
1363         pcr_arch_init();
1364 }
1365
1366 void smp_send_reschedule(int cpu)
1367 {
1368         xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1369                       cpumask_of(cpu));
1370 }
1371
1372 void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1373 {
1374         clear_softint(1 << irq);
1375         scheduler_ipi();
1376 }
1377
1378 /* This is a nop because we capture all other cpus
1379  * anyways when making the PROM active.
1380  */
1381 void smp_send_stop(void)
1382 {
1383 }
1384
1385 /**
1386  * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1387  * @cpu: cpu to allocate for
1388  * @size: size allocation in bytes
1389  * @align: alignment
1390  *
1391  * Allocate @size bytes aligned at @align for cpu @cpu.  This wrapper
1392  * does the right thing for NUMA regardless of the current
1393  * configuration.
1394  *
1395  * RETURNS:
1396  * Pointer to the allocated area on success, NULL on failure.
1397  */
1398 static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1399                                         size_t align)
1400 {
1401         const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1402 #ifdef CONFIG_NEED_MULTIPLE_NODES
1403         int node = cpu_to_node(cpu);
1404         void *ptr;
1405
1406         if (!node_online(node) || !NODE_DATA(node)) {
1407                 ptr = __alloc_bootmem(size, align, goal);
1408                 pr_info("cpu %d has no node %d or node-local memory\n",
1409                         cpu, node);
1410                 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1411                          cpu, size, __pa(ptr));
1412         } else {
1413                 ptr = __alloc_bootmem_node(NODE_DATA(node),
1414                                            size, align, goal);
1415                 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1416                          "%016lx\n", cpu, size, node, __pa(ptr));
1417         }
1418         return ptr;
1419 #else
1420         return __alloc_bootmem(size, align, goal);
1421 #endif
1422 }
1423
1424 static void __init pcpu_free_bootmem(void *ptr, size_t size)
1425 {
1426         free_bootmem(__pa(ptr), size);
1427 }
1428
1429 static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1430 {
1431         if (cpu_to_node(from) == cpu_to_node(to))
1432                 return LOCAL_DISTANCE;
1433         else
1434                 return REMOTE_DISTANCE;
1435 }
1436
1437 static void __init pcpu_populate_pte(unsigned long addr)
1438 {
1439         pgd_t *pgd = pgd_offset_k(addr);
1440         pud_t *pud;
1441         pmd_t *pmd;
1442
1443         pud = pud_offset(pgd, addr);
1444         if (pud_none(*pud)) {
1445                 pmd_t *new;
1446
1447                 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1448                 pud_populate(&init_mm, pud, new);
1449         }
1450
1451         pmd = pmd_offset(pud, addr);
1452         if (!pmd_present(*pmd)) {
1453                 pte_t *new;
1454
1455                 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1456                 pmd_populate_kernel(&init_mm, pmd, new);
1457         }
1458 }
1459
1460 void __init setup_per_cpu_areas(void)
1461 {
1462         unsigned long delta;
1463         unsigned int cpu;
1464         int rc = -EINVAL;
1465
1466         if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1467                 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1468                                             PERCPU_DYNAMIC_RESERVE, 4 << 20,
1469                                             pcpu_cpu_distance,
1470                                             pcpu_alloc_bootmem,
1471                                             pcpu_free_bootmem);
1472                 if (rc)
1473                         pr_warning("PERCPU: %s allocator failed (%d), "
1474                                    "falling back to page size\n",
1475                                    pcpu_fc_names[pcpu_chosen_fc], rc);
1476         }
1477         if (rc < 0)
1478                 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1479                                            pcpu_alloc_bootmem,
1480                                            pcpu_free_bootmem,
1481                                            pcpu_populate_pte);
1482         if (rc < 0)
1483                 panic("cannot initialize percpu area (err=%d)", rc);
1484
1485         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1486         for_each_possible_cpu(cpu)
1487                 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1488
1489         /* Setup %g5 for the boot cpu.  */
1490         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1491
1492         of_fill_in_cpu_data();
1493         if (tlb_type == hypervisor)
1494                 mdesc_fill_in_cpu_data(cpu_all_mask);
1495 }