Pileus Git - ~andy/linux/blob - arch/powerpc/include/asm/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * Simple spin lock operations.
   7  *
   8  * Copyright (C) 2001-2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   9  * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
  10  * Copyright (C) 2002 Dave Engebretsen <engebret@us.ibm.com>, IBM
  11  *      Rework to support virtual processors
  12  *
  13  * Type of int is used as a full 64b word is not necessary.
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  *
  20  * (the type definitions are in asm/spinlock_types.h)
  21  */
  22 #include <linux/irqflags.h>
  23 #ifdef CONFIG_PPC64
  24 #include <asm/paca.h>
  25 #include <asm/hvcall.h>
  26 #endif
  27 #include <asm/asm-compat.h>
  28 #include <asm/synch.h>
  29 #include <asm/ppc-opcode.h>
  30
  31 #define smp_mb__after_unlock_lock()     smp_mb()  /* Full ordering for lock. */
  32
  33 #define arch_spin_is_locked(x)          ((x)->slock != 0)
  34
  35 #ifdef CONFIG_PPC64
  36 /* use 0x800000yy when locked, where yy == CPU number */
  37 #ifdef __BIG_ENDIAN__
  38 #define LOCK_TOKEN      (*(u32 *)(&get_paca()->lock_token))
  39 #else
  40 #define LOCK_TOKEN      (*(u32 *)(&get_paca()->paca_index))
  41 #endif
  42 #else
  43 #define LOCK_TOKEN      1
  44 #endif
  45
  46 #if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
  47 #define CLEAR_IO_SYNC   (get_paca()->io_sync = 0)
  48 #define SYNC_IO         do {                                            \
  49                                 if (unlikely(get_paca()->io_sync)) {    \
  50                                         mb();                           \
  51                                         get_paca()->io_sync = 0;        \
  52                                 }                                       \
  53                         } while (0)
  54 #else
  55 #define CLEAR_IO_SYNC
  56 #define SYNC_IO
  57 #endif
  58
  59 /*
  60  * This returns the old value in the lock, so we succeeded
  61  * in getting the lock if the return value is 0.
  62  */
  63 static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
  64 {
  65         unsigned long tmp, token;
  66
  67         token = LOCK_TOKEN;
  68         __asm__ __volatile__(
  69 "1:     " PPC_LWARX(%0,0,%2,1) "\n\
  70         cmpwi           0,%0,0\n\
  71         bne-            2f\n\
  72         stwcx.          %1,0,%2\n\
  73         bne-            1b\n"
  74         PPC_ACQUIRE_BARRIER
  75 "2:"
  76         : "=&r" (tmp)
  77         : "r" (token), "r" (&lock->slock)
  78         : "cr0", "memory");
  79
  80         return tmp;
  81 }
  82
  83 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  84 {
  85         CLEAR_IO_SYNC;
  86         return __arch_spin_trylock(lock) == 0;
  87 }
  88
  89 /*
  90  * On a system with shared processors (that is, where a physical
  91  * processor is multiplexed between several virtual processors),
  92  * there is no point spinning on a lock if the holder of the lock
  93  * isn't currently scheduled on a physical processor.  Instead
  94  * we detect this situation and ask the hypervisor to give the
  95  * rest of our timeslice to the lock holder.
  96  *
  97  * So that we can tell which virtual processor is holding a lock,
  98  * we put 0x80000000 | smp_processor_id() in the lock when it is
  99  * held.  Conveniently, we have a word in the paca that holds this
 100  * value.
 101  */
 102
 103 #if defined(CONFIG_PPC_SPLPAR)
 104 /* We only yield to the hypervisor if we are in shared processor mode */
 105 #define SHARED_PROCESSOR (lppaca_shared_proc(local_paca->lppaca_ptr))
 106 extern void __spin_yield(arch_spinlock_t *lock);
 107 extern void __rw_yield(arch_rwlock_t *lock);
 108 #else /* SPLPAR */
 109 #define __spin_yield(x) barrier()
 110 #define __rw_yield(x)   barrier()
 111 #define SHARED_PROCESSOR        0
 112 #endif
 113
 114 static inline void arch_spin_lock(arch_spinlock_t *lock)
 115 {
 116         CLEAR_IO_SYNC;
 117         while (1) {
 118                 if (likely(__arch_spin_trylock(lock) == 0))
 119                         break;
 120                 do {
 121                         HMT_low();
 122                         if (SHARED_PROCESSOR)
 123                                 __spin_yield(lock);
 124                 } while (unlikely(lock->slock != 0));
 125                 HMT_medium();
 126         }
 127 }
 128
 129 static inline
 130 void arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
 131 {
 132         unsigned long flags_dis;
 133
 134         CLEAR_IO_SYNC;
 135         while (1) {
 136                 if (likely(__arch_spin_trylock(lock) == 0))
 137                         break;
 138                 local_save_flags(flags_dis);
 139                 local_irq_restore(flags);
 140                 do {
 141                         HMT_low();
 142                         if (SHARED_PROCESSOR)
 143                                 __spin_yield(lock);
 144                 } while (unlikely(lock->slock != 0));
 145                 HMT_medium();
 146                 local_irq_restore(flags_dis);
 147         }
 148 }
 149
 150 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 151 {
 152         SYNC_IO;
 153         __asm__ __volatile__("# arch_spin_unlock\n\t"
 154                                 PPC_RELEASE_BARRIER: : :"memory");
 155         lock->slock = 0;
 156 }
 157
 158 #ifdef CONFIG_PPC64
 159 extern void arch_spin_unlock_wait(arch_spinlock_t *lock);
 160 #else
 161 #define arch_spin_unlock_wait(lock) \
 162         do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 163 #endif
 164
 165 /*
 166  * Read-write spinlocks, allowing multiple readers
 167  * but only one writer.
 168  *
 169  * NOTE! it is quite common to have readers in interrupts
 170  * but no interrupt writers. For those circumstances we
 171  * can "mix" irq-safe locks - any writer needs to get a
 172  * irq-safe write-lock, but readers can get non-irqsafe
 173  * read-locks.
 174  */
 175
 176 #define arch_read_can_lock(rw)          ((rw)->lock >= 0)
 177 #define arch_write_can_lock(rw) (!(rw)->lock)
 178
 179 #ifdef CONFIG_PPC64
 180 #define __DO_SIGN_EXTEND        "extsw  %0,%0\n"
 181 #define WRLOCK_TOKEN            LOCK_TOKEN      /* it's negative */
 182 #else
 183 #define __DO_SIGN_EXTEND
 184 #define WRLOCK_TOKEN            (-1)
 185 #endif
 186
 187 /*
 188  * This returns the old value in the lock + 1,
 189  * so we got a read lock if the return value is > 0.
 190  */
 191 static inline long __arch_read_trylock(arch_rwlock_t *rw)
 192 {
 193         long tmp;
 194
 195         __asm__ __volatile__(
 196 "1:     " PPC_LWARX(%0,0,%1,1) "\n"
 197         __DO_SIGN_EXTEND
 198 "       addic.          %0,%0,1\n\
 199         ble-            2f\n"
 200         PPC405_ERR77(0,%1)
 201 "       stwcx.          %0,0,%1\n\
 202         bne-            1b\n"
 203         PPC_ACQUIRE_BARRIER
 204 "2:"    : "=&r" (tmp)
 205         : "r" (&rw->lock)
 206         : "cr0", "xer", "memory");
 207
 208         return tmp;
 209 }
 210
 211 /*
 212  * This returns the old value in the lock,
 213  * so we got the write lock if the return value is 0.
 214  */
 215 static inline long __arch_write_trylock(arch_rwlock_t *rw)
 216 {
 217         long tmp, token;
 218
 219         token = WRLOCK_TOKEN;
 220         __asm__ __volatile__(
 221 "1:     " PPC_LWARX(%0,0,%2,1) "\n\
 222         cmpwi           0,%0,0\n\
 223         bne-            2f\n"
 224         PPC405_ERR77(0,%1)
 225 "       stwcx.          %1,0,%2\n\
 226         bne-            1b\n"
 227         PPC_ACQUIRE_BARRIER
 228 "2:"    : "=&r" (tmp)
 229         : "r" (token), "r" (&rw->lock)
 230         : "cr0", "memory");
 231
 232         return tmp;
 233 }
 234
 235 static inline void arch_read_lock(arch_rwlock_t *rw)
 236 {
 237         while (1) {
 238                 if (likely(__arch_read_trylock(rw) > 0))
 239                         break;
 240                 do {
 241                         HMT_low();
 242                         if (SHARED_PROCESSOR)
 243                                 __rw_yield(rw);
 244                 } while (unlikely(rw->lock < 0));
 245                 HMT_medium();
 246         }
 247 }
 248
 249 static inline void arch_write_lock(arch_rwlock_t *rw)
 250 {
 251         while (1) {
 252                 if (likely(__arch_write_trylock(rw) == 0))
 253                         break;
 254                 do {
 255                         HMT_low();
 256                         if (SHARED_PROCESSOR)
 257                                 __rw_yield(rw);
 258                 } while (unlikely(rw->lock != 0));
 259                 HMT_medium();
 260         }
 261 }
 262
 263 static inline int arch_read_trylock(arch_rwlock_t *rw)
 264 {
 265         return __arch_read_trylock(rw) > 0;
 266 }
 267
 268 static inline int arch_write_trylock(arch_rwlock_t *rw)
 269 {
 270         return __arch_write_trylock(rw) == 0;
 271 }
 272
 273 static inline void arch_read_unlock(arch_rwlock_t *rw)
 274 {
 275         long tmp;
 276
 277         __asm__ __volatile__(
 278         "# read_unlock\n\t"
 279         PPC_RELEASE_BARRIER
 280 "1:     lwarx           %0,0,%1\n\
 281         addic           %0,%0,-1\n"
 282         PPC405_ERR77(0,%1)
 283 "       stwcx.          %0,0,%1\n\
 284         bne-            1b"
 285         : "=&r"(tmp)
 286         : "r"(&rw->lock)
 287         : "cr0", "xer", "memory");
 288 }
 289
 290 static inline void arch_write_unlock(arch_rwlock_t *rw)
 291 {
 292         __asm__ __volatile__("# write_unlock\n\t"
 293                                 PPC_RELEASE_BARRIER: : :"memory");
 294         rw->lock = 0;
 295 }
 296
 297 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 298 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 299
 300 #define arch_spin_relax(lock)   __spin_yield(lock)
 301 #define arch_read_relax(lock)   __rw_yield(lock)
 302 #define arch_write_relax(lock)  __rw_yield(lock)
 303
 304 #endif /* __KERNEL__ */
 305 #endif /* __ASM_SPINLOCK_H */