Pileus Git - ~andy/linux/blob - arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/power/smartreflex.h>
  23 #include <linux/i2c-omap.h>
  24
  25 #include <linux/omap-dma.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "omap_hwmod_common_data.h"
  32 #include "cm1_7xx.h"
  33 #include "cm2_7xx.h"
  34 #include "prm7xx.h"
  35 #include "i2c.h"
  36 #include "mmc.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all DRA7XX interrupts external to MPUSS */
  40 #define DRA7XX_IRQ_GIC_START    32
  41
  42 /* Base offset for all DRA7XX dma requests */
  43 #define DRA7XX_DMA_REQ_START    1
  44
  45
  46 /*
  47  * IP blocks
  48  */
  49
  50 /*
  51  * 'l3' class
  52  * instance(s): l3_instr, l3_main_1, l3_main_2
  53  */
  54 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  55         .name   = "l3",
  56 };
  57
  58 /* l3_instr */
  59 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  60         .name           = "l3_instr",
  61         .class          = &dra7xx_l3_hwmod_class,
  62         .clkdm_name     = "l3instr_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  66                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  67                         .modulemode   = MODULEMODE_HWCTRL,
  68                 },
  69         },
  70 };
  71
  72 /* l3_main_1 */
  73 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  74         .name           = "l3_main_1",
  75         .class          = &dra7xx_l3_hwmod_class,
  76         .clkdm_name     = "l3main1_clkdm",
  77         .prcm = {
  78                 .omap4 = {
  79                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  80                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  81                 },
  82         },
  83 };
  84
  85 /* l3_main_2 */
  86 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  87         .name           = "l3_main_2",
  88         .class          = &dra7xx_l3_hwmod_class,
  89         .clkdm_name     = "l3instr_clkdm",
  90         .prcm = {
  91                 .omap4 = {
  92                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  93                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  94                         .modulemode   = MODULEMODE_HWCTRL,
  95                 },
  96         },
  97 };
  98
  99 /*
 100  * 'l4' class
 101  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 102  */
 103 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 104         .name   = "l4",
 105 };
 106
 107 /* l4_cfg */
 108 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 109         .name           = "l4_cfg",
 110         .class          = &dra7xx_l4_hwmod_class,
 111         .clkdm_name     = "l4cfg_clkdm",
 112         .prcm = {
 113                 .omap4 = {
 114                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 115                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 116                 },
 117         },
 118 };
 119
 120 /* l4_per1 */
 121 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 122         .name           = "l4_per1",
 123         .class          = &dra7xx_l4_hwmod_class,
 124         .clkdm_name     = "l4per_clkdm",
 125         .prcm = {
 126                 .omap4 = {
 127                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 128                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 129                 },
 130         },
 131 };
 132
 133 /* l4_per2 */
 134 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 135         .name           = "l4_per2",
 136         .class          = &dra7xx_l4_hwmod_class,
 137         .clkdm_name     = "l4per2_clkdm",
 138         .prcm = {
 139                 .omap4 = {
 140                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 141                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 142                 },
 143         },
 144 };
 145
 146 /* l4_per3 */
 147 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 148         .name           = "l4_per3",
 149         .class          = &dra7xx_l4_hwmod_class,
 150         .clkdm_name     = "l4per3_clkdm",
 151         .prcm = {
 152                 .omap4 = {
 153                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 154                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 155                 },
 156         },
 157 };
 158
 159 /* l4_wkup */
 160 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 161         .name           = "l4_wkup",
 162         .class          = &dra7xx_l4_hwmod_class,
 163         .clkdm_name     = "wkupaon_clkdm",
 164         .prcm = {
 165                 .omap4 = {
 166                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 167                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 168                 },
 169         },
 170 };
 171
 172 /*
 173  * 'atl' class
 174  *
 175  */
 176
 177 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 178         .name   = "atl",
 179 };
 180
 181 /* atl */
 182 static struct omap_hwmod dra7xx_atl_hwmod = {
 183         .name           = "atl",
 184         .class          = &dra7xx_atl_hwmod_class,
 185         .clkdm_name     = "atl_clkdm",
 186         .main_clk       = "atl_gfclk_mux",
 187         .prcm = {
 188                 .omap4 = {
 189                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 190                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 191                         .modulemode   = MODULEMODE_SWCTRL,
 192                 },
 193         },
 194 };
 195
 196 /*
 197  * 'bb2d' class
 198  *
 199  */
 200
 201 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 202         .name   = "bb2d",
 203 };
 204
 205 /* bb2d */
 206 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 207         .name           = "bb2d",
 208         .class          = &dra7xx_bb2d_hwmod_class,
 209         .clkdm_name     = "dss_clkdm",
 210         .main_clk       = "dpll_core_h24x2_ck",
 211         .prcm = {
 212                 .omap4 = {
 213                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 214                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 215                         .modulemode   = MODULEMODE_SWCTRL,
 216                 },
 217         },
 218 };
 219
 220 /*
 221  * 'counter' class
 222  *
 223  */
 224
 225 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 226         .rev_offs       = 0x0000,
 227         .sysc_offs      = 0x0010,
 228         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 229         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 230                            SIDLE_SMART_WKUP),
 231         .sysc_fields    = &omap_hwmod_sysc_type1,
 232 };
 233
 234 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 235         .name   = "counter",
 236         .sysc   = &dra7xx_counter_sysc,
 237 };
 238
 239 /* counter_32k */
 240 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 241         .name           = "counter_32k",
 242         .class          = &dra7xx_counter_hwmod_class,
 243         .clkdm_name     = "wkupaon_clkdm",
 244         .flags          = HWMOD_SWSUP_SIDLE,
 245         .main_clk       = "wkupaon_iclk_mux",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 249                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'ctrl_module' class
 256  *
 257  */
 258
 259 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 260         .name   = "ctrl_module",
 261 };
 262
 263 /* ctrl_module_wkup */
 264 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 265         .name           = "ctrl_module_wkup",
 266         .class          = &dra7xx_ctrl_module_hwmod_class,
 267         .clkdm_name     = "wkupaon_clkdm",
 268         .prcm = {
 269                 .omap4 = {
 270                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 271                 },
 272         },
 273 };
 274
 275 /*
 276  * 'dcan' class
 277  *
 278  */
 279
 280 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 281         .name   = "dcan",
 282 };
 283
 284 /* dcan1 */
 285 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 286         .name           = "dcan1",
 287         .class          = &dra7xx_dcan_hwmod_class,
 288         .clkdm_name     = "wkupaon_clkdm",
 289         .main_clk       = "dcan1_sys_clk_mux",
 290         .prcm = {
 291                 .omap4 = {
 292                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 293                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 294                         .modulemode   = MODULEMODE_SWCTRL,
 295                 },
 296         },
 297 };
 298
 299 /* dcan2 */
 300 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 301         .name           = "dcan2",
 302         .class          = &dra7xx_dcan_hwmod_class,
 303         .clkdm_name     = "l4per2_clkdm",
 304         .main_clk       = "sys_clkin1",
 305         .prcm = {
 306                 .omap4 = {
 307                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 308                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 309                         .modulemode   = MODULEMODE_SWCTRL,
 310                 },
 311         },
 312 };
 313
 314 /*
 315  * 'dma' class
 316  *
 317  */
 318
 319 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 320         .rev_offs       = 0x0000,
 321         .sysc_offs      = 0x002c,
 322         .syss_offs      = 0x0028,
 323         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 324                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 325                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 326                            SYSS_HAS_RESET_STATUS),
 327         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 328                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 329                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 330         .sysc_fields    = &omap_hwmod_sysc_type1,
 331 };
 332
 333 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 334         .name   = "dma",
 335         .sysc   = &dra7xx_dma_sysc,
 336 };
 337
 338 /* dma dev_attr */
 339 static struct omap_dma_dev_attr dma_dev_attr = {
 340         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 341                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 342         .lch_count      = 32,
 343 };
 344
 345 /* dma_system */
 346 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
 347         { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
 348         { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
 349         { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
 350         { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
 351         { .irq = -1 }
 352 };
 353
 354 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 355         .name           = "dma_system",
 356         .class          = &dra7xx_dma_hwmod_class,
 357         .clkdm_name     = "dma_clkdm",
 358         .mpu_irqs       = dra7xx_dma_system_irqs,
 359         .main_clk       = "l3_iclk_div",
 360         .prcm = {
 361                 .omap4 = {
 362                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 363                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 364                 },
 365         },
 366         .dev_attr       = &dma_dev_attr,
 367 };
 368
 369 /*
 370  * 'dss' class
 371  *
 372  */
 373
 374 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 375         .rev_offs       = 0x0000,
 376         .syss_offs      = 0x0014,
 377         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 378 };
 379
 380 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 381         .name   = "dss",
 382         .sysc   = &dra7xx_dss_sysc,
 383         .reset  = omap_dss_reset,
 384 };
 385
 386 /* dss */
 387 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 388         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 389         { .dma_req = -1 }
 390 };
 391
 392 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 393         { .role = "dss_clk", .clk = "dss_dss_clk" },
 394         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 395         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 396         { .role = "video2_clk", .clk = "dss_video2_clk" },
 397         { .role = "video1_clk", .clk = "dss_video1_clk" },
 398         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 399 };
 400
 401 static struct omap_hwmod dra7xx_dss_hwmod = {
 402         .name           = "dss_core",
 403         .class          = &dra7xx_dss_hwmod_class,
 404         .clkdm_name     = "dss_clkdm",
 405         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 406         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 407         .main_clk       = "dss_dss_clk",
 408         .prcm = {
 409                 .omap4 = {
 410                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 411                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 412                         .modulemode   = MODULEMODE_SWCTRL,
 413                 },
 414         },
 415         .opt_clks       = dss_opt_clks,
 416         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 417 };
 418
 419 /*
 420  * 'dispc' class
 421  * display controller
 422  */
 423
 424 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 425         .rev_offs       = 0x0000,
 426         .sysc_offs      = 0x0010,
 427         .syss_offs      = 0x0014,
 428         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 429                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 430                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 431                            SYSS_HAS_RESET_STATUS),
 432         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 433                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 434         .sysc_fields    = &omap_hwmod_sysc_type1,
 435 };
 436
 437 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 438         .name   = "dispc",
 439         .sysc   = &dra7xx_dispc_sysc,
 440 };
 441
 442 /* dss_dispc */
 443 /* dss_dispc dev_attr */
 444 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 445         .has_framedonetv_irq    = 1,
 446         .manager_count          = 4,
 447 };
 448
 449 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 450         .name           = "dss_dispc",
 451         .class          = &dra7xx_dispc_hwmod_class,
 452         .clkdm_name     = "dss_clkdm",
 453         .main_clk       = "dss_dss_clk",
 454         .prcm = {
 455                 .omap4 = {
 456                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 457                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 458                 },
 459         },
 460         .dev_attr       = &dss_dispc_dev_attr,
 461 };
 462
 463 /*
 464  * 'hdmi' class
 465  * hdmi controller
 466  */
 467
 468 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 469         .rev_offs       = 0x0000,
 470         .sysc_offs      = 0x0010,
 471         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 472                            SYSC_HAS_SOFTRESET),
 473         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 474                            SIDLE_SMART_WKUP),
 475         .sysc_fields    = &omap_hwmod_sysc_type2,
 476 };
 477
 478 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 479         .name   = "hdmi",
 480         .sysc   = &dra7xx_hdmi_sysc,
 481 };
 482
 483 /* dss_hdmi */
 484
 485 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 486         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 487 };
 488
 489 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 490         .name           = "dss_hdmi",
 491         .class          = &dra7xx_hdmi_hwmod_class,
 492         .clkdm_name     = "dss_clkdm",
 493         .main_clk       = "dss_48mhz_clk",
 494         .prcm = {
 495                 .omap4 = {
 496                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 497                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 498                 },
 499         },
 500         .opt_clks       = dss_hdmi_opt_clks,
 501         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 502 };
 503
 504 /*
 505  * 'elm' class
 506  *
 507  */
 508
 509 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 510         .rev_offs       = 0x0000,
 511         .sysc_offs      = 0x0010,
 512         .syss_offs      = 0x0014,
 513         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 514                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 515                            SYSS_HAS_RESET_STATUS),
 516         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 517                            SIDLE_SMART_WKUP),
 518         .sysc_fields    = &omap_hwmod_sysc_type1,
 519 };
 520
 521 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 522         .name   = "elm",
 523         .sysc   = &dra7xx_elm_sysc,
 524 };
 525
 526 /* elm */
 527
 528 static struct omap_hwmod dra7xx_elm_hwmod = {
 529         .name           = "elm",
 530         .class          = &dra7xx_elm_hwmod_class,
 531         .clkdm_name     = "l4per_clkdm",
 532         .main_clk       = "l3_iclk_div",
 533         .prcm = {
 534                 .omap4 = {
 535                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 536                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 537                 },
 538         },
 539 };
 540
 541 /*
 542  * 'gpio' class
 543  *
 544  */
 545
 546 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 547         .rev_offs       = 0x0000,
 548         .sysc_offs      = 0x0010,
 549         .syss_offs      = 0x0114,
 550         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 551                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 552                            SYSS_HAS_RESET_STATUS),
 553         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 554                            SIDLE_SMART_WKUP),
 555         .sysc_fields    = &omap_hwmod_sysc_type1,
 556 };
 557
 558 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 559         .name   = "gpio",
 560         .sysc   = &dra7xx_gpio_sysc,
 561         .rev    = 2,
 562 };
 563
 564 /* gpio dev_attr */
 565 static struct omap_gpio_dev_attr gpio_dev_attr = {
 566         .bank_width     = 32,
 567         .dbck_flag      = true,
 568 };
 569
 570 /* gpio1 */
 571 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 572         { .role = "dbclk", .clk = "gpio1_dbclk" },
 573 };
 574
 575 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 576         .name           = "gpio1",
 577         .class          = &dra7xx_gpio_hwmod_class,
 578         .clkdm_name     = "wkupaon_clkdm",
 579         .main_clk       = "wkupaon_iclk_mux",
 580         .prcm = {
 581                 .omap4 = {
 582                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 583                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 584                         .modulemode   = MODULEMODE_HWCTRL,
 585                 },
 586         },
 587         .opt_clks       = gpio1_opt_clks,
 588         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 589         .dev_attr       = &gpio_dev_attr,
 590 };
 591
 592 /* gpio2 */
 593 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 594         { .role = "dbclk", .clk = "gpio2_dbclk" },
 595 };
 596
 597 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 598         .name           = "gpio2",
 599         .class          = &dra7xx_gpio_hwmod_class,
 600         .clkdm_name     = "l4per_clkdm",
 601         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 602         .main_clk       = "l3_iclk_div",
 603         .prcm = {
 604                 .omap4 = {
 605                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 606                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 607                         .modulemode   = MODULEMODE_HWCTRL,
 608                 },
 609         },
 610         .opt_clks       = gpio2_opt_clks,
 611         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 612         .dev_attr       = &gpio_dev_attr,
 613 };
 614
 615 /* gpio3 */
 616 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 617         { .role = "dbclk", .clk = "gpio3_dbclk" },
 618 };
 619
 620 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 621         .name           = "gpio3",
 622         .class          = &dra7xx_gpio_hwmod_class,
 623         .clkdm_name     = "l4per_clkdm",
 624         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 625         .main_clk       = "l3_iclk_div",
 626         .prcm = {
 627                 .omap4 = {
 628                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 629                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 630                         .modulemode   = MODULEMODE_HWCTRL,
 631                 },
 632         },
 633         .opt_clks       = gpio3_opt_clks,
 634         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 635         .dev_attr       = &gpio_dev_attr,
 636 };
 637
 638 /* gpio4 */
 639 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 640         { .role = "dbclk", .clk = "gpio4_dbclk" },
 641 };
 642
 643 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 644         .name           = "gpio4",
 645         .class          = &dra7xx_gpio_hwmod_class,
 646         .clkdm_name     = "l4per_clkdm",
 647         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 648         .main_clk       = "l3_iclk_div",
 649         .prcm = {
 650                 .omap4 = {
 651                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 652                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 653                         .modulemode   = MODULEMODE_HWCTRL,
 654                 },
 655         },
 656         .opt_clks       = gpio4_opt_clks,
 657         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 658         .dev_attr       = &gpio_dev_attr,
 659 };
 660
 661 /* gpio5 */
 662 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 663         { .role = "dbclk", .clk = "gpio5_dbclk" },
 664 };
 665
 666 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 667         .name           = "gpio5",
 668         .class          = &dra7xx_gpio_hwmod_class,
 669         .clkdm_name     = "l4per_clkdm",
 670         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 671         .main_clk       = "l3_iclk_div",
 672         .prcm = {
 673                 .omap4 = {
 674                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 675                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 676                         .modulemode   = MODULEMODE_HWCTRL,
 677                 },
 678         },
 679         .opt_clks       = gpio5_opt_clks,
 680         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 681         .dev_attr       = &gpio_dev_attr,
 682 };
 683
 684 /* gpio6 */
 685 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 686         { .role = "dbclk", .clk = "gpio6_dbclk" },
 687 };
 688
 689 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 690         .name           = "gpio6",
 691         .class          = &dra7xx_gpio_hwmod_class,
 692         .clkdm_name     = "l4per_clkdm",
 693         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 694         .main_clk       = "l3_iclk_div",
 695         .prcm = {
 696                 .omap4 = {
 697                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 698                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 699                         .modulemode   = MODULEMODE_HWCTRL,
 700                 },
 701         },
 702         .opt_clks       = gpio6_opt_clks,
 703         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 704         .dev_attr       = &gpio_dev_attr,
 705 };
 706
 707 /* gpio7 */
 708 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 709         { .role = "dbclk", .clk = "gpio7_dbclk" },
 710 };
 711
 712 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 713         .name           = "gpio7",
 714         .class          = &dra7xx_gpio_hwmod_class,
 715         .clkdm_name     = "l4per_clkdm",
 716         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 717         .main_clk       = "l3_iclk_div",
 718         .prcm = {
 719                 .omap4 = {
 720                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 721                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 722                         .modulemode   = MODULEMODE_HWCTRL,
 723                 },
 724         },
 725         .opt_clks       = gpio7_opt_clks,
 726         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 727         .dev_attr       = &gpio_dev_attr,
 728 };
 729
 730 /* gpio8 */
 731 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 732         { .role = "dbclk", .clk = "gpio8_dbclk" },
 733 };
 734
 735 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 736         .name           = "gpio8",
 737         .class          = &dra7xx_gpio_hwmod_class,
 738         .clkdm_name     = "l4per_clkdm",
 739         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 740         .main_clk       = "l3_iclk_div",
 741         .prcm = {
 742                 .omap4 = {
 743                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 744                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 745                         .modulemode   = MODULEMODE_HWCTRL,
 746                 },
 747         },
 748         .opt_clks       = gpio8_opt_clks,
 749         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 750         .dev_attr       = &gpio_dev_attr,
 751 };
 752
 753 /*
 754  * 'gpmc' class
 755  *
 756  */
 757
 758 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 759         .rev_offs       = 0x0000,
 760         .sysc_offs      = 0x0010,
 761         .syss_offs      = 0x0014,
 762         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 763                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 764         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 765                            SIDLE_SMART_WKUP),
 766         .sysc_fields    = &omap_hwmod_sysc_type1,
 767 };
 768
 769 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 770         .name   = "gpmc",
 771         .sysc   = &dra7xx_gpmc_sysc,
 772 };
 773
 774 /* gpmc */
 775
 776 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 777         .name           = "gpmc",
 778         .class          = &dra7xx_gpmc_hwmod_class,
 779         .clkdm_name     = "l3main1_clkdm",
 780         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 781         .main_clk       = "l3_iclk_div",
 782         .prcm = {
 783                 .omap4 = {
 784                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 785                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 786                         .modulemode   = MODULEMODE_HWCTRL,
 787                 },
 788         },
 789 };
 790
 791 /*
 792  * 'hdq1w' class
 793  *
 794  */
 795
 796 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 797         .rev_offs       = 0x0000,
 798         .sysc_offs      = 0x0014,
 799         .syss_offs      = 0x0018,
 800         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 801                            SYSS_HAS_RESET_STATUS),
 802         .sysc_fields    = &omap_hwmod_sysc_type1,
 803 };
 804
 805 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 806         .name   = "hdq1w",
 807         .sysc   = &dra7xx_hdq1w_sysc,
 808 };
 809
 810 /* hdq1w */
 811
 812 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 813         .name           = "hdq1w",
 814         .class          = &dra7xx_hdq1w_hwmod_class,
 815         .clkdm_name     = "l4per_clkdm",
 816         .flags          = HWMOD_INIT_NO_RESET,
 817         .main_clk       = "func_12m_fclk",
 818         .prcm = {
 819                 .omap4 = {
 820                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 821                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 822                         .modulemode   = MODULEMODE_SWCTRL,
 823                 },
 824         },
 825 };
 826
 827 /*
 828  * 'i2c' class
 829  *
 830  */
 831
 832 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
 833         .sysc_offs      = 0x0010,
 834         .syss_offs      = 0x0090,
 835         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 836                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 837                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 838         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 839                            SIDLE_SMART_WKUP),
 840         .clockact       = CLOCKACT_TEST_ICLK,
 841         .sysc_fields    = &omap_hwmod_sysc_type1,
 842 };
 843
 844 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
 845         .name   = "i2c",
 846         .sysc   = &dra7xx_i2c_sysc,
 847         .reset  = &omap_i2c_reset,
 848         .rev    = OMAP_I2C_IP_VERSION_2,
 849 };
 850
 851 /* i2c dev_attr */
 852 static struct omap_i2c_dev_attr i2c_dev_attr = {
 853         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 854 };
 855
 856 /* i2c1 */
 857 static struct omap_hwmod dra7xx_i2c1_hwmod = {
 858         .name           = "i2c1",
 859         .class          = &dra7xx_i2c_hwmod_class,
 860         .clkdm_name     = "l4per_clkdm",
 861         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 862         .main_clk       = "func_96m_fclk",
 863         .prcm = {
 864                 .omap4 = {
 865                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 866                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 867                         .modulemode   = MODULEMODE_SWCTRL,
 868                 },
 869         },
 870         .dev_attr       = &i2c_dev_attr,
 871 };
 872
 873 /* i2c2 */
 874 static struct omap_hwmod dra7xx_i2c2_hwmod = {
 875         .name           = "i2c2",
 876         .class          = &dra7xx_i2c_hwmod_class,
 877         .clkdm_name     = "l4per_clkdm",
 878         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 879         .main_clk       = "func_96m_fclk",
 880         .prcm = {
 881                 .omap4 = {
 882                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 883                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 884                         .modulemode   = MODULEMODE_SWCTRL,
 885                 },
 886         },
 887         .dev_attr       = &i2c_dev_attr,
 888 };
 889
 890 /* i2c3 */
 891 static struct omap_hwmod dra7xx_i2c3_hwmod = {
 892         .name           = "i2c3",
 893         .class          = &dra7xx_i2c_hwmod_class,
 894         .clkdm_name     = "l4per_clkdm",
 895         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 896         .main_clk       = "func_96m_fclk",
 897         .prcm = {
 898                 .omap4 = {
 899                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 900                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 901                         .modulemode   = MODULEMODE_SWCTRL,
 902                 },
 903         },
 904         .dev_attr       = &i2c_dev_attr,
 905 };
 906
 907 /* i2c4 */
 908 static struct omap_hwmod dra7xx_i2c4_hwmod = {
 909         .name           = "i2c4",
 910         .class          = &dra7xx_i2c_hwmod_class,
 911         .clkdm_name     = "l4per_clkdm",
 912         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 913         .main_clk       = "func_96m_fclk",
 914         .prcm = {
 915                 .omap4 = {
 916                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 917                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 918                         .modulemode   = MODULEMODE_SWCTRL,
 919                 },
 920         },
 921         .dev_attr       = &i2c_dev_attr,
 922 };
 923
 924 /* i2c5 */
 925 static struct omap_hwmod dra7xx_i2c5_hwmod = {
 926         .name           = "i2c5",
 927         .class          = &dra7xx_i2c_hwmod_class,
 928         .clkdm_name     = "ipu_clkdm",
 929         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 930         .main_clk       = "func_96m_fclk",
 931         .prcm = {
 932                 .omap4 = {
 933                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
 934                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
 935                         .modulemode   = MODULEMODE_SWCTRL,
 936                 },
 937         },
 938         .dev_attr       = &i2c_dev_attr,
 939 };
 940
 941 /*
 942  * 'mcspi' class
 943  *
 944  */
 945
 946 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
 947         .rev_offs       = 0x0000,
 948         .sysc_offs      = 0x0010,
 949         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 950                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 951         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 952                            SIDLE_SMART_WKUP),
 953         .sysc_fields    = &omap_hwmod_sysc_type2,
 954 };
 955
 956 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
 957         .name   = "mcspi",
 958         .sysc   = &dra7xx_mcspi_sysc,
 959         .rev    = OMAP4_MCSPI_REV,
 960 };
 961
 962 /* mcspi1 */
 963 /* mcspi1 dev_attr */
 964 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
 965         .num_chipselect = 4,
 966 };
 967
 968 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
 969         .name           = "mcspi1",
 970         .class          = &dra7xx_mcspi_hwmod_class,
 971         .clkdm_name     = "l4per_clkdm",
 972         .main_clk       = "func_48m_fclk",
 973         .prcm = {
 974                 .omap4 = {
 975                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
 976                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
 977                         .modulemode   = MODULEMODE_SWCTRL,
 978                 },
 979         },
 980         .dev_attr       = &mcspi1_dev_attr,
 981 };
 982
 983 /* mcspi2 */
 984 /* mcspi2 dev_attr */
 985 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
 986         .num_chipselect = 2,
 987 };
 988
 989 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
 990         .name           = "mcspi2",
 991         .class          = &dra7xx_mcspi_hwmod_class,
 992         .clkdm_name     = "l4per_clkdm",
 993         .main_clk       = "func_48m_fclk",
 994         .prcm = {
 995                 .omap4 = {
 996                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
 997                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
 998                         .modulemode   = MODULEMODE_SWCTRL,
 999                 },
1000         },
1001         .dev_attr       = &mcspi2_dev_attr,
1002 };
1003
1004 /* mcspi3 */
1005 /* mcspi3 dev_attr */
1006 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007         .num_chipselect = 2,
1008 };
1009
1010 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011         .name           = "mcspi3",
1012         .class          = &dra7xx_mcspi_hwmod_class,
1013         .clkdm_name     = "l4per_clkdm",
1014         .main_clk       = "func_48m_fclk",
1015         .prcm = {
1016                 .omap4 = {
1017                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019                         .modulemode   = MODULEMODE_SWCTRL,
1020                 },
1021         },
1022         .dev_attr       = &mcspi3_dev_attr,
1023 };
1024
1025 /* mcspi4 */
1026 /* mcspi4 dev_attr */
1027 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028         .num_chipselect = 1,
1029 };
1030
1031 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032         .name           = "mcspi4",
1033         .class          = &dra7xx_mcspi_hwmod_class,
1034         .clkdm_name     = "l4per_clkdm",
1035         .main_clk       = "func_48m_fclk",
1036         .prcm = {
1037                 .omap4 = {
1038                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040                         .modulemode   = MODULEMODE_SWCTRL,
1041                 },
1042         },
1043         .dev_attr       = &mcspi4_dev_attr,
1044 };
1045
1046 /*
1047  * 'mmc' class
1048  *
1049  */
1050
1051 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052         .rev_offs       = 0x0000,
1053         .sysc_offs      = 0x0010,
1054         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056                            SYSC_HAS_SOFTRESET),
1057         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060         .sysc_fields    = &omap_hwmod_sysc_type2,
1061 };
1062
1063 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064         .name   = "mmc",
1065         .sysc   = &dra7xx_mmc_sysc,
1066 };
1067
1068 /* mmc1 */
1069 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070         { .role = "clk32k", .clk = "mmc1_clk32k" },
1071 };
1072
1073 /* mmc1 dev_attr */
1074 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076 };
1077
1078 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079         .name           = "mmc1",
1080         .class          = &dra7xx_mmc_hwmod_class,
1081         .clkdm_name     = "l3init_clkdm",
1082         .main_clk       = "mmc1_fclk_div",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .opt_clks       = mmc1_opt_clks,
1091         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1092         .dev_attr       = &mmc1_dev_attr,
1093 };
1094
1095 /* mmc2 */
1096 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097         { .role = "clk32k", .clk = "mmc2_clk32k" },
1098 };
1099
1100 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101         .name           = "mmc2",
1102         .class          = &dra7xx_mmc_hwmod_class,
1103         .clkdm_name     = "l3init_clkdm",
1104         .main_clk       = "mmc2_fclk_div",
1105         .prcm = {
1106                 .omap4 = {
1107                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109                         .modulemode   = MODULEMODE_SWCTRL,
1110                 },
1111         },
1112         .opt_clks       = mmc2_opt_clks,
1113         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1114 };
1115
1116 /* mmc3 */
1117 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118         { .role = "clk32k", .clk = "mmc3_clk32k" },
1119 };
1120
1121 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122         .name           = "mmc3",
1123         .class          = &dra7xx_mmc_hwmod_class,
1124         .clkdm_name     = "l4per_clkdm",
1125         .main_clk       = "mmc3_gfclk_div",
1126         .prcm = {
1127                 .omap4 = {
1128                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130                         .modulemode   = MODULEMODE_SWCTRL,
1131                 },
1132         },
1133         .opt_clks       = mmc3_opt_clks,
1134         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1135 };
1136
1137 /* mmc4 */
1138 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139         { .role = "clk32k", .clk = "mmc4_clk32k" },
1140 };
1141
1142 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143         .name           = "mmc4",
1144         .class          = &dra7xx_mmc_hwmod_class,
1145         .clkdm_name     = "l4per_clkdm",
1146         .main_clk       = "mmc4_gfclk_div",
1147         .prcm = {
1148                 .omap4 = {
1149                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151                         .modulemode   = MODULEMODE_SWCTRL,
1152                 },
1153         },
1154         .opt_clks       = mmc4_opt_clks,
1155         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1156 };
1157
1158 /*
1159  * 'mpu' class
1160  *
1161  */
1162
1163 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164         .name   = "mpu",
1165 };
1166
1167 /* mpu */
1168 static struct omap_hwmod dra7xx_mpu_hwmod = {
1169         .name           = "mpu",
1170         .class          = &dra7xx_mpu_hwmod_class,
1171         .clkdm_name     = "mpu_clkdm",
1172         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173         .main_clk       = "dpll_mpu_m2_ck",
1174         .prcm = {
1175                 .omap4 = {
1176                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178                 },
1179         },
1180 };
1181
1182 /*
1183  * 'ocp2scp' class
1184  *
1185  */
1186
1187 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188         .rev_offs       = 0x0000,
1189         .sysc_offs      = 0x0010,
1190         .syss_offs      = 0x0014,
1191         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194                            SIDLE_SMART_WKUP),
1195         .sysc_fields    = &omap_hwmod_sysc_type1,
1196 };
1197
1198 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199         .name   = "ocp2scp",
1200         .sysc   = &dra7xx_ocp2scp_sysc,
1201 };
1202
1203 /* ocp2scp1 */
1204 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205         .name           = "ocp2scp1",
1206         .class          = &dra7xx_ocp2scp_hwmod_class,
1207         .clkdm_name     = "l3init_clkdm",
1208         .main_clk       = "l4_root_clk_div",
1209         .prcm = {
1210                 .omap4 = {
1211                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213                         .modulemode   = MODULEMODE_HWCTRL,
1214                 },
1215         },
1216 };
1217
1218 /*
1219  * 'qspi' class
1220  *
1221  */
1222
1223 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224         .sysc_offs      = 0x0010,
1225         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1226         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227                            SIDLE_SMART_WKUP),
1228         .sysc_fields    = &omap_hwmod_sysc_type2,
1229 };
1230
1231 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232         .name   = "qspi",
1233         .sysc   = &dra7xx_qspi_sysc,
1234 };
1235
1236 /* qspi */
1237 static struct omap_hwmod dra7xx_qspi_hwmod = {
1238         .name           = "qspi",
1239         .class          = &dra7xx_qspi_hwmod_class,
1240         .clkdm_name     = "l4per2_clkdm",
1241         .main_clk       = "qspi_gfclk_div",
1242         .prcm = {
1243                 .omap4 = {
1244                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246                         .modulemode   = MODULEMODE_SWCTRL,
1247                 },
1248         },
1249 };
1250
1251 /*
1252  * 'sata' class
1253  *
1254  */
1255
1256 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257         .sysc_offs      = 0x0000,
1258         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262         .sysc_fields    = &omap_hwmod_sysc_type2,
1263 };
1264
1265 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266         .name   = "sata",
1267         .sysc   = &dra7xx_sata_sysc,
1268 };
1269
1270 /* sata */
1271 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272         { .role = "ref_clk", .clk = "sata_ref_clk" },
1273 };
1274
1275 static struct omap_hwmod dra7xx_sata_hwmod = {
1276         .name           = "sata",
1277         .class          = &dra7xx_sata_hwmod_class,
1278         .clkdm_name     = "l3init_clkdm",
1279         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280         .main_clk       = "func_48m_fclk",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_SWCTRL,
1286                 },
1287         },
1288         .opt_clks       = sata_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(sata_opt_clks),
1290 };
1291
1292 /*
1293  * 'smartreflex' class
1294  *
1295  */
1296
1297 /* The IP is not compliant to type1 / type2 scheme */
1298 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299         .sidle_shift    = 24,
1300         .enwkup_shift   = 26,
1301 };
1302
1303 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304         .sysc_offs      = 0x0038,
1305         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307                            SIDLE_SMART_WKUP),
1308         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1309 };
1310
1311 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312         .name   = "smartreflex",
1313         .sysc   = &dra7xx_smartreflex_sysc,
1314         .rev    = 2,
1315 };
1316
1317 /* smartreflex_core */
1318 /* smartreflex_core dev_attr */
1319 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320         .sensor_voltdm_name     = "core",
1321 };
1322
1323 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324         .name           = "smartreflex_core",
1325         .class          = &dra7xx_smartreflex_hwmod_class,
1326         .clkdm_name     = "coreaon_clkdm",
1327         .main_clk       = "wkupaon_iclk_mux",
1328         .prcm = {
1329                 .omap4 = {
1330                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332                         .modulemode   = MODULEMODE_SWCTRL,
1333                 },
1334         },
1335         .dev_attr       = &smartreflex_core_dev_attr,
1336 };
1337
1338 /* smartreflex_mpu */
1339 /* smartreflex_mpu dev_attr */
1340 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341         .sensor_voltdm_name     = "mpu",
1342 };
1343
1344 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345         .name           = "smartreflex_mpu",
1346         .class          = &dra7xx_smartreflex_hwmod_class,
1347         .clkdm_name     = "coreaon_clkdm",
1348         .main_clk       = "wkupaon_iclk_mux",
1349         .prcm = {
1350                 .omap4 = {
1351                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353                         .modulemode   = MODULEMODE_SWCTRL,
1354                 },
1355         },
1356         .dev_attr       = &smartreflex_mpu_dev_attr,
1357 };
1358
1359 /*
1360  * 'spinlock' class
1361  *
1362  */
1363
1364 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365         .rev_offs       = 0x0000,
1366         .sysc_offs      = 0x0010,
1367         .syss_offs      = 0x0014,
1368         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1370                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1371         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1372                            SIDLE_SMART_WKUP),
1373         .sysc_fields    = &omap_hwmod_sysc_type1,
1374 };
1375
1376 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1377         .name   = "spinlock",
1378         .sysc   = &dra7xx_spinlock_sysc,
1379 };
1380
1381 /* spinlock */
1382 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1383         .name           = "spinlock",
1384         .class          = &dra7xx_spinlock_hwmod_class,
1385         .clkdm_name     = "l4cfg_clkdm",
1386         .main_clk       = "l3_iclk_div",
1387         .prcm = {
1388                 .omap4 = {
1389                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1390                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1391                 },
1392         },
1393 };
1394
1395 /*
1396  * 'timer' class
1397  *
1398  * This class contains several variants: ['timer_1ms', 'timer_secure',
1399  * 'timer']
1400  */
1401
1402 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1403         .rev_offs       = 0x0000,
1404         .sysc_offs      = 0x0010,
1405         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1406                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408                            SIDLE_SMART_WKUP),
1409         .sysc_fields    = &omap_hwmod_sysc_type2,
1410 };
1411
1412 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1413         .name   = "timer",
1414         .sysc   = &dra7xx_timer_1ms_sysc,
1415 };
1416
1417 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1418         .rev_offs       = 0x0000,
1419         .sysc_offs      = 0x0010,
1420         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1421                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1422         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423                            SIDLE_SMART_WKUP),
1424         .sysc_fields    = &omap_hwmod_sysc_type2,
1425 };
1426
1427 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1428         .name   = "timer",
1429         .sysc   = &dra7xx_timer_secure_sysc,
1430 };
1431
1432 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1433         .rev_offs       = 0x0000,
1434         .sysc_offs      = 0x0010,
1435         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1436                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1437         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438                            SIDLE_SMART_WKUP),
1439         .sysc_fields    = &omap_hwmod_sysc_type2,
1440 };
1441
1442 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1443         .name   = "timer",
1444         .sysc   = &dra7xx_timer_sysc,
1445 };
1446
1447 /* timer1 */
1448 static struct omap_hwmod dra7xx_timer1_hwmod = {
1449         .name           = "timer1",
1450         .class          = &dra7xx_timer_1ms_hwmod_class,
1451         .clkdm_name     = "wkupaon_clkdm",
1452         .main_clk       = "timer1_gfclk_mux",
1453         .prcm = {
1454                 .omap4 = {
1455                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1456                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1457                         .modulemode   = MODULEMODE_SWCTRL,
1458                 },
1459         },
1460 };
1461
1462 /* timer2 */
1463 static struct omap_hwmod dra7xx_timer2_hwmod = {
1464         .name           = "timer2",
1465         .class          = &dra7xx_timer_1ms_hwmod_class,
1466         .clkdm_name     = "l4per_clkdm",
1467         .main_clk       = "timer2_gfclk_mux",
1468         .prcm = {
1469                 .omap4 = {
1470                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1471                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1472                         .modulemode   = MODULEMODE_SWCTRL,
1473                 },
1474         },
1475 };
1476
1477 /* timer3 */
1478 static struct omap_hwmod dra7xx_timer3_hwmod = {
1479         .name           = "timer3",
1480         .class          = &dra7xx_timer_hwmod_class,
1481         .clkdm_name     = "l4per_clkdm",
1482         .main_clk       = "timer3_gfclk_mux",
1483         .prcm = {
1484                 .omap4 = {
1485                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1486                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1487                         .modulemode   = MODULEMODE_SWCTRL,
1488                 },
1489         },
1490 };
1491
1492 /* timer4 */
1493 static struct omap_hwmod dra7xx_timer4_hwmod = {
1494         .name           = "timer4",
1495         .class          = &dra7xx_timer_secure_hwmod_class,
1496         .clkdm_name     = "l4per_clkdm",
1497         .main_clk       = "timer4_gfclk_mux",
1498         .prcm = {
1499                 .omap4 = {
1500                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1501                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1502                         .modulemode   = MODULEMODE_SWCTRL,
1503                 },
1504         },
1505 };
1506
1507 /* timer5 */
1508 static struct omap_hwmod dra7xx_timer5_hwmod = {
1509         .name           = "timer5",
1510         .class          = &dra7xx_timer_hwmod_class,
1511         .clkdm_name     = "ipu_clkdm",
1512         .main_clk       = "timer5_gfclk_mux",
1513         .prcm = {
1514                 .omap4 = {
1515                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1516                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1517                         .modulemode   = MODULEMODE_SWCTRL,
1518                 },
1519         },
1520 };
1521
1522 /* timer6 */
1523 static struct omap_hwmod dra7xx_timer6_hwmod = {
1524         .name           = "timer6",
1525         .class          = &dra7xx_timer_hwmod_class,
1526         .clkdm_name     = "ipu_clkdm",
1527         .main_clk       = "timer6_gfclk_mux",
1528         .prcm = {
1529                 .omap4 = {
1530                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1531                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1532                         .modulemode   = MODULEMODE_SWCTRL,
1533                 },
1534         },
1535 };
1536
1537 /* timer7 */
1538 static struct omap_hwmod dra7xx_timer7_hwmod = {
1539         .name           = "timer7",
1540         .class          = &dra7xx_timer_hwmod_class,
1541         .clkdm_name     = "ipu_clkdm",
1542         .main_clk       = "timer7_gfclk_mux",
1543         .prcm = {
1544                 .omap4 = {
1545                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1546                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1547                         .modulemode   = MODULEMODE_SWCTRL,
1548                 },
1549         },
1550 };
1551
1552 /* timer8 */
1553 static struct omap_hwmod dra7xx_timer8_hwmod = {
1554         .name           = "timer8",
1555         .class          = &dra7xx_timer_hwmod_class,
1556         .clkdm_name     = "ipu_clkdm",
1557         .main_clk       = "timer8_gfclk_mux",
1558         .prcm = {
1559                 .omap4 = {
1560                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1561                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1562                         .modulemode   = MODULEMODE_SWCTRL,
1563                 },
1564         },
1565 };
1566
1567 /* timer9 */
1568 static struct omap_hwmod dra7xx_timer9_hwmod = {
1569         .name           = "timer9",
1570         .class          = &dra7xx_timer_hwmod_class,
1571         .clkdm_name     = "l4per_clkdm",
1572         .main_clk       = "timer9_gfclk_mux",
1573         .prcm = {
1574                 .omap4 = {
1575                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1576                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1577                         .modulemode   = MODULEMODE_SWCTRL,
1578                 },
1579         },
1580 };
1581
1582 /* timer10 */
1583 static struct omap_hwmod dra7xx_timer10_hwmod = {
1584         .name           = "timer10",
1585         .class          = &dra7xx_timer_1ms_hwmod_class,
1586         .clkdm_name     = "l4per_clkdm",
1587         .main_clk       = "timer10_gfclk_mux",
1588         .prcm = {
1589                 .omap4 = {
1590                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1591                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1592                         .modulemode   = MODULEMODE_SWCTRL,
1593                 },
1594         },
1595 };
1596
1597 /* timer11 */
1598 static struct omap_hwmod dra7xx_timer11_hwmod = {
1599         .name           = "timer11",
1600         .class          = &dra7xx_timer_hwmod_class,
1601         .clkdm_name     = "l4per_clkdm",
1602         .main_clk       = "timer11_gfclk_mux",
1603         .prcm = {
1604                 .omap4 = {
1605                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1606                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1607                         .modulemode   = MODULEMODE_SWCTRL,
1608                 },
1609         },
1610 };
1611
1612 /*
1613  * 'uart' class
1614  *
1615  */
1616
1617 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1618         .rev_offs       = 0x0050,
1619         .sysc_offs      = 0x0054,
1620         .syss_offs      = 0x0058,
1621         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1622                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1623                            SYSS_HAS_RESET_STATUS),
1624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625                            SIDLE_SMART_WKUP),
1626         .sysc_fields    = &omap_hwmod_sysc_type1,
1627 };
1628
1629 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1630         .name   = "uart",
1631         .sysc   = &dra7xx_uart_sysc,
1632 };
1633
1634 /* uart1 */
1635 static struct omap_hwmod dra7xx_uart1_hwmod = {
1636         .name           = "uart1",
1637         .class          = &dra7xx_uart_hwmod_class,
1638         .clkdm_name     = "l4per_clkdm",
1639         .main_clk       = "uart1_gfclk_mux",
1640         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1641         .prcm = {
1642                 .omap4 = {
1643                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1644                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1645                         .modulemode   = MODULEMODE_SWCTRL,
1646                 },
1647         },
1648 };
1649
1650 /* uart2 */
1651 static struct omap_hwmod dra7xx_uart2_hwmod = {
1652         .name           = "uart2",
1653         .class          = &dra7xx_uart_hwmod_class,
1654         .clkdm_name     = "l4per_clkdm",
1655         .main_clk       = "uart2_gfclk_mux",
1656         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1657         .prcm = {
1658                 .omap4 = {
1659                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1660                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1661                         .modulemode   = MODULEMODE_SWCTRL,
1662                 },
1663         },
1664 };
1665
1666 /* uart3 */
1667 static struct omap_hwmod dra7xx_uart3_hwmod = {
1668         .name           = "uart3",
1669         .class          = &dra7xx_uart_hwmod_class,
1670         .clkdm_name     = "l4per_clkdm",
1671         .main_clk       = "uart3_gfclk_mux",
1672         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1673         .prcm = {
1674                 .omap4 = {
1675                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1676                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1677                         .modulemode   = MODULEMODE_SWCTRL,
1678                 },
1679         },
1680 };
1681
1682 /* uart4 */
1683 static struct omap_hwmod dra7xx_uart4_hwmod = {
1684         .name           = "uart4",
1685         .class          = &dra7xx_uart_hwmod_class,
1686         .clkdm_name     = "l4per_clkdm",
1687         .main_clk       = "uart4_gfclk_mux",
1688         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1689         .prcm = {
1690                 .omap4 = {
1691                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1692                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1693                         .modulemode   = MODULEMODE_SWCTRL,
1694                 },
1695         },
1696 };
1697
1698 /* uart5 */
1699 static struct omap_hwmod dra7xx_uart5_hwmod = {
1700         .name           = "uart5",
1701         .class          = &dra7xx_uart_hwmod_class,
1702         .clkdm_name     = "l4per_clkdm",
1703         .main_clk       = "uart5_gfclk_mux",
1704         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1708                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1709                         .modulemode   = MODULEMODE_SWCTRL,
1710                 },
1711         },
1712 };
1713
1714 /* uart6 */
1715 static struct omap_hwmod dra7xx_uart6_hwmod = {
1716         .name           = "uart6",
1717         .class          = &dra7xx_uart_hwmod_class,
1718         .clkdm_name     = "ipu_clkdm",
1719         .main_clk       = "uart6_gfclk_mux",
1720         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1721         .prcm = {
1722                 .omap4 = {
1723                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1724                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1725                         .modulemode   = MODULEMODE_SWCTRL,
1726                 },
1727         },
1728 };
1729
1730 /*
1731  * 'usb_otg_ss' class
1732  *
1733  */
1734
1735 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1736         .name   = "usb_otg_ss",
1737 };
1738
1739 /* usb_otg_ss1 */
1740 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1741         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1742 };
1743
1744 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1745         .name           = "usb_otg_ss1",
1746         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1747         .clkdm_name     = "l3init_clkdm",
1748         .main_clk       = "dpll_core_h13x2_ck",
1749         .prcm = {
1750                 .omap4 = {
1751                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1752                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1753                         .modulemode   = MODULEMODE_HWCTRL,
1754                 },
1755         },
1756         .opt_clks       = usb_otg_ss1_opt_clks,
1757         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1758 };
1759
1760 /* usb_otg_ss2 */
1761 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1762         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1763 };
1764
1765 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1766         .name           = "usb_otg_ss2",
1767         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1768         .clkdm_name     = "l3init_clkdm",
1769         .main_clk       = "dpll_core_h13x2_ck",
1770         .prcm = {
1771                 .omap4 = {
1772                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1773                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1774                         .modulemode   = MODULEMODE_HWCTRL,
1775                 },
1776         },
1777         .opt_clks       = usb_otg_ss2_opt_clks,
1778         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1779 };
1780
1781 /* usb_otg_ss3 */
1782 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1783         .name           = "usb_otg_ss3",
1784         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1785         .clkdm_name     = "l3init_clkdm",
1786         .main_clk       = "dpll_core_h13x2_ck",
1787         .prcm = {
1788                 .omap4 = {
1789                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1790                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1791                         .modulemode   = MODULEMODE_HWCTRL,
1792                 },
1793         },
1794 };
1795
1796 /* usb_otg_ss4 */
1797 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1798         .name           = "usb_otg_ss4",
1799         .class          = &dra7xx_usb_otg_ss_hwmod_class,
1800         .clkdm_name     = "l3init_clkdm",
1801         .main_clk       = "dpll_core_h13x2_ck",
1802         .prcm = {
1803                 .omap4 = {
1804                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1805                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1806                         .modulemode   = MODULEMODE_HWCTRL,
1807                 },
1808         },
1809 };
1810
1811 /*
1812  * 'vcp' class
1813  *
1814  */
1815
1816 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1817         .name   = "vcp",
1818 };
1819
1820 /* vcp1 */
1821 static struct omap_hwmod dra7xx_vcp1_hwmod = {
1822         .name           = "vcp1",
1823         .class          = &dra7xx_vcp_hwmod_class,
1824         .clkdm_name     = "l3main1_clkdm",
1825         .main_clk       = "l3_iclk_div",
1826         .prcm = {
1827                 .omap4 = {
1828                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1829                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1830                 },
1831         },
1832 };
1833
1834 /* vcp2 */
1835 static struct omap_hwmod dra7xx_vcp2_hwmod = {
1836         .name           = "vcp2",
1837         .class          = &dra7xx_vcp_hwmod_class,
1838         .clkdm_name     = "l3main1_clkdm",
1839         .main_clk       = "l3_iclk_div",
1840         .prcm = {
1841                 .omap4 = {
1842                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1843                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1844                 },
1845         },
1846 };
1847
1848 /*
1849  * 'wd_timer' class
1850  *
1851  */
1852
1853 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1854         .rev_offs       = 0x0000,
1855         .sysc_offs      = 0x0010,
1856         .syss_offs      = 0x0014,
1857         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1858                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860                            SIDLE_SMART_WKUP),
1861         .sysc_fields    = &omap_hwmod_sysc_type1,
1862 };
1863
1864 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1865         .name           = "wd_timer",
1866         .sysc           = &dra7xx_wd_timer_sysc,
1867         .pre_shutdown   = &omap2_wd_timer_disable,
1868         .reset          = &omap2_wd_timer_reset,
1869 };
1870
1871 /* wd_timer2 */
1872 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1873         .name           = "wd_timer2",
1874         .class          = &dra7xx_wd_timer_hwmod_class,
1875         .clkdm_name     = "wkupaon_clkdm",
1876         .main_clk       = "sys_32k_ck",
1877         .prcm = {
1878                 .omap4 = {
1879                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1880                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1881                         .modulemode   = MODULEMODE_SWCTRL,
1882                 },
1883         },
1884 };
1885
1886
1887 /*
1888  * Interfaces
1889  */
1890
1891 /* l3_main_2 -> l3_instr */
1892 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1893         .master         = &dra7xx_l3_main_2_hwmod,
1894         .slave          = &dra7xx_l3_instr_hwmod,
1895         .clk            = "l3_iclk_div",
1896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /* l4_cfg -> l3_main_1 */
1900 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1901         .master         = &dra7xx_l4_cfg_hwmod,
1902         .slave          = &dra7xx_l3_main_1_hwmod,
1903         .clk            = "l3_iclk_div",
1904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1905 };
1906
1907 /* mpu -> l3_main_1 */
1908 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1909         .master         = &dra7xx_mpu_hwmod,
1910         .slave          = &dra7xx_l3_main_1_hwmod,
1911         .clk            = "l3_iclk_div",
1912         .user           = OCP_USER_MPU,
1913 };
1914
1915 /* l3_main_1 -> l3_main_2 */
1916 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1917         .master         = &dra7xx_l3_main_1_hwmod,
1918         .slave          = &dra7xx_l3_main_2_hwmod,
1919         .clk            = "l3_iclk_div",
1920         .user           = OCP_USER_MPU,
1921 };
1922
1923 /* l4_cfg -> l3_main_2 */
1924 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1925         .master         = &dra7xx_l4_cfg_hwmod,
1926         .slave          = &dra7xx_l3_main_2_hwmod,
1927         .clk            = "l3_iclk_div",
1928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1929 };
1930
1931 /* l3_main_1 -> l4_cfg */
1932 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1933         .master         = &dra7xx_l3_main_1_hwmod,
1934         .slave          = &dra7xx_l4_cfg_hwmod,
1935         .clk            = "l3_iclk_div",
1936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1937 };
1938
1939 /* l3_main_1 -> l4_per1 */
1940 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1941         .master         = &dra7xx_l3_main_1_hwmod,
1942         .slave          = &dra7xx_l4_per1_hwmod,
1943         .clk            = "l3_iclk_div",
1944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1945 };
1946
1947 /* l3_main_1 -> l4_per2 */
1948 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1949         .master         = &dra7xx_l3_main_1_hwmod,
1950         .slave          = &dra7xx_l4_per2_hwmod,
1951         .clk            = "l3_iclk_div",
1952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1953 };
1954
1955 /* l3_main_1 -> l4_per3 */
1956 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1957         .master         = &dra7xx_l3_main_1_hwmod,
1958         .slave          = &dra7xx_l4_per3_hwmod,
1959         .clk            = "l3_iclk_div",
1960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1961 };
1962
1963 /* l3_main_1 -> l4_wkup */
1964 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1965         .master         = &dra7xx_l3_main_1_hwmod,
1966         .slave          = &dra7xx_l4_wkup_hwmod,
1967         .clk            = "wkupaon_iclk_mux",
1968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1969 };
1970
1971 /* l4_per2 -> atl */
1972 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1973         .master         = &dra7xx_l4_per2_hwmod,
1974         .slave          = &dra7xx_atl_hwmod,
1975         .clk            = "l3_iclk_div",
1976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1977 };
1978
1979 /* l3_main_1 -> bb2d */
1980 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1981         .master         = &dra7xx_l3_main_1_hwmod,
1982         .slave          = &dra7xx_bb2d_hwmod,
1983         .clk            = "l3_iclk_div",
1984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1985 };
1986
1987 /* l4_wkup -> counter_32k */
1988 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1989         .master         = &dra7xx_l4_wkup_hwmod,
1990         .slave          = &dra7xx_counter_32k_hwmod,
1991         .clk            = "wkupaon_iclk_mux",
1992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1993 };
1994
1995 /* l4_wkup -> ctrl_module_wkup */
1996 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1997         .master         = &dra7xx_l4_wkup_hwmod,
1998         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
1999         .clk            = "wkupaon_iclk_mux",
2000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2001 };
2002
2003 /* l4_wkup -> dcan1 */
2004 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2005         .master         = &dra7xx_l4_wkup_hwmod,
2006         .slave          = &dra7xx_dcan1_hwmod,
2007         .clk            = "wkupaon_iclk_mux",
2008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2009 };
2010
2011 /* l4_per2 -> dcan2 */
2012 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2013         .master         = &dra7xx_l4_per2_hwmod,
2014         .slave          = &dra7xx_dcan2_hwmod,
2015         .clk            = "l3_iclk_div",
2016         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2017 };
2018
2019 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2020         {
2021                 .pa_start       = 0x4a056000,
2022                 .pa_end         = 0x4a056fff,
2023                 .flags          = ADDR_TYPE_RT
2024         },
2025         { }
2026 };
2027
2028 /* l4_cfg -> dma_system */
2029 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2030         .master         = &dra7xx_l4_cfg_hwmod,
2031         .slave          = &dra7xx_dma_system_hwmod,
2032         .clk            = "l3_iclk_div",
2033         .addr           = dra7xx_dma_system_addrs,
2034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2035 };
2036
2037 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2038         {
2039                 .name           = "family",
2040                 .pa_start       = 0x58000000,
2041                 .pa_end         = 0x5800007f,
2042                 .flags          = ADDR_TYPE_RT
2043         },
2044 };
2045
2046 /* l3_main_1 -> dss */
2047 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2048         .master         = &dra7xx_l3_main_1_hwmod,
2049         .slave          = &dra7xx_dss_hwmod,
2050         .clk            = "l3_iclk_div",
2051         .addr           = dra7xx_dss_addrs,
2052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2053 };
2054
2055 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2056         {
2057                 .name           = "dispc",
2058                 .pa_start       = 0x58001000,
2059                 .pa_end         = 0x58001fff,
2060                 .flags          = ADDR_TYPE_RT
2061         },
2062 };
2063
2064 /* l3_main_1 -> dispc */
2065 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2066         .master         = &dra7xx_l3_main_1_hwmod,
2067         .slave          = &dra7xx_dss_dispc_hwmod,
2068         .clk            = "l3_iclk_div",
2069         .addr           = dra7xx_dss_dispc_addrs,
2070         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2071 };
2072
2073 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2074         {
2075                 .name           = "hdmi_wp",
2076                 .pa_start       = 0x58040000,
2077                 .pa_end         = 0x580400ff,
2078                 .flags          = ADDR_TYPE_RT
2079         },
2080         { }
2081 };
2082
2083 /* l3_main_1 -> dispc */
2084 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2085         .master         = &dra7xx_l3_main_1_hwmod,
2086         .slave          = &dra7xx_dss_hdmi_hwmod,
2087         .clk            = "l3_iclk_div",
2088         .addr           = dra7xx_dss_hdmi_addrs,
2089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2090 };
2091
2092 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2093         {
2094                 .pa_start       = 0x48078000,
2095                 .pa_end         = 0x48078fff,
2096                 .flags          = ADDR_TYPE_RT
2097         },
2098         { }
2099 };
2100
2101 /* l4_per1 -> elm */
2102 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2103         .master         = &dra7xx_l4_per1_hwmod,
2104         .slave          = &dra7xx_elm_hwmod,
2105         .clk            = "l3_iclk_div",
2106         .addr           = dra7xx_elm_addrs,
2107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2108 };
2109
2110 /* l4_wkup -> gpio1 */
2111 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2112         .master         = &dra7xx_l4_wkup_hwmod,
2113         .slave          = &dra7xx_gpio1_hwmod,
2114         .clk            = "wkupaon_iclk_mux",
2115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2116 };
2117
2118 /* l4_per1 -> gpio2 */
2119 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2120         .master         = &dra7xx_l4_per1_hwmod,
2121         .slave          = &dra7xx_gpio2_hwmod,
2122         .clk            = "l3_iclk_div",
2123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2124 };
2125
2126 /* l4_per1 -> gpio3 */
2127 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2128         .master         = &dra7xx_l4_per1_hwmod,
2129         .slave          = &dra7xx_gpio3_hwmod,
2130         .clk            = "l3_iclk_div",
2131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2132 };
2133
2134 /* l4_per1 -> gpio4 */
2135 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2136         .master         = &dra7xx_l4_per1_hwmod,
2137         .slave          = &dra7xx_gpio4_hwmod,
2138         .clk            = "l3_iclk_div",
2139         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2140 };
2141
2142 /* l4_per1 -> gpio5 */
2143 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2144         .master         = &dra7xx_l4_per1_hwmod,
2145         .slave          = &dra7xx_gpio5_hwmod,
2146         .clk            = "l3_iclk_div",
2147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2148 };
2149
2150 /* l4_per1 -> gpio6 */
2151 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2152         .master         = &dra7xx_l4_per1_hwmod,
2153         .slave          = &dra7xx_gpio6_hwmod,
2154         .clk            = "l3_iclk_div",
2155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2156 };
2157
2158 /* l4_per1 -> gpio7 */
2159 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2160         .master         = &dra7xx_l4_per1_hwmod,
2161         .slave          = &dra7xx_gpio7_hwmod,
2162         .clk            = "l3_iclk_div",
2163         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2164 };
2165
2166 /* l4_per1 -> gpio8 */
2167 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2168         .master         = &dra7xx_l4_per1_hwmod,
2169         .slave          = &dra7xx_gpio8_hwmod,
2170         .clk            = "l3_iclk_div",
2171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2172 };
2173
2174 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2175         {
2176                 .pa_start       = 0x50000000,
2177                 .pa_end         = 0x500003ff,
2178                 .flags          = ADDR_TYPE_RT
2179         },
2180         { }
2181 };
2182
2183 /* l3_main_1 -> gpmc */
2184 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2185         .master         = &dra7xx_l3_main_1_hwmod,
2186         .slave          = &dra7xx_gpmc_hwmod,
2187         .clk            = "l3_iclk_div",
2188         .addr           = dra7xx_gpmc_addrs,
2189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2190 };
2191
2192 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2193         {
2194                 .pa_start       = 0x480b2000,
2195                 .pa_end         = 0x480b201f,
2196                 .flags          = ADDR_TYPE_RT
2197         },
2198         { }
2199 };
2200
2201 /* l4_per1 -> hdq1w */
2202 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2203         .master         = &dra7xx_l4_per1_hwmod,
2204         .slave          = &dra7xx_hdq1w_hwmod,
2205         .clk            = "l3_iclk_div",
2206         .addr           = dra7xx_hdq1w_addrs,
2207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2208 };
2209
2210 /* l4_per1 -> i2c1 */
2211 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2212         .master         = &dra7xx_l4_per1_hwmod,
2213         .slave          = &dra7xx_i2c1_hwmod,
2214         .clk            = "l3_iclk_div",
2215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* l4_per1 -> i2c2 */
2219 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2220         .master         = &dra7xx_l4_per1_hwmod,
2221         .slave          = &dra7xx_i2c2_hwmod,
2222         .clk            = "l3_iclk_div",
2223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* l4_per1 -> i2c3 */
2227 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2228         .master         = &dra7xx_l4_per1_hwmod,
2229         .slave          = &dra7xx_i2c3_hwmod,
2230         .clk            = "l3_iclk_div",
2231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2232 };
2233
2234 /* l4_per1 -> i2c4 */
2235 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2236         .master         = &dra7xx_l4_per1_hwmod,
2237         .slave          = &dra7xx_i2c4_hwmod,
2238         .clk            = "l3_iclk_div",
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 /* l4_per1 -> i2c5 */
2243 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2244         .master         = &dra7xx_l4_per1_hwmod,
2245         .slave          = &dra7xx_i2c5_hwmod,
2246         .clk            = "l3_iclk_div",
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* l4_per1 -> mcspi1 */
2251 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2252         .master         = &dra7xx_l4_per1_hwmod,
2253         .slave          = &dra7xx_mcspi1_hwmod,
2254         .clk            = "l3_iclk_div",
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* l4_per1 -> mcspi2 */
2259 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2260         .master         = &dra7xx_l4_per1_hwmod,
2261         .slave          = &dra7xx_mcspi2_hwmod,
2262         .clk            = "l3_iclk_div",
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* l4_per1 -> mcspi3 */
2267 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2268         .master         = &dra7xx_l4_per1_hwmod,
2269         .slave          = &dra7xx_mcspi3_hwmod,
2270         .clk            = "l3_iclk_div",
2271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2272 };
2273
2274 /* l4_per1 -> mcspi4 */
2275 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2276         .master         = &dra7xx_l4_per1_hwmod,
2277         .slave          = &dra7xx_mcspi4_hwmod,
2278         .clk            = "l3_iclk_div",
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* l4_per1 -> mmc1 */
2283 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2284         .master         = &dra7xx_l4_per1_hwmod,
2285         .slave          = &dra7xx_mmc1_hwmod,
2286         .clk            = "l3_iclk_div",
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* l4_per1 -> mmc2 */
2291 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2292         .master         = &dra7xx_l4_per1_hwmod,
2293         .slave          = &dra7xx_mmc2_hwmod,
2294         .clk            = "l3_iclk_div",
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* l4_per1 -> mmc3 */
2299 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2300         .master         = &dra7xx_l4_per1_hwmod,
2301         .slave          = &dra7xx_mmc3_hwmod,
2302         .clk            = "l3_iclk_div",
2303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2304 };
2305
2306 /* l4_per1 -> mmc4 */
2307 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2308         .master         = &dra7xx_l4_per1_hwmod,
2309         .slave          = &dra7xx_mmc4_hwmod,
2310         .clk            = "l3_iclk_div",
2311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2312 };
2313
2314 /* l4_cfg -> mpu */
2315 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2316         .master         = &dra7xx_l4_cfg_hwmod,
2317         .slave          = &dra7xx_mpu_hwmod,
2318         .clk            = "l3_iclk_div",
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2323         {
2324                 .pa_start       = 0x4a080000,
2325                 .pa_end         = 0x4a08001f,
2326                 .flags          = ADDR_TYPE_RT
2327         },
2328         { }
2329 };
2330
2331 /* l4_cfg -> ocp2scp1 */
2332 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2333         .master         = &dra7xx_l4_cfg_hwmod,
2334         .slave          = &dra7xx_ocp2scp1_hwmod,
2335         .clk            = "l4_root_clk_div",
2336         .addr           = dra7xx_ocp2scp1_addrs,
2337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2338 };
2339
2340 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2341         {
2342                 .pa_start       = 0x4b300000,
2343                 .pa_end         = 0x4b30007f,
2344                 .flags          = ADDR_TYPE_RT
2345         },
2346         { }
2347 };
2348
2349 /* l3_main_1 -> qspi */
2350 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2351         .master         = &dra7xx_l3_main_1_hwmod,
2352         .slave          = &dra7xx_qspi_hwmod,
2353         .clk            = "l3_iclk_div",
2354         .addr           = dra7xx_qspi_addrs,
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2359         {
2360                 .name           = "sysc",
2361                 .pa_start       = 0x4a141100,
2362                 .pa_end         = 0x4a141107,
2363                 .flags          = ADDR_TYPE_RT
2364         },
2365         { }
2366 };
2367
2368 /* l4_cfg -> sata */
2369 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2370         .master         = &dra7xx_l4_cfg_hwmod,
2371         .slave          = &dra7xx_sata_hwmod,
2372         .clk            = "l3_iclk_div",
2373         .addr           = dra7xx_sata_addrs,
2374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2375 };
2376
2377 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2378         {
2379                 .pa_start       = 0x4a0dd000,
2380                 .pa_end         = 0x4a0dd07f,
2381                 .flags          = ADDR_TYPE_RT
2382         },
2383         { }
2384 };
2385
2386 /* l4_cfg -> smartreflex_core */
2387 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2388         .master         = &dra7xx_l4_cfg_hwmod,
2389         .slave          = &dra7xx_smartreflex_core_hwmod,
2390         .clk            = "l4_root_clk_div",
2391         .addr           = dra7xx_smartreflex_core_addrs,
2392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2393 };
2394
2395 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2396         {
2397                 .pa_start       = 0x4a0d9000,
2398                 .pa_end         = 0x4a0d907f,
2399                 .flags          = ADDR_TYPE_RT
2400         },
2401         { }
2402 };
2403
2404 /* l4_cfg -> smartreflex_mpu */
2405 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2406         .master         = &dra7xx_l4_cfg_hwmod,
2407         .slave          = &dra7xx_smartreflex_mpu_hwmod,
2408         .clk            = "l4_root_clk_div",
2409         .addr           = dra7xx_smartreflex_mpu_addrs,
2410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2411 };
2412
2413 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2414         {
2415                 .pa_start       = 0x4a0f6000,
2416                 .pa_end         = 0x4a0f6fff,
2417                 .flags          = ADDR_TYPE_RT
2418         },
2419         { }
2420 };
2421
2422 /* l4_cfg -> spinlock */
2423 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2424         .master         = &dra7xx_l4_cfg_hwmod,
2425         .slave          = &dra7xx_spinlock_hwmod,
2426         .clk            = "l3_iclk_div",
2427         .addr           = dra7xx_spinlock_addrs,
2428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2429 };
2430
2431 /* l4_wkup -> timer1 */
2432 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2433         .master         = &dra7xx_l4_wkup_hwmod,
2434         .slave          = &dra7xx_timer1_hwmod,
2435         .clk            = "wkupaon_iclk_mux",
2436         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2437 };
2438
2439 /* l4_per1 -> timer2 */
2440 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2441         .master         = &dra7xx_l4_per1_hwmod,
2442         .slave          = &dra7xx_timer2_hwmod,
2443         .clk            = "l3_iclk_div",
2444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 /* l4_per1 -> timer3 */
2448 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2449         .master         = &dra7xx_l4_per1_hwmod,
2450         .slave          = &dra7xx_timer3_hwmod,
2451         .clk            = "l3_iclk_div",
2452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2453 };
2454
2455 /* l4_per1 -> timer4 */
2456 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2457         .master         = &dra7xx_l4_per1_hwmod,
2458         .slave          = &dra7xx_timer4_hwmod,
2459         .clk            = "l3_iclk_div",
2460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462
2463 /* l4_per3 -> timer5 */
2464 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2465         .master         = &dra7xx_l4_per3_hwmod,
2466         .slave          = &dra7xx_timer5_hwmod,
2467         .clk            = "l3_iclk_div",
2468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2469 };
2470
2471 /* l4_per3 -> timer6 */
2472 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2473         .master         = &dra7xx_l4_per3_hwmod,
2474         .slave          = &dra7xx_timer6_hwmod,
2475         .clk            = "l3_iclk_div",
2476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2477 };
2478
2479 /* l4_per3 -> timer7 */
2480 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2481         .master         = &dra7xx_l4_per3_hwmod,
2482         .slave          = &dra7xx_timer7_hwmod,
2483         .clk            = "l3_iclk_div",
2484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2485 };
2486
2487 /* l4_per3 -> timer8 */
2488 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2489         .master         = &dra7xx_l4_per3_hwmod,
2490         .slave          = &dra7xx_timer8_hwmod,
2491         .clk            = "l3_iclk_div",
2492         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2493 };
2494
2495 /* l4_per1 -> timer9 */
2496 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2497         .master         = &dra7xx_l4_per1_hwmod,
2498         .slave          = &dra7xx_timer9_hwmod,
2499         .clk            = "l3_iclk_div",
2500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2501 };
2502
2503 /* l4_per1 -> timer10 */
2504 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2505         .master         = &dra7xx_l4_per1_hwmod,
2506         .slave          = &dra7xx_timer10_hwmod,
2507         .clk            = "l3_iclk_div",
2508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 /* l4_per1 -> timer11 */
2512 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2513         .master         = &dra7xx_l4_per1_hwmod,
2514         .slave          = &dra7xx_timer11_hwmod,
2515         .clk            = "l3_iclk_div",
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* l4_per1 -> uart1 */
2520 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2521         .master         = &dra7xx_l4_per1_hwmod,
2522         .slave          = &dra7xx_uart1_hwmod,
2523         .clk            = "l3_iclk_div",
2524         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2525 };
2526
2527 /* l4_per1 -> uart2 */
2528 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2529         .master         = &dra7xx_l4_per1_hwmod,
2530         .slave          = &dra7xx_uart2_hwmod,
2531         .clk            = "l3_iclk_div",
2532         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2533 };
2534
2535 /* l4_per1 -> uart3 */
2536 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2537         .master         = &dra7xx_l4_per1_hwmod,
2538         .slave          = &dra7xx_uart3_hwmod,
2539         .clk            = "l3_iclk_div",
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 /* l4_per1 -> uart4 */
2544 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2545         .master         = &dra7xx_l4_per1_hwmod,
2546         .slave          = &dra7xx_uart4_hwmod,
2547         .clk            = "l3_iclk_div",
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 /* l4_per1 -> uart5 */
2552 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2553         .master         = &dra7xx_l4_per1_hwmod,
2554         .slave          = &dra7xx_uart5_hwmod,
2555         .clk            = "l3_iclk_div",
2556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2557 };
2558
2559 /* l4_per1 -> uart6 */
2560 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2561         .master         = &dra7xx_l4_per1_hwmod,
2562         .slave          = &dra7xx_uart6_hwmod,
2563         .clk            = "l3_iclk_div",
2564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2565 };
2566
2567 /* l4_per3 -> usb_otg_ss1 */
2568 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2569         .master         = &dra7xx_l4_per3_hwmod,
2570         .slave          = &dra7xx_usb_otg_ss1_hwmod,
2571         .clk            = "dpll_core_h13x2_ck",
2572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2573 };
2574
2575 /* l4_per3 -> usb_otg_ss2 */
2576 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2577         .master         = &dra7xx_l4_per3_hwmod,
2578         .slave          = &dra7xx_usb_otg_ss2_hwmod,
2579         .clk            = "dpll_core_h13x2_ck",
2580         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* l4_per3 -> usb_otg_ss3 */
2584 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2585         .master         = &dra7xx_l4_per3_hwmod,
2586         .slave          = &dra7xx_usb_otg_ss3_hwmod,
2587         .clk            = "dpll_core_h13x2_ck",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 /* l4_per3 -> usb_otg_ss4 */
2592 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2593         .master         = &dra7xx_l4_per3_hwmod,
2594         .slave          = &dra7xx_usb_otg_ss4_hwmod,
2595         .clk            = "dpll_core_h13x2_ck",
2596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2597 };
2598
2599 /* l3_main_1 -> vcp1 */
2600 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2601         .master         = &dra7xx_l3_main_1_hwmod,
2602         .slave          = &dra7xx_vcp1_hwmod,
2603         .clk            = "l3_iclk_div",
2604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2605 };
2606
2607 /* l4_per2 -> vcp1 */
2608 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2609         .master         = &dra7xx_l4_per2_hwmod,
2610         .slave          = &dra7xx_vcp1_hwmod,
2611         .clk            = "l3_iclk_div",
2612         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2613 };
2614
2615 /* l3_main_1 -> vcp2 */
2616 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2617         .master         = &dra7xx_l3_main_1_hwmod,
2618         .slave          = &dra7xx_vcp2_hwmod,
2619         .clk            = "l3_iclk_div",
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 /* l4_per2 -> vcp2 */
2624 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2625         .master         = &dra7xx_l4_per2_hwmod,
2626         .slave          = &dra7xx_vcp2_hwmod,
2627         .clk            = "l3_iclk_div",
2628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2629 };
2630
2631 /* l4_wkup -> wd_timer2 */
2632 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2633         .master         = &dra7xx_l4_wkup_hwmod,
2634         .slave          = &dra7xx_wd_timer2_hwmod,
2635         .clk            = "wkupaon_iclk_mux",
2636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2637 };
2638
2639 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2640         &dra7xx_l3_main_2__l3_instr,
2641         &dra7xx_l4_cfg__l3_main_1,
2642         &dra7xx_mpu__l3_main_1,
2643         &dra7xx_l3_main_1__l3_main_2,
2644         &dra7xx_l4_cfg__l3_main_2,
2645         &dra7xx_l3_main_1__l4_cfg,
2646         &dra7xx_l3_main_1__l4_per1,
2647         &dra7xx_l3_main_1__l4_per2,
2648         &dra7xx_l3_main_1__l4_per3,
2649         &dra7xx_l3_main_1__l4_wkup,
2650         &dra7xx_l4_per2__atl,
2651         &dra7xx_l3_main_1__bb2d,
2652         &dra7xx_l4_wkup__counter_32k,
2653         &dra7xx_l4_wkup__ctrl_module_wkup,
2654         &dra7xx_l4_wkup__dcan1,
2655         &dra7xx_l4_per2__dcan2,
2656         &dra7xx_l4_cfg__dma_system,
2657         &dra7xx_l3_main_1__dss,
2658         &dra7xx_l3_main_1__dispc,
2659         &dra7xx_l3_main_1__hdmi,
2660         &dra7xx_l4_per1__elm,
2661         &dra7xx_l4_wkup__gpio1,
2662         &dra7xx_l4_per1__gpio2,
2663         &dra7xx_l4_per1__gpio3,
2664         &dra7xx_l4_per1__gpio4,
2665         &dra7xx_l4_per1__gpio5,
2666         &dra7xx_l4_per1__gpio6,
2667         &dra7xx_l4_per1__gpio7,
2668         &dra7xx_l4_per1__gpio8,
2669         &dra7xx_l3_main_1__gpmc,
2670         &dra7xx_l4_per1__hdq1w,
2671         &dra7xx_l4_per1__i2c1,
2672         &dra7xx_l4_per1__i2c2,
2673         &dra7xx_l4_per1__i2c3,
2674         &dra7xx_l4_per1__i2c4,
2675         &dra7xx_l4_per1__i2c5,
2676         &dra7xx_l4_per1__mcspi1,
2677         &dra7xx_l4_per1__mcspi2,
2678         &dra7xx_l4_per1__mcspi3,
2679         &dra7xx_l4_per1__mcspi4,
2680         &dra7xx_l4_per1__mmc1,
2681         &dra7xx_l4_per1__mmc2,
2682         &dra7xx_l4_per1__mmc3,
2683         &dra7xx_l4_per1__mmc4,
2684         &dra7xx_l4_cfg__mpu,
2685         &dra7xx_l4_cfg__ocp2scp1,
2686         &dra7xx_l3_main_1__qspi,
2687         &dra7xx_l4_cfg__sata,
2688         &dra7xx_l4_cfg__smartreflex_core,
2689         &dra7xx_l4_cfg__smartreflex_mpu,
2690         &dra7xx_l4_cfg__spinlock,
2691         &dra7xx_l4_wkup__timer1,
2692         &dra7xx_l4_per1__timer2,
2693         &dra7xx_l4_per1__timer3,
2694         &dra7xx_l4_per1__timer4,
2695         &dra7xx_l4_per3__timer5,
2696         &dra7xx_l4_per3__timer6,
2697         &dra7xx_l4_per3__timer7,
2698         &dra7xx_l4_per3__timer8,
2699         &dra7xx_l4_per1__timer9,
2700         &dra7xx_l4_per1__timer10,
2701         &dra7xx_l4_per1__timer11,
2702         &dra7xx_l4_per1__uart1,
2703         &dra7xx_l4_per1__uart2,
2704         &dra7xx_l4_per1__uart3,
2705         &dra7xx_l4_per1__uart4,
2706         &dra7xx_l4_per1__uart5,
2707         &dra7xx_l4_per1__uart6,
2708         &dra7xx_l4_per3__usb_otg_ss1,
2709         &dra7xx_l4_per3__usb_otg_ss2,
2710         &dra7xx_l4_per3__usb_otg_ss3,
2711         &dra7xx_l4_per3__usb_otg_ss4,
2712         &dra7xx_l3_main_1__vcp1,
2713         &dra7xx_l4_per2__vcp1,
2714         &dra7xx_l3_main_1__vcp2,
2715         &dra7xx_l4_per2__vcp2,
2716         &dra7xx_l4_wkup__wd_timer2,
2717         NULL,
2718 };
2719
2720 int __init dra7xx_hwmod_init(void)
2721 {
2722         omap_hwmod_init();
2723         return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2724 }