Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21         };
  22
  23         cpus {
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a8";
  26                 };
  27         };
  28
  29         memory {
  30                 reg = <0x40000000 0x20000000>;
  31         };
  32
  33         clocks {
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 /*
  39                  * This is a dummy clock, to be used as placeholder on
  40                  * other mux clocks when a specific parent clock is not
  41                  * yet implemented. It should be dropped when the driver
  42                  * is complete.
  43                  */
  44                 dummy: dummy {
  45                         #clock-cells = <0>;
  46                         compatible = "fixed-clock";
  47                         clock-frequency = <0>;
  48                 };
  49
  50                 osc24M: osc24M@01c20050 {
  51                         #clock-cells = <0>;
  52                         compatible = "allwinner,sun4i-osc-clk";
  53                         reg = <0x01c20050 0x4>;
  54                         clock-frequency = <24000000>;
  55                 };
  56
  57                 osc32k: osc32k {
  58                         #clock-cells = <0>;
  59                         compatible = "fixed-clock";
  60                         clock-frequency = <32768>;
  61                 };
  62
  63                 pll1: pll1@01c20000 {
  64                         #clock-cells = <0>;
  65                         compatible = "allwinner,sun4i-pll1-clk";
  66                         reg = <0x01c20000 0x4>;
  67                         clocks = <&osc24M>;
  68                 };
  69
  70                 pll4: pll4@01c20018 {
  71                         #clock-cells = <0>;
  72                         compatible = "allwinner,sun4i-pll1-clk";
  73                         reg = <0x01c20018 0x4>;
  74                         clocks = <&osc24M>;
  75                 };
  76
  77                 pll5: pll5@01c20020 {
  78                         #clock-cells = <1>;
  79                         compatible = "allwinner,sun4i-pll5-clk";
  80                         reg = <0x01c20020 0x4>;
  81                         clocks = <&osc24M>;
  82                         clock-output-names = "pll5_ddr", "pll5_other";
  83                 };
  84
  85                 pll6: pll6@01c20028 {
  86                         #clock-cells = <1>;
  87                         compatible = "allwinner,sun4i-pll6-clk";
  88                         reg = <0x01c20028 0x4>;
  89                         clocks = <&osc24M>;
  90                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  91                 };
  92
  93                 /* dummy is 200M */
  94                 cpu: cpu@01c20054 {
  95                         #clock-cells = <0>;
  96                         compatible = "allwinner,sun4i-cpu-clk";
  97                         reg = <0x01c20054 0x4>;
  98                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  99                 };
 100
 101                 axi: axi@01c20054 {
 102                         #clock-cells = <0>;
 103                         compatible = "allwinner,sun4i-axi-clk";
 104                         reg = <0x01c20054 0x4>;
 105                         clocks = <&cpu>;
 106                 };
 107
 108                 axi_gates: axi_gates@01c2005c {
 109                         #clock-cells = <1>;
 110                         compatible = "allwinner,sun4i-axi-gates-clk";
 111                         reg = <0x01c2005c 0x4>;
 112                         clocks = <&axi>;
 113                         clock-output-names = "axi_dram";
 114                 };
 115
 116                 ahb: ahb@01c20054 {
 117                         #clock-cells = <0>;
 118                         compatible = "allwinner,sun4i-ahb-clk";
 119                         reg = <0x01c20054 0x4>;
 120                         clocks = <&axi>;
 121                 };
 122
 123                 ahb_gates: ahb_gates@01c20060 {
 124                         #clock-cells = <1>;
 125                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 126                         reg = <0x01c20060 0x8>;
 127                         clocks = <&ahb>;
 128                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 129                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 130                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 131                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 132                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 133                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 134                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 135                 };
 136
 137                 apb0: apb0@01c20054 {
 138                         #clock-cells = <0>;
 139                         compatible = "allwinner,sun4i-apb0-clk";
 140                         reg = <0x01c20054 0x4>;
 141                         clocks = <&ahb>;
 142                 };
 143
 144                 apb0_gates: apb0_gates@01c20068 {
 145                         #clock-cells = <1>;
 146                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 147                         reg = <0x01c20068 0x4>;
 148                         clocks = <&apb0>;
 149                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 150                                 "apb0_ir", "apb0_keypad";
 151                 };
 152
 153                 apb1_mux: apb1_mux@01c20058 {
 154                         #clock-cells = <0>;
 155                         compatible = "allwinner,sun4i-apb1-mux-clk";
 156                         reg = <0x01c20058 0x4>;
 157                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 158                 };
 159
 160                 apb1: apb1@01c20058 {
 161                         #clock-cells = <0>;
 162                         compatible = "allwinner,sun4i-apb1-clk";
 163                         reg = <0x01c20058 0x4>;
 164                         clocks = <&apb1_mux>;
 165                 };
 166
 167                 apb1_gates: apb1_gates@01c2006c {
 168                         #clock-cells = <1>;
 169                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 170                         reg = <0x01c2006c 0x4>;
 171                         clocks = <&apb1>;
 172                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 173                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 174                                 "apb1_uart2", "apb1_uart3";
 175                 };
 176
 177                 nand_clk: clk@01c20080 {
 178                         #clock-cells = <0>;
 179                         compatible = "allwinner,sun4i-mod0-clk";
 180                         reg = <0x01c20080 0x4>;
 181                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 182                         clock-output-names = "nand";
 183                 };
 184
 185                 ms_clk: clk@01c20084 {
 186                         #clock-cells = <0>;
 187                         compatible = "allwinner,sun4i-mod0-clk";
 188                         reg = <0x01c20084 0x4>;
 189                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 190                         clock-output-names = "ms";
 191                 };
 192
 193                 mmc0_clk: clk@01c20088 {
 194                         #clock-cells = <0>;
 195                         compatible = "allwinner,sun4i-mod0-clk";
 196                         reg = <0x01c20088 0x4>;
 197                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 198                         clock-output-names = "mmc0";
 199                 };
 200
 201                 mmc1_clk: clk@01c2008c {
 202                         #clock-cells = <0>;
 203                         compatible = "allwinner,sun4i-mod0-clk";
 204                         reg = <0x01c2008c 0x4>;
 205                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 206                         clock-output-names = "mmc1";
 207                 };
 208
 209                 mmc2_clk: clk@01c20090 {
 210                         #clock-cells = <0>;
 211                         compatible = "allwinner,sun4i-mod0-clk";
 212                         reg = <0x01c20090 0x4>;
 213                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 214                         clock-output-names = "mmc2";
 215                 };
 216
 217                 ts_clk: clk@01c20098 {
 218                         #clock-cells = <0>;
 219                         compatible = "allwinner,sun4i-mod0-clk";
 220                         reg = <0x01c20098 0x4>;
 221                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 222                         clock-output-names = "ts";
 223                 };
 224
 225                 ss_clk: clk@01c2009c {
 226                         #clock-cells = <0>;
 227                         compatible = "allwinner,sun4i-mod0-clk";
 228                         reg = <0x01c2009c 0x4>;
 229                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 230                         clock-output-names = "ss";
 231                 };
 232
 233                 spi0_clk: clk@01c200a0 {
 234                         #clock-cells = <0>;
 235                         compatible = "allwinner,sun4i-mod0-clk";
 236                         reg = <0x01c200a0 0x4>;
 237                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 238                         clock-output-names = "spi0";
 239                 };
 240
 241                 spi1_clk: clk@01c200a4 {
 242                         #clock-cells = <0>;
 243                         compatible = "allwinner,sun4i-mod0-clk";
 244                         reg = <0x01c200a4 0x4>;
 245                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 246                         clock-output-names = "spi1";
 247                 };
 248
 249                 spi2_clk: clk@01c200a8 {
 250                         #clock-cells = <0>;
 251                         compatible = "allwinner,sun4i-mod0-clk";
 252                         reg = <0x01c200a8 0x4>;
 253                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 254                         clock-output-names = "spi2";
 255                 };
 256
 257                 ir0_clk: clk@01c200b0 {
 258                         #clock-cells = <0>;
 259                         compatible = "allwinner,sun4i-mod0-clk";
 260                         reg = <0x01c200b0 0x4>;
 261                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 262                         clock-output-names = "ir0";
 263                 };
 264
 265                 mbus_clk: clk@01c2015c {
 266                         #clock-cells = <0>;
 267                         compatible = "allwinner,sun4i-mod0-clk";
 268                         reg = <0x01c2015c 0x4>;
 269                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 270                         clock-output-names = "mbus";
 271                 };
 272         };
 273
 274         soc@01c00000 {
 275                 compatible = "simple-bus";
 276                 #address-cells = <1>;
 277                 #size-cells = <1>;
 278                 ranges;
 279
 280                 emac: ethernet@01c0b000 {
 281                         compatible = "allwinner,sun4i-emac";
 282                         reg = <0x01c0b000 0x1000>;
 283                         interrupts = <55>;
 284                         clocks = <&ahb_gates 17>;
 285                         status = "disabled";
 286                 };
 287
 288                 mdio@01c0b080 {
 289                         compatible = "allwinner,sun4i-mdio";
 290                         reg = <0x01c0b080 0x14>;
 291                         status = "disabled";
 292                         #address-cells = <1>;
 293                         #size-cells = <0>;
 294                 };
 295
 296                 intc: interrupt-controller@01c20400 {
 297                         compatible = "allwinner,sun4i-ic";
 298                         reg = <0x01c20400 0x400>;
 299                         interrupt-controller;
 300                         #interrupt-cells = <1>;
 301                 };
 302
 303                 pio: pinctrl@01c20800 {
 304                         compatible = "allwinner,sun5i-a10s-pinctrl";
 305                         reg = <0x01c20800 0x400>;
 306                         interrupts = <28>;
 307                         clocks = <&apb0_gates 5>;
 308                         gpio-controller;
 309                         interrupt-controller;
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         #gpio-cells = <3>;
 313
 314                         uart0_pins_a: uart0@0 {
 315                                 allwinner,pins = "PB19", "PB20";
 316                                 allwinner,function = "uart0";
 317                                 allwinner,drive = <0>;
 318                                 allwinner,pull = <0>;
 319                         };
 320
 321                         uart2_pins_a: uart2@0 {
 322                                 allwinner,pins = "PC18", "PC19";
 323                                 allwinner,function = "uart2";
 324                                 allwinner,drive = <0>;
 325                                 allwinner,pull = <0>;
 326                         };
 327
 328                         uart3_pins_a: uart3@0 {
 329                                 allwinner,pins = "PG9", "PG10";
 330                                 allwinner,function = "uart3";
 331                                 allwinner,drive = <0>;
 332                                 allwinner,pull = <0>;
 333                         };
 334
 335                         emac_pins_a: emac0@0 {
 336                                 allwinner,pins = "PA0", "PA1", "PA2",
 337                                                 "PA3", "PA4", "PA5", "PA6",
 338                                                 "PA7", "PA8", "PA9", "PA10",
 339                                                 "PA11", "PA12", "PA13", "PA14",
 340                                                 "PA15", "PA16";
 341                                 allwinner,function = "emac";
 342                                 allwinner,drive = <0>;
 343                                 allwinner,pull = <0>;
 344                         };
 345
 346                         i2c0_pins_a: i2c0@0 {
 347                                 allwinner,pins = "PB0", "PB1";
 348                                 allwinner,function = "i2c0";
 349                                 allwinner,drive = <0>;
 350                                 allwinner,pull = <0>;
 351                         };
 352
 353                         i2c1_pins_a: i2c1@0 {
 354                                 allwinner,pins = "PB15", "PB16";
 355                                 allwinner,function = "i2c1";
 356                                 allwinner,drive = <0>;
 357                                 allwinner,pull = <0>;
 358                         };
 359
 360                         i2c2_pins_a: i2c2@0 {
 361                                 allwinner,pins = "PB17", "PB18";
 362                                 allwinner,function = "i2c2";
 363                                 allwinner,drive = <0>;
 364                                 allwinner,pull = <0>;
 365                         };
 366                 };
 367
 368                 timer@01c20c00 {
 369                         compatible = "allwinner,sun4i-timer";
 370                         reg = <0x01c20c00 0x90>;
 371                         interrupts = <22>;
 372                         clocks = <&osc24M>;
 373                 };
 374
 375                 wdt: watchdog@01c20c90 {
 376                         compatible = "allwinner,sun4i-wdt";
 377                         reg = <0x01c20c90 0x10>;
 378                 };
 379
 380                 sid: eeprom@01c23800 {
 381                         compatible = "allwinner,sun4i-sid";
 382                         reg = <0x01c23800 0x10>;
 383                 };
 384
 385                 uart0: serial@01c28000 {
 386                         compatible = "snps,dw-apb-uart";
 387                         reg = <0x01c28000 0x400>;
 388                         interrupts = <1>;
 389                         reg-shift = <2>;
 390                         reg-io-width = <4>;
 391                         clocks = <&apb1_gates 16>;
 392                         status = "disabled";
 393                 };
 394
 395                 uart1: serial@01c28400 {
 396                         compatible = "snps,dw-apb-uart";
 397                         reg = <0x01c28400 0x400>;
 398                         interrupts = <2>;
 399                         reg-shift = <2>;
 400                         reg-io-width = <4>;
 401                         clocks = <&apb1_gates 17>;
 402                         status = "disabled";
 403                 };
 404
 405                 uart2: serial@01c28800 {
 406                         compatible = "snps,dw-apb-uart";
 407                         reg = <0x01c28800 0x400>;
 408                         interrupts = <3>;
 409                         reg-shift = <2>;
 410                         reg-io-width = <4>;
 411                         clocks = <&apb1_gates 18>;
 412                         status = "disabled";
 413                 };
 414
 415                 uart3: serial@01c28c00 {
 416                         compatible = "snps,dw-apb-uart";
 417                         reg = <0x01c28c00 0x400>;
 418                         interrupts = <4>;
 419                         reg-shift = <2>;
 420                         reg-io-width = <4>;
 421                         clocks = <&apb1_gates 19>;
 422                         status = "disabled";
 423                 };
 424
 425                 i2c0: i2c@01c2ac00 {
 426                         #address-cells = <1>;
 427                         #size-cells = <0>;
 428                         compatible = "allwinner,sun4i-i2c";
 429                         reg = <0x01c2ac00 0x400>;
 430                         interrupts = <7>;
 431                         clocks = <&apb1_gates 0>;
 432                         clock-frequency = <100000>;
 433                         status = "disabled";
 434                 };
 435
 436                 i2c1: i2c@01c2b000 {
 437                         #address-cells = <1>;
 438                         #size-cells = <0>;
 439                         compatible = "allwinner,sun4i-i2c";
 440                         reg = <0x01c2b000 0x400>;
 441                         interrupts = <8>;
 442                         clocks = <&apb1_gates 1>;
 443                         clock-frequency = <100000>;
 444                         status = "disabled";
 445                 };
 446
 447                 i2c2: i2c@01c2b400 {
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         compatible = "allwinner,sun4i-i2c";
 451                         reg = <0x01c2b400 0x400>;
 452                         interrupts = <9>;
 453                         clocks = <&apb1_gates 2>;
 454                         clock-frequency = <100000>;
 455                         status = "disabled";
 456                 };
 457         };
 458 };