Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 serial3 = &uart4;
  21                 serial4 = &uart5;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29         };
  30
  31         tzic: tz-interrupt-controller@0fffc000 {
  32                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  33                 interrupt-controller;
  34                 #interrupt-cells = <1>;
  35                 reg = <0x0fffc000 0x4000>;
  36         };
  37
  38         clocks {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 ckil {
  43                         compatible = "fsl,imx-ckil", "fixed-clock";
  44                         clock-frequency = <32768>;
  45                 };
  46
  47                 ckih1 {
  48                         compatible = "fsl,imx-ckih1", "fixed-clock";
  49                         clock-frequency = <22579200>;
  50                 };
  51
  52                 ckih2 {
  53                         compatible = "fsl,imx-ckih2", "fixed-clock";
  54                         clock-frequency = <0>;
  55                 };
  56
  57                 osc {
  58                         compatible = "fsl,imx-osc", "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61         };
  62
  63         soc {
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 compatible = "simple-bus";
  67                 interrupt-parent = <&tzic>;
  68                 ranges;
  69
  70                 aips@50000000 { /* AIPS1 */
  71                         compatible = "fsl,aips-bus", "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         reg = <0x50000000 0x10000000>;
  75                         ranges;
  76
  77                         spba@50000000 {
  78                                 compatible = "fsl,spba-bus", "simple-bus";
  79                                 #address-cells = <1>;
  80                                 #size-cells = <1>;
  81                                 reg = <0x50000000 0x40000>;
  82                                 ranges;
  83
  84                                 esdhc@50004000 { /* ESDHC1 */
  85                                         compatible = "fsl,imx53-esdhc";
  86                                         reg = <0x50004000 0x4000>;
  87                                         interrupts = <1>;
  88                                         status = "disabled";
  89                                 };
  90
  91                                 esdhc@50008000 { /* ESDHC2 */
  92                                         compatible = "fsl,imx53-esdhc";
  93                                         reg = <0x50008000 0x4000>;
  94                                         interrupts = <2>;
  95                                         status = "disabled";
  96                                 };
  97
  98                                 uart3: serial@5000c000 {
  99                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 100                                         reg = <0x5000c000 0x4000>;
 101                                         interrupts = <33>;
 102                                         status = "disabled";
 103                                 };
 104
 105                                 ecspi@50010000 { /* ECSPI1 */
 106                                         #address-cells = <1>;
 107                                         #size-cells = <0>;
 108                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 109                                         reg = <0x50010000 0x4000>;
 110                                         interrupts = <36>;
 111                                         status = "disabled";
 112                                 };
 113
 114                                 ssi2: ssi@50014000 {
 115                                         compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 116                                         reg = <0x50014000 0x4000>;
 117                                         interrupts = <30>;
 118                                         fsl,fifo-depth = <15>;
 119                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 120                                         status = "disabled";
 121                                 };
 122
 123                                 esdhc@50020000 { /* ESDHC3 */
 124                                         compatible = "fsl,imx53-esdhc";
 125                                         reg = <0x50020000 0x4000>;
 126                                         interrupts = <3>;
 127                                         status = "disabled";
 128                                 };
 129
 130                                 esdhc@50024000 { /* ESDHC4 */
 131                                         compatible = "fsl,imx53-esdhc";
 132                                         reg = <0x50024000 0x4000>;
 133                                         interrupts = <4>;
 134                                         status = "disabled";
 135                                 };
 136                         };
 137
 138                         gpio1: gpio@53f84000 {
 139                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 140                                 reg = <0x53f84000 0x4000>;
 141                                 interrupts = <50 51>;
 142                                 gpio-controller;
 143                                 #gpio-cells = <2>;
 144                                 interrupt-controller;
 145                                 #interrupt-cells = <2>;
 146                         };
 147
 148                         gpio2: gpio@53f88000 {
 149                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 150                                 reg = <0x53f88000 0x4000>;
 151                                 interrupts = <52 53>;
 152                                 gpio-controller;
 153                                 #gpio-cells = <2>;
 154                                 interrupt-controller;
 155                                 #interrupt-cells = <2>;
 156                         };
 157
 158                         gpio3: gpio@53f8c000 {
 159                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 160                                 reg = <0x53f8c000 0x4000>;
 161                                 interrupts = <54 55>;
 162                                 gpio-controller;
 163                                 #gpio-cells = <2>;
 164                                 interrupt-controller;
 165                                 #interrupt-cells = <2>;
 166                         };
 167
 168                         gpio4: gpio@53f90000 {
 169                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 170                                 reg = <0x53f90000 0x4000>;
 171                                 interrupts = <56 57>;
 172                                 gpio-controller;
 173                                 #gpio-cells = <2>;
 174                                 interrupt-controller;
 175                                 #interrupt-cells = <2>;
 176                         };
 177
 178                         wdog@53f98000 { /* WDOG1 */
 179                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 180                                 reg = <0x53f98000 0x4000>;
 181                                 interrupts = <58>;
 182                                 status = "disabled";
 183                         };
 184
 185                         wdog@53f9c000 { /* WDOG2 */
 186                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 187                                 reg = <0x53f9c000 0x4000>;
 188                                 interrupts = <59>;
 189                                 status = "disabled";
 190                         };
 191
 192                         uart1: serial@53fbc000 {
 193                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 194                                 reg = <0x53fbc000 0x4000>;
 195                                 interrupts = <31>;
 196                                 status = "disabled";
 197                         };
 198
 199                         uart2: serial@53fc0000 {
 200                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 201                                 reg = <0x53fc0000 0x4000>;
 202                                 interrupts = <32>;
 203                                 status = "disabled";
 204                         };
 205
 206                         gpio5: gpio@53fdc000 {
 207                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 208                                 reg = <0x53fdc000 0x4000>;
 209                                 interrupts = <103 104>;
 210                                 gpio-controller;
 211                                 #gpio-cells = <2>;
 212                                 interrupt-controller;
 213                                 #interrupt-cells = <2>;
 214                         };
 215
 216                         gpio6: gpio@53fe0000 {
 217                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 218                                 reg = <0x53fe0000 0x4000>;
 219                                 interrupts = <105 106>;
 220                                 gpio-controller;
 221                                 #gpio-cells = <2>;
 222                                 interrupt-controller;
 223                                 #interrupt-cells = <2>;
 224                         };
 225
 226                         gpio7: gpio@53fe4000 {
 227                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 228                                 reg = <0x53fe4000 0x4000>;
 229                                 interrupts = <107 108>;
 230                                 gpio-controller;
 231                                 #gpio-cells = <2>;
 232                                 interrupt-controller;
 233                                 #interrupt-cells = <2>;
 234                         };
 235
 236                         i2c@53fec000 { /* I2C3 */
 237                                 #address-cells = <1>;
 238                                 #size-cells = <0>;
 239                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 240                                 reg = <0x53fec000 0x4000>;
 241                                 interrupts = <64>;
 242                                 status = "disabled";
 243                         };
 244
 245                         uart4: serial@53ff0000 {
 246                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 247                                 reg = <0x53ff0000 0x4000>;
 248                                 interrupts = <13>;
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 aips@60000000 { /* AIPS2 */
 254                         compatible = "fsl,aips-bus", "simple-bus";
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257                         reg = <0x60000000 0x10000000>;
 258                         ranges;
 259
 260                         uart5: serial@63f90000 {
 261                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 262                                 reg = <0x63f90000 0x4000>;
 263                                 interrupts = <86>;
 264                                 status = "disabled";
 265                         };
 266
 267                         ecspi@63fac000 { /* ECSPI2 */
 268                                 #address-cells = <1>;
 269                                 #size-cells = <0>;
 270                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 271                                 reg = <0x63fac000 0x4000>;
 272                                 interrupts = <37>;
 273                                 status = "disabled";
 274                         };
 275
 276                         sdma@63fb0000 {
 277                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 278                                 reg = <0x63fb0000 0x4000>;
 279                                 interrupts = <6>;
 280                         };
 281
 282                         cspi@63fc0000 {
 283                                 #address-cells = <1>;
 284                                 #size-cells = <0>;
 285                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 286                                 reg = <0x63fc0000 0x4000>;
 287                                 interrupts = <38>;
 288                                 status = "disabled";
 289                         };
 290
 291                         i2c@63fc4000 { /* I2C2 */
 292                                 #address-cells = <1>;
 293                                 #size-cells = <0>;
 294                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 295                                 reg = <0x63fc4000 0x4000>;
 296                                 interrupts = <63>;
 297                                 status = "disabled";
 298                         };
 299
 300                         i2c@63fc8000 { /* I2C1 */
 301                                 #address-cells = <1>;
 302                                 #size-cells = <0>;
 303                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
 304                                 reg = <0x63fc8000 0x4000>;
 305                                 interrupts = <62>;
 306                                 status = "disabled";
 307                         };
 308
 309                         ssi1: ssi@63fcc000 {
 310                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 311                                 reg = <0x63fcc000 0x4000>;
 312                                 interrupts = <29>;
 313                                 fsl,fifo-depth = <15>;
 314                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 315                                 status = "disabled";
 316                         };
 317
 318                         audmux@63fd0000 {
 319                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 320                                 reg = <0x63fd0000 0x4000>;
 321                                 status = "disabled";
 322                         };
 323
 324                         nand@63fdb000 {
 325                                 compatible = "fsl,imx53-nand";
 326                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 327                                 interrupts = <8>;
 328                                 status = "disabled";
 329                         };
 330
 331                         ssi3: ssi@63fe8000 {
 332                                 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
 333                                 reg = <0x63fe8000 0x4000>;
 334                                 interrupts = <96>;
 335                                 fsl,fifo-depth = <15>;
 336                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 337                                 status = "disabled";
 338                         };
 339
 340                         ethernet@63fec000 {
 341                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 342                                 reg = <0x63fec000 0x4000>;
 343                                 interrupts = <87>;
 344                                 status = "disabled";
 345                         };
 346                 };
 347         };
 348 };