Pileus Git - ~andy/linux/blob - arch/arm/boot/dts/armada-xp-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP evaluation board
   3  * (DB-78460-BP)
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 /include/ "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Evaluation Board";
  21         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
  30         };
  31
  32         soc {
  33                 ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
  34                           0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
  35                           0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
  36
  37                 internal-regs {
  38                         serial@12000 {
  39                                 clock-frequency = <250000000>;
  40                                 status = "okay";
  41                         };
  42                         serial@12100 {
  43                                 clock-frequency = <250000000>;
  44                                 status = "okay";
  45                         };
  46                         serial@12200 {
  47                                 clock-frequency = <250000000>;
  48                                 status = "okay";
  49                         };
  50                         serial@12300 {
  51                                 clock-frequency = <250000000>;
  52                                 status = "okay";
  53                         };
  54
  55                         sata@a0000 {
  56                                 nr-ports = <2>;
  57                                 status = "okay";
  58                         };
  59
  60                         mdio {
  61                                 phy0: ethernet-phy@0 {
  62                                         reg = <0>;
  63                                 };
  64
  65                                 phy1: ethernet-phy@1 {
  66                                         reg = <1>;
  67                                 };
  68
  69                                 phy2: ethernet-phy@2 {
  70                                         reg = <25>;
  71                                 };
  72
  73                                 phy3: ethernet-phy@3 {
  74                                         reg = <27>;
  75                                 };
  76                         };
  77
  78                         ethernet@70000 {
  79                                 status = "okay";
  80                                 phy = <&phy0>;
  81                                 phy-mode = "rgmii-id";
  82                         };
  83                         ethernet@74000 {
  84                                 status = "okay";
  85                                 phy = <&phy1>;
  86                                 phy-mode = "rgmii-id";
  87                         };
  88                         ethernet@30000 {
  89                                 status = "okay";
  90                                 phy = <&phy2>;
  91                                 phy-mode = "sgmii";
  92                         };
  93                         ethernet@34000 {
  94                                 status = "okay";
  95                                 phy = <&phy3>;
  96                                 phy-mode = "sgmii";
  97                         };
  98
  99                         mvsdio@d4000 {
 100                                 pinctrl-0 = <&sdio_pins>;
 101                                 pinctrl-names = "default";
 102                                 status = "okay";
 103                                 /* No CD or WP GPIOs */
 104                                 broken-cd;
 105                         };
 106
 107                         usb@50000 {
 108                                 status = "okay";
 109                         };
 110
 111                         usb@51000 {
 112                                 status = "okay";
 113                         };
 114
 115                         usb@52000 {
 116                                 status = "okay";
 117                         };
 118
 119                         spi0: spi@10600 {
 120                                 status = "okay";
 121
 122                                 spi-flash@0 {
 123                                         #address-cells = <1>;
 124                                         #size-cells = <1>;
 125                                         compatible = "m25p64";
 126                                         reg = <0>; /* Chip select 0 */
 127                                         spi-max-frequency = <20000000>;
 128                                 };
 129                         };
 130
 131                         pcie-controller {
 132                                 status = "okay";
 133
 134                                 /*
 135                                  * All 6 slots are physically present as
 136                                  * standard PCIe slots on the board.
 137                                  */
 138                                 pcie@1,0 {
 139                                         /* Port 0, Lane 0 */
 140                                         status = "okay";
 141                                 };
 142                                 pcie@2,0 {
 143                                         /* Port 0, Lane 1 */
 144                                         status = "okay";
 145                                 };
 146                                 pcie@3,0 {
 147                                         /* Port 0, Lane 2 */
 148                                         status = "okay";
 149                                 };
 150                                 pcie@4,0 {
 151                                         /* Port 0, Lane 3 */
 152                                         status = "okay";
 153                                 };
 154                                 pcie@9,0 {
 155                                         /* Port 2, Lane 0 */
 156                                         status = "okay";
 157                                 };
 158                                 pcie@10,0 {
 159                                         /* Port 3, Lane 0 */
 160                                         status = "okay";
 161                                 };
 162                         };
 163
 164                         devbus-bootcs@10400 {
 165                                 status = "okay";
 166                                 ranges = <0 0xf0000000 0x1000000>;
 167
 168                                 /* Device Bus parameters are required */
 169
 170                                 /* Read parameters */
 171                                 devbus,bus-width    = <8>;
 172                                 devbus,turn-off-ps  = <60000>;
 173                                 devbus,badr-skew-ps = <0>;
 174                                 devbus,acc-first-ps = <124000>;
 175                                 devbus,acc-next-ps  = <248000>;
 176                                 devbus,rd-setup-ps  = <0>;
 177                                 devbus,rd-hold-ps   = <0>;
 178
 179                                 /* Write parameters */
 180                                 devbus,sync-enable = <0>;
 181                                 devbus,wr-high-ps  = <60000>;
 182                                 devbus,wr-low-ps   = <60000>;
 183                                 devbus,ale-wr-ps   = <60000>;
 184
 185                                 /* NOR 16 MiB */
 186                                 nor@0 {
 187                                         compatible = "cfi-flash";
 188                                         reg = <0 0x1000000>;
 189                                         bank-width = <2>;
 190                                 };
 191                         };
 192                 };
 193         };
 194 };