+\r
+/* Wait for DMA receive complete */\r
+void sdma_wait(sdma_t *port, uint64_t *time)\r
+{\r
+ int req = (void*)port->pin_rcv > (void*)PORTD ? SDMA_REQ_PTD :\r
+ (void*)port->pin_rcv > (void*)PORTC ? SDMA_REQ_PTC :\r
+ (void*)port->pin_rcv > (void*)PORTA ? SDMA_REQ_PTA : 0;\r
+\r
+ // Reset channel\r
+ port->dma_rcv->dsr = DMA_DSR_BCR_DONE_MASK;\r
+\r
+ // Configure channel\r
+ port->dma_rcv->dcr = DMA_DCR_SINC_MASK\r
+ | DMA_DCR_DINC_MASK\r
+ | DMA_DCR_SSIZE(0)\r
+ | DMA_DCR_DSIZE(0)\r
+ | DMA_DCR_D_REQ_MASK;\r
+\r
+ // Setup muxing\r
+ port->mux_rcv->cfg = DMAMUX_CHCFG_SOURCE(req)\r
+ | DMAMUX_CHCFG_ENBL_MASK;\r
+\r
+ // Set address and size\r
+ port->dma_rcv->sar = (uint32_t)&PIT->LTMR64H;\r
+ port->dma_rcv->dar = (uint32_t)&port->time_rcv;\r
+ port->dma_rcv->dsr = DMA_DSR_BCR_BCR(sizeof(uint64_t));\r
+\r
+ // Enable DMA transmit\r
+ port->dma_rcv->dcr |= DMA_DCR_ERQ_MASK;\r
+\r
+ // set pin to generate DMA req\r
+ port->pin_rcv->pcr = PORT_PCR_ISF_MASK\r
+ | PORT_PCR_IRQC(1)\r
+ | PORT_PCR_MUX(3)\r
+ | PORT_PCR_PE_MASK;\r
+\r
+ // Wait for transmit complete\r
+ while ((port->dma_rcv->dsr & DMA_DSR_BCR_BCR_MASK))\r
+ port->stuck++;\r
+\r
+ // Save recv time\r
+ *time = ((uint64_t)~port->time_rcv[0]) << 32\r
+ | ((uint64_t)~port->time_rcv[1]) << 0;\r
+\r
+ // pcr:00030302 dsr:41000008\r
+ printf(" - pcr:%08lx dsr:%08lx time:%08lx:%08lx",\r
+ port->pin_rcv->pcr, port->dma_rcv->dsr,\r
+ (uint32_t)(*time >> 32), (uint32_t)*time);\r
+}\r
+\r
+/* Write ASCII data to the output queue */\r
+void sdma_vprintf(sdma_t *port, const char *fmt, va_list ap)\r
+{\r
+ int pos = port->length[port->index];\r
+ void *dst = &port->queue[port->index][pos];\r
+ port->length[port->index] +=\r
+ vsnprintf((char*)dst, SDMA_LEN-pos, fmt, ap);\r
+}\r
+\r
+void sdma_printf(sdma_t *port, const char *fmt, ...)\r
+{\r
+ va_list ap;\r
+ va_start(ap, fmt);\r
+ sdma_vprintf(port, fmt, ap);\r
+ va_end(ap);\r
+}\r