]> Pileus Git - ~andy/linux/commit
net/mlx4_core: Set number of msix vectors under SRIOV mode to firmware defaults
authorOr Gerlitz <ogerlitz@mellanox.com>
Thu, 17 Jan 2013 05:30:43 +0000 (05:30 +0000)
committerDavid S. Miller <davem@davemloft.net>
Fri, 18 Jan 2013 19:25:28 +0000 (14:25 -0500)
commitca4c7b35f75492de7fbf5ee95be07481c348caee
treebc23c6c1f58c7486f38c5beeac91a2cb116c8af7
parent213815a1e6ae70b9648483b110bc5081795f99e8
net/mlx4_core: Set number of msix vectors under SRIOV mode to firmware defaults

The lines

if (mlx4_is_mfunc(dev)) {
nreq = 2;
} else {

which hard code the number of requested msi-x vectors under multi-function
mode to two can be removed completely, since the firmware sets num_eqs and
reserved_eqs appropriately Thus, the code line:

nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, nreq);

is by itself sufficient and correct for all cases. Currently, for mfunc
mode num_eqs = 32 and reserved_eqs = 28, hence four vectors will be enabled.

This triples (one vector is used for the async events and commands EQ) the
horse power provided for processing of incoming packets on netdev RSS scheme,
IO initiators/targets commands processing flows, etc.

Reviewed-by: Jack Morgenstein <jackm@dev.mellanox.co.il>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx4/main.c