]> Pileus Git - ~andy/linux/commit
drm/i915: Optimize pipe irq handling on bdw
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 7 Nov 2013 10:05:40 +0000 (11:05 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 8 Nov 2013 17:10:10 +0000 (18:10 +0100)
commitc42664cceb368ee04848e23a9964afd953a9145c
treeb4f29ca4cbb58fb558b547cd794ce422df99a438
parent40c499f93fdefa2c496f59d18483b417ea06448b
drm/i915: Optimize pipe irq handling on bdw

We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h