]> Pileus Git - ~andy/linux/commit
PCI: Stop clearing bridge Secondary Status when setting up I/O aperture
authorBjorn Helgaas <bhelgaas@google.com>
Thu, 28 Nov 2013 00:24:50 +0000 (17:24 -0700)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 13 Dec 2013 15:44:30 +0000 (08:44 -0700)
commit5b764b834ea925b7fc87df4a87a0fde95acbecb9
treebc373ac83ea818d5c3a208a267400f6f5a4b15b8
parentd2f54d9b3ee32bc006a7ff25d716b32feba4b522
PCI: Stop clearing bridge Secondary Status when setting up I/O aperture

pci_setup_bridge_io() accessed PCI_IO_BASE and PCI_IO_LIMIT using dword
(32-bit) reads and writes, which also access the Secondary Status register.
Since the Secondary Status register is in the upper 16 bits of the dword,
and we preserved those upper 16 bits, this had the effect of clearing any
of the write-1-to-clear bits that happened to be set in the Secondary
Status register.

That's not what we want, so use word (16-bit) accesses to update only
PCI_IO_BASE and PCI_IO_LIMIT.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/setup-bus.c