#include "mbed.h"\r
+#include "serial_dma.h"\r
\r
/**\r
* Mode of operation:\r
* 4. The offset is used to compensate the receivers local clock.\r
*\r
* Time synchronization is performed in both directions.\r
+ *\r
+ *\r
+ * Only port A, C, and D can do aysnc DMA (p. 67)\r
+ *\r
+ * Uart Sources:\r
+ * UART 0 UART 1 UART 2\r
+ * xmt rcv xmt rcv xmt rcv\r
+ * --- --- --- --- --- ---\r
+ * A2 A1 **A19 A18** - -\r
+ * A14 A15 - - - -\r
+ * B17 B16 - - - -\r
+ * - - **C4 C3** - -\r
+ * D7 D6 - - **D3 D2** <<<\r
+ * - - - - **D5 D4**\r
+ * E20 E21 E0 E1 E16 E17 \r
+ * - - - - E22 E23 \r
+ *\r
+ * Pinout\r
+ * A1 B18 E30 C1 \r
+ * A2 B19 B20 C2 \r
+ * D3 C0 E23 B3 \r
+ * A12 C4 E22 B2 \r
+ * A4 C6 E21 B1 \r
+ * A5 C7 E20 B0 \r
+ * C8 C10 \r
+ * C9 C11 E2 P5-9V \r
+ * E3 GND \r
+ * A13 C13 E6 GND \r
+ * D2 C16 E16 P5V-USB \r
+ * D4 A7 E17 P3V3 \r
+ * D6 A6 E18 RST \r
+ * D7 A14 E19 P3V3 \r
+ * D5 A15 E31 SDA/D5 \r
+ * GND A15 \r
+ * VREFH A17 \r
+ * E0 B9 \r
+ * E1 --\r
*/\r
\r
+/* Trigger select options */\r
+\r
+#define TMP_CONF_TRGSEL_EXTRG 0x0 // 0b0000 External trigger pin input (EXTRG_IN)\r
+#define TMP_CONF_TRGSEL_CMP0 0x1 // 0b0001 CMP0 output\r
+#define TMP_CONF_TRGSEL_PIT0 0x4 // 0b0100 PIT trigger 0\r
+#define TMP_CONF_TRGSEL_PIT1 0x5 // 0b0101 PIT trigger 1\r
+#define TMP_CONF_TRGSEL_TPM0 0x8 // 0b1000 TPM0 overflow\r
+#define TMP_CONF_TRGSEL_TPM1 0x9 // 0b1001 TPM1 overflow\r
+#define TMP_CONF_TRGSEL_TPM2 0xA // 0b1010 TPM2 overflow\r
+#define TMP_CONF_TRGSEL_RTCA 0xC // 0b1100 RTC alarm\r
+#define TMP_CONF_TRGSEL_RTCS 0xD // 0b1101 RTC seconds\r
+#define TMP_CONF_TRGSEL_LPTMR 0xE // 0b1110 LPTMR trigger\r
+\r
/***********************\r
* Message Definitions *\r
***********************/\r
{\r
}\r
\r
+/***********************\r
+ * Timestamp functions *\r
+ ***********************/\r
+\r
+//void stamp() {\r
+//}\r
+\r
/********************\r
* Data definitions *\r
********************/\r
// UARTs tx rx\r
Serial uart0(USBTX, USBRX);\r
Serial uart1(PTE0, PTE1);\r
-Serial uart2(PTE16, PTE17);\r
+Serial uart2(PTD3, PTD2);\r
+\r
+// Serial DMA\r
+sdma_t *sdma0;\r
+sdma_t *sdma1;\r
+sdma_t *sdma2;\r
\r
/********\r
* Main *\r
********/\r
\r
+void test_tpm_init(void)\r
+{\r
+ // EXTRG_IN - PTB8 - alt 3\r
+ // PTC0 - alt 3\r
+ // PTC6 - alt 3\r
+\r
+ // Setup System Integration Module\r
+ SIM_Type *sim = SIM;\r
+\r
+ sim->SCGC5 |= SIM_SCGC5_PORTA_MASK\r
+ | SIM_SCGC5_PORTB_MASK\r
+ | SIM_SCGC5_PORTC_MASK\r
+ | SIM_SCGC5_PORTD_MASK\r
+ | SIM_SCGC5_PORTE_MASK\r
+ | SIM_SCGC5_LPTMR_MASK;\r
+\r
+ sim->SCGC6 |= SIM_SCGC6_TPM0_MASK\r
+ | SIM_SCGC6_TPM1_MASK\r
+ | SIM_SCGC6_TPM2_MASK\r
+ | SIM_SCGC6_DAC0_MASK\r
+ | SIM_SCGC6_ADC0_MASK\r
+ | SIM_SCGC6_PIT_MASK\r
+ | SIM_SCGC6_DMAMUX_MASK\r
+ | SIM_SCGC6_RTC_MASK;\r
+\r
+ sim->SOPT2 |= SIM_SOPT2_TPMSRC(1);\r
+\r
+ sim->SOPT4 = SIM_SOPT4_TPM1CLKSEL_MASK\r
+ | SIM_SOPT4_TPM1CH0SRC(3);\r
+\r
+ printf("SOPT2:%08lx SCGC5:%08lx SCGC6:%08lx\r\n",\r
+ sim->SOPT2, sim->SCGC5, sim->SCGC6);\r
+ //SOPT2:05010000 SCGC5:00003f83 SCGC6:07800001\r
+\r
+ //sim->SOPT7 |= SIM_SOPT7_ADC0TRGSEL(TMP_CONF_TRGSEL_EXTRG);\r
+\r
+ // Setup Port Control\r
+ PORT_Type *port = PORTC;\r
+\r
+ PORTE->PCR[25] = PORT_PCR_ISF_MASK\r
+ | PORT_PCR_IRQC(0x1)\r
+ | PORT_PCR_MUX(3) ;\r
+\r
+ port->PCR[0] = PORT_PCR_ISF_MASK\r
+ | PORT_PCR_IRQC(0x1)\r
+ | PORT_PCR_MUX(3)\r
+ | PORT_PCR_PE_MASK;\r
+\r
+ // Setup Timer/PWM Module\r
+ volatile TPM_Type *tpm = TPM1;\r
+\r
+ tpm->SC = TPM_SC_PS(0x7)\r
+ | TPM_SC_TOF_MASK;\r
+\r
+ tpm->CNT = TPM_CNT_COUNT(0);\r
+\r
+ tpm->MOD = TPM_CNT_COUNT(0xFFFF);\r
+\r
+ tpm->CONTROLS[1].CnV = 0x1234;\r
+ tpm->CONTROLS[1].CnSC = TPM_CnSC_CHF_MASK\r
+ | TPM_CnSC_CHIE_MASK\r
+ | TPM_CnSC_ELSA_MASK;\r
+\r
+ //tpm->CONTROLS[0].CnSC = TPM_CnSC_CHF_MASK\r
+ // | TPM_CnSC_CHIE_MASK\r
+ // | TPM_CnSC_MSB_MASK\r
+ // | TPM_CnSC_MSA_MASK\r
+ // | TPM_CnSC_ELSB_MASK\r
+ // | TPM_CnSC_ELSA_MASK;\r
+\r
+ tpm->STATUS = TPM_STATUS_CH0F_MASK\r
+ | TPM_STATUS_CH1F_MASK\r
+ | TPM_STATUS_CH2F_MASK\r
+ | TPM_STATUS_CH3F_MASK\r
+ | TPM_STATUS_CH4F_MASK\r
+ | TPM_STATUS_CH5F_MASK\r
+ | TPM_STATUS_TOF_MASK;\r
+\r
+ tpm->CONF = TPM_CONF_TRGSEL(TMP_CONF_TRGSEL_EXTRG)\r
+ | TPM_CONF_CSOO_MASK\r
+ | TPM_CONF_CSOT_MASK\r
+ | TPM_CONF_GTBEEN_MASK\r
+ | TPM_CONF_DBGMODE_MASK;\r
+\r
+ tpm->SC = TPM_SC_CMOD(1)\r
+ | TPM_SC_PS(0x7)\r
+ | TPM_SC_TOF_MASK;\r
+\r
+ printf("test - %02lx %08lx\r\n", tpm->CONTROLS[1].CnSC, tpm->CONTROLS[1].CnV); wait(0.1);\r
+}\r
+\r
+void test_tpm_run(void)\r
+{\r
+ //static DigitalIn pin(PTC0);\r
+ //static DigitalIn pin(PTC2);\r
+ static int pin = 0;\r
+\r
+ printf("%lx - PTC0:%08lx GPCR:%08lx:%08lx - SC:%04lx CNT:%04lx MOD:%04lx STATUS:%04lx CONF:%08lx - CnSC:%02lx CnV:%04lx\r\n",\r
+ (long)pin, PORTC->PCR[0], PORTC->GPCHR, PORTC->GPCLR,\r
+ TPM1->SC, TPM1->CNT, TPM1->MOD, TPM1->STATUS, TPM1->CONF,\r
+ TPM1->CONTROLS[1].CnSC, TPM1->CONTROLS[1].CnV);\r
+ TPM1->SC |= TPM_STATUS_TOF_MASK;\r
+ TPM1->STATUS |= TPM_STATUS_TOF_MASK;\r
+}\r
+\r
+void test_pit_init(void)\r
+{\r
+ //printf("test_pit_init\r\n");\r
+\r
+ // Enable\r
+ SIM->SCGC6 |= SIM_SCGC6_PIT_MASK;\r
+ PIT->MCR = 0;\r
+\r
+ // Channel 0\r
+ PIT->CHANNEL[0].LDVAL = 0xFFFFFFFF;\r
+ PIT->CHANNEL[0].TCTRL = 0;\r
+\r
+ // Channel 1\r
+ PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;\r
+ PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK;\r
+\r
+ // Start timers\r
+ PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TEN_MASK;\r
+ PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK;\r
+\r
+}\r
+\r
+void test_pit_run(void)\r
+{\r
+ register volatile uint32_t *tmh asm("r4") = &PIT->LTMR64H;\r
+ register volatile uint32_t *tml asm("r5") = &PIT->LTMR64L;\r
+\r
+ register uint32_t hi0 asm("r0"), lo0 asm("r1");\r
+ register uint32_t hi1 asm("r2"), lo1 asm("r3");\r
+\r
+ asm("ldr %0, [%4]\n\t" // Two clocks per load\r
+ "ldr %1, [%5]\n\t"\r
+ "ldr %2, [%4]\n\t"\r
+ "ldr %3, [%5]\n\t"\r
+ : "=r"(hi0), "=r"(lo0), "=r"(hi1), "=r"(lo1)\r
+ : "r"(tmh), "r"(tml));\r
+\r
+ uint64_t tm0 = ~((uint64_t)hi0 << 32 | lo0);\r
+ uint64_t tm1 = ~((uint64_t)hi1 << 32 | lo1);\r
+ double bus = 24E6; // 24 MHz bus clock\r
+\r
+ printf("tick %08lx:%08lx", (uint32_t)(tm0>>32), (uint32_t)tm0);\r
+ printf( " %08lx:%08lx", (uint32_t)(tm1>>32), (uint32_t)tm1);\r
+ printf( " %08lx", (uint32_t)(tm1-tm0));\r
+ printf( " %f\r\n", (double)tm0 / bus);\r
+}\r
+\r
void test_uart(void)\r
{\r
char xmt[32] = "hello, world";\r
char rcv[32] = {};\r
\r
- printf("start\r\n");\r
- for (int i = 0; xmt[i]; i++) {\r
- uart1.putc(xmt[i]);\r
+ sdma_write(sdma1, xmt, strlen(xmt));\r
+ sdma_flush(sdma1);\r
+\r
+ for (int i = 0; xmt[i]; i++)\r
rcv[i] = uart2.getc();\r
- }\r
- printf("xmt: %s\r\n", xmt);\r
- printf("rcv: %s\r\n", rcv);\r
+\r
+ printf("xmt: %s ", xmt);\r
+ printf("rcv: %s ", rcv);\r
+ printf("tag: dir:%08lx in:%08lx\r\n",\r
+ FPTD->PDDR, FPTD->PDIR);\r
}\r
\r
void test_leds(void)\r
uart1.baud(115200);\r
uart2.baud(115200);\r
\r
+ sdma1 = sdma_open(SDMA_UART1, SDMA_CHANNEL1);\r
+ sdma2 = sdma_open(SDMA_UART2, SDMA_CHANNEL2);\r
+\r
test_uart();\r
- test_leds();\r
+ //test_leds();\r
+ test_pit_init();\r
+ //test_tpm_init();\r
\r
while (1) {\r
- printf("tick\r\n");\r
- test_leds();\r
+ test_uart();\r
+ //test_leds();\r
+ //test_pit_run();\r
+ //test_tpm_run();\r
}\r
}\r
--- /dev/null
+#include <MKL46Z4.h>\r
+\r
+#include <stdint.h>\r
+#include <stdarg.h>\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+#include "serial_dma.h"\r
+\r
+/* Defines */\r
+#define SDMA_NUM 2\r
+#define SDMA_LEN 1024\r
+\r
+/* Port structure */\r
+struct sdma_t {\r
+ /* DMA channel */\r
+ struct {\r
+ uint32_t sar; // offset 0x00, Source Address Register\r
+ uint32_t dar; // offset 0x04, Destination Address Register\r
+ uint32_t dsr; // offset 0x08, DMA Status Register / Byte Count Register\r
+ uint32_t dcr; // offset 0x0C, DMA Control Register\r
+ } *dma;\r
+\r
+ /* DMA mux */\r
+ struct {\r
+ uint8_t cfg; // offset 0x00, Channel Configuration register\r
+ } *mux;\r
+\r
+ /* Data buffering */\r
+ int index;\r
+ int length[SDMA_NUM];\r
+ uint8_t queue[SDMA_NUM][SDMA_LEN];\r
+\r
+ /* Error logging */\r
+ int stuck;\r
+ int full;\r
+};\r
+\r
+/* DMA Request Sources */\r
+static int sdma_req_rx[] = {\r
+ [SDMA_UART0] 2,\r
+ [SDMA_UART1] 4,\r
+ [SDMA_UART2] 6,\r
+};\r
+static int sdma_req_tx[] = {\r
+ [SDMA_UART0] 3,\r
+ [SDMA_UART1] 5,\r
+ [SDMA_UART2] 7,\r
+};\r
+\r
+/* Port data */\r
+static sdma_t sdma_ports[SDMA_NUM_UART];\r
+\r
+/* DMA Functions */\r
+sdma_t *sdma_open(sdma_uart_t uart, sdma_dma_t dma)\r
+{\r
+ int rxreq = sdma_req_rx[uart]; (void)rxreq;\r
+ int txreq = sdma_req_tx[uart]; (void)txreq;\r
+\r
+ // Setup port\r
+ sdma_t *port = &sdma_ports[uart];\r
+\r
+ port->dma = (void*)&DMA0->DMA[dma];\r
+ port->mux = (void*)&DMAMUX0->CHCFG[dma];\r
+\r
+ // Enable DMA Cock\r
+ SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;\r
+ SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;\r
+\r
+ // Reset channel\r
+ port->dma->dsr = DMA_DSR_BCR_DONE_MASK;\r
+\r
+ // Configure DMA transfer\r
+ port->dma->dar = (uint32_t)&UART1->D;\r
+ port->dma->dcr = DMA_DCR_CS_MASK |\r
+ DMA_DCR_SINC_MASK |\r
+ DMA_DCR_SSIZE(1) |\r
+ DMA_DCR_DSIZE(1) |\r
+ DMA_DCR_D_REQ_MASK;\r
+\r
+ // Configure DMA Mux\r
+ port->mux->cfg = DMAMUX_CHCFG_SOURCE(txreq) |\r
+ DMAMUX_CHCFG_ENBL_MASK;\r
+\r
+ // Configure UART for DMA Channel 0\r
+ switch (uart) {\r
+ case SDMA_UART0:\r
+ UART0->C5 |= UART0_C5_TDMAE_MASK;\r
+ break;\r
+\r
+ case SDMA_UART1:\r
+ UART1->C2 = UART_C2_TIE_MASK\r
+ | UART_C2_TE_MASK\r
+ | UART_C2_RE_MASK;\r
+ UART1->C4 = UART_C4_TDMAS_MASK;\r
+ break;\r
+\r
+ case SDMA_UART2:\r
+ UART2->C2 = UART_C2_TIE_MASK\r
+ | UART_C2_TE_MASK\r
+ | UART_C2_RE_MASK;\r
+ UART2->C4 = UART_C4_TDMAS_MASK;\r
+ break;\r
+ }\r
+ return port;\r
+}\r
+\r
+/* Write binary data out the DMA output queue */\r
+void sdma_write(sdma_t *port, void *data, int len)\r
+{\r
+ if (port->length[port->index] + len > SDMA_LEN) {\r
+ port->full++;\r
+ } else {\r
+ int pos = port->length[port->index];\r
+ void *dst = &port->queue[port->index][pos];\r
+ memcpy(dst, data, len);\r
+ port->length[port->index] += len;\r
+ }\r
+}\r
+\r
+/* Write ASCII data to the output queue */\r
+void sdma_vprintf(sdma_t *port, const char *fmt, va_list ap)\r
+{\r
+ int pos = port->length[port->index];\r
+ void *dst = &port->queue[port->index][pos];\r
+ port->length[port->index] +=\r
+ vsnprintf((char*)dst, SDMA_LEN-pos, fmt, ap);\r
+}\r
+\r
+void sdma_printf(sdma_t *port, const char *fmt, ...)\r
+{\r
+ va_list ap;\r
+ va_start(ap, fmt);\r
+ sdma_vprintf(port, fmt, ap);\r
+ va_end(ap);\r
+}\r
+\r
+/* Trigger DMA transmit of the current output queue\r
+ * and swap buffers so we can write into unused space */\r
+void sdma_flush(sdma_t *port)\r
+{\r
+ if (port->length[port->index] == 0)\r
+ return;\r
+\r
+ // Wait for transmit complete\r
+ while (port->dma->dsr & DMA_DSR_BCR_BCR_MASK)\r
+ port->stuck++;\r
+\r
+ // Reset channel\r
+ port->dma->dsr = DMA_DSR_BCR_DONE_MASK;\r
+\r
+ // Set source address and length\r
+ port->dma->sar = (uint32_t)&port->queue[port->index];\r
+ port->dma->dsr = DMA_DSR_BCR_BCR(port->length[port->index]);\r
+\r
+ // Enable DMA transmit\r
+ port->dma->dcr |= DMA_DCR_ERQ_MASK;\r
+\r
+ // Swap buffers\r
+ port->length[port->index] = 0;\r
+ port->index = (port->index + 1) % SDMA_NUM;\r
+}\r