From: Anders Grafström Date: Thu, 16 Oct 2008 16:37:24 +0000 (+0100) Subject: [ARM] 5310/1: Fix cache flush functions for ARMv4 X-Git-Tag: v2.6.28-rc1~63^2~10 X-Git-Url: http://pileus.org/git/?a=commitdiff_plain;h=e4d2a5985af957d2c0da61fb978d0c414b92a562;p=~andy%2Flinux [ARM] 5310/1: Fix cache flush functions for ARMv4 ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels. The issue was introduced by commit f12d0d7c7786af39435ef6ae9defe47fb58f6091 This patch corrects the CPU_CP15 ifdef statements so that they actually do something. Signed-off-by: Anders Grafström Signed-off-by: Russell King --- diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S index 33926c9fcda..5786adf1004 100644 --- a/arch/arm/mm/cache-v4.S +++ b/arch/arm/mm/cache-v4.S @@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all) * Clean and invalidate the entire cache. */ ENTRY(v4_flush_kern_cache_all) -#ifdef CPU_CP15 +#ifdef CONFIG_CPU_CP15 mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mov pc, lr @@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all) * - flags - vma_area_struct flags describing address space */ ENTRY(v4_flush_user_cache_range) -#ifdef CPU_CP15 +#ifdef CONFIG_CPU_CP15 mov ip, #0 mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache mov pc, lr @@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range) * - end - virtual end address */ ENTRY(v4_dma_flush_range) -#ifdef CPU_CP15 +#ifdef CONFIG_CPU_CP15 mov r0, #0 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache #endif