From: Russell King Date: Thu, 25 Feb 2010 22:06:43 +0000 (+0000) Subject: Merge branches 'at91', 'cache', 'cup', 'ep93xx', 'ixp4xx', 'nuc', 'pending-dma-stream... X-Git-Tag: v2.6.34-rc1~241^2~4 X-Git-Url: http://pileus.org/git/?a=commitdiff_plain;h=3560adf62075829393743667ff338dd8fd26a5c2;p=~andy%2Flinux Merge branches 'at91', 'cache', 'cup', 'ep93xx', 'ixp4xx', 'nuc', 'pending-dma-streaming', 'u300' and 'umc' into devel --- 3560adf62075829393743667ff338dd8fd26a5c2 diff --cc arch/arm/common/dmabounce.c index cc32c1e54a5,bc90364a96c,734ac913599,cc32c1e54a5,cc32c1e54a5,cc32c1e54a5,51499d68b16,cc32c1e54a5,cc32c1e54a5..cc0a932bbea --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c @@@@@@@@@@ -308,13 -308,13 -308,17 -308,13 -308,13 -308,13 -308,15 -308,13 -308,13 +308,15 @@@@@@@@@@ static inline void unmap_single(struct memcpy(ptr, buf->safe, size); /* - * DMA buffers must have the same cache properties - * as if they were really used for DMA - which means - * data must be written back to RAM. Note that - * we don't use dmac_flush_range() here for the - * bidirectional case because we know the cache - * lines will be coherent with the data written. + * Since we may have written to a page cache page, + * we need to ensure that the data will be coherent + * with user mappings. */ - - __cpuc_flush_kernel_dcache_area(ptr, size); - dmac_clean_range(ptr, ptr + size); - outer_clean_range(__pa(ptr), __pa(ptr) + size); ++ + __cpuc_flush_dcache_area(ptr, size); } free_safe_buffer(dev->archdata.dmabounce, buf); ++++++ ++ } else { ++++++ ++ __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir); } } diff --cc arch/arm/include/asm/cacheflush.h index 730aefcfbee,3d2ef54c7cb,fd03fb63a33,730aefcfbee,730aefcfbee,730aefcfbee,e2908858741,730aefcfbee,730aefcfbee..be8b4d79cf4 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@@@@@@@@@ -211,10 -211,10 -211,10 -211,10 -211,10 -211,10 -196,11 -211,10 -211,10 +196,11 @@@@@@@@@@ struct cpu_cache_fns void (*coherent_kern_range)(unsigned long, unsigned long); void (*coherent_user_range)(unsigned long, unsigned long); - void (*flush_kern_dcache_page)(void *); + void (*flush_kern_dcache_area)(void *, size_t); + -- --- -- void (*dma_inv_range)(const void *, const void *); -- --- -- void (*dma_clean_range)(const void *, const void *); ++++++ ++ void (*dma_map_area)(const void *, size_t, int); ++++++ ++ void (*dma_unmap_area)(const void *, size_t, int); ++ +++ ++ - void (*dma_inv_range)(const void *, const void *); - void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); }; @@@@@@@@@@ -355,26 -351,13 -355,16 -355,26 -355,26 -355,26 -341,26 -355,26 -355,26 +337,13 @@@@@@@@@@ vivt_flush_cache_page(struct vm_area_st } } - -------static inline void - ------vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page, - flush_ptrace_access(struct vm_area_struct *vma, struct page *page, - ------- unsigned long uaddr, void *kaddr, - ------- unsigned long len, int write) - -------{ - ------- if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) { - ------- unsigned long addr = (unsigned long)kaddr; - ------- __cpuc_coherent_kern_range(addr, addr + len); - ------- } - -------} - ------ + #ifndef CONFIG_CPU_CACHE_VIPT + #define flush_cache_mm(mm) \ + vivt_flush_cache_mm(mm) + #define flush_cache_range(vma,start,end) \ + vivt_flush_cache_range(vma,start,end) + #define flush_cache_page(vma,addr,pfn) \ + vivt_flush_cache_page(vma,addr,pfn) - ------#define flush_ptrace_access(vma,page,ua,ka,len,write) \ - ------ vivt_flush_ptrace_access(vma,page,ua,ka,len,write) #else extern void flush_cache_mm(struct mm_struct *mm); extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); diff --cc arch/arm/mm/copypage-v6.c index 0fa1319273d,841f355319b,334d5602770,0fa1319273d,0fa1319273d,0fa1319273d,841f355319b,0fa1319273d,0fa1319273d..8bca4dea6df --- a/arch/arm/mm/copypage-v6.c +++ b/arch/arm/mm/copypage-v6.c @@@@@@@@@@ -41,14 -41,14 -41,6 -41,14 -41,14 -41,14 -41,14 -41,14 -41,14 +41,14 @@@@@@@@@@ static void v6_copy_user_highpage_nonal kfrom = kmap_atomic(from, KM_USER0); kto = kmap_atomic(to, KM_USER1); copy_page(kto, kfrom); + #ifdef CONFIG_HIGHMEM + /* + * kmap_atomic() doesn't set the page virtual address, and + * kunmap_atomic() takes care of cache flushing already. + */ + if (page_address(to) != NULL) + #endif - - __cpuc_flush_dcache_page(kto); ++ + __cpuc_flush_dcache_area(kto, PAGE_SIZE); kunmap_atomic(kto, KM_USER1); kunmap_atomic(kfrom, KM_USER0); } diff --cc arch/arm/mm/proc-xsc3.S index 96456f54879,96456f54879,2028f370288,96456f54879,96456f54879,96456f54879,046b3d88955,96456f54879,8e4f6dca899..e5797f1c1db --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@@@@@@@@@ -310,9 -310,9 -309,9 -310,9 -310,9 -310,9 -334,9 -310,9 -310,9 +334,9 @@@@@@@@@@ ENTRY(xsc3_cache_fns .long xsc3_flush_user_cache_range .long xsc3_coherent_kern_range .long xsc3_coherent_user_range - .long xsc3_flush_kern_dcache_page - .long xsc3_dma_inv_range - .long xsc3_dma_clean_range + .long xsc3_flush_kern_dcache_area -- --- -- .long xsc3_dma_inv_range -- --- -- .long xsc3_dma_clean_range ++++++ ++ .long xsc3_dma_map_area ++++++ ++ .long xsc3_dma_unmap_area .long xsc3_dma_flush_range ENTRY(cpu_xsc3_dcache_clean_area)