]> Pileus Git - ~andy/linux/commitdiff
hwmon: Fix PCI device reference leak in quirk
authorJean Delvare <khali@linux-fr.org>
Wed, 19 Dec 2012 21:16:59 +0000 (22:16 +0100)
committerJean Delvare <khali@endymion.delvare>
Wed, 19 Dec 2012 21:16:59 +0000 (22:16 +0100)
Thankfully this only affects systems with one specific south bridge
and is most probably harmless unless the hwmon module is heavily
cycled.

Signed-off-by: Jean Delvare <khali@linux-fr.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
drivers/hwmon/hwmon.c

index c3c471ca202f5c17fe25ff6c5d9db47d3527b333..646314f7c8397e05cfb1c89da7786005e6e41b7a 100644 (file)
@@ -84,19 +84,21 @@ static void __init hwmon_pci_quirks(void)
 
        /* Open access to 0x295-0x296 on MSI MS-7031 */
        sb = pci_get_device(PCI_VENDOR_ID_ATI, 0x436c, NULL);
-       if (sb &&
-           (sb->subsystem_vendor == 0x1462 &&  /* MSI */
-            sb->subsystem_device == 0x0031)) { /* MS-7031 */
-
-               pci_read_config_byte(sb, 0x48, &enable);
-               pci_read_config_word(sb, 0x64, &base);
-
-               if (base == 0 && !(enable & BIT(2))) {
-                       dev_info(&sb->dev,
-                                "Opening wide generic port at 0x295\n");
-                       pci_write_config_word(sb, 0x64, 0x295);
-                       pci_write_config_byte(sb, 0x48, enable | BIT(2));
+       if (sb) {
+               if (sb->subsystem_vendor == 0x1462 &&   /* MSI */
+                   sb->subsystem_device == 0x0031) {   /* MS-7031 */
+                       pci_read_config_byte(sb, 0x48, &enable);
+                       pci_read_config_word(sb, 0x64, &base);
+
+                       if (base == 0 && !(enable & BIT(2))) {
+                               dev_info(&sb->dev,
+                                        "Opening wide generic port at 0x295\n");
+                               pci_write_config_word(sb, 0x64, 0x295);
+                               pci_write_config_byte(sb, 0x48,
+                                                     enable | BIT(2));
+                       }
                }
+               pci_dev_put(sb);
        }
 #endif
 }