]> Pileus Git - ~andy/linux/commitdiff
agp: Use pci_resource_start() to get CPU physical address for BAR
authorBjorn Helgaas <bhelgaas@google.com>
Mon, 6 Jan 2014 22:21:16 +0000 (15:21 -0700)
committerBjorn Helgaas <bhelgaas@google.com>
Tue, 7 Jan 2014 18:36:35 +0000 (11:36 -0700)
amd_irongate_configure(), ati_configure(), and nvidia_configure() call
ioremap() on an address read directly from a BAR.  But a BAR contains a
bus address, and ioremap() expects a CPU physical address.  Use
pci_resource_start() to obtain the physical address.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/char/agp/amd-k7-agp.c
drivers/char/agp/ati-agp.c
drivers/char/agp/nvidia-agp.c

index 5f028cb1d6e80802b080251276f729febe59f99d..3661a51e93e2d37db31d1aa4997b0bdfeb149a05 100644 (file)
@@ -11,7 +11,7 @@
 #include <linux/slab.h>
 #include "agp.h"
 
-#define AMD_MMBASE     0x14
+#define AMD_MMBASE_BAR 1
 #define AMD_APSIZE     0xac
 #define AMD_MODECNTL   0xb0
 #define AMD_MODECNTL2  0xb2
@@ -205,6 +205,7 @@ static int amd_irongate_fetch_size(void)
 static int amd_irongate_configure(void)
 {
        struct aper_size_info_lvl2 *current_size;
+       phys_addr_t reg;
        u32 temp;
        u16 enable_reg;
 
@@ -212,9 +213,8 @@ static int amd_irongate_configure(void)
 
        if (!amd_irongate_private.registers) {
                /* Get the memory mapped registers */
-               pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp);
-               temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
-               amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
+               reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
+               amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
                if (!amd_irongate_private.registers)
                        return -ENOMEM;
        }
index 53cb310d433eedc580d31e8ab941b4d6eb16cff7..ba83c11186ce493ee60bed25d93b31fa7728e108 100644 (file)
@@ -12,7 +12,7 @@
 #include <asm/agp.h>
 #include "agp.h"
 
-#define ATI_GART_MMBASE_ADDR   0x14
+#define ATI_GART_MMBASE_BAR    1
 #define ATI_RS100_APSIZE       0xac
 #define ATI_RS100_IG_AGPMODE   0xb0
 #define ATI_RS300_APSIZE       0xf8
@@ -196,12 +196,12 @@ static void ati_cleanup(void)
 
 static int ati_configure(void)
 {
+       phys_addr_t reg;
        u32 temp;
 
        /* Get the memory mapped registers */
-       pci_read_config_dword(agp_bridge->dev, ATI_GART_MMBASE_ADDR, &temp);
-       temp = (temp & 0xfffff000);
-       ati_generic_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
+       reg = pci_resource_start(agp_bridge->dev, ATI_GART_MMBASE_BAR);
+       ati_generic_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
 
        if (!ati_generic_private.registers)
                return -ENOMEM;
index ab65d55272c4767eed98b7cba9965c33617aefba..a1861b75eb31a9fe433e32105ef623092741052e 100644 (file)
@@ -106,6 +106,7 @@ static int nvidia_configure(void)
 {
        int i, rc, num_dirs;
        u32 apbase, aplimit;
+       phys_addr_t apbase_phys;
        struct aper_size_info_8 *current_size;
        u32 temp;
 
@@ -152,8 +153,9 @@ static int nvidia_configure(void)
        pci_write_config_dword(agp_bridge->dev, NVIDIA_0_APSIZE, temp | 0x100);
 
        /* map aperture */
+       apbase_phys = pci_resource_start(agp_bridge->dev, AGP_APERTURE_BAR);
        nvidia_private.aperture =
-               (volatile u32 __iomem *) ioremap(apbase, 33 * PAGE_SIZE);
+               (volatile u32 __iomem *) ioremap(apbase_phys, 33 * PAGE_SIZE);
 
        if (!nvidia_private.aperture)
                return -ENOMEM;