Merge branch 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc

* 'features/imx3' of git://git.pengutronix.de/git/imx/linux-2.6:
  ARM: mx3: Setup AIPS registers
  ARM: mx3: Let mx31 and mx35 enter in LPM mode in WFI

Conflicts:
	arch/arm/mach-imx/mm-imx3.c

diff --cc arch/arm/mach-imx/mm-imx3.c
index 8404ee72555ac4dda154e27d33b9c6f7804afaab,35ce8b5fe75da120bb54a7bbc185b76ede2cb1f8..b23bd3f09a60a1dee7c98e0f65ee1eddf7c27c9d
--- 1/arch/arm/mach-imx/mm-imx3.c
--- 2/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@@ -34,29 -34,33 +34,31 @@@ static void imx3_idle(void
  {
        unsigned long reg = 0;
  
 -      if (!need_resched())
 -              __asm__ __volatile__(
 -                      /* disable I and D cache */
 -                      "mrc p15, 0, %0, c1, c0, 0\n"
 -                      "bic %0, %0, #0x00001000\n"
 -                      "bic %0, %0, #0x00000004\n"
 -                      "mcr p15, 0, %0, c1, c0, 0\n"
 -                      /* invalidate I cache */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c5, 0\n"
 -                      /* clear and invalidate D cache */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c14, 0\n"
 -                      /* WFI */
 -                      "mov %0, #0\n"
 -                      "mcr p15, 0, %0, c7, c0, 4\n"
 -                      "nop\n" "nop\n" "nop\n" "nop\n"
 -                      "nop\n" "nop\n" "nop\n"
 -                      /* enable I and D cache */
 -                      "mrc p15, 0, %0, c1, c0, 0\n"
 -                      "orr %0, %0, #0x00001000\n"
 -                      "orr %0, %0, #0x00000004\n"
 -                      "mcr p15, 0, %0, c1, c0, 0\n"
 -                      : "=r" (reg));
 -      local_irq_enable();
+       mx3_cpu_lp_set(MX3_WAIT);
+ 
 +      __asm__ __volatile__(
 +              /* disable I and D cache */
 +              "mrc p15, 0, %0, c1, c0, 0\n"
 +              "bic %0, %0, #0x00001000\n"
 +              "bic %0, %0, #0x00000004\n"
 +              "mcr p15, 0, %0, c1, c0, 0\n"
 +              /* invalidate I cache */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c5, 0\n"
 +              /* clear and invalidate D cache */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c14, 0\n"
 +              /* WFI */
 +              "mov %0, #0\n"
 +              "mcr p15, 0, %0, c7, c0, 4\n"
 +              "nop\n" "nop\n" "nop\n" "nop\n"
 +              "nop\n" "nop\n" "nop\n"
 +              /* enable I and D cache */
 +              "mrc p15, 0, %0, c1, c0, 0\n"
 +              "orr %0, %0, #0x00001000\n"
 +              "orr %0, %0, #0x00000004\n"
 +              "mcr p15, 0, %0, c1, c0, 0\n"
 +              : "=r" (reg));
  }
  
  static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,