]> Pileus Git - ~andy/linux/commitdiff
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
authorLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Jan 2010 17:46:20 +0000 (09:46 -0800)
committerLinus Torvalds <torvalds@linux-foundation.org>
Mon, 11 Jan 2010 17:46:20 +0000 (09:46 -0800)
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (45 commits)
  drm/nv04: Fix set_operation software method.
  drm/nouveau: initialise DMA tracking parameters earlier
  drm/nouveau: use dma.max rather than pushbuf size for checking GET validity
  drm/nv04: differentiate between nv04/nv05
  drm/nouveau: Fix null deref in nouveau_fence_emit due to deleted fence
  drm/nv50: prevent a possible ctxprog hang
  drm/nouveau: have ttm's fault handler called directly
  drm/nv50: restore correct cache1 get/put address on fifoctx load
  drm/nouveau: create function for "dealing" with gpu lockup
  drm/nouveau: remove unused nouveau_channel_idle() function
  drm/nouveau: fix handling of fbcon colours in 8bpp
  drm/nv04: Context switching fixes.
  drm/nouveau: Use the software object for fencing.
  drm/nouveau: Allocate a per-channel instance of NV_SW.
  drm/nv50: make the blocksize depend on vram size
  drm/nouveau: better alignment of bo sizes and use roundup instead of ALIGN
  drm/nouveau: Don't skip card take down on nv0x.
  drm/nouveau: Implement nv42-nv43 TV load detection.
  drm/nouveau: Clean up the nv17-nv4x load detection code a bit.
  drm/nv50: fix fillrect color
  ...

1  2 
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/rv770.c

index 5124401f266a168ea5202acfe24684ae9a339b1a,fa19c2b9820f7609fa23989339bdfa536cba83a6..d91fb8c0b7b31673f43b885e8b0c38b0c1b6ec50
@@@ -158,6 -158,7 +158,7 @@@ static struct drm_conn_prop_enum_list d
        { DRM_MODE_CONNECTOR_HDMIA, "HDMI Type A", 0 },
        { DRM_MODE_CONNECTOR_HDMIB, "HDMI Type B", 0 },
        { DRM_MODE_CONNECTOR_TV, "TV", 0 },
+       { DRM_MODE_CONNECTOR_eDP, "Embedded DisplayPort", 0 },
  };
  
  static struct drm_prop_enum_list drm_encoder_enum_list[] =
@@@ -282,7 -283,7 +283,7 @@@ EXPORT_SYMBOL(drm_mode_object_find)
   * functions & device file and adds it to the master fd list.
   *
   * RETURNS:
 - * Zero on success, error code on falure.
 + * Zero on success, error code on failure.
   */
  int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb,
                         const struct drm_framebuffer_funcs *funcs)
@@@ -2433,7 -2434,7 +2434,7 @@@ int drm_mode_connector_property_set_ioc
        } else if (connector->funcs->set_property)
                ret = connector->funcs->set_property(connector, property, out_resp->value);
  
 -      /* store the property value if succesful */
 +      /* store the property value if successful */
        if (!ret)
                drm_connector_property_set_value(connector, property, out_resp->value);
  out:
index a0ac3c134b1bb560503b6d60418ce9563f614990,1f4f83d6fbe65e50d8d674d6206e9b100efdfa57..c0651991c3e41ab7dd54ef77a464b7ff8cb889c6
@@@ -285,7 -285,8 +285,8 @@@ void r600_hpd_init(struct radeon_devic
                        }
                }
        }
-       r600_irq_set(rdev);
+       if (rdev->irq.installed)
+               r600_irq_set(rdev);
  }
  
  void r600_hpd_fini(struct radeon_device *rdev)
@@@ -677,11 -678,11 +678,11 @@@ int r600_mc_init(struct radeon_device *
                 * AGP so that GPU can catch out of VRAM/AGP access
                 */
                if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 -                      /* Enought place before */
 +                      /* Enough place before */
                        rdev->mc.vram_location = rdev->mc.gtt_location -
                                                        rdev->mc.mc_vram_size;
                } else if (tmp > rdev->mc.mc_vram_size) {
 -                      /* Enought place after */
 +                      /* Enough place after */
                        rdev->mc.vram_location = rdev->mc.gtt_location +
                                                        rdev->mc.gtt_size;
                } else {
        a.full = rfixed_const(100);
        rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
        rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
+       if (rdev->flags & RADEON_IS_IGP)
+               rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
        return 0;
  }
  
@@@ -1384,11 -1389,6 +1389,6 @@@ void r600_pciep_wreg(struct radeon_devi
        (void)RREG32(PCIE_PORT_DATA);
  }
  
- void r600_hdp_flush(struct radeon_device *rdev)
- {
-       WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
- }
  /*
   * CP & Ring
   */
@@@ -1785,6 -1785,8 +1785,8 @@@ void r600_fence_ring_emit(struct radeon
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
        radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
        radeon_ring_write(rdev, fence->seq);
+       radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
+       radeon_ring_write(rdev, 1);
        /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
        radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
        radeon_ring_write(rdev, RB_INT_STAT);
@@@ -2089,8 -2091,7 +2091,7 @@@ void r600_fini(struct radeon_device *rd
        radeon_gem_fini(rdev);
        radeon_fence_driver_fini(rdev);
        radeon_clocks_fini(rdev);
-       if (rdev->flags & RADEON_IS_AGP)
-               radeon_agp_fini(rdev);
+       radeon_agp_fini(rdev);
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        kfree(rdev->bios);
@@@ -2461,6 -2462,10 +2462,10 @@@ int r600_irq_set(struct radeon_device *
        u32 mode_int = 0;
        u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
  
+       if (!rdev->irq.installed) {
+               WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+               return -EINVAL;
+       }
        /* don't enable anything if the ih is disabled */
        if (!rdev->ih.enabled)
                return 0;
index 3bcb66e52786c3ef0018d8e2c43bf29d3825b154,16f7317fa1af8877a2309f826cf8659b00a88393..59c71245fb91e66d0429dd31cb8da36ef57015b6
@@@ -833,11 -833,11 +833,11 @@@ int rv770_mc_init(struct radeon_device 
                 * AGP so that GPU can catch out of VRAM/AGP access
                 */
                if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
 -                      /* Enought place before */
 +                      /* Enough place before */
                        rdev->mc.vram_location = rdev->mc.gtt_location -
                                                        rdev->mc.mc_vram_size;
                } else if (tmp > rdev->mc.mc_vram_size) {
 -                      /* Enought place after */
 +                      /* Enough place after */
                        rdev->mc.vram_location = rdev->mc.gtt_location +
                                                        rdev->mc.gtt_size;
                } else {
@@@ -1096,8 -1096,7 +1096,7 @@@ void rv770_fini(struct radeon_device *r
        radeon_gem_fini(rdev);
        radeon_fence_driver_fini(rdev);
        radeon_clocks_fini(rdev);
-       if (rdev->flags & RADEON_IS_AGP)
-               radeon_agp_fini(rdev);
+       radeon_agp_fini(rdev);
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        kfree(rdev->bios);