]> Pileus Git - ~andy/linux/commitdiff
[IA64] forbid ptrace changes psr.ri to 3
authorShaohua Li <shaohua.li@intel.com>
Fri, 17 Aug 2007 20:43:50 +0000 (13:43 -0700)
committerTony Luck <tony.luck@intel.com>
Fri, 17 Aug 2007 20:43:50 +0000 (13:43 -0700)
The "ri" field in the processor status register only has defined
values of 0, 1, 2.  Do not let ptrace set this to 3.  As with
other reserved fields in registers we silently discard the value.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
arch/ia64/kernel/ptrace.c

index 00f80324694829f5eef2e647299a8227213689f1..122444a97897d7f02a7707cdd3f178248a1efdf5 100644 (file)
@@ -951,10 +951,14 @@ access_uarea (struct task_struct *child, unsigned long addr,
                        return 0;
 
                      case PT_CR_IPSR:
-                       if (write_access)
-                               pt->cr_ipsr = ((*data & IPSR_MASK)
+                       if (write_access) {
+                               unsigned long tmp = *data;
+                               /* psr.ri==3 is a reserved value: SDM 2:25 */
+                               if ((tmp & IA64_PSR_RI) == IA64_PSR_RI)
+                                       tmp &= ~IA64_PSR_RI;
+                               pt->cr_ipsr = ((tmp & IPSR_MASK)
                                               | (pt->cr_ipsr & ~IPSR_MASK));
-                       else
+                       else
                                *data = (pt->cr_ipsr & IPSR_MASK);
                        return 0;